1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <strings.h> 7 #include <stdint.h> 8 #include <sys/mman.h> 9 10 #include <rte_malloc.h> 11 #include <rte_log.h> 12 #include <rte_errno.h> 13 #include <rte_bus_pci.h> 14 #include <rte_pci.h> 15 #include <rte_regexdev_driver.h> 16 #include <rte_mbuf.h> 17 18 #include <infiniband/mlx5dv.h> 19 #include <mlx5_glue.h> 20 #include <mlx5_common.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_regex_utils.h" 24 #include "mlx5_rxp.h" 25 #include "mlx5_regex.h" 26 27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 28 #define MLX5_REGEX_METADATA_SIZE UINT32_C(64) 29 #define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 36 static inline uint32_t 37 sq_size_get(struct mlx5_regex_sq *sq) 38 { 39 return (1U << sq->log_nb_desc); 40 } 41 42 static inline uint32_t 43 cq_size_get(struct mlx5_regex_cq *cq) 44 { 45 return (1U << cq->log_nb_desc); 46 } 47 48 struct mlx5_regex_job { 49 uint64_t user_id; 50 volatile uint8_t *output; 51 volatile uint8_t *metadata; 52 } __rte_cached_aligned; 53 54 static inline void 55 set_data_seg(struct mlx5_wqe_data_seg *seg, 56 uint32_t length, uint32_t lkey, 57 uintptr_t address) 58 { 59 seg->byte_count = rte_cpu_to_be_32(length); 60 seg->lkey = rte_cpu_to_be_32(lkey); 61 seg->addr = rte_cpu_to_be_64(address); 62 } 63 64 static inline void 65 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 66 uint32_t mmo_control_31_0, uint32_t lkey, 67 uintptr_t address) 68 { 69 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 70 seg->lkey = rte_cpu_to_be_32(lkey); 71 seg->addr = rte_cpu_to_be_64(address); 72 } 73 74 static inline void 75 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 76 uint16_t subset_id1, uint16_t subset_id2, 77 uint16_t subset_id3, uint8_t ctrl) 78 { 79 MLX5_SET(regexp_mmo_control, seg, le, le); 80 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 81 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 84 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 85 } 86 87 static inline void 88 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 89 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 90 uint8_t signature, uint32_t imm) 91 { 92 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 93 ((uint32_t)pi << 8) | 94 opcode); 95 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 96 seg->fm_ce_se = fm_ce_se; 97 seg->signature = signature; 98 seg->imm = imm; 99 } 100 101 static inline void 102 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 103 struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 104 struct mlx5_regex_job *job) 105 { 106 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 107 uint32_t lkey; 108 uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ? 109 op->group_id0 : 0; 110 uint16_t group1 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F ? 111 op->group_id1 : 0; 112 uint16_t group2 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F ? 113 op->group_id2 : 0; 114 uint16_t group3 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F ? 115 op->group_id3 : 0; 116 uint8_t control = op->req_flags & 117 RTE_REGEX_OPS_REQ_MATCH_HIGH_PRIORITY_F ? 1 : 0; 118 119 /* For backward compatibility. */ 120 if (!(op->req_flags & (RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F | 121 RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F | 122 RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F | 123 RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F))) 124 group0 = op->group_id0; 125 lkey = mlx5_mr_addr2mr_bh(priv->pd, 0, 126 &priv->mr_scache, &qp->mr_ctrl, 127 rte_pktmbuf_mtod(op->mbuf, uintptr_t), 128 !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); 129 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 130 int ds = 4; /* ctrl + meta + input + output */ 131 132 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 133 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, 134 sq->sq_obj.sq->id, 0, ds, 0, 0); 135 set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3, 136 control); 137 struct mlx5_wqe_data_seg *input_seg = 138 (struct mlx5_wqe_data_seg *)(wqe + 139 MLX5_REGEX_WQE_GATHER_OFFSET); 140 input_seg->byte_count = 141 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 142 input_seg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(op->mbuf, 143 uintptr_t)); 144 input_seg->lkey = lkey; 145 job->user_id = op->user_id; 146 sq->db_pi = sq->pi; 147 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 148 } 149 150 static inline void 151 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 152 { 153 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 154 MLX5_SEND_WQE_BB; 155 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 156 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 157 uint64_t *doorbell_addr = 158 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 159 rte_io_wmb(); 160 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 161 MLX5_REGEX_MAX_WQE_INDEX); 162 rte_wmb(); 163 *doorbell_addr = *(volatile uint64_t *)wqe; 164 rte_wmb(); 165 } 166 167 static inline int 168 can_send(struct mlx5_regex_sq *sq) { 169 return ((uint16_t)(sq->pi - sq->ci) < sq_size_get(sq)); 170 } 171 172 static inline uint32_t 173 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 174 return qid * sq_size + (index & (sq_size - 1)); 175 } 176 177 uint16_t 178 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 179 struct rte_regex_ops **ops, uint16_t nb_ops) 180 { 181 struct mlx5_regex_priv *priv = dev->data->dev_private; 182 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 183 struct mlx5_regex_sq *sq; 184 size_t sqid, job_id, i = 0; 185 186 while ((sqid = ffs(queue->free_sqs))) { 187 sqid--; /* ffs returns 1 for bit 0 */ 188 sq = &queue->sqs[sqid]; 189 while (can_send(sq)) { 190 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 191 prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); 192 i++; 193 if (unlikely(i == nb_ops)) { 194 send_doorbell(priv->uar, sq); 195 goto out; 196 } 197 } 198 queue->free_sqs &= ~(1 << sqid); 199 send_doorbell(priv->uar, sq); 200 } 201 202 out: 203 queue->pi += i; 204 return i; 205 } 206 207 #define MLX5_REGEX_RESP_SZ 8 208 209 static inline void 210 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 211 { 212 size_t j; 213 size_t offset; 214 uint16_t status; 215 216 op->user_id = job->user_id; 217 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 218 MLX5_REGEX_METADATA_OFF, 219 match_count); 220 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 221 job->metadata + 222 MLX5_REGEX_METADATA_OFF, 223 detected_match_count); 224 for (j = 0; j < op->nb_matches; j++) { 225 offset = MLX5_REGEX_RESP_SZ * j; 226 op->matches[j].rule_id = 227 MLX5_GET_VOLATILE(regexp_match_tuple, 228 (job->output + offset), rule_id); 229 op->matches[j].start_offset = 230 MLX5_GET_VOLATILE(regexp_match_tuple, 231 (job->output + offset), start_ptr); 232 op->matches[j].len = 233 MLX5_GET_VOLATILE(regexp_match_tuple, 234 (job->output + offset), length); 235 } 236 status = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 237 MLX5_REGEX_METADATA_OFF, 238 status); 239 op->rsp_flags = 0; 240 if (status & MLX5_RXP_RESP_STATUS_PMI_SOJ) 241 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F; 242 if (status & MLX5_RXP_RESP_STATUS_PMI_EOJ) 243 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F; 244 if (status & MLX5_RXP_RESP_STATUS_MAX_LATENCY) 245 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F; 246 if (status & MLX5_RXP_RESP_STATUS_MAX_MATCH) 247 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F; 248 if (status & MLX5_RXP_RESP_STATUS_MAX_PREFIX) 249 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F; 250 if (status & MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS) 251 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 252 if (status & MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS) 253 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 254 } 255 256 static inline volatile struct mlx5_cqe * 257 poll_one(struct mlx5_regex_cq *cq) 258 { 259 volatile struct mlx5_cqe *cqe; 260 size_t next_cqe_offset; 261 262 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 263 cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset); 264 rte_io_wmb(); 265 266 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 267 268 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 269 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 270 return NULL; 271 } 272 273 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 274 return NULL; 275 276 return cqe; 277 } 278 279 280 /** 281 * DPDK callback for dequeue. 282 * 283 * @param dev 284 * Pointer to the regex dev structure. 285 * @param qp_id 286 * The queue to enqueue the traffic to. 287 * @param ops 288 * List of regex ops to dequeue. 289 * @param nb_ops 290 * Number of ops in ops parameter. 291 * 292 * @return 293 * Number of packets successfully dequeued (<= pkts_n). 294 */ 295 uint16_t 296 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 297 struct rte_regex_ops **ops, uint16_t nb_ops) 298 { 299 struct mlx5_regex_priv *priv = dev->data->dev_private; 300 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 301 struct mlx5_regex_cq *cq = &queue->cq; 302 volatile struct mlx5_cqe *cqe; 303 size_t i = 0; 304 305 while ((cqe = poll_one(cq))) { 306 uint16_t wq_counter 307 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 308 MLX5_REGEX_MAX_WQE_INDEX; 309 size_t sqid = cqe->rsvd3[2]; 310 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 311 while (sq->ci != wq_counter) { 312 if (unlikely(i == nb_ops)) { 313 /* Return without updating cq->ci */ 314 goto out; 315 } 316 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 317 sq->ci); 318 extract_result(ops[i], &queue->jobs[job_id]); 319 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 320 i++; 321 } 322 cq->ci = (cq->ci + 1) & 0xffffff; 323 rte_wmb(); 324 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); 325 queue->free_sqs |= (1 << sqid); 326 } 327 328 out: 329 queue->ci += i; 330 return i; 331 } 332 333 static void 334 setup_sqs(struct mlx5_regex_qp *queue) 335 { 336 size_t sqid, entry; 337 uint32_t job_id; 338 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 339 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 340 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes; 341 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 342 job_id = sqid * sq_size_get(sq) + entry; 343 struct mlx5_regex_job *job = &queue->jobs[job_id]; 344 345 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 346 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 347 0, queue->metadata->lkey, 348 (uintptr_t)job->metadata); 349 set_data_seg((struct mlx5_wqe_data_seg *) 350 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 351 MLX5_REGEX_MAX_OUTPUT, 352 queue->outputs->lkey, 353 (uintptr_t)job->output); 354 wqe += 64; 355 } 356 queue->free_sqs |= 1 << sqid; 357 } 358 } 359 360 static int 361 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 362 { 363 uint32_t i; 364 int err; 365 366 void *ptr = rte_calloc(__func__, qp->nb_desc, 367 MLX5_REGEX_METADATA_SIZE, 368 MLX5_REGEX_METADATA_SIZE); 369 if (!ptr) 370 return -ENOMEM; 371 372 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 373 MLX5_REGEX_METADATA_SIZE * qp->nb_desc, 374 IBV_ACCESS_LOCAL_WRITE); 375 if (!qp->metadata) { 376 DRV_LOG(ERR, "Failed to register metadata"); 377 rte_free(ptr); 378 return -EINVAL; 379 } 380 381 ptr = rte_calloc(__func__, qp->nb_desc, 382 MLX5_REGEX_MAX_OUTPUT, 383 MLX5_REGEX_MAX_OUTPUT); 384 if (!ptr) { 385 err = -ENOMEM; 386 goto err_output; 387 } 388 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 389 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 390 IBV_ACCESS_LOCAL_WRITE); 391 if (!qp->outputs) { 392 rte_free(ptr); 393 DRV_LOG(ERR, "Failed to register output"); 394 err = -EINVAL; 395 goto err_output; 396 } 397 398 /* distribute buffers to jobs */ 399 for (i = 0; i < qp->nb_desc; i++) { 400 qp->jobs[i].output = 401 (uint8_t *)qp->outputs->addr + 402 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 403 qp->jobs[i].metadata = 404 (uint8_t *)qp->metadata->addr + 405 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 406 } 407 return 0; 408 409 err_output: 410 ptr = qp->metadata->addr; 411 rte_free(ptr); 412 mlx5_glue->dereg_mr(qp->metadata); 413 return err; 414 } 415 416 int 417 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 418 { 419 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 420 int err; 421 422 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 423 if (!qp->jobs) 424 return -ENOMEM; 425 err = setup_buffers(qp, priv->pd); 426 if (err) { 427 rte_free(qp->jobs); 428 return err; 429 } 430 setup_sqs(qp); 431 return 0; 432 } 433 434 static void 435 free_buffers(struct mlx5_regex_qp *qp) 436 { 437 if (qp->metadata) { 438 mlx5_glue->dereg_mr(qp->metadata); 439 rte_free(qp->metadata->addr); 440 } 441 if (qp->outputs) { 442 mlx5_glue->dereg_mr(qp->outputs); 443 rte_free(qp->outputs->addr); 444 } 445 } 446 447 void 448 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 449 { 450 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 451 452 if (qp) { 453 free_buffers(qp); 454 if (qp->jobs) 455 rte_free(qp->jobs); 456 } 457 } 458