1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <sys/mman.h> 7 8 #include <rte_malloc.h> 9 #include <rte_log.h> 10 #include <rte_errno.h> 11 #include <rte_bus_pci.h> 12 #include <rte_pci.h> 13 #include <rte_regexdev_driver.h> 14 #include <rte_mbuf.h> 15 16 #include <infiniband/mlx5dv.h> 17 #include <mlx5_glue.h> 18 #include <mlx5_common.h> 19 #include <mlx5_prm.h> 20 #include <strings.h> 21 22 #include "mlx5_regex_utils.h" 23 #include "mlx5_rxp.h" 24 #include "mlx5_regex.h" 25 26 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 27 #define MLX5_REGEX_METADATA_SIZE 64 28 #define MLX5_REGEX_MAX_OUTPUT (1 << 11) 29 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 30 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 31 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 32 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 33 #define MLX5_REGEX_METADATA_OFF 32 34 35 static inline uint32_t 36 sq_size_get(struct mlx5_regex_sq *sq) 37 { 38 return (1U << sq->log_nb_desc); 39 } 40 41 static inline uint32_t 42 cq_size_get(struct mlx5_regex_cq *cq) 43 { 44 return (1U << cq->log_nb_desc); 45 } 46 47 struct mlx5_regex_job { 48 uint64_t user_id; 49 volatile uint8_t *output; 50 volatile uint8_t *metadata; 51 } __rte_cached_aligned; 52 53 static inline void 54 set_data_seg(struct mlx5_wqe_data_seg *seg, 55 uint32_t length, uint32_t lkey, 56 uintptr_t address) 57 { 58 seg->byte_count = rte_cpu_to_be_32(length); 59 seg->lkey = rte_cpu_to_be_32(lkey); 60 seg->addr = rte_cpu_to_be_64(address); 61 } 62 63 static inline void 64 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 65 uint32_t mmo_control_31_0, uint32_t lkey, 66 uintptr_t address) 67 { 68 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 69 seg->lkey = rte_cpu_to_be_32(lkey); 70 seg->addr = rte_cpu_to_be_64(address); 71 } 72 73 static inline void 74 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 75 uint16_t subset_id1, uint16_t subset_id2, 76 uint16_t subset_id3, uint8_t ctrl) 77 { 78 MLX5_SET(regexp_mmo_control, seg, le, le); 79 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 80 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 81 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 84 } 85 86 static inline void 87 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 88 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 89 uint8_t signature, uint32_t imm) 90 { 91 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 92 ((uint32_t)pi << 8) | 93 opcode); 94 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 95 seg->fm_ce_se = fm_ce_se; 96 seg->signature = signature; 97 seg->imm = imm; 98 } 99 100 static inline void 101 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 102 struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 103 struct mlx5_regex_job *job) 104 { 105 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 106 uint32_t lkey; 107 108 lkey = mlx5_mr_addr2mr_bh(priv->pd, 0, 109 &priv->mr_scache, &qp->mr_ctrl, 110 rte_pktmbuf_mtod(op->mbuf, uintptr_t), 111 !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); 112 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 113 int ds = 4; /* ctrl + meta + input + output */ 114 115 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 116 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, sq->obj->id, 117 0, ds, 0, 0); 118 set_regex_ctrl_seg(wqe + 12, 0, op->group_id0, op->group_id1, 119 op->group_id2, 120 op->group_id3, 0); 121 struct mlx5_wqe_data_seg *input_seg = 122 (struct mlx5_wqe_data_seg *)(wqe + 123 MLX5_REGEX_WQE_GATHER_OFFSET); 124 input_seg->byte_count = 125 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 126 input_seg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(op->mbuf, 127 uintptr_t)); 128 input_seg->lkey = lkey; 129 job->user_id = op->user_id; 130 sq->db_pi = sq->pi; 131 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 132 } 133 134 static inline void 135 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 136 { 137 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 138 MLX5_SEND_WQE_BB; 139 uint8_t *wqe = (uint8_t *)sq->wqe + wqe_offset; 140 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 141 uint64_t *doorbell_addr = 142 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 143 rte_io_wmb(); 144 sq->dbr[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 145 MLX5_REGEX_MAX_WQE_INDEX); 146 rte_wmb(); 147 *doorbell_addr = *(volatile uint64_t *)wqe; 148 rte_wmb(); 149 } 150 151 static inline int 152 can_send(struct mlx5_regex_sq *sq) { 153 return ((uint16_t)(sq->pi - sq->ci) < sq_size_get(sq)); 154 } 155 156 static inline uint32_t 157 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 158 return qid * sq_size + (index & (sq_size - 1)); 159 } 160 161 uint16_t 162 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 163 struct rte_regex_ops **ops, uint16_t nb_ops) 164 { 165 struct mlx5_regex_priv *priv = dev->data->dev_private; 166 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 167 struct mlx5_regex_sq *sq; 168 size_t sqid, job_id, i = 0; 169 170 while ((sqid = ffs(queue->free_sqs))) { 171 sqid--; /* ffs returns 1 for bit 0 */ 172 sq = &queue->sqs[sqid]; 173 while (can_send(sq)) { 174 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 175 prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); 176 i++; 177 if (unlikely(i == nb_ops)) { 178 send_doorbell(priv->uar, sq); 179 goto out; 180 } 181 } 182 queue->free_sqs &= ~(1 << sqid); 183 send_doorbell(priv->uar, sq); 184 } 185 186 out: 187 queue->pi += i; 188 return i; 189 } 190 191 #define MLX5_REGEX_RESP_SZ 8 192 193 static inline void 194 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 195 { 196 size_t j, offset; 197 op->user_id = job->user_id; 198 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 199 MLX5_REGEX_METADATA_OFF, 200 match_count); 201 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 202 job->metadata + 203 MLX5_REGEX_METADATA_OFF, 204 detected_match_count); 205 for (j = 0; j < op->nb_matches; j++) { 206 offset = MLX5_REGEX_RESP_SZ * j; 207 op->matches[j].rule_id = 208 MLX5_GET_VOLATILE(regexp_match_tuple, 209 (job->output + offset), rule_id); 210 op->matches[j].start_offset = 211 MLX5_GET_VOLATILE(regexp_match_tuple, 212 (job->output + offset), start_ptr); 213 op->matches[j].len = 214 MLX5_GET_VOLATILE(regexp_match_tuple, 215 (job->output + offset), length); 216 } 217 } 218 219 static inline volatile struct mlx5_cqe * 220 poll_one(struct mlx5_regex_cq *cq) 221 { 222 volatile struct mlx5_cqe *cqe; 223 size_t next_cqe_offset; 224 225 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 226 cqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset); 227 rte_io_wmb(); 228 229 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 230 231 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 232 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 233 return NULL; 234 } 235 236 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 237 return NULL; 238 239 return cqe; 240 } 241 242 243 /** 244 * DPDK callback for dequeue. 245 * 246 * @param dev 247 * Pointer to the regex dev structure. 248 * @param qp_id 249 * The queue to enqueue the traffic to. 250 * @param ops 251 * List of regex ops to dequeue. 252 * @param nb_ops 253 * Number of ops in ops parameter. 254 * 255 * @return 256 * Number of packets successfully dequeued (<= pkts_n). 257 */ 258 uint16_t 259 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 260 struct rte_regex_ops **ops, uint16_t nb_ops) 261 { 262 struct mlx5_regex_priv *priv = dev->data->dev_private; 263 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 264 struct mlx5_regex_cq *cq = &queue->cq; 265 volatile struct mlx5_cqe *cqe; 266 size_t i = 0; 267 268 while ((cqe = poll_one(cq))) { 269 uint16_t wq_counter 270 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 271 MLX5_REGEX_MAX_WQE_INDEX; 272 size_t sqid = cqe->rsvd3[2]; 273 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 274 while (sq->ci != wq_counter) { 275 if (unlikely(i == nb_ops)) { 276 /* Return without updating cq->ci */ 277 goto out; 278 } 279 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 280 sq->ci); 281 extract_result(ops[i], &queue->jobs[job_id]); 282 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 283 i++; 284 } 285 cq->ci = (cq->ci + 1) & 0xffffff; 286 rte_wmb(); 287 cq->dbr[0] = rte_cpu_to_be_32(cq->ci); 288 queue->free_sqs |= (1 << sqid); 289 } 290 291 out: 292 queue->ci += i; 293 return i; 294 } 295 296 static void 297 setup_sqs(struct mlx5_regex_qp *queue) 298 { 299 size_t sqid, entry; 300 uint32_t job_id; 301 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 302 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 303 uint8_t *wqe = (uint8_t *)sq->wqe; 304 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 305 job_id = sqid * sq_size_get(sq) + entry; 306 struct mlx5_regex_job *job = &queue->jobs[job_id]; 307 308 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 309 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 310 0, queue->metadata->lkey, 311 (uintptr_t)job->metadata); 312 set_data_seg((struct mlx5_wqe_data_seg *) 313 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 314 MLX5_REGEX_MAX_OUTPUT, 315 queue->outputs->lkey, 316 (uintptr_t)job->output); 317 wqe += 64; 318 } 319 queue->free_sqs |= 1 << sqid; 320 } 321 } 322 323 static int 324 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 325 { 326 uint32_t i; 327 int err; 328 329 void *ptr = rte_calloc(__func__, qp->nb_desc, 330 MLX5_REGEX_METADATA_SIZE, 331 MLX5_REGEX_METADATA_SIZE); 332 if (!ptr) 333 return -ENOMEM; 334 335 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 336 MLX5_REGEX_METADATA_SIZE*qp->nb_desc, 337 IBV_ACCESS_LOCAL_WRITE); 338 if (!qp->metadata) { 339 DRV_LOG(ERR, "Failed to register metadata"); 340 rte_free(ptr); 341 return -EINVAL; 342 } 343 344 ptr = rte_calloc(__func__, qp->nb_desc, 345 MLX5_REGEX_MAX_OUTPUT, 346 MLX5_REGEX_MAX_OUTPUT); 347 if (!ptr) { 348 err = -ENOMEM; 349 goto err_output; 350 } 351 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 352 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 353 IBV_ACCESS_LOCAL_WRITE); 354 if (!qp->outputs) { 355 rte_free(ptr); 356 DRV_LOG(ERR, "Failed to register output"); 357 err = -EINVAL; 358 goto err_output; 359 } 360 361 /* distribute buffers to jobs */ 362 for (i = 0; i < qp->nb_desc; i++) { 363 qp->jobs[i].output = 364 (uint8_t *)qp->outputs->addr + 365 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 366 qp->jobs[i].metadata = 367 (uint8_t *)qp->metadata->addr + 368 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 369 } 370 return 0; 371 372 err_output: 373 ptr = qp->metadata->addr; 374 rte_free(ptr); 375 mlx5_glue->dereg_mr(qp->metadata); 376 return err; 377 } 378 379 int 380 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 381 { 382 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 383 int err; 384 385 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 386 if (!qp->jobs) 387 return -ENOMEM; 388 err = setup_buffers(qp, priv->pd); 389 if (err) { 390 rte_free(qp->jobs); 391 return err; 392 } 393 setup_sqs(qp); 394 return 0; 395 } 396 397 static void 398 free_buffers(struct mlx5_regex_qp *qp) 399 { 400 if (qp->metadata) { 401 mlx5_glue->dereg_mr(qp->metadata); 402 rte_free(qp->metadata->addr); 403 } 404 if (qp->outputs) { 405 mlx5_glue->dereg_mr(qp->outputs); 406 rte_free(qp->outputs->addr); 407 } 408 } 409 410 void 411 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 412 { 413 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 414 415 if (qp) { 416 free_buffers(qp); 417 if (qp->jobs) 418 rte_free(qp->jobs); 419 } 420 } 421