1*72c00ae9SLiron Himi /* SPDX-License-Identifier: BSD-3-Clause 2*72c00ae9SLiron Himi * Copyright (C) 2020 Marvell International Ltd. 3*72c00ae9SLiron Himi */ 4*72c00ae9SLiron Himi 5*72c00ae9SLiron Himi #ifndef _CN9K_REGEXDEV_H_ 6*72c00ae9SLiron Himi #define _CN9K_REGEXDEV_H_ 7*72c00ae9SLiron Himi 8*72c00ae9SLiron Himi #include <rte_common.h> 9*72c00ae9SLiron Himi #include <rte_regexdev.h> 10*72c00ae9SLiron Himi 11*72c00ae9SLiron Himi #include "roc_api.h" 12*72c00ae9SLiron Himi 13*72c00ae9SLiron Himi #define cn9k_ree_dbg plt_ree_dbg 14*72c00ae9SLiron Himi #define cn9k_err plt_err 15*72c00ae9SLiron Himi 16*72c00ae9SLiron Himi #define ree_func_trace cn9k_ree_dbg 17*72c00ae9SLiron Himi 18*72c00ae9SLiron Himi /* Marvell CN9K Regex PMD device name */ 19*72c00ae9SLiron Himi #define REGEXDEV_NAME_CN9K_PMD regex_cn9k 20*72c00ae9SLiron Himi 21*72c00ae9SLiron Himi /** 22*72c00ae9SLiron Himi * Device private data 23*72c00ae9SLiron Himi */ 24*72c00ae9SLiron Himi struct cn9k_ree_data { 25*72c00ae9SLiron Himi uint32_t regexdev_capa; 26*72c00ae9SLiron Himi uint64_t rule_flags; 27*72c00ae9SLiron Himi /**< Feature flags exposes HW/SW features for the given device */ 28*72c00ae9SLiron Himi uint16_t max_rules_per_group; 29*72c00ae9SLiron Himi /**< Maximum rules supported per subset by this device */ 30*72c00ae9SLiron Himi uint16_t max_groups; 31*72c00ae9SLiron Himi /**< Maximum subset supported by this device */ 32*72c00ae9SLiron Himi void **queue_pairs; 33*72c00ae9SLiron Himi /**< Array of pointers to queue pairs. */ 34*72c00ae9SLiron Himi uint16_t nb_queue_pairs; 35*72c00ae9SLiron Himi /**< Number of device queue pairs. */ 36*72c00ae9SLiron Himi struct roc_ree_vf vf; 37*72c00ae9SLiron Himi /**< vf data */ 38*72c00ae9SLiron Himi struct rte_regexdev_rule *rules; 39*72c00ae9SLiron Himi /**< rules to be compiled */ 40*72c00ae9SLiron Himi uint16_t nb_rules; 41*72c00ae9SLiron Himi /**< number of rules */ 42*72c00ae9SLiron Himi } __rte_cache_aligned; 43*72c00ae9SLiron Himi 44*72c00ae9SLiron Himi #endif /* _CN9K_REGEXDEV_H_ */ 45