172c00ae9SLiron Himi /* SPDX-License-Identifier: BSD-3-Clause 272c00ae9SLiron Himi * Copyright (C) 2020 Marvell International Ltd. 372c00ae9SLiron Himi */ 472c00ae9SLiron Himi 572c00ae9SLiron Himi #ifndef _CN9K_REGEXDEV_H_ 672c00ae9SLiron Himi #define _CN9K_REGEXDEV_H_ 772c00ae9SLiron Himi 872c00ae9SLiron Himi #include <rte_common.h> 972c00ae9SLiron Himi #include <rte_regexdev.h> 1072c00ae9SLiron Himi 1172c00ae9SLiron Himi #include "roc_api.h" 1272c00ae9SLiron Himi 1372c00ae9SLiron Himi #define cn9k_ree_dbg plt_ree_dbg 1472c00ae9SLiron Himi #define cn9k_err plt_err 1572c00ae9SLiron Himi 1672c00ae9SLiron Himi #define ree_func_trace cn9k_ree_dbg 1772c00ae9SLiron Himi 1872c00ae9SLiron Himi /* Marvell CN9K Regex PMD device name */ 1972c00ae9SLiron Himi #define REGEXDEV_NAME_CN9K_PMD regex_cn9k 2072c00ae9SLiron Himi 2172c00ae9SLiron Himi /** 2272c00ae9SLiron Himi * Device private data 2372c00ae9SLiron Himi */ 24*27595cd8STyler Retzlaff struct __rte_cache_aligned cn9k_ree_data { 2572c00ae9SLiron Himi uint32_t regexdev_capa; 2672c00ae9SLiron Himi uint64_t rule_flags; 2772c00ae9SLiron Himi /**< Feature flags exposes HW/SW features for the given device */ 2872c00ae9SLiron Himi uint16_t max_rules_per_group; 2972c00ae9SLiron Himi /**< Maximum rules supported per subset by this device */ 3072c00ae9SLiron Himi uint16_t max_groups; 3172c00ae9SLiron Himi /**< Maximum subset supported by this device */ 3272c00ae9SLiron Himi void **queue_pairs; 3372c00ae9SLiron Himi /**< Array of pointers to queue pairs. */ 3472c00ae9SLiron Himi uint16_t nb_queue_pairs; 3572c00ae9SLiron Himi /**< Number of device queue pairs. */ 3672c00ae9SLiron Himi struct roc_ree_vf vf; 3772c00ae9SLiron Himi /**< vf data */ 3872c00ae9SLiron Himi struct rte_regexdev_rule *rules; 3972c00ae9SLiron Himi /**< rules to be compiled */ 4072c00ae9SLiron Himi uint16_t nb_rules; 4172c00ae9SLiron Himi /**< number of rules */ 42*27595cd8STyler Retzlaff }; 4372c00ae9SLiron Himi 4472c00ae9SLiron Himi #endif /* _CN9K_REGEXDEV_H_ */ 45