1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019 Intel Corporation. 3 */ 4 5 #ifndef _NTB_HW_INTEL_H_ 6 #define _NTB_HW_INTEL_H_ 7 8 /* Ntb control and link status */ 9 #define NTB_CTL_CFG_LOCK 1 10 #define NTB_CTL_DISABLE 2 11 #define NTB_CTL_S2P_BAR2_SNOOP (1 << 2) 12 #define NTB_CTL_P2S_BAR2_SNOOP (1 << 4) 13 #define NTB_CTL_S2P_BAR4_SNOOP (1 << 6) 14 #define NTB_CTL_P2S_BAR4_SNOOP (1 << 8) 15 #define NTB_CTL_S2P_BAR5_SNOOP (1 << 12) 16 #define NTB_CTL_P2S_BAR5_SNOOP (1 << 14) 17 18 #define NTB_LNK_STA_ACTIVE_BIT 0x2000 19 #define NTB_LNK_STA_SPEED_MASK 0x000f 20 #define NTB_LNK_STA_WIDTH_MASK 0x03f0 21 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT)) 22 #define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) 23 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) 24 25 /* Intel Xeon hardware */ 26 #define XEON_IMBAR1SZ_OFFSET 0x00d0 27 #define XEON_IMBAR2SZ_OFFSET 0x00d1 28 #define XEON_EMBAR1SZ_OFFSET 0x00d2 29 #define XEON_EMBAR2SZ_OFFSET 0x00d3 30 #define XEON_DEVCTRL_OFFSET 0x0098 31 #define XEON_DEVSTS_OFFSET 0x009a 32 #define XEON_UNCERRSTS_OFFSET 0x014c 33 #define XEON_CORERRSTS_OFFSET 0x0158 34 #define XEON_GEN3_LINK_STATUS_OFFSET 0x01a2 35 /* Link status and PPD are in MMIO but not config space for Gen4 NTB */ 36 #define XEON_GEN4_PPD0_OFFSET 0xb0d4 37 #define XEON_GEN4_PPD1_OFFSET 0xb4c0 38 #define XEON_GEN4_LINK_CTRL_OFFSET 0xb050 39 #define XEON_GEN4_LINK_STATUS_OFFSET 0xb052 40 #define XEON_GEN4_LINK_CTRL_LINK_DIS 0x0010 41 42 #define XEON_NTBCNTL_OFFSET 0x0000 43 #define XEON_BAR_INTERVAL_OFFSET 0x0010 44 #define XEON_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */ 45 #define XEON_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */ 46 #define XEON_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */ 47 #define XEON_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */ 48 #define XEON_GEN4_XBASEIDX_INTERVAL 0x0002 49 #define XEON_GEN4_IM1XBASEIDX_OFFSET 0x0074 50 #define XEON_GEN4_IM2XBASEIDX_OFFSET 0x0076 51 #define XEON_IM_INT_STATUS_OFFSET 0x0040 52 #define XEON_IM_INT_DISABLE_OFFSET 0x0048 53 #define XEON_IM_SPAD_OFFSET 0x0080 /* SPAD */ 54 #define XEON_GEN3_B2B_SPAD_OFFSET 0x0180 /* GEN3 B2B SPAD */ 55 #define XEON_GEN4_B2B_SPAD_OFFSET 0x8080 /* GEN4 B2B SPAD */ 56 #define XEON_USMEMMISS_OFFSET 0x0070 57 #define XEON_GEN3_INTVEC_OFFSET 0x00d0 58 #define XEON_GEN4_INTVEC_OFFSET 0x0050 59 #define XEON_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */ 60 #define XEON_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */ 61 #define XEON_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */ 62 #define XEON_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */ 63 #define XEON_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */ 64 #define XEON_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */ 65 #define XEON_EM_INT_STATUS_OFFSET 0x4040 66 #define XEON_EM_INT_DISABLE_OFFSET 0x4048 67 #define XEON_EM_SPAD_OFFSET 0x4080 /* remote SPAD */ 68 #define XEON_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */ 69 #define XEON_SPCICMD_OFFSET 0x4504 /* SPCICMD */ 70 #define XEON_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */ 71 #define XEON_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */ 72 #define XEON_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */ 73 74 #define XEON_PPD_OFFSET 0x00d4 75 #define XEON_PPD_CONN_MASK 0x03 76 #define XEON_PPD_CONN_TRANSPARENT 0x00 77 #define XEON_PPD_CONN_B2B 0x01 78 #define XEON_PPD_CONN_RP 0x02 79 #define XEON_PPD_DEV_MASK 0x10 80 #define XEON_PPD_DEV_USD 0x00 81 #define XEON_PPD_DEV_DSD 0x10 82 #define XEON_PPD_SPLIT_BAR_MASK 0x40 83 84 #define XEON_GEN4_PPD_CONN_MASK 0x0300 85 #define XEON_GEN4_PPD_CONN_B2B 0x0200 86 #define XEON_GEN4_PPD_DEV_MASK 0x1000 87 #define XEON_GEN4_PPD_DEV_DSD 0x1000 88 #define XEON_GEN4_PPD_DEV_USD 0x0000 89 #define XEON_GEN4_PPD_LINKTRN 0x0008 90 #define XEON_GEN4_SLOTSTS 0xb05a 91 #define XEON_GEN4_SLOTSTS_DLLSCS 0x100 92 93 #define XEON_MW_COUNT 2 94 95 #define XEON_DB_COUNT 32 96 #define XEON_DB_LINK 32 97 #define XEON_DB_LINK_BIT (1ULL << XEON_DB_LINK) 98 #define XEON_DB_MSIX_VECTOR_COUNT 33 99 #define XEON_DB_MSIX_VECTOR_SHIFT 1 100 #define XEON_DB_TOTAL_SHIFT 33 101 #define XEON_SPAD_COUNT 16 102 103 extern const struct ntb_dev_ops intel_ntb_ops; 104 105 #endif /* _NTB_HW_INTEL_H_ */ 106