1473c88f9SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 2473c88f9SBruce Richardson * Copyright(c) 2010-2018 Intel Corporation 3473c88f9SBruce Richardson */ 4473c88f9SBruce Richardson 5473c88f9SBruce Richardson #ifndef _IFPGA_RAWDEV_H_ 6473c88f9SBruce Richardson #define _IFPGA_RAWDEV_H_ 7473c88f9SBruce Richardson 8473c88f9SBruce Richardson extern int ifpga_rawdev_logtype; 92b843cacSDavid Marchand #define RTE_LOGTYPE_IFPGA_RAWDEV ifpga_rawdev_logtype 10473c88f9SBruce Richardson 11978bb0b3SWei Huang #define IFPGA_RAWDEV_NAME_FMT "IFPGA:%02x:%02x.%x" 12978bb0b3SWei Huang 132b843cacSDavid Marchand #define IFPGA_RAWDEV_PMD_LOG(level, ...) \ 142b843cacSDavid Marchand RTE_LOG_LINE_PREFIX(level, IFPGA_RAWDEV, "%s(): ", __func__, __VA_ARGS__) 15473c88f9SBruce Richardson 16473c88f9SBruce Richardson #define IFPGA_RAWDEV_PMD_FUNC_TRACE() IFPGA_RAWDEV_PMD_LOG(DEBUG, ">>") 17473c88f9SBruce Richardson 18*fd51012dSAndre Muezerie #define IFPGA_RAWDEV_PMD_DEBUG(fmt, ...) \ 19*fd51012dSAndre Muezerie IFPGA_RAWDEV_PMD_LOG(DEBUG, fmt, ## __VA_ARGS__) 20*fd51012dSAndre Muezerie #define IFPGA_RAWDEV_PMD_INFO(fmt, ...) \ 21*fd51012dSAndre Muezerie IFPGA_RAWDEV_PMD_LOG(INFO, fmt, ## __VA_ARGS__) 22*fd51012dSAndre Muezerie #define IFPGA_RAWDEV_PMD_ERR(fmt, ...) \ 23*fd51012dSAndre Muezerie IFPGA_RAWDEV_PMD_LOG(ERR, fmt, ## __VA_ARGS__) 24*fd51012dSAndre Muezerie #define IFPGA_RAWDEV_PMD_WARN(fmt, ...) \ 25*fd51012dSAndre Muezerie IFPGA_RAWDEV_PMD_LOG(WARNING, fmt, ## __VA_ARGS__) 26473c88f9SBruce Richardson 27473c88f9SBruce Richardson enum ifpga_rawdev_device_state { 28473c88f9SBruce Richardson IFPGA_IDLE, 29473c88f9SBruce Richardson IFPGA_READY, 30473c88f9SBruce Richardson IFPGA_ERROR 31473c88f9SBruce Richardson }; 32473c88f9SBruce Richardson 33473c88f9SBruce Richardson /** Set a bit in the uint64 variable */ 34473c88f9SBruce Richardson #define IFPGA_BIT_SET(var, pos) \ 35473c88f9SBruce Richardson ((var) |= ((uint64_t)1 << ((pos)))) 36473c88f9SBruce Richardson 37473c88f9SBruce Richardson /** Reset the bit in the variable */ 38473c88f9SBruce Richardson #define IFPGA_BIT_RESET(var, pos) \ 39473c88f9SBruce Richardson ((var) &= ~((uint64_t)1 << ((pos)))) 40473c88f9SBruce Richardson 41473c88f9SBruce Richardson /** Check the bit is set in the variable */ 42473c88f9SBruce Richardson #define IFPGA_BIT_ISSET(var, pos) \ 43473c88f9SBruce Richardson (((var) & ((uint64_t)1 << ((pos)))) ? 1 : 0) 44473c88f9SBruce Richardson 45473c88f9SBruce Richardson static inline struct opae_adapter * 46473c88f9SBruce Richardson ifpga_rawdev_get_priv(const struct rte_rawdev *rawdev) 47473c88f9SBruce Richardson { 48f724a802SWei Huang return (struct opae_adapter *)rawdev->dev_private; 49473c88f9SBruce Richardson } 50473c88f9SBruce Richardson 519c006c45SRosen Xu #define IFPGA_RAWDEV_MSIX_IRQ_NUM 7 529c006c45SRosen Xu #define IFPGA_RAWDEV_NUM 32 53ae835abaSWei Huang #define IFPGA_MAX_VDEV 4 5420659eb3SWei Huang #define IFPGA_MAX_IRQ 12 559c006c45SRosen Xu 569c006c45SRosen Xu struct ifpga_rawdev { 579c006c45SRosen Xu int dev_id; 589c006c45SRosen Xu struct rte_rawdev *rawdev; 599c006c45SRosen Xu int aer_enable; 609c006c45SRosen Xu int intr_fd[IFPGA_RAWDEV_MSIX_IRQ_NUM+1]; 619c006c45SRosen Xu uint32_t aer_old[2]; 629c006c45SRosen Xu char fvl_bdf[8][16]; 639c006c45SRosen Xu char parent_bdf[16]; 6420659eb3SWei Huang /* 0 for FME interrupt, others are reserved for AFU irq */ 6520659eb3SWei Huang void *intr_handle[IFPGA_MAX_IRQ]; 662479a1e9SWei Huang /* enable monitor thread poll device's sensors or not */ 672479a1e9SWei Huang int poll_enabled; 68ae835abaSWei Huang /* name of virtual devices created on raw device */ 69ae835abaSWei Huang char *vdev_name[IFPGA_MAX_VDEV]; 70ae835abaSWei Huang }; 71ae835abaSWei Huang 72ae835abaSWei Huang struct ifpga_vdev_args { 73ae835abaSWei Huang char bdf[PCI_PRI_STR_SIZE]; 74ae835abaSWei Huang int port; 759c006c45SRosen Xu }; 769c006c45SRosen Xu 779c006c45SRosen Xu struct ifpga_rawdev * 789c006c45SRosen Xu ifpga_rawdev_get(const struct rte_rawdev *rawdev); 799c006c45SRosen Xu 80e0a1aafeSTianfei Zhang enum ifpga_irq_type { 81e0a1aafeSTianfei Zhang IFPGA_FME_IRQ = 0, 82e0a1aafeSTianfei Zhang IFPGA_AFU_IRQ = 1, 83e0a1aafeSTianfei Zhang }; 84e0a1aafeSTianfei Zhang 85e0a1aafeSTianfei Zhang int 8620659eb3SWei Huang ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id, 87e0a1aafeSTianfei Zhang enum ifpga_irq_type type, int vec_start, int count, 88e0a1aafeSTianfei Zhang rte_intr_callback_fn handler, const char *name, 89e0a1aafeSTianfei Zhang void *arg); 90e0a1aafeSTianfei Zhang int 9120659eb3SWei Huang ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type, 92e0a1aafeSTianfei Zhang int vec_start, rte_intr_callback_fn handler, void *arg); 93e0a1aafeSTianfei Zhang 94f724a802SWei Huang int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port, 95f724a802SWei Huang const char *file); 96f724a802SWei Huang void ifpga_rawdev_cleanup(void); 97f724a802SWei Huang 98473c88f9SBruce Richardson #endif /* _IFPGA_RAWDEV_H_ */ 99