1473c88f9SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 2473c88f9SBruce Richardson * Copyright(c) 2010-2018 Intel Corporation 3473c88f9SBruce Richardson */ 4473c88f9SBruce Richardson 5473c88f9SBruce Richardson #ifndef _OSDEP_RTE_GENERIC_H 6473c88f9SBruce Richardson #define _OSDEP_RTE_GENERIC_H 7473c88f9SBruce Richardson 872b452c5SDmitry Kozlyuk #include <stdlib.h> 972b452c5SDmitry Kozlyuk 10473c88f9SBruce Richardson #include <rte_common.h> 11473c88f9SBruce Richardson #include <rte_cycles.h> 12473c88f9SBruce Richardson #include <rte_spinlock.h> 13473c88f9SBruce Richardson #include <rte_log.h> 14473c88f9SBruce Richardson #include <rte_io.h> 15473c88f9SBruce Richardson #include <rte_malloc.h> 16473c88f9SBruce Richardson #include <rte_byteorder.h> 17473c88f9SBruce Richardson #include <rte_memcpy.h> 18473c88f9SBruce Richardson 193178e37cSDavid Marchand extern int ifpga_rawdev_logtype; 203178e37cSDavid Marchand #define RTE_LOGTYPE_IFPGA_RAWDEV ifpga_rawdev_logtype 213178e37cSDavid Marchand 22*fd51012dSAndre Muezerie #define dev_printf(level, fmt, ...) \ 23*fd51012dSAndre Muezerie RTE_LOG(level, IFPGA_RAWDEV, "osdep_rte: " fmt, ## __VA_ARGS__) 24473c88f9SBruce Richardson 25473c88f9SBruce Richardson #define osdep_panic(...) rte_panic(...) 26473c88f9SBruce Richardson 27473c88f9SBruce Richardson #define opae_udelay(x) rte_delay_us(x) 28473c88f9SBruce Richardson 29473c88f9SBruce Richardson #define opae_readb(addr) rte_read8(addr) 30473c88f9SBruce Richardson #define opae_readw(addr) rte_read16(addr) 31473c88f9SBruce Richardson #define opae_readl(addr) rte_read32(addr) 32473c88f9SBruce Richardson #define opae_readq(addr) rte_read64(addr) 33473c88f9SBruce Richardson #define opae_writeb(value, addr) rte_write8(value, addr) 34473c88f9SBruce Richardson #define opae_writew(value, addr) rte_write16(value, addr) 35473c88f9SBruce Richardson #define opae_writel(value, addr) rte_write32(value, addr) 36473c88f9SBruce Richardson #define opae_writeq(value, addr) rte_write64(value, addr) 37473c88f9SBruce Richardson 38473c88f9SBruce Richardson #define opae_malloc(size) rte_malloc(NULL, size, 0) 39473c88f9SBruce Richardson #define opae_zmalloc(size) rte_zmalloc(NULL, size, 0) 40473c88f9SBruce Richardson #define opae_free(addr) rte_free(addr) 41473c88f9SBruce Richardson 42473c88f9SBruce Richardson #define ARRAY_SIZE(arr) RTE_DIM(arr) 43473c88f9SBruce Richardson 44473c88f9SBruce Richardson #define min(a, b) RTE_MIN(a, b) 45473c88f9SBruce Richardson #define max(a, b) RTE_MAX(a, b) 46473c88f9SBruce Richardson 4740277bb9SDavid Marchand #define min_t(type, x, y) RTE_MIN_T(x, y, type) 4840277bb9SDavid Marchand #define max_t(type, x, y) RTE_MAX_T(x, y, type) 49b74ee6c8SWei Huang 50473c88f9SBruce Richardson #define spinlock_t rte_spinlock_t 51473c88f9SBruce Richardson #define spinlock_init(x) rte_spinlock_init(x) 52473c88f9SBruce Richardson #define spinlock_lock(x) rte_spinlock_lock(x) 53473c88f9SBruce Richardson #define spinlock_unlock(x) rte_spinlock_unlock(x) 54473c88f9SBruce Richardson 55473c88f9SBruce Richardson #define cpu_to_be16(o) rte_cpu_to_be_16(o) 56473c88f9SBruce Richardson #define cpu_to_be32(o) rte_cpu_to_be_32(o) 57473c88f9SBruce Richardson #define cpu_to_be64(o) rte_cpu_to_be_64(o) 58473c88f9SBruce Richardson #define cpu_to_le16(o) rte_cpu_to_le_16(o) 59473c88f9SBruce Richardson #define cpu_to_le32(o) rte_cpu_to_le_32(o) 60473c88f9SBruce Richardson #define cpu_to_le64(o) rte_cpu_to_le_64(o) 61473c88f9SBruce Richardson 62473c88f9SBruce Richardson #define opae_memcpy(a, b, c) rte_memcpy((a), (b), (c)) 63473c88f9SBruce Richardson 64473c88f9SBruce Richardson static inline unsigned long msecs_to_timer_cycles(unsigned int m) 65473c88f9SBruce Richardson { 66473c88f9SBruce Richardson return rte_get_timer_hz() * (m / 1000); 67473c88f9SBruce Richardson } 68473c88f9SBruce Richardson 69473c88f9SBruce Richardson #endif 70