1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2019 Intel Corporation 3 */ 4 5 #ifndef _OPAE_SPI_H 6 #define _OPAE_SPI_H 7 8 #include "opae_osdep.h" 9 10 #define ALTERA_SPI_RXDATA 0 11 #define ALTERA_SPI_TXDATA 4 12 #define ALTERA_SPI_STATUS 8 13 #define ALTERA_SPI_CONTROL 12 14 #define ALTERA_SPI_SLAVE_SEL 20 15 16 #define ALTERA_SPI_STATUS_ROE_MSK 0x8 17 #define ALTERA_SPI_STATUS_TOE_MSK 0x10 18 #define ALTERA_SPI_STATUS_TMT_MSK 0x20 19 #define ALTERA_SPI_STATUS_TRDY_MSK 0x40 20 #define ALTERA_SPI_STATUS_RRDY_MSK 0x80 21 #define ALTERA_SPI_STATUS_E_MSK 0x100 22 23 #define ALTERA_SPI_CONTROL_IROE_MSK 0x8 24 #define ALTERA_SPI_CONTROL_ITOE_MSK 0x10 25 #define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40 26 #define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80 27 #define ALTERA_SPI_CONTROL_IE_MSK 0x100 28 #define ALTERA_SPI_CONTROL_SSO_MSK 0x400 29 30 #define SPI_CORE_PARAM 0x8 31 #define SPI_CTRL 0x10 32 #define CTRL_R BIT_ULL(9) 33 #define CTRL_W BIT_ULL(8) 34 #define CTRL_ADDR_MASK GENMASK_ULL(2, 0) 35 #define SPI_READ 0x18 36 #define READ_DATA_VALID BIT_ULL(32) 37 #define READ_DATA_MASK GENMASK_ULL(31, 0) 38 #define SPI_WRITE 0x20 39 #define WRITE_DATA_MASK GENMASK_ULL(31, 0) 40 41 #define SPI_MAX_RETRY 100000 42 43 #define TYPE_SPI 0 44 #define TYPE_NIOS_SPI 1 45 46 struct spi_core_param { 47 union { 48 u64 info; 49 struct { 50 u8 type:1; 51 u8 endian:1; 52 u8 data_width:6; 53 u8 num_chipselect:6; 54 u8 clock_polarity:1; 55 u8 clock_phase:1; 56 u8 stages:2; 57 u8 resvd:4; 58 u16 clock:10; 59 u16 peripheral_id:16; 60 u8 controller_type:1; 61 u16 resvd1:15; 62 }; 63 }; 64 }; 65 66 struct altera_spi_device { 67 u8 *regs; 68 struct spi_core_param spi_param; 69 int data_width; /* how many bytes for data width */ 70 int endian; 71 #define SPI_BIG_ENDIAN 0 72 #define SPI_LITTLE_ENDIAN 1 73 int num_chipselect; 74 unsigned char *rxbuf; 75 unsigned char *txbuf; 76 unsigned int len; 77 int (*reg_read)(struct altera_spi_device *dev, u32 reg, u32 *val); 78 int (*reg_write)(struct altera_spi_device *dev, u32 reg, 79 u32 value); 80 }; 81 82 #define HEADER_LEN 8 83 #define RESPONSE_LEN 4 84 #define SPI_TRANSACTION_MAX_LEN 1024 85 #define TRAN_SEND_MAX_LEN (SPI_TRANSACTION_MAX_LEN + HEADER_LEN) 86 #define TRAN_RESP_MAX_LEN SPI_TRANSACTION_MAX_LEN 87 #define PACKET_SEND_MAX_LEN (2*TRAN_SEND_MAX_LEN + 4) 88 #define PACKET_RESP_MAX_LEN (2*TRAN_RESP_MAX_LEN + 4) 89 #define BYTES_SEND_MAX_LEN (2*PACKET_SEND_MAX_LEN) 90 #define BYTES_RESP_MAX_LEN (2*PACKET_RESP_MAX_LEN) 91 92 struct spi_tran_buffer { 93 unsigned char tran_send[TRAN_SEND_MAX_LEN]; 94 unsigned char tran_resp[TRAN_RESP_MAX_LEN]; 95 unsigned char packet_send[PACKET_SEND_MAX_LEN]; 96 unsigned char packet_resp[PACKET_RESP_MAX_LEN]; 97 unsigned char bytes_send[BYTES_SEND_MAX_LEN]; 98 unsigned char bytes_resp[2*BYTES_RESP_MAX_LEN]; 99 }; 100 101 struct spi_transaction_dev { 102 struct altera_spi_device *dev; 103 int chipselect; 104 struct spi_tran_buffer *buffer; 105 }; 106 107 struct spi_tran_header { 108 u8 trans_type; 109 u8 reserve; 110 u16 size; 111 u32 addr; 112 }; 113 114 int spi_command(struct altera_spi_device *dev, unsigned int chip_select, 115 unsigned int wlen, void *wdata, unsigned int rlen, void *rdata); 116 void spi_cs_deactivate(struct altera_spi_device *dev); 117 void spi_cs_activate(struct altera_spi_device *dev, unsigned int chip_select); 118 struct altera_spi_device *altera_spi_alloc(void *base, int type); 119 void altera_spi_init(struct altera_spi_device *dev); 120 void altera_spi_release(struct altera_spi_device *dev); 121 int spi_transaction_read(struct spi_transaction_dev *dev, unsigned int addr, 122 unsigned int size, unsigned char *data); 123 int spi_transaction_write(struct spi_transaction_dev *dev, unsigned int addr, 124 unsigned int size, unsigned char *data); 125 struct spi_transaction_dev *spi_transaction_init(struct altera_spi_device *dev, 126 int chipselect); 127 void spi_transaction_remove(struct spi_transaction_dev *dev); 128 int spi_reg_write(struct altera_spi_device *dev, u32 reg, 129 u32 value); 130 int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val); 131 132 #define NIOS_SPI_PARAM 0x8 133 #define CONTROL_TYPE BIT_ULL(48) 134 #define PERI_ID GENMASK_ULL(47, 32) 135 #define SPI_CLK GENMASK_ULL(31, 22) 136 #define SYNC_STAGES GENMASK_ULL(17, 16) 137 #define CLOCK_PHASE BIT_ULL(15) 138 #define CLOCK_POLARITY BIT_ULL(14) 139 #define NUM_SELECT GENMASK_ULL(13, 8) 140 #define DATA_WIDTH GENMASK_ULL(7, 2) 141 #define SHIFT_DIRECTION BIT_ULL(1) 142 #define SPI_TYPE BIT_ULL(0) 143 #define NIOS_SPI_CTRL 0x10 144 #define NIOS_SPI_RD (0x1ULL << 62) 145 #define NIOS_SPI_WR (0x2ULL << 62) 146 #define NIOS_SPI_COMMAND GENMASK_ULL(63, 62) 147 #define NIOS_SPI_ADDR GENMASK_ULL(44, 32) 148 #define NIOS_SPI_WRITE_DATA GENMASK_ULL(31, 0) 149 #define NIOS_SPI_STAT 0x18 150 #define NIOS_SPI_VALID BIT_ULL(32) 151 #define NIOS_SPI_READ_DATA GENMASK_ULL(31, 0) 152 #define NIOS_SPI_INIT_DONE 0x1000 153 154 #define NIOS_SPI_INIT_DONE 0x1000 155 #define NIOS_SPI_INIT_STS0 0x1020 156 #define NIOS_SPI_INIT_STS1 0x1024 157 #define PKVL_STATUS_RESET 0 158 #define PKVL_10G_MODE 1 159 #define PKVL_25G_MODE 2 160 #endif 161