xref: /dpdk/drivers/raw/ifpga/base/opae_hw_api.h (revision 68a03efeed657e6e05f281479b33b51102797e15)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2018 Intel Corporation
3  */
4 
5 #ifndef _OPAE_HW_API_H_
6 #define _OPAE_HW_API_H_
7 
8 #include <stdint.h>
9 #include <stdlib.h>
10 #include <stdio.h>
11 #include <sys/queue.h>
12 
13 #include "opae_osdep.h"
14 #include "opae_intel_max10.h"
15 #include "opae_eth_group.h"
16 #include "ifpga_defines.h"
17 
18 #ifndef PCI_MAX_RESOURCE
19 #define PCI_MAX_RESOURCE 6
20 #endif
21 
22 struct opae_adapter;
23 
24 enum opae_adapter_type {
25 	OPAE_FPGA_PCI,
26 	OPAE_FPGA_NET,
27 };
28 
29 /* OPAE Manager Data Structure */
30 struct opae_manager_ops;
31 struct opae_manager_networking_ops;
32 
33 /*
34  * opae_manager has pointer to its parent adapter, as it could be able to manage
35  * all components on this FPGA device (adapter). If not the case, don't set this
36  * adapter, which limit opae_manager ops to manager itself.
37  */
38 struct opae_manager {
39 	const char *name;
40 	struct opae_adapter *adapter;
41 	struct opae_manager_ops *ops;
42 	struct opae_manager_networking_ops *network_ops;
43 	struct opae_sensor_list *sensor_list;
44 	void *data;
45 };
46 
47 /* FIXME: add more management ops, e.g power/thermal and etc */
48 struct opae_manager_ops {
49 	int (*flash)(struct opae_manager *mgr, int id, const char *buffer,
50 		     u32 size, u64 *status);
51 	int (*get_eth_group_region_info)(struct opae_manager *mgr,
52 			struct opae_eth_group_region_info *info);
53 	int (*get_sensor_value)(struct opae_manager *mgr,
54 			struct opae_sensor_info *sensor,
55 			unsigned int *value);
56 	int (*get_board_info)(struct opae_manager *mgr,
57 			struct opae_board_info **info);
58 	int (*get_uuid)(struct opae_manager *mgr, struct uuid *uuid);
59 	int (*update_flash)(struct opae_manager *mgr, const char *image,
60 			u64 *status);
61 	int (*stop_flash_update)(struct opae_manager *mgr, int force);
62 	int (*reload)(struct opae_manager *mgr, int type, int page);
63 };
64 
65 /* networking management ops in FME */
66 struct opae_manager_networking_ops {
67 	int (*read_mac_rom)(struct opae_manager *mgr, int offset, void *buf,
68 			int size);
69 	int (*write_mac_rom)(struct opae_manager *mgr, int offset, void *buf,
70 			int size);
71 	int (*get_eth_group_nums)(struct opae_manager *mgr);
72 	int (*get_eth_group_info)(struct opae_manager *mgr,
73 			u8 group_id, struct opae_eth_group_info *info);
74 	int (*eth_group_reg_read)(struct opae_manager *mgr, u8 group_id,
75 			u8 type, u8 index, u16 addr, u32 *data);
76 	int (*eth_group_reg_write)(struct opae_manager *mgr, u8 group_id,
77 			u8 type, u8 index, u16 addr, u32 data);
78 	int (*get_retimer_info)(struct opae_manager *mgr,
79 			struct opae_retimer_info *info);
80 	int (*get_retimer_status)(struct opae_manager *mgr,
81 			struct opae_retimer_status *status);
82 };
83 
84 #define opae_mgr_for_each_sensor(mgr, sensor) \
85 	TAILQ_FOREACH(sensor, mgr->sensor_list, node)
86 
87 /* OPAE Manager APIs */
88 struct opae_manager *
89 opae_manager_alloc(const char *name, struct opae_manager_ops *ops,
90 		struct opae_manager_networking_ops *network_ops, void *data);
91 #define opae_manager_free(mgr) opae_free(mgr)
92 int opae_manager_flash(struct opae_manager *mgr, int acc_id, const char *buf,
93 		       u32 size, u64 *status);
94 int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,
95 		u8 group_id, struct opae_eth_group_region_info *info);
96 struct opae_sensor_info *opae_mgr_get_sensor_by_name(struct opae_manager *mgr,
97 		const char *name);
98 struct opae_sensor_info *opae_mgr_get_sensor_by_id(struct opae_manager *mgr,
99 		unsigned int id);
100 int opae_mgr_get_sensor_value_by_name(struct opae_manager *mgr,
101 		const char *name, unsigned int *value);
102 int opae_mgr_get_sensor_value_by_id(struct opae_manager *mgr,
103 		unsigned int id, unsigned int *value);
104 int opae_mgr_get_sensor_value(struct opae_manager *mgr,
105 		struct opae_sensor_info *sensor,
106 		unsigned int *value);
107 
108 /* OPAE Bridge Data Structure */
109 struct opae_bridge_ops;
110 
111 /*
112  * opae_bridge only has pointer to its downstream accelerator.
113  */
114 struct opae_bridge {
115 	const char *name;
116 	int id;
117 	struct opae_accelerator *acc;
118 	struct opae_bridge_ops *ops;
119 	void *data;
120 };
121 
122 struct opae_bridge_ops {
123 	int (*reset)(struct opae_bridge *br);
124 };
125 
126 /* OPAE Bridge APIs */
127 struct opae_bridge *
128 opae_bridge_alloc(const char *name, struct opae_bridge_ops *ops, void *data);
129 int opae_bridge_reset(struct opae_bridge *br);
130 #define opae_bridge_free(br) opae_free(br)
131 
132 /* OPAE Acceleraotr Data Structure */
133 struct opae_accelerator_ops;
134 
135 /*
136  * opae_accelerator has pointer to its upstream bridge(port).
137  * In some cases, if we allow same user to do PR on its own accelerator, then
138  * set the manager pointer during the enumeration. But in other cases, the PR
139  * functions only could be done via manager in another module / thread / service
140  * / application for better protection.
141  */
142 struct opae_accelerator {
143 	TAILQ_ENTRY(opae_accelerator) node;
144 	const char *name;
145 	int index;
146 	struct opae_bridge *br;
147 	struct opae_manager *mgr;
148 	struct opae_accelerator_ops *ops;
149 	void *data;
150 };
151 
152 struct opae_acc_info {
153 	unsigned int num_regions;
154 	unsigned int num_irqs;
155 };
156 
157 struct opae_acc_region_info {
158 	u32 flags;
159 #define ACC_REGION_READ		(1 << 0)
160 #define ACC_REGION_WRITE	(1 << 1)
161 #define ACC_REGION_MMIO		(1 << 2)
162 	u32 index;
163 	u64 phys_addr;
164 	u64 len;
165 	u8 *addr;
166 };
167 
168 struct opae_accelerator_ops {
169 	int (*read)(struct opae_accelerator *acc, unsigned int region_idx,
170 		    u64 offset, unsigned int byte, void *data);
171 	int (*write)(struct opae_accelerator *acc, unsigned int region_idx,
172 		     u64 offset, unsigned int byte, void *data);
173 	int (*get_info)(struct opae_accelerator *acc,
174 			struct opae_acc_info *info);
175 	int (*get_region_info)(struct opae_accelerator *acc,
176 			       struct opae_acc_region_info *info);
177 	int (*set_irq)(struct opae_accelerator *acc,
178 		       u32 start, u32 count, s32 evtfds[]);
179 	int (*get_uuid)(struct opae_accelerator *acc,
180 			struct uuid *uuid);
181 };
182 
183 /* OPAE accelerator APIs */
184 struct opae_accelerator *
185 opae_accelerator_alloc(const char *name, struct opae_accelerator_ops *ops,
186 		       void *data);
187 #define opae_accelerator_free(acc) opae_free(acc)
188 int opae_acc_get_info(struct opae_accelerator *acc, struct opae_acc_info *info);
189 int opae_acc_get_region_info(struct opae_accelerator *acc,
190 			     struct opae_acc_region_info *info);
191 int opae_acc_set_irq(struct opae_accelerator *acc,
192 		     u32 start, u32 count, s32 evtfds[]);
193 int opae_acc_get_uuid(struct opae_accelerator *acc,
194 		      struct uuid *uuid);
195 
196 static inline struct opae_bridge *
197 opae_acc_get_br(struct opae_accelerator *acc)
198 {
199 	return acc ? acc->br : NULL;
200 }
201 
202 static inline struct opae_manager *
203 opae_acc_get_mgr(struct opae_accelerator *acc)
204 {
205 	return acc ? acc->mgr : NULL;
206 }
207 
208 int opae_acc_reg_read(struct opae_accelerator *acc, unsigned int region_idx,
209 		      u64 offset, unsigned int byte, void *data);
210 int opae_acc_reg_write(struct opae_accelerator *acc, unsigned int region_idx,
211 		       u64 offset, unsigned int byte, void *data);
212 
213 #define opae_acc_reg_read64(acc, region, offset, data) \
214 	opae_acc_reg_read(acc, region, offset, 8, data)
215 #define opae_acc_reg_write64(acc, region, offset, data) \
216 	opae_acc_reg_write(acc, region, offset, 8, data)
217 #define opae_acc_reg_read32(acc, region, offset, data) \
218 	opae_acc_reg_read(acc, region, offset, 4, data)
219 #define opae_acc_reg_write32(acc, region, offset, data) \
220 	opae_acc_reg_write(acc, region, offset, 4, data)
221 #define opae_acc_reg_read16(acc, region, offset, data) \
222 	opae_acc_reg_read(acc, region, offset, 2, data)
223 #define opae_acc_reg_write16(acc, region, offset, data) \
224 	opae_acc_reg_write(acc, region, offset, 2, data)
225 #define opae_acc_reg_read8(acc, region, offset, data) \
226 	opae_acc_reg_read(acc, region, offset, 1, data)
227 #define opae_acc_reg_write8(acc, region, offset, data) \
228 	opae_acc_reg_write(acc, region, offset, 1, data)
229 
230 /*for data stream read/write*/
231 int opae_acc_data_read(struct opae_accelerator *acc, unsigned int flags,
232 		       u64 offset, unsigned int byte, void *data);
233 int opae_acc_data_write(struct opae_accelerator *acc, unsigned int flags,
234 			u64 offset, unsigned int byte, void *data);
235 
236 /* OPAE Adapter Data Structure */
237 struct opae_adapter_data {
238 	enum opae_adapter_type type;
239 };
240 
241 struct opae_reg_region {
242 	u64 phys_addr;
243 	u64 len;
244 	u8 *addr;
245 };
246 
247 struct opae_adapter_data_pci {
248 	enum opae_adapter_type type;
249 	u16 device_id;
250 	u16 vendor_id;
251 	u16 bus; /*Device bus for PCI */
252 	u16 devid; /* Device ID */
253 	u16 function; /* Device function */
254 	struct opae_reg_region region[PCI_MAX_RESOURCE];
255 	int vfio_dev_fd;  /* VFIO device file descriptor */
256 };
257 
258 /* FIXME: OPAE_FPGA_NET type */
259 struct opae_adapter_data_net {
260 	enum opae_adapter_type type;
261 };
262 
263 struct opae_adapter_ops {
264 	int (*enumerate)(struct opae_adapter *adapter);
265 	void (*destroy)(struct opae_adapter *adapter);
266 };
267 
268 TAILQ_HEAD(opae_accelerator_list, opae_accelerator);
269 
270 #define opae_adapter_for_each_acc(adatper, acc) \
271 	TAILQ_FOREACH(acc, &adapter->acc_list, node)
272 
273 #define SHM_PREFIX     "/IFPGA:"
274 #define SHM_BLK_SIZE   0x2000
275 
276 typedef struct {
277 	union {
278 		u8 byte[SHM_BLK_SIZE];
279 		struct {
280 			pthread_mutex_t spi_mutex;
281 			pthread_mutex_t i2c_mutex;
282 			u32 ref_cnt;    /* reference count of shared memory */
283 			u32 dtb_size;   /* actual length of DTB data in byte */
284 			u32 rsu_ctrl;   /* used to control rsu */
285 			u32 rsu_stat;   /* used to report status for rsu */
286 		};
287 	};
288 	u8 dtb[SHM_BLK_SIZE];   /* DTB data */
289 } opae_share_data;
290 
291 typedef struct  {
292 	int id;       /* shared memory id returned by shm_open */
293 	u32 size;     /* size of shared memory in byte */
294 	void *ptr;    /* start address of shared memory */
295 } opae_share_memory;
296 
297 struct opae_adapter {
298 	const char *name;
299 	struct opae_manager *mgr;
300 	struct opae_accelerator_list acc_list;
301 	struct opae_adapter_ops *ops;
302 	void *data;
303 	pthread_mutex_t *lock;   /* multi-process mutex for IFPGA */
304 	opae_share_memory shm;
305 };
306 
307 /* OPAE Adapter APIs */
308 void *opae_adapter_data_alloc(enum opae_adapter_type type);
309 #define opae_adapter_data_free(data) opae_free(data)
310 
311 int opae_adapter_init(struct opae_adapter *adapter,
312 		const char *name, void *data);
313 #define opae_adapter_free(adapter) opae_free(adapter)
314 int opae_adapter_lock(struct opae_adapter *adapter, int timeout);
315 int opae_adapter_unlock(struct opae_adapter *adapter);
316 int opae_adapter_enumerate(struct opae_adapter *adapter);
317 void opae_adapter_destroy(struct opae_adapter *adapter);
318 static inline struct opae_manager *
319 opae_adapter_get_mgr(struct opae_adapter *adapter)
320 {
321 	return adapter ? adapter->mgr : NULL;
322 }
323 
324 struct opae_accelerator *
325 opae_adapter_get_acc(struct opae_adapter *adapter, int acc_id);
326 
327 static inline void opae_adapter_add_acc(struct opae_adapter *adapter,
328 					struct opae_accelerator *acc)
329 {
330 	TAILQ_INSERT_TAIL(&adapter->acc_list, acc, node);
331 }
332 
333 static inline void opae_adapter_remove_acc(struct opae_adapter *adapter,
334 					   struct opae_accelerator *acc)
335 {
336 	TAILQ_REMOVE(&adapter->acc_list, acc, node);
337 }
338 
339 /* OPAE vBNG network datastruct */
340 #define OPAE_ETHER_ADDR_LEN 6
341 
342 struct opae_ether_addr {
343 	unsigned char addr_bytes[OPAE_ETHER_ADDR_LEN];
344 } __rte_packed;
345 
346 /* OPAE vBNG network API*/
347 int opae_manager_read_mac_rom(struct opae_manager *mgr, int port,
348 		struct opae_ether_addr *addr);
349 int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,
350 		struct opae_ether_addr *addr);
351 int opae_manager_get_retimer_info(struct opae_manager *mgr,
352 		struct opae_retimer_info *info);
353 int opae_manager_get_retimer_status(struct opae_manager *mgr,
354 		struct opae_retimer_status *status);
355 int opae_manager_get_eth_group_nums(struct opae_manager *mgr);
356 int opae_manager_get_eth_group_info(struct opae_manager *mgr,
357 		u8 group_id, struct opae_eth_group_info *info);
358 int opae_manager_eth_group_write_reg(struct opae_manager *mgr, u8 group_id,
359 		u8 type, u8 index, u16 addr, u32 data);
360 int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,
361 		u8 type, u8 index, u16 addr, u32 *data);
362 int opae_mgr_get_board_info(struct opae_manager *mgr,
363 		struct opae_board_info **info);
364 int opae_mgr_get_uuid(struct opae_manager *mgr, struct uuid *uuid);
365 int opae_mgr_update_flash(struct opae_manager *mgr, const char *image,
366 		uint64_t *status);
367 int opae_mgr_stop_flash_update(struct opae_manager *mgr, int force);
368 int opae_mgr_reload(struct opae_manager *mgr, int type, int page);
369 #endif /* _OPAE_HW_API_H_*/
370