1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2020 Intel Corporation 3 */ 4 5 #ifndef _IFPGA_FME_RSU_H_ 6 #define _IFPGA_FME_RSU_H_ 7 8 9 #include "ifpga_hw.h" 10 11 #define IFPGA_N3000_VID 0x8086 12 #define IFPGA_N3000_DID 0x0b30 13 14 #define IFPGA_BOOT_TYPE_FPGA 0 15 #define IFPGA_BOOT_TYPE_BMC 1 16 17 #define IFPGA_BOOT_PAGE_FACTORY 0 18 #define IFPGA_BOOT_PAGE_USER 1 19 20 #define IFPGA_RSU_DATA_BLK_SIZE 32768 21 #define IFPGA_RSU_START_RETRY 120 22 #define IFPGA_RSU_WRITE_RETRY 10 23 #define IFPGA_RSU_CANCEL_RETRY 30 24 25 #define IFPGA_N3000_COPY_SPEED 42700 26 27 /* status */ 28 #define IFPGA_RSU_IDLE 0 29 #define IFPGA_RSU_PREPARE 1 30 #define IFPGA_RSU_READY 2 31 #define IFPGA_RSU_COPYING 3 32 #define IFPGA_RSU_REBOOT 4 33 34 #define IFPGA_RSU_GET_STAT(v) (((v) >> 16) & 0xffff) 35 #define IFPGA_RSU_GET_PROG(v) ((v) & 0xffff) 36 #define IFPGA_RSU_STATUS(s, p) ((((s) << 16) & 0xffff0000) | ((p) & 0xffff)) 37 38 /* control */ 39 #define IFPGA_RSU_ABORT 1 40 41 #define IFPGA_DUAL_CFG_CTRL0 0x200020 42 #define IFPGA_DUAL_CFG_CTRL1 0x200024 43 44 #define IFPGA_SEC_START_INTERVAL_MS 100 45 #define IFPGA_SEC_START_TIMEOUT_MS 20000 46 #define IFPGA_NIOS_HANDSHAKE_INTERVAL_MS 100 47 #define IFPGA_NIOS_HANDSHAKE_TIMEOUT_MS 5000 48 49 #define IFPGA_RSU_ERR_HW_ERROR -1 50 #define IFPGA_RSU_ERR_TIMEOUT -2 51 #define IFPGA_RSU_ERR_CANCELED -3 52 #define IFPGA_RSU_ERR_BUSY -4 53 #define IFPGA_RSU_ERR_INVALID_SIZE -5 54 #define IFPGA_RSU_ERR_RW_ERROR -6 55 #define IFPGA_RSU_ERR_WEAROUT -7 56 #define IFPGA_RSU_ERR_FILE_READ -8 57 58 struct ifpga_sec_mgr; 59 60 struct ifpga_sec_ops { 61 int (*prepare)(struct ifpga_sec_mgr *smgr); 62 int (*write_blk)(struct ifpga_sec_mgr *smgr, char *buf, uint32_t offset, 63 uint32_t size); 64 int (*write_done)(struct ifpga_sec_mgr *smgr); 65 int (*check_complete)(struct ifpga_sec_mgr *smgr); 66 int (*reload)(struct ifpga_sec_mgr *smgr, int type, int page); 67 int (*cancel)(struct ifpga_sec_mgr *smgr); 68 void (*cleanup)(struct ifpga_sec_mgr *smgr); 69 u64 (*get_hw_errinfo)(struct ifpga_sec_mgr *smgr); 70 }; 71 72 struct ifpga_sec_mgr { 73 struct ifpga_fme_hw *fme; 74 struct intel_max10_device *max10_dev; 75 unsigned int rsu_length; 76 /* number of bytes that copied from staging area to working area 77 * in one second, which is calculated by experiment 78 */ 79 unsigned int copy_speed; 80 unsigned int *rsu_control; 81 unsigned int *rsu_status; 82 const struct ifpga_sec_ops *ops; 83 }; 84 85 int init_sec_mgr(struct ifpga_fme_hw *fme); 86 void release_sec_mgr(struct ifpga_fme_hw *fme); 87 int fpga_update_flash(struct ifpga_fme_hw *fme, const char *image, 88 uint64_t *status); 89 int fpga_stop_flash_update(struct ifpga_fme_hw *fme, int force); 90 int fpga_reload(struct ifpga_fme_hw *fme, int type, int page); 91 92 93 #endif /* _IFPGA_FME_RSU_H_ */ 94