xref: /dpdk/drivers/raw/ifpga/base/ifpga_compat.h (revision 68a03efeed657e6e05f281479b33b51102797e15)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2018 Intel Corporation
3  */
4 
5 #ifndef _IFPGA_COMPAT_H_
6 #define _IFPGA_COMPAT_H_
7 
8 #include "opae_osdep.h"
9 
10 #undef container_of
11 #define container_of(ptr, type, member) ({ \
12 		typeof(((type *)0)->member)(*__mptr) = (ptr); \
13 		(type *)((char *)__mptr - offsetof(type, member)); })
14 
15 #define IFPGA_PAGE_SHIFT       12
16 #define IFPGA_PAGE_SIZE        (1 << IFPGA_PAGE_SHIFT)
17 #define IFPGA_PAGE_MASK        (~(IFPGA_PAGE_SIZE - 1))
18 #define IFPGA_PAGE_ALIGN(addr) (((addr) + IFPGA_PAGE_SIZE - 1)\
19 		& IFPGA_PAGE_MASK)
20 #define IFPGA_ALIGN(x, a)  (((x) + (a) - 1) & ~((a) - 1))
21 
22 #define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
23 #define PAGE_ALIGNED(addr) IS_ALIGNED((unsigned long)(addr), IFPGA_PAGE_SIZE)
24 
25 #define readl(addr) opae_readl(addr)
26 #define readq(addr) opae_readq(addr)
27 #define writel(value, addr) opae_writel(value, addr)
28 #define writeq(value, addr) opae_writeq(value, addr)
29 
30 #define malloc(size) opae_malloc(size)
31 #define zmalloc(size) opae_zmalloc(size)
32 #define free(size) opae_free(size)
33 
34 /*
35  * Wait register's _field to be changed to the given value (_expect's _field)
36  * by polling with given interval and timeout.
37  */
38 #define fpga_wait_register_field(_field, _expect, _reg_addr, _timeout, _invl)\
39 ({									     \
40 	int wait = 0;							     \
41 	int ret = -ETIMEDOUT;						     \
42 	typeof(_expect) value;						     \
43 	for (; wait <= _timeout; wait += _invl) {			     \
44 		value.csr = readq(_reg_addr);				     \
45 		if (_expect._field == value._field) {			     \
46 			ret = 0;					     \
47 			break;						     \
48 		}							     \
49 		udelay(_invl);						     \
50 	}								     \
51 	ret;								     \
52 })
53 
54 #define __maybe_unused __rte_unused
55 
56 #define UNUSED(x)	(void)(x)
57 
58 #endif /* _IFPGA_COMPAT_H_ */
59