1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 60 DEV_RX_OFFLOAD_RSS_HASH) 61 62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 65 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 67 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 74 int wait_to_complete); 75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 76 int wait_to_complete); 77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 79 struct rte_eth_stats *stats); 80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 82 struct rte_eth_xstat_name *xstats, 83 unsigned int n); 84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 85 struct rte_eth_xstat *xstats, unsigned int n); 86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 87 struct rte_eth_dev_info *dev_info); 88 static const uint32_t * 89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 90 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 91 uint16_t vid, int on); 92 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 93 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 94 struct rte_ether_addr *mac_addr); 95 static void vmxnet3_interrupt_handler(void *param); 96 97 int vmxnet3_logtype_init; 98 int vmxnet3_logtype_driver; 99 100 /* 101 * The set of PCI devices this driver supports 102 */ 103 #define VMWARE_PCI_VENDOR_ID 0x15AD 104 #define VMWARE_DEV_ID_VMXNET3 0x07B0 105 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 106 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 107 { .vendor_id = 0, /* sentinel */ }, 108 }; 109 110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 111 .dev_configure = vmxnet3_dev_configure, 112 .dev_start = vmxnet3_dev_start, 113 .dev_stop = vmxnet3_dev_stop, 114 .dev_close = vmxnet3_dev_close, 115 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 116 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 117 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 118 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 119 .link_update = vmxnet3_dev_link_update, 120 .stats_get = vmxnet3_dev_stats_get, 121 .xstats_get_names = vmxnet3_dev_xstats_get_names, 122 .xstats_get = vmxnet3_dev_xstats_get, 123 .stats_reset = vmxnet3_dev_stats_reset, 124 .mac_addr_set = vmxnet3_mac_addr_set, 125 .dev_infos_get = vmxnet3_dev_info_get, 126 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 127 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 128 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 129 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 130 .rx_queue_release = vmxnet3_dev_rx_queue_release, 131 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 132 .tx_queue_release = vmxnet3_dev_tx_queue_release, 133 }; 134 135 struct vmxnet3_xstats_name_off { 136 char name[RTE_ETH_XSTATS_NAME_SIZE]; 137 unsigned int offset; 138 }; 139 140 /* tx_qX_ is prepended to the name string here */ 141 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 142 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 143 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 144 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 145 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 146 }; 147 148 /* rx_qX_ is prepended to the name string here */ 149 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 150 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 151 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 152 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 153 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 154 }; 155 156 static const struct rte_memzone * 157 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 158 const char *post_string, int socket_id, 159 uint16_t align, bool reuse) 160 { 161 char z_name[RTE_MEMZONE_NAMESIZE]; 162 const struct rte_memzone *mz; 163 164 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 165 dev->data->port_id, post_string); 166 167 mz = rte_memzone_lookup(z_name); 168 if (!reuse) { 169 if (mz) 170 rte_memzone_free(mz); 171 return rte_memzone_reserve_aligned(z_name, size, socket_id, 172 RTE_MEMZONE_IOVA_CONTIG, align); 173 } 174 175 if (mz) 176 return mz; 177 178 return rte_memzone_reserve_aligned(z_name, size, socket_id, 179 RTE_MEMZONE_IOVA_CONTIG, align); 180 } 181 182 /* 183 * This function is based on vmxnet3_disable_intr() 184 */ 185 static void 186 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 187 { 188 int i; 189 190 PMD_INIT_FUNC_TRACE(); 191 192 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 193 for (i = 0; i < hw->num_intrs; i++) 194 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 195 } 196 197 static void 198 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 199 { 200 int i; 201 202 PMD_INIT_FUNC_TRACE(); 203 204 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 205 for (i = 0; i < hw->num_intrs; i++) 206 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 207 } 208 209 /* 210 * Gets tx data ring descriptor size. 211 */ 212 static uint16_t 213 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 214 { 215 uint16 txdata_desc_size; 216 217 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 218 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 219 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 220 221 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 222 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 223 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 224 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 225 } 226 227 /* 228 * It returns 0 on success. 229 */ 230 static int 231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 232 { 233 struct rte_pci_device *pci_dev; 234 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 235 uint32_t mac_hi, mac_lo, ver; 236 struct rte_eth_link link; 237 238 PMD_INIT_FUNC_TRACE(); 239 240 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 241 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 242 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 243 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 244 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 245 246 /* 247 * for secondary processes, we don't initialize any further as primary 248 * has already done this work. 249 */ 250 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 251 return 0; 252 253 rte_eth_copy_pci_info(eth_dev, pci_dev); 254 255 /* Vendor and Device ID need to be set before init of shared code */ 256 hw->device_id = pci_dev->id.device_id; 257 hw->vendor_id = pci_dev->id.vendor_id; 258 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 259 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 260 261 hw->num_rx_queues = 1; 262 hw->num_tx_queues = 1; 263 hw->bufs_per_pkt = 1; 264 265 /* Check h/w version compatibility with driver. */ 266 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 267 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 268 269 if (ver & (1 << VMXNET3_REV_4)) { 270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 271 1 << VMXNET3_REV_4); 272 hw->version = VMXNET3_REV_4 + 1; 273 } else if (ver & (1 << VMXNET3_REV_3)) { 274 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 275 1 << VMXNET3_REV_3); 276 hw->version = VMXNET3_REV_3 + 1; 277 } else if (ver & (1 << VMXNET3_REV_2)) { 278 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 279 1 << VMXNET3_REV_2); 280 hw->version = VMXNET3_REV_2 + 1; 281 } else if (ver & (1 << VMXNET3_REV_1)) { 282 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 283 1 << VMXNET3_REV_1); 284 hw->version = VMXNET3_REV_1 + 1; 285 } else { 286 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 287 return -EIO; 288 } 289 290 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 291 292 /* Check UPT version compatibility with driver. */ 293 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 294 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 295 if (ver & 0x1) 296 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 297 else { 298 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 299 return -EIO; 300 } 301 302 /* Getting MAC Address */ 303 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 304 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 305 memcpy(hw->perm_addr, &mac_lo, 4); 306 memcpy(hw->perm_addr + 4, &mac_hi, 2); 307 308 /* Allocate memory for storing MAC addresses */ 309 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 310 VMXNET3_MAX_MAC_ADDRS, 0); 311 if (eth_dev->data->mac_addrs == NULL) { 312 PMD_INIT_LOG(ERR, 313 "Failed to allocate %d bytes needed to store MAC addresses", 314 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 315 return -ENOMEM; 316 } 317 /* Copy the permanent MAC address */ 318 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 319 ð_dev->data->mac_addrs[0]); 320 321 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 322 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 323 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 324 325 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 326 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 327 328 /* Put device in Quiesce Mode */ 329 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 330 331 /* allow untagged pkts */ 332 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 333 334 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 335 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 336 337 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 338 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 339 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 340 hw->rxdata_desc_size); 341 342 /* clear shadow stats */ 343 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 344 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 345 346 /* clear snapshot stats */ 347 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 348 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 349 350 /* set the initial link status */ 351 memset(&link, 0, sizeof(link)); 352 link.link_duplex = ETH_LINK_FULL_DUPLEX; 353 link.link_speed = ETH_SPEED_NUM_10G; 354 link.link_autoneg = ETH_LINK_FIXED; 355 rte_eth_linkstatus_set(eth_dev, &link); 356 357 return 0; 358 } 359 360 static int 361 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 362 { 363 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 364 365 PMD_INIT_FUNC_TRACE(); 366 367 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 368 return 0; 369 370 if (hw->adapter_stopped == 0) { 371 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 372 return -EBUSY; 373 } 374 375 eth_dev->dev_ops = NULL; 376 eth_dev->rx_pkt_burst = NULL; 377 eth_dev->tx_pkt_burst = NULL; 378 eth_dev->tx_pkt_prepare = NULL; 379 380 return 0; 381 } 382 383 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 384 struct rte_pci_device *pci_dev) 385 { 386 return rte_eth_dev_pci_generic_probe(pci_dev, 387 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 388 } 389 390 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 391 { 392 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 393 } 394 395 static struct rte_pci_driver rte_vmxnet3_pmd = { 396 .id_table = pci_id_vmxnet3_map, 397 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 398 .probe = eth_vmxnet3_pci_probe, 399 .remove = eth_vmxnet3_pci_remove, 400 }; 401 402 static int 403 vmxnet3_dev_configure(struct rte_eth_dev *dev) 404 { 405 const struct rte_memzone *mz; 406 struct vmxnet3_hw *hw = dev->data->dev_private; 407 size_t size; 408 409 PMD_INIT_FUNC_TRACE(); 410 411 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 412 413 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 414 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 415 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 416 return -EINVAL; 417 } 418 419 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 420 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 421 return -EINVAL; 422 } 423 424 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 425 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 426 427 if (size > UINT16_MAX) 428 return -EINVAL; 429 430 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 431 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 432 433 /* 434 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 435 * on current socket 436 */ 437 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 438 "shared", rte_socket_id(), 8, 1); 439 440 if (mz == NULL) { 441 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 442 return -ENOMEM; 443 } 444 memset(mz->addr, 0, mz->len); 445 446 hw->shared = mz->addr; 447 hw->sharedPA = mz->iova; 448 449 /* 450 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 451 * on current socket. 452 * 453 * We cannot reuse this memzone from previous allocation as its size 454 * depends on the number of tx and rx queues, which could be different 455 * from one config to another. 456 */ 457 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 458 VMXNET3_QUEUE_DESC_ALIGN, 0); 459 if (mz == NULL) { 460 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 461 return -ENOMEM; 462 } 463 memset(mz->addr, 0, mz->len); 464 465 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 466 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 467 468 hw->queueDescPA = mz->iova; 469 hw->queue_desc_len = (uint16_t)size; 470 471 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 472 /* Allocate memory structure for UPT1_RSSConf and configure */ 473 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 474 "rss_conf", rte_socket_id(), 475 RTE_CACHE_LINE_SIZE, 1); 476 if (mz == NULL) { 477 PMD_INIT_LOG(ERR, 478 "ERROR: Creating rss_conf structure zone"); 479 return -ENOMEM; 480 } 481 memset(mz->addr, 0, mz->len); 482 483 hw->rss_conf = mz->addr; 484 hw->rss_confPA = mz->iova; 485 } 486 487 return 0; 488 } 489 490 static void 491 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 492 { 493 uint32_t val; 494 495 PMD_INIT_LOG(DEBUG, 496 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 497 addr[0], addr[1], addr[2], 498 addr[3], addr[4], addr[5]); 499 500 memcpy(&val, addr, 4); 501 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 502 503 memcpy(&val, addr + 4, 2); 504 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 505 } 506 507 static int 508 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 509 { 510 struct vmxnet3_hw *hw = dev->data->dev_private; 511 Vmxnet3_DriverShared *shared = hw->shared; 512 Vmxnet3_CmdInfo *cmdInfo; 513 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 514 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 515 uint32_t num, i, j, size; 516 517 if (hw->memRegsPA == 0) { 518 const struct rte_memzone *mz; 519 520 size = sizeof(Vmxnet3_MemRegs) + 521 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 522 sizeof(Vmxnet3_MemoryRegion); 523 524 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 525 1); 526 if (mz == NULL) { 527 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 528 return -ENOMEM; 529 } 530 memset(mz->addr, 0, mz->len); 531 hw->memRegs = mz->addr; 532 hw->memRegsPA = mz->iova; 533 } 534 535 num = hw->num_rx_queues; 536 537 for (i = 0; i < num; i++) { 538 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 539 540 mp[i] = rxq->mp; 541 index[i] = 1 << i; 542 } 543 544 /* 545 * The same mempool could be used by multiple queues. In such a case, 546 * remove duplicate mempool entries. Only one entry is kept with 547 * bitmask indicating queues that are using this mempool. 548 */ 549 for (i = 1; i < num; i++) { 550 for (j = 0; j < i; j++) { 551 if (mp[i] == mp[j]) { 552 mp[i] = NULL; 553 index[j] |= 1 << i; 554 break; 555 } 556 } 557 } 558 559 j = 0; 560 for (i = 0; i < num; i++) { 561 if (mp[i] == NULL) 562 continue; 563 564 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 565 566 mr->startPA = 567 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 568 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 569 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 570 mr->txQueueBits = index[i]; 571 mr->rxQueueBits = index[i]; 572 573 PMD_INIT_LOG(INFO, 574 "index: %u startPA: %" PRIu64 " length: %u, " 575 "rxBits: %x", 576 j, mr->startPA, mr->length, mr->rxQueueBits); 577 j++; 578 } 579 hw->memRegs->numRegs = j; 580 PMD_INIT_LOG(INFO, "numRegs: %u", j); 581 582 size = sizeof(Vmxnet3_MemRegs) + 583 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 584 585 cmdInfo = &shared->cu.cmdInfo; 586 cmdInfo->varConf.confVer = 1; 587 cmdInfo->varConf.confLen = size; 588 cmdInfo->varConf.confPA = hw->memRegsPA; 589 590 return 0; 591 } 592 593 static int 594 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 595 { 596 struct rte_eth_conf port_conf = dev->data->dev_conf; 597 struct vmxnet3_hw *hw = dev->data->dev_private; 598 uint32_t mtu = dev->data->mtu; 599 Vmxnet3_DriverShared *shared = hw->shared; 600 Vmxnet3_DSDevRead *devRead = &shared->devRead; 601 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 602 uint32_t i; 603 int ret; 604 605 hw->mtu = mtu; 606 607 shared->magic = VMXNET3_REV1_MAGIC; 608 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 609 610 /* Setting up Guest OS information */ 611 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 612 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 613 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 614 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 615 devRead->misc.driverInfo.uptVerSpt = 1; 616 617 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 618 devRead->misc.queueDescPA = hw->queueDescPA; 619 devRead->misc.queueDescLen = hw->queue_desc_len; 620 devRead->misc.numTxQueues = hw->num_tx_queues; 621 devRead->misc.numRxQueues = hw->num_rx_queues; 622 623 /* 624 * Set number of interrupts to 1 625 * PMD by default disables all the interrupts but this is MUST 626 * to activate device. It needs at least one interrupt for 627 * link events to handle 628 */ 629 hw->num_intrs = devRead->intrConf.numIntrs = 1; 630 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 631 632 for (i = 0; i < hw->num_tx_queues; i++) { 633 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 634 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 635 636 txq->shared = &hw->tqd_start[i]; 637 638 tqd->ctrl.txNumDeferred = 0; 639 tqd->ctrl.txThreshold = 1; 640 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 641 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 642 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 643 644 tqd->conf.txRingSize = txq->cmd_ring.size; 645 tqd->conf.compRingSize = txq->comp_ring.size; 646 tqd->conf.dataRingSize = txq->data_ring.size; 647 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 648 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 649 tqd->status.stopped = TRUE; 650 tqd->status.error = 0; 651 memset(&tqd->stats, 0, sizeof(tqd->stats)); 652 } 653 654 for (i = 0; i < hw->num_rx_queues; i++) { 655 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 656 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 657 658 rxq->shared = &hw->rqd_start[i]; 659 660 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 661 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 662 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 663 664 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 665 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 666 rqd->conf.compRingSize = rxq->comp_ring.size; 667 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 668 if (VMXNET3_VERSION_GE_3(hw)) { 669 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 670 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 671 } 672 rqd->status.stopped = TRUE; 673 rqd->status.error = 0; 674 memset(&rqd->stats, 0, sizeof(rqd->stats)); 675 } 676 677 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 678 devRead->rxFilterConf.rxMode = 0; 679 680 /* Setting up feature flags */ 681 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 682 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 683 684 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 685 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 686 devRead->misc.maxNumRxSG = 0; 687 } 688 689 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 690 ret = vmxnet3_rss_configure(dev); 691 if (ret != VMXNET3_SUCCESS) 692 return ret; 693 694 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 695 devRead->rssConfDesc.confVer = 1; 696 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 697 devRead->rssConfDesc.confPA = hw->rss_confPA; 698 } 699 700 ret = vmxnet3_dev_vlan_offload_set(dev, 701 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 702 if (ret) 703 return ret; 704 705 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 706 707 return VMXNET3_SUCCESS; 708 } 709 710 /* 711 * Configure device link speed and setup link. 712 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 713 * It returns 0 on success. 714 */ 715 static int 716 vmxnet3_dev_start(struct rte_eth_dev *dev) 717 { 718 int ret; 719 struct vmxnet3_hw *hw = dev->data->dev_private; 720 721 PMD_INIT_FUNC_TRACE(); 722 723 /* Save stats before it is reset by CMD_ACTIVATE */ 724 vmxnet3_hw_stats_save(hw); 725 726 ret = vmxnet3_setup_driver_shared(dev); 727 if (ret != VMXNET3_SUCCESS) 728 return ret; 729 730 /* check if lsc interrupt feature is enabled */ 731 if (dev->data->dev_conf.intr_conf.lsc) { 732 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 733 734 /* Setup interrupt callback */ 735 rte_intr_callback_register(&pci_dev->intr_handle, 736 vmxnet3_interrupt_handler, dev); 737 738 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 739 PMD_INIT_LOG(ERR, "interrupt enable failed"); 740 return -EIO; 741 } 742 } 743 744 /* Exchange shared data with device */ 745 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 746 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 747 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 748 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 749 750 /* Activate device by register write */ 751 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 752 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 753 754 if (ret != 0) { 755 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 756 return -EINVAL; 757 } 758 759 /* Setup memory region for rx buffers */ 760 ret = vmxnet3_dev_setup_memreg(dev); 761 if (ret == 0) { 762 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 763 VMXNET3_CMD_REGISTER_MEMREGS); 764 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 765 if (ret != 0) 766 PMD_INIT_LOG(DEBUG, 767 "Failed in setup memory region cmd\n"); 768 ret = 0; 769 } else { 770 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 771 } 772 773 if (VMXNET3_VERSION_GE_4(hw)) { 774 /* Check for additional RSS */ 775 ret = vmxnet3_v4_rss_configure(dev); 776 if (ret != VMXNET3_SUCCESS) { 777 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 778 return ret; 779 } 780 } 781 782 /* Disable interrupts */ 783 vmxnet3_disable_intr(hw); 784 785 /* 786 * Load RX queues with blank mbufs and update next2fill index for device 787 * Update RxMode of the device 788 */ 789 ret = vmxnet3_dev_rxtx_init(dev); 790 if (ret != VMXNET3_SUCCESS) { 791 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 792 return ret; 793 } 794 795 hw->adapter_stopped = FALSE; 796 797 /* Setting proper Rx Mode and issue Rx Mode Update command */ 798 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 799 800 if (dev->data->dev_conf.intr_conf.lsc) { 801 vmxnet3_enable_intr(hw); 802 803 /* 804 * Update link state from device since this won't be 805 * done upon starting with lsc in use. This is done 806 * only after enabling interrupts to avoid any race 807 * where the link state could change without an 808 * interrupt being fired. 809 */ 810 __vmxnet3_dev_link_update(dev, 0); 811 } 812 813 return VMXNET3_SUCCESS; 814 } 815 816 /* 817 * Stop device: disable rx and tx functions to allow for reconfiguring. 818 */ 819 static void 820 vmxnet3_dev_stop(struct rte_eth_dev *dev) 821 { 822 struct rte_eth_link link; 823 struct vmxnet3_hw *hw = dev->data->dev_private; 824 825 PMD_INIT_FUNC_TRACE(); 826 827 if (hw->adapter_stopped == 1) { 828 PMD_INIT_LOG(DEBUG, "Device already stopped."); 829 return; 830 } 831 832 /* disable interrupts */ 833 vmxnet3_disable_intr(hw); 834 835 if (dev->data->dev_conf.intr_conf.lsc) { 836 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 837 838 rte_intr_disable(&pci_dev->intr_handle); 839 840 rte_intr_callback_unregister(&pci_dev->intr_handle, 841 vmxnet3_interrupt_handler, dev); 842 } 843 844 /* quiesce the device first */ 845 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 846 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 847 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 848 849 /* reset the device */ 850 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 851 PMD_INIT_LOG(DEBUG, "Device reset."); 852 853 vmxnet3_dev_clear_queues(dev); 854 855 /* Clear recorded link status */ 856 memset(&link, 0, sizeof(link)); 857 link.link_duplex = ETH_LINK_FULL_DUPLEX; 858 link.link_speed = ETH_SPEED_NUM_10G; 859 link.link_autoneg = ETH_LINK_FIXED; 860 rte_eth_linkstatus_set(dev, &link); 861 862 hw->adapter_stopped = 1; 863 } 864 865 static void 866 vmxnet3_free_queues(struct rte_eth_dev *dev) 867 { 868 int i; 869 870 PMD_INIT_FUNC_TRACE(); 871 872 for (i = 0; i < dev->data->nb_rx_queues; i++) { 873 void *rxq = dev->data->rx_queues[i]; 874 875 vmxnet3_dev_rx_queue_release(rxq); 876 } 877 dev->data->nb_rx_queues = 0; 878 879 for (i = 0; i < dev->data->nb_tx_queues; i++) { 880 void *txq = dev->data->tx_queues[i]; 881 882 vmxnet3_dev_tx_queue_release(txq); 883 } 884 dev->data->nb_tx_queues = 0; 885 } 886 887 /* 888 * Reset and stop device. 889 */ 890 static void 891 vmxnet3_dev_close(struct rte_eth_dev *dev) 892 { 893 PMD_INIT_FUNC_TRACE(); 894 895 vmxnet3_dev_stop(dev); 896 vmxnet3_free_queues(dev); 897 } 898 899 static void 900 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 901 struct UPT1_TxStats *res) 902 { 903 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 904 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 905 (h)->saved_tx_stats[(i)].f) 906 907 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 908 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 909 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 910 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 911 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 912 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 913 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 914 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 915 916 #undef VMXNET3_UPDATE_TX_STAT 917 } 918 919 static void 920 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 921 struct UPT1_RxStats *res) 922 { 923 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 924 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 925 (h)->saved_rx_stats[(i)].f) 926 927 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 928 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 929 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 930 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 931 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 932 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 933 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 934 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 935 936 #undef VMXNET3_UPDATE_RX_STAT 937 } 938 939 static void 940 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 941 struct UPT1_TxStats *res) 942 { 943 vmxnet3_hw_tx_stats_get(hw, q, res); 944 945 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 946 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 947 948 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 949 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 950 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 951 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 953 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 954 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 955 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 956 957 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 958 } 959 960 static void 961 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 962 struct UPT1_RxStats *res) 963 { 964 vmxnet3_hw_rx_stats_get(hw, q, res); 965 966 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 967 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 968 969 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 970 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 971 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 972 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 974 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 975 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 976 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 977 978 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 979 } 980 981 static void 982 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 983 { 984 unsigned int i; 985 986 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 987 988 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 989 990 for (i = 0; i < hw->num_tx_queues; i++) 991 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 992 for (i = 0; i < hw->num_rx_queues; i++) 993 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 994 } 995 996 static int 997 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 998 struct rte_eth_xstat_name *xstats_names, 999 unsigned int n) 1000 { 1001 unsigned int i, t, count = 0; 1002 unsigned int nstats = 1003 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1004 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1005 1006 if (!xstats_names || n < nstats) 1007 return nstats; 1008 1009 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1010 if (!dev->data->rx_queues[i]) 1011 continue; 1012 1013 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1014 snprintf(xstats_names[count].name, 1015 sizeof(xstats_names[count].name), 1016 "rx_q%u_%s", i, 1017 vmxnet3_rxq_stat_strings[t].name); 1018 count++; 1019 } 1020 } 1021 1022 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1023 if (!dev->data->tx_queues[i]) 1024 continue; 1025 1026 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1027 snprintf(xstats_names[count].name, 1028 sizeof(xstats_names[count].name), 1029 "tx_q%u_%s", i, 1030 vmxnet3_txq_stat_strings[t].name); 1031 count++; 1032 } 1033 } 1034 1035 return count; 1036 } 1037 1038 static int 1039 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1040 unsigned int n) 1041 { 1042 unsigned int i, t, count = 0; 1043 unsigned int nstats = 1044 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1045 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1046 1047 if (n < nstats) 1048 return nstats; 1049 1050 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1051 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1052 1053 if (rxq == NULL) 1054 continue; 1055 1056 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1057 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1058 vmxnet3_rxq_stat_strings[t].offset); 1059 xstats[count].id = count; 1060 count++; 1061 } 1062 } 1063 1064 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1065 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1066 1067 if (txq == NULL) 1068 continue; 1069 1070 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1071 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1072 vmxnet3_txq_stat_strings[t].offset); 1073 xstats[count].id = count; 1074 count++; 1075 } 1076 } 1077 1078 return count; 1079 } 1080 1081 static int 1082 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1083 { 1084 unsigned int i; 1085 struct vmxnet3_hw *hw = dev->data->dev_private; 1086 struct UPT1_TxStats txStats; 1087 struct UPT1_RxStats rxStats; 1088 1089 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1090 1091 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1092 for (i = 0; i < hw->num_tx_queues; i++) { 1093 vmxnet3_tx_stats_get(hw, i, &txStats); 1094 1095 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1096 txStats.mcastPktsTxOK + 1097 txStats.bcastPktsTxOK; 1098 1099 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1100 txStats.mcastBytesTxOK + 1101 txStats.bcastBytesTxOK; 1102 1103 stats->opackets += stats->q_opackets[i]; 1104 stats->obytes += stats->q_obytes[i]; 1105 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1106 } 1107 1108 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1109 for (i = 0; i < hw->num_rx_queues; i++) { 1110 vmxnet3_rx_stats_get(hw, i, &rxStats); 1111 1112 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1113 rxStats.mcastPktsRxOK + 1114 rxStats.bcastPktsRxOK; 1115 1116 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1117 rxStats.mcastBytesRxOK + 1118 rxStats.bcastBytesRxOK; 1119 1120 stats->ipackets += stats->q_ipackets[i]; 1121 stats->ibytes += stats->q_ibytes[i]; 1122 1123 stats->q_errors[i] = rxStats.pktsRxError; 1124 stats->ierrors += rxStats.pktsRxError; 1125 stats->imissed += rxStats.pktsRxOutOfBuf; 1126 } 1127 1128 return 0; 1129 } 1130 1131 static int 1132 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1133 { 1134 unsigned int i; 1135 struct vmxnet3_hw *hw = dev->data->dev_private; 1136 struct UPT1_TxStats txStats = {0}; 1137 struct UPT1_RxStats rxStats = {0}; 1138 1139 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1140 1141 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1142 1143 for (i = 0; i < hw->num_tx_queues; i++) { 1144 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1145 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1146 sizeof(hw->snapshot_tx_stats[0])); 1147 } 1148 for (i = 0; i < hw->num_rx_queues; i++) { 1149 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1150 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1151 sizeof(hw->snapshot_rx_stats[0])); 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int 1158 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1159 struct rte_eth_dev_info *dev_info) 1160 { 1161 struct vmxnet3_hw *hw = dev->data->dev_private; 1162 1163 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1164 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1165 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1166 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1167 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1168 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1169 1170 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1171 1172 if (VMXNET3_VERSION_GE_4(hw)) { 1173 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1174 } 1175 1176 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1177 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1178 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1179 .nb_align = 1, 1180 }; 1181 1182 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1183 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1184 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1185 .nb_align = 1, 1186 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1187 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1188 }; 1189 1190 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1191 dev_info->rx_queue_offload_capa = 0; 1192 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1193 dev_info->tx_queue_offload_capa = 0; 1194 1195 return 0; 1196 } 1197 1198 static const uint32_t * 1199 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1200 { 1201 static const uint32_t ptypes[] = { 1202 RTE_PTYPE_L3_IPV4_EXT, 1203 RTE_PTYPE_L3_IPV4, 1204 RTE_PTYPE_UNKNOWN 1205 }; 1206 1207 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1208 return ptypes; 1209 return NULL; 1210 } 1211 1212 static int 1213 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1214 { 1215 struct vmxnet3_hw *hw = dev->data->dev_private; 1216 1217 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1218 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1219 return 0; 1220 } 1221 1222 /* return 0 means link status changed, -1 means not changed */ 1223 static int 1224 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1225 __rte_unused int wait_to_complete) 1226 { 1227 struct vmxnet3_hw *hw = dev->data->dev_private; 1228 struct rte_eth_link link; 1229 uint32_t ret; 1230 1231 memset(&link, 0, sizeof(link)); 1232 1233 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1234 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1235 1236 if (ret & 0x1) 1237 link.link_status = ETH_LINK_UP; 1238 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1239 link.link_speed = ETH_SPEED_NUM_10G; 1240 link.link_autoneg = ETH_LINK_FIXED; 1241 1242 return rte_eth_linkstatus_set(dev, &link); 1243 } 1244 1245 static int 1246 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1247 { 1248 /* Link status doesn't change for stopped dev */ 1249 if (dev->data->dev_started == 0) 1250 return -1; 1251 1252 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1253 } 1254 1255 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1256 static void 1257 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1258 { 1259 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1260 1261 if (set) 1262 rxConf->rxMode = rxConf->rxMode | feature; 1263 else 1264 rxConf->rxMode = rxConf->rxMode & (~feature); 1265 1266 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1267 } 1268 1269 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1270 static int 1271 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1272 { 1273 struct vmxnet3_hw *hw = dev->data->dev_private; 1274 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1275 1276 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1277 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1278 1279 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1280 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1281 1282 return 0; 1283 } 1284 1285 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1286 static int 1287 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1288 { 1289 struct vmxnet3_hw *hw = dev->data->dev_private; 1290 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1291 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1292 1293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1294 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1295 else 1296 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1297 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1298 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1299 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1300 1301 return 0; 1302 } 1303 1304 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1305 static int 1306 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1307 { 1308 struct vmxnet3_hw *hw = dev->data->dev_private; 1309 1310 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1311 1312 return 0; 1313 } 1314 1315 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1316 static int 1317 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1318 { 1319 struct vmxnet3_hw *hw = dev->data->dev_private; 1320 1321 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1322 1323 return 0; 1324 } 1325 1326 /* Enable/disable filter on vlan */ 1327 static int 1328 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1329 { 1330 struct vmxnet3_hw *hw = dev->data->dev_private; 1331 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1332 uint32_t *vf_table = rxConf->vfTable; 1333 1334 /* save state for restore */ 1335 if (on) 1336 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1337 else 1338 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1339 1340 /* don't change active filter if in promiscuous mode */ 1341 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1342 return 0; 1343 1344 /* set in hardware */ 1345 if (on) 1346 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1347 else 1348 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1349 1350 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1351 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1352 return 0; 1353 } 1354 1355 static int 1356 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1357 { 1358 struct vmxnet3_hw *hw = dev->data->dev_private; 1359 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1360 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1361 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1362 1363 if (mask & ETH_VLAN_STRIP_MASK) { 1364 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1365 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1366 else 1367 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1368 1369 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1370 VMXNET3_CMD_UPDATE_FEATURE); 1371 } 1372 1373 if (mask & ETH_VLAN_FILTER_MASK) { 1374 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1375 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1376 else 1377 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1378 1379 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1380 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1381 } 1382 1383 return 0; 1384 } 1385 1386 static void 1387 vmxnet3_process_events(struct rte_eth_dev *dev) 1388 { 1389 struct vmxnet3_hw *hw = dev->data->dev_private; 1390 uint32_t events = hw->shared->ecr; 1391 1392 if (!events) 1393 return; 1394 1395 /* 1396 * ECR bits when written with 1b are cleared. Hence write 1397 * events back to ECR so that the bits which were set will be reset. 1398 */ 1399 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1400 1401 /* Check if link state has changed */ 1402 if (events & VMXNET3_ECR_LINK) { 1403 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1404 if (vmxnet3_dev_link_update(dev, 0) == 0) 1405 _rte_eth_dev_callback_process(dev, 1406 RTE_ETH_EVENT_INTR_LSC, 1407 NULL); 1408 } 1409 1410 /* Check if there is an error on xmit/recv queues */ 1411 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1412 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1413 VMXNET3_CMD_GET_QUEUE_STATUS); 1414 1415 if (hw->tqd_start->status.stopped) 1416 PMD_DRV_LOG(ERR, "tq error 0x%x", 1417 hw->tqd_start->status.error); 1418 1419 if (hw->rqd_start->status.stopped) 1420 PMD_DRV_LOG(ERR, "rq error 0x%x", 1421 hw->rqd_start->status.error); 1422 1423 /* Reset the device */ 1424 /* Have to reset the device */ 1425 } 1426 1427 if (events & VMXNET3_ECR_DIC) 1428 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1429 1430 if (events & VMXNET3_ECR_DEBUG) 1431 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1432 } 1433 1434 static void 1435 vmxnet3_interrupt_handler(void *param) 1436 { 1437 struct rte_eth_dev *dev = param; 1438 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1439 1440 vmxnet3_process_events(dev); 1441 1442 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1443 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1444 } 1445 1446 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1447 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1448 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1449 1450 RTE_INIT(vmxnet3_init_log) 1451 { 1452 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1453 if (vmxnet3_logtype_init >= 0) 1454 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1455 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1456 if (vmxnet3_logtype_driver >= 0) 1457 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1458 } 1459