1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 46 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 47 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 48 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 49 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 50 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 51 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 52 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 53 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 54 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 55 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 56 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 57 int wait_to_complete); 58 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 59 int wait_to_complete); 60 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 61 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 62 struct rte_eth_stats *stats); 63 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 64 struct rte_eth_xstat_name *xstats, 65 unsigned int n); 66 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 67 struct rte_eth_xstat *xstats, unsigned int n); 68 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 69 struct rte_eth_dev_info *dev_info); 70 static const uint32_t * 71 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 73 uint16_t vid, int on); 74 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 75 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 76 struct ether_addr *mac_addr); 77 static void vmxnet3_interrupt_handler(void *param); 78 79 int vmxnet3_logtype_init; 80 int vmxnet3_logtype_driver; 81 82 /* 83 * The set of PCI devices this driver supports 84 */ 85 #define VMWARE_PCI_VENDOR_ID 0x15AD 86 #define VMWARE_DEV_ID_VMXNET3 0x07B0 87 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 88 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 89 { .vendor_id = 0, /* sentinel */ }, 90 }; 91 92 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 93 .dev_configure = vmxnet3_dev_configure, 94 .dev_start = vmxnet3_dev_start, 95 .dev_stop = vmxnet3_dev_stop, 96 .dev_close = vmxnet3_dev_close, 97 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 98 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 99 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 100 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 101 .link_update = vmxnet3_dev_link_update, 102 .stats_get = vmxnet3_dev_stats_get, 103 .xstats_get_names = vmxnet3_dev_xstats_get_names, 104 .xstats_get = vmxnet3_dev_xstats_get, 105 .mac_addr_set = vmxnet3_mac_addr_set, 106 .dev_infos_get = vmxnet3_dev_info_get, 107 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 108 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 109 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 110 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 111 .rx_queue_release = vmxnet3_dev_rx_queue_release, 112 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 113 .tx_queue_release = vmxnet3_dev_tx_queue_release, 114 }; 115 116 struct vmxnet3_xstats_name_off { 117 char name[RTE_ETH_XSTATS_NAME_SIZE]; 118 unsigned int offset; 119 }; 120 121 /* tx_qX_ is prepended to the name string here */ 122 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 123 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 124 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 125 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 126 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 127 }; 128 129 /* rx_qX_ is prepended to the name string here */ 130 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 131 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 132 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 133 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 134 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 135 }; 136 137 static const struct rte_memzone * 138 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 139 const char *post_string, int socket_id, 140 uint16_t align, bool reuse) 141 { 142 char z_name[RTE_MEMZONE_NAMESIZE]; 143 const struct rte_memzone *mz; 144 145 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 146 dev->device->driver->name, dev->data->port_id, post_string); 147 148 mz = rte_memzone_lookup(z_name); 149 if (!reuse) { 150 if (mz) 151 rte_memzone_free(mz); 152 return rte_memzone_reserve_aligned(z_name, size, socket_id, 153 RTE_MEMZONE_IOVA_CONTIG, align); 154 } 155 156 if (mz) 157 return mz; 158 159 return rte_memzone_reserve_aligned(z_name, size, socket_id, 160 RTE_MEMZONE_IOVA_CONTIG, align); 161 } 162 163 /* 164 * This function is based on vmxnet3_disable_intr() 165 */ 166 static void 167 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 168 { 169 int i; 170 171 PMD_INIT_FUNC_TRACE(); 172 173 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 174 for (i = 0; i < hw->num_intrs; i++) 175 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 176 } 177 178 static void 179 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 180 { 181 int i; 182 183 PMD_INIT_FUNC_TRACE(); 184 185 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 186 for (i = 0; i < hw->num_intrs; i++) 187 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 188 } 189 190 /* 191 * Gets tx data ring descriptor size. 192 */ 193 static uint16_t 194 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 195 { 196 uint16 txdata_desc_size; 197 198 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 199 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 200 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 201 202 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 203 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 204 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 205 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 206 } 207 208 /* 209 * It returns 0 on success. 210 */ 211 static int 212 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 213 { 214 struct rte_pci_device *pci_dev; 215 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 216 uint32_t mac_hi, mac_lo, ver; 217 struct rte_eth_link link; 218 219 PMD_INIT_FUNC_TRACE(); 220 221 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 222 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 223 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 224 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 225 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 226 227 /* 228 * for secondary processes, we don't initialize any further as primary 229 * has already done this work. 230 */ 231 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 232 return 0; 233 234 rte_eth_copy_pci_info(eth_dev, pci_dev); 235 236 /* Vendor and Device ID need to be set before init of shared code */ 237 hw->device_id = pci_dev->id.device_id; 238 hw->vendor_id = pci_dev->id.vendor_id; 239 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 240 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 241 242 hw->num_rx_queues = 1; 243 hw->num_tx_queues = 1; 244 hw->bufs_per_pkt = 1; 245 246 /* Check h/w version compatibility with driver. */ 247 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 248 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 249 250 if (ver & (1 << VMXNET3_REV_3)) { 251 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 252 1 << VMXNET3_REV_3); 253 hw->version = VMXNET3_REV_3 + 1; 254 } else if (ver & (1 << VMXNET3_REV_2)) { 255 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 256 1 << VMXNET3_REV_2); 257 hw->version = VMXNET3_REV_2 + 1; 258 } else if (ver & (1 << VMXNET3_REV_1)) { 259 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 260 1 << VMXNET3_REV_1); 261 hw->version = VMXNET3_REV_1 + 1; 262 } else { 263 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 264 return -EIO; 265 } 266 267 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 268 269 /* Check UPT version compatibility with driver. */ 270 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 271 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 272 if (ver & 0x1) 273 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 274 else { 275 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 276 return -EIO; 277 } 278 279 /* Getting MAC Address */ 280 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 281 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 282 memcpy(hw->perm_addr, &mac_lo, 4); 283 memcpy(hw->perm_addr + 4, &mac_hi, 2); 284 285 /* Allocate memory for storing MAC addresses */ 286 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 287 VMXNET3_MAX_MAC_ADDRS, 0); 288 if (eth_dev->data->mac_addrs == NULL) { 289 PMD_INIT_LOG(ERR, 290 "Failed to allocate %d bytes needed to store MAC addresses", 291 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 292 return -ENOMEM; 293 } 294 /* Copy the permanent MAC address */ 295 ether_addr_copy((struct ether_addr *) hw->perm_addr, 296 ð_dev->data->mac_addrs[0]); 297 298 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 299 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 300 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 301 302 /* Put device in Quiesce Mode */ 303 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 304 305 /* allow untagged pkts */ 306 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 307 308 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 309 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 310 311 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 312 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 313 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 314 hw->rxdata_desc_size); 315 316 /* clear shadow stats */ 317 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 318 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 319 320 /* set the initial link status */ 321 memset(&link, 0, sizeof(link)); 322 link.link_duplex = ETH_LINK_FULL_DUPLEX; 323 link.link_speed = ETH_SPEED_NUM_10G; 324 link.link_autoneg = ETH_LINK_FIXED; 325 rte_eth_linkstatus_set(eth_dev, &link); 326 327 return 0; 328 } 329 330 static int 331 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 332 { 333 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 334 335 PMD_INIT_FUNC_TRACE(); 336 337 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 338 return 0; 339 340 if (hw->adapter_stopped == 0) 341 vmxnet3_dev_close(eth_dev); 342 343 eth_dev->dev_ops = NULL; 344 eth_dev->rx_pkt_burst = NULL; 345 eth_dev->tx_pkt_burst = NULL; 346 eth_dev->tx_pkt_prepare = NULL; 347 348 rte_free(eth_dev->data->mac_addrs); 349 eth_dev->data->mac_addrs = NULL; 350 351 return 0; 352 } 353 354 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 355 struct rte_pci_device *pci_dev) 356 { 357 return rte_eth_dev_pci_generic_probe(pci_dev, 358 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 359 } 360 361 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 362 { 363 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 364 } 365 366 static struct rte_pci_driver rte_vmxnet3_pmd = { 367 .id_table = pci_id_vmxnet3_map, 368 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 369 .probe = eth_vmxnet3_pci_probe, 370 .remove = eth_vmxnet3_pci_remove, 371 }; 372 373 static int 374 vmxnet3_dev_configure(struct rte_eth_dev *dev) 375 { 376 const struct rte_memzone *mz; 377 struct vmxnet3_hw *hw = dev->data->dev_private; 378 size_t size; 379 380 PMD_INIT_FUNC_TRACE(); 381 382 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 383 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 384 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 385 return -EINVAL; 386 } 387 388 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 389 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 390 return -EINVAL; 391 } 392 393 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 394 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 395 396 if (size > UINT16_MAX) 397 return -EINVAL; 398 399 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 400 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 401 402 /* 403 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 404 * on current socket 405 */ 406 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 407 "shared", rte_socket_id(), 8, 1); 408 409 if (mz == NULL) { 410 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 411 return -ENOMEM; 412 } 413 memset(mz->addr, 0, mz->len); 414 415 hw->shared = mz->addr; 416 hw->sharedPA = mz->iova; 417 418 /* 419 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 420 * on current socket. 421 * 422 * We cannot reuse this memzone from previous allocation as its size 423 * depends on the number of tx and rx queues, which could be different 424 * from one config to another. 425 */ 426 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 427 VMXNET3_QUEUE_DESC_ALIGN, 0); 428 if (mz == NULL) { 429 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 430 return -ENOMEM; 431 } 432 memset(mz->addr, 0, mz->len); 433 434 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 435 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 436 437 hw->queueDescPA = mz->iova; 438 hw->queue_desc_len = (uint16_t)size; 439 440 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 441 /* Allocate memory structure for UPT1_RSSConf and configure */ 442 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 443 "rss_conf", rte_socket_id(), 444 RTE_CACHE_LINE_SIZE, 1); 445 if (mz == NULL) { 446 PMD_INIT_LOG(ERR, 447 "ERROR: Creating rss_conf structure zone"); 448 return -ENOMEM; 449 } 450 memset(mz->addr, 0, mz->len); 451 452 hw->rss_conf = mz->addr; 453 hw->rss_confPA = mz->iova; 454 } 455 456 return 0; 457 } 458 459 static void 460 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 461 { 462 uint32_t val; 463 464 PMD_INIT_LOG(DEBUG, 465 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 466 addr[0], addr[1], addr[2], 467 addr[3], addr[4], addr[5]); 468 469 memcpy(&val, addr, 4); 470 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 471 472 memcpy(&val, addr + 4, 2); 473 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 474 } 475 476 static int 477 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 478 { 479 struct vmxnet3_hw *hw = dev->data->dev_private; 480 Vmxnet3_DriverShared *shared = hw->shared; 481 Vmxnet3_CmdInfo *cmdInfo; 482 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 483 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 484 uint32_t num, i, j, size; 485 486 if (hw->memRegsPA == 0) { 487 const struct rte_memzone *mz; 488 489 size = sizeof(Vmxnet3_MemRegs) + 490 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 491 sizeof(Vmxnet3_MemoryRegion); 492 493 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 494 1); 495 if (mz == NULL) { 496 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 497 return -ENOMEM; 498 } 499 memset(mz->addr, 0, mz->len); 500 hw->memRegs = mz->addr; 501 hw->memRegsPA = mz->iova; 502 } 503 504 num = hw->num_rx_queues; 505 506 for (i = 0; i < num; i++) { 507 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 508 509 mp[i] = rxq->mp; 510 index[i] = 1 << i; 511 } 512 513 /* 514 * The same mempool could be used by multiple queues. In such a case, 515 * remove duplicate mempool entries. Only one entry is kept with 516 * bitmask indicating queues that are using this mempool. 517 */ 518 for (i = 1; i < num; i++) { 519 for (j = 0; j < i; j++) { 520 if (mp[i] == mp[j]) { 521 mp[i] = NULL; 522 index[j] |= 1 << i; 523 break; 524 } 525 } 526 } 527 528 j = 0; 529 for (i = 0; i < num; i++) { 530 if (mp[i] == NULL) 531 continue; 532 533 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 534 535 mr->startPA = 536 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 537 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 538 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 539 mr->txQueueBits = index[i]; 540 mr->rxQueueBits = index[i]; 541 542 PMD_INIT_LOG(INFO, 543 "index: %u startPA: %" PRIu64 " length: %u, " 544 "rxBits: %x", 545 j, mr->startPA, mr->length, mr->rxQueueBits); 546 j++; 547 } 548 hw->memRegs->numRegs = j; 549 PMD_INIT_LOG(INFO, "numRegs: %u", j); 550 551 size = sizeof(Vmxnet3_MemRegs) + 552 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 553 554 cmdInfo = &shared->cu.cmdInfo; 555 cmdInfo->varConf.confVer = 1; 556 cmdInfo->varConf.confLen = size; 557 cmdInfo->varConf.confPA = hw->memRegsPA; 558 559 return 0; 560 } 561 562 static int 563 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 564 { 565 struct rte_eth_conf port_conf = dev->data->dev_conf; 566 struct vmxnet3_hw *hw = dev->data->dev_private; 567 uint32_t mtu = dev->data->mtu; 568 Vmxnet3_DriverShared *shared = hw->shared; 569 Vmxnet3_DSDevRead *devRead = &shared->devRead; 570 uint32_t i; 571 int ret; 572 573 shared->magic = VMXNET3_REV1_MAGIC; 574 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 575 576 /* Setting up Guest OS information */ 577 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 578 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 579 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 580 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 581 devRead->misc.driverInfo.uptVerSpt = 1; 582 583 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 584 devRead->misc.queueDescPA = hw->queueDescPA; 585 devRead->misc.queueDescLen = hw->queue_desc_len; 586 devRead->misc.numTxQueues = hw->num_tx_queues; 587 devRead->misc.numRxQueues = hw->num_rx_queues; 588 589 /* 590 * Set number of interrupts to 1 591 * PMD by default disables all the interrupts but this is MUST 592 * to activate device. It needs at least one interrupt for 593 * link events to handle 594 */ 595 hw->num_intrs = devRead->intrConf.numIntrs = 1; 596 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 597 598 for (i = 0; i < hw->num_tx_queues; i++) { 599 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 600 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 601 602 txq->shared = &hw->tqd_start[i]; 603 604 tqd->ctrl.txNumDeferred = 0; 605 tqd->ctrl.txThreshold = 1; 606 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 607 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 608 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 609 610 tqd->conf.txRingSize = txq->cmd_ring.size; 611 tqd->conf.compRingSize = txq->comp_ring.size; 612 tqd->conf.dataRingSize = txq->data_ring.size; 613 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 614 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 615 tqd->status.stopped = TRUE; 616 tqd->status.error = 0; 617 memset(&tqd->stats, 0, sizeof(tqd->stats)); 618 } 619 620 for (i = 0; i < hw->num_rx_queues; i++) { 621 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 622 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 623 624 rxq->shared = &hw->rqd_start[i]; 625 626 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 627 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 628 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 629 630 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 631 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 632 rqd->conf.compRingSize = rxq->comp_ring.size; 633 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 634 if (VMXNET3_VERSION_GE_3(hw)) { 635 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 636 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 637 } 638 rqd->status.stopped = TRUE; 639 rqd->status.error = 0; 640 memset(&rqd->stats, 0, sizeof(rqd->stats)); 641 } 642 643 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 644 devRead->rxFilterConf.rxMode = 0; 645 646 /* Setting up feature flags */ 647 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 648 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 649 650 if (dev->data->dev_conf.rxmode.enable_lro) { 651 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 652 devRead->misc.maxNumRxSG = 0; 653 } 654 655 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 656 ret = vmxnet3_rss_configure(dev); 657 if (ret != VMXNET3_SUCCESS) 658 return ret; 659 660 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 661 devRead->rssConfDesc.confVer = 1; 662 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 663 devRead->rssConfDesc.confPA = hw->rss_confPA; 664 } 665 666 ret = vmxnet3_dev_vlan_offload_set(dev, 667 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 668 if (ret) 669 return ret; 670 671 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 672 673 return VMXNET3_SUCCESS; 674 } 675 676 /* 677 * Configure device link speed and setup link. 678 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 679 * It returns 0 on success. 680 */ 681 static int 682 vmxnet3_dev_start(struct rte_eth_dev *dev) 683 { 684 int ret; 685 struct vmxnet3_hw *hw = dev->data->dev_private; 686 687 PMD_INIT_FUNC_TRACE(); 688 689 /* Save stats before it is reset by CMD_ACTIVATE */ 690 vmxnet3_hw_stats_save(hw); 691 692 ret = vmxnet3_setup_driver_shared(dev); 693 if (ret != VMXNET3_SUCCESS) 694 return ret; 695 696 /* check if lsc interrupt feature is enabled */ 697 if (dev->data->dev_conf.intr_conf.lsc) { 698 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 699 700 /* Setup interrupt callback */ 701 rte_intr_callback_register(&pci_dev->intr_handle, 702 vmxnet3_interrupt_handler, dev); 703 704 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 705 PMD_INIT_LOG(ERR, "interrupt enable failed"); 706 return -EIO; 707 } 708 } 709 710 /* Exchange shared data with device */ 711 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 712 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 713 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 714 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 715 716 /* Activate device by register write */ 717 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 718 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 719 720 if (ret != 0) { 721 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 722 return -EINVAL; 723 } 724 725 /* Setup memory region for rx buffers */ 726 ret = vmxnet3_dev_setup_memreg(dev); 727 if (ret == 0) { 728 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 729 VMXNET3_CMD_REGISTER_MEMREGS); 730 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 731 if (ret != 0) 732 PMD_INIT_LOG(DEBUG, 733 "Failed in setup memory region cmd\n"); 734 ret = 0; 735 } else { 736 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 737 } 738 739 /* Disable interrupts */ 740 vmxnet3_disable_intr(hw); 741 742 /* 743 * Load RX queues with blank mbufs and update next2fill index for device 744 * Update RxMode of the device 745 */ 746 ret = vmxnet3_dev_rxtx_init(dev); 747 if (ret != VMXNET3_SUCCESS) { 748 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 749 return ret; 750 } 751 752 hw->adapter_stopped = FALSE; 753 754 /* Setting proper Rx Mode and issue Rx Mode Update command */ 755 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 756 757 if (dev->data->dev_conf.intr_conf.lsc) { 758 vmxnet3_enable_intr(hw); 759 760 /* 761 * Update link state from device since this won't be 762 * done upon starting with lsc in use. This is done 763 * only after enabling interrupts to avoid any race 764 * where the link state could change without an 765 * interrupt being fired. 766 */ 767 __vmxnet3_dev_link_update(dev, 0); 768 } 769 770 return VMXNET3_SUCCESS; 771 } 772 773 /* 774 * Stop device: disable rx and tx functions to allow for reconfiguring. 775 */ 776 static void 777 vmxnet3_dev_stop(struct rte_eth_dev *dev) 778 { 779 struct rte_eth_link link; 780 struct vmxnet3_hw *hw = dev->data->dev_private; 781 782 PMD_INIT_FUNC_TRACE(); 783 784 if (hw->adapter_stopped == 1) { 785 PMD_INIT_LOG(DEBUG, "Device already closed."); 786 return; 787 } 788 789 /* disable interrupts */ 790 vmxnet3_disable_intr(hw); 791 792 if (dev->data->dev_conf.intr_conf.lsc) { 793 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 794 795 rte_intr_disable(&pci_dev->intr_handle); 796 797 rte_intr_callback_unregister(&pci_dev->intr_handle, 798 vmxnet3_interrupt_handler, dev); 799 } 800 801 /* quiesce the device first */ 802 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 803 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 804 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 805 806 /* reset the device */ 807 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 808 PMD_INIT_LOG(DEBUG, "Device reset."); 809 hw->adapter_stopped = 0; 810 811 vmxnet3_dev_clear_queues(dev); 812 813 /* Clear recorded link status */ 814 memset(&link, 0, sizeof(link)); 815 link.link_duplex = ETH_LINK_FULL_DUPLEX; 816 link.link_speed = ETH_SPEED_NUM_10G; 817 link.link_autoneg = ETH_LINK_FIXED; 818 rte_eth_linkstatus_set(dev, &link); 819 } 820 821 /* 822 * Reset and stop device. 823 */ 824 static void 825 vmxnet3_dev_close(struct rte_eth_dev *dev) 826 { 827 struct vmxnet3_hw *hw = dev->data->dev_private; 828 829 PMD_INIT_FUNC_TRACE(); 830 831 vmxnet3_dev_stop(dev); 832 hw->adapter_stopped = 1; 833 } 834 835 static void 836 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 837 struct UPT1_TxStats *res) 838 { 839 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 840 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 841 (h)->saved_tx_stats[(i)].f) 842 843 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 844 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 845 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 846 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 847 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 848 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 849 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 850 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 851 852 #undef VMXNET3_UPDATE_TX_STAT 853 } 854 855 static void 856 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 857 struct UPT1_RxStats *res) 858 { 859 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 860 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 861 (h)->saved_rx_stats[(i)].f) 862 863 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 864 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 865 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 866 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 867 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 868 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 869 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 870 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 871 872 #undef VMXNET3_UPDATE_RX_STATS 873 } 874 875 static void 876 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 877 { 878 unsigned int i; 879 880 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 881 882 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 883 884 for (i = 0; i < hw->num_tx_queues; i++) 885 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 886 for (i = 0; i < hw->num_rx_queues; i++) 887 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 888 } 889 890 static int 891 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 892 struct rte_eth_xstat_name *xstats_names, 893 unsigned int n) 894 { 895 unsigned int i, t, count = 0; 896 unsigned int nstats = 897 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 898 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 899 900 if (!xstats_names || n < nstats) 901 return nstats; 902 903 for (i = 0; i < dev->data->nb_rx_queues; i++) { 904 if (!dev->data->rx_queues[i]) 905 continue; 906 907 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 908 snprintf(xstats_names[count].name, 909 sizeof(xstats_names[count].name), 910 "rx_q%u_%s", i, 911 vmxnet3_rxq_stat_strings[t].name); 912 count++; 913 } 914 } 915 916 for (i = 0; i < dev->data->nb_tx_queues; i++) { 917 if (!dev->data->tx_queues[i]) 918 continue; 919 920 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 921 snprintf(xstats_names[count].name, 922 sizeof(xstats_names[count].name), 923 "tx_q%u_%s", i, 924 vmxnet3_txq_stat_strings[t].name); 925 count++; 926 } 927 } 928 929 return count; 930 } 931 932 static int 933 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 934 unsigned int n) 935 { 936 unsigned int i, t, count = 0; 937 unsigned int nstats = 938 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 939 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 940 941 if (n < nstats) 942 return nstats; 943 944 for (i = 0; i < dev->data->nb_rx_queues; i++) { 945 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 946 947 if (rxq == NULL) 948 continue; 949 950 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 951 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 952 vmxnet3_rxq_stat_strings[t].offset); 953 xstats[count].id = count; 954 count++; 955 } 956 } 957 958 for (i = 0; i < dev->data->nb_tx_queues; i++) { 959 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 960 961 if (txq == NULL) 962 continue; 963 964 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 965 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 966 vmxnet3_txq_stat_strings[t].offset); 967 xstats[count].id = count; 968 count++; 969 } 970 } 971 972 return count; 973 } 974 975 static int 976 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 977 { 978 unsigned int i; 979 struct vmxnet3_hw *hw = dev->data->dev_private; 980 struct UPT1_TxStats txStats; 981 struct UPT1_RxStats rxStats; 982 983 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 984 985 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 986 for (i = 0; i < hw->num_tx_queues; i++) { 987 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 988 989 stats->q_opackets[i] = txStats.ucastPktsTxOK + 990 txStats.mcastPktsTxOK + 991 txStats.bcastPktsTxOK; 992 993 stats->q_obytes[i] = txStats.ucastBytesTxOK + 994 txStats.mcastBytesTxOK + 995 txStats.bcastBytesTxOK; 996 997 stats->opackets += stats->q_opackets[i]; 998 stats->obytes += stats->q_obytes[i]; 999 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1000 } 1001 1002 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1003 for (i = 0; i < hw->num_rx_queues; i++) { 1004 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1005 1006 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1007 rxStats.mcastPktsRxOK + 1008 rxStats.bcastPktsRxOK; 1009 1010 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1011 rxStats.mcastBytesRxOK + 1012 rxStats.bcastBytesRxOK; 1013 1014 stats->ipackets += stats->q_ipackets[i]; 1015 stats->ibytes += stats->q_ibytes[i]; 1016 1017 stats->q_errors[i] = rxStats.pktsRxError; 1018 stats->ierrors += rxStats.pktsRxError; 1019 stats->imissed += rxStats.pktsRxOutOfBuf; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static void 1026 vmxnet3_dev_info_get(struct rte_eth_dev *dev __rte_unused, 1027 struct rte_eth_dev_info *dev_info) 1028 { 1029 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1030 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1031 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1032 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1033 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1034 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1035 1036 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 1037 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1038 1039 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1040 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1041 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1042 .nb_align = 1, 1043 }; 1044 1045 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1046 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1047 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1048 .nb_align = 1, 1049 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1050 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1051 }; 1052 1053 dev_info->rx_offload_capa = 1054 DEV_RX_OFFLOAD_VLAN_STRIP | 1055 DEV_RX_OFFLOAD_UDP_CKSUM | 1056 DEV_RX_OFFLOAD_TCP_CKSUM | 1057 DEV_RX_OFFLOAD_TCP_LRO; 1058 1059 dev_info->tx_offload_capa = 1060 DEV_TX_OFFLOAD_VLAN_INSERT | 1061 DEV_TX_OFFLOAD_TCP_CKSUM | 1062 DEV_TX_OFFLOAD_UDP_CKSUM | 1063 DEV_TX_OFFLOAD_TCP_TSO; 1064 } 1065 1066 static const uint32_t * 1067 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1068 { 1069 static const uint32_t ptypes[] = { 1070 RTE_PTYPE_L3_IPV4_EXT, 1071 RTE_PTYPE_L3_IPV4, 1072 RTE_PTYPE_UNKNOWN 1073 }; 1074 1075 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1076 return ptypes; 1077 return NULL; 1078 } 1079 1080 static int 1081 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1082 { 1083 struct vmxnet3_hw *hw = dev->data->dev_private; 1084 1085 ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr)); 1086 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1087 return 0; 1088 } 1089 1090 /* return 0 means link status changed, -1 means not changed */ 1091 static int 1092 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1093 __rte_unused int wait_to_complete) 1094 { 1095 struct vmxnet3_hw *hw = dev->data->dev_private; 1096 struct rte_eth_link link; 1097 uint32_t ret; 1098 1099 memset(&link, 0, sizeof(link)); 1100 1101 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1102 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1103 1104 if (ret & 0x1) 1105 link.link_status = ETH_LINK_UP; 1106 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1107 link.link_speed = ETH_SPEED_NUM_10G; 1108 link.link_autoneg = ETH_LINK_AUTONEG; 1109 1110 return rte_eth_linkstatus_set(dev, &link); 1111 } 1112 1113 static int 1114 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1115 { 1116 /* Link status doesn't change for stopped dev */ 1117 if (dev->data->dev_started == 0) 1118 return -1; 1119 1120 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1121 } 1122 1123 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1124 static void 1125 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1126 { 1127 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1128 1129 if (set) 1130 rxConf->rxMode = rxConf->rxMode | feature; 1131 else 1132 rxConf->rxMode = rxConf->rxMode & (~feature); 1133 1134 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1135 } 1136 1137 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1138 static void 1139 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1140 { 1141 struct vmxnet3_hw *hw = dev->data->dev_private; 1142 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1143 1144 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1145 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1146 1147 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1148 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1149 } 1150 1151 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1152 static void 1153 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1154 { 1155 struct vmxnet3_hw *hw = dev->data->dev_private; 1156 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1157 1158 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1159 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1160 else 1161 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1162 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1163 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1164 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1165 } 1166 1167 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1168 static void 1169 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1170 { 1171 struct vmxnet3_hw *hw = dev->data->dev_private; 1172 1173 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1174 } 1175 1176 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1177 static void 1178 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1179 { 1180 struct vmxnet3_hw *hw = dev->data->dev_private; 1181 1182 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1183 } 1184 1185 /* Enable/disable filter on vlan */ 1186 static int 1187 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1188 { 1189 struct vmxnet3_hw *hw = dev->data->dev_private; 1190 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1191 uint32_t *vf_table = rxConf->vfTable; 1192 1193 /* save state for restore */ 1194 if (on) 1195 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1196 else 1197 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1198 1199 /* don't change active filter if in promiscuous mode */ 1200 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1201 return 0; 1202 1203 /* set in hardware */ 1204 if (on) 1205 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1206 else 1207 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1208 1209 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1210 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1211 return 0; 1212 } 1213 1214 static int 1215 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1216 { 1217 struct vmxnet3_hw *hw = dev->data->dev_private; 1218 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1219 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1220 1221 if (mask & ETH_VLAN_STRIP_MASK) { 1222 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1223 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1224 else 1225 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1226 1227 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1228 VMXNET3_CMD_UPDATE_FEATURE); 1229 } 1230 1231 if (mask & ETH_VLAN_FILTER_MASK) { 1232 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1233 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1234 else 1235 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1236 1237 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1238 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static void 1245 vmxnet3_process_events(struct rte_eth_dev *dev) 1246 { 1247 struct vmxnet3_hw *hw = dev->data->dev_private; 1248 uint32_t events = hw->shared->ecr; 1249 1250 if (!events) 1251 return; 1252 1253 /* 1254 * ECR bits when written with 1b are cleared. Hence write 1255 * events back to ECR so that the bits which were set will be reset. 1256 */ 1257 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1258 1259 /* Check if link state has changed */ 1260 if (events & VMXNET3_ECR_LINK) { 1261 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1262 if (vmxnet3_dev_link_update(dev, 0) == 0) 1263 _rte_eth_dev_callback_process(dev, 1264 RTE_ETH_EVENT_INTR_LSC, 1265 NULL); 1266 } 1267 1268 /* Check if there is an error on xmit/recv queues */ 1269 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1271 VMXNET3_CMD_GET_QUEUE_STATUS); 1272 1273 if (hw->tqd_start->status.stopped) 1274 PMD_DRV_LOG(ERR, "tq error 0x%x", 1275 hw->tqd_start->status.error); 1276 1277 if (hw->rqd_start->status.stopped) 1278 PMD_DRV_LOG(ERR, "rq error 0x%x", 1279 hw->rqd_start->status.error); 1280 1281 /* Reset the device */ 1282 /* Have to reset the device */ 1283 } 1284 1285 if (events & VMXNET3_ECR_DIC) 1286 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1287 1288 if (events & VMXNET3_ECR_DEBUG) 1289 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1290 } 1291 1292 static void 1293 vmxnet3_interrupt_handler(void *param) 1294 { 1295 struct rte_eth_dev *dev = param; 1296 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1297 1298 vmxnet3_process_events(dev); 1299 1300 if (rte_intr_enable(&pci_dev->intr_handle) < 0) 1301 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1302 } 1303 1304 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1305 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1306 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1307 1308 RTE_INIT(vmxnet3_init_log); 1309 static void 1310 vmxnet3_init_log(void) 1311 { 1312 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1313 if (vmxnet3_logtype_init >= 0) 1314 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1315 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1316 if (vmxnet3_logtype_driver >= 0) 1317 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1318 } 1319