1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 60 DEV_RX_OFFLOAD_RSS_HASH) 61 62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 65 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 67 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 74 int wait_to_complete); 75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 76 int wait_to_complete); 77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 79 struct rte_eth_stats *stats); 80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 82 struct rte_eth_xstat_name *xstats, 83 unsigned int n); 84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 85 struct rte_eth_xstat *xstats, unsigned int n); 86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 87 struct rte_eth_dev_info *dev_info); 88 static const uint32_t * 89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 90 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 92 uint16_t vid, int on); 93 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 94 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 95 struct rte_ether_addr *mac_addr); 96 static void vmxnet3_interrupt_handler(void *param); 97 98 int vmxnet3_logtype_init; 99 int vmxnet3_logtype_driver; 100 101 /* 102 * The set of PCI devices this driver supports 103 */ 104 #define VMWARE_PCI_VENDOR_ID 0x15AD 105 #define VMWARE_DEV_ID_VMXNET3 0x07B0 106 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 107 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 108 { .vendor_id = 0, /* sentinel */ }, 109 }; 110 111 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 112 .dev_configure = vmxnet3_dev_configure, 113 .dev_start = vmxnet3_dev_start, 114 .dev_stop = vmxnet3_dev_stop, 115 .dev_close = vmxnet3_dev_close, 116 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 117 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 118 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 119 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 120 .link_update = vmxnet3_dev_link_update, 121 .stats_get = vmxnet3_dev_stats_get, 122 .xstats_get_names = vmxnet3_dev_xstats_get_names, 123 .xstats_get = vmxnet3_dev_xstats_get, 124 .stats_reset = vmxnet3_dev_stats_reset, 125 .mac_addr_set = vmxnet3_mac_addr_set, 126 .dev_infos_get = vmxnet3_dev_info_get, 127 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 128 .mtu_set = vmxnet3_dev_mtu_set, 129 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 130 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 131 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 132 .rx_queue_release = vmxnet3_dev_rx_queue_release, 133 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 134 .tx_queue_release = vmxnet3_dev_tx_queue_release, 135 }; 136 137 struct vmxnet3_xstats_name_off { 138 char name[RTE_ETH_XSTATS_NAME_SIZE]; 139 unsigned int offset; 140 }; 141 142 /* tx_qX_ is prepended to the name string here */ 143 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 144 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 145 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 146 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 147 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 148 }; 149 150 /* rx_qX_ is prepended to the name string here */ 151 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 152 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 153 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 154 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 155 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 156 }; 157 158 static const struct rte_memzone * 159 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 160 const char *post_string, int socket_id, 161 uint16_t align, bool reuse) 162 { 163 char z_name[RTE_MEMZONE_NAMESIZE]; 164 const struct rte_memzone *mz; 165 166 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 167 dev->data->port_id, post_string); 168 169 mz = rte_memzone_lookup(z_name); 170 if (!reuse) { 171 if (mz) 172 rte_memzone_free(mz); 173 return rte_memzone_reserve_aligned(z_name, size, socket_id, 174 RTE_MEMZONE_IOVA_CONTIG, align); 175 } 176 177 if (mz) 178 return mz; 179 180 return rte_memzone_reserve_aligned(z_name, size, socket_id, 181 RTE_MEMZONE_IOVA_CONTIG, align); 182 } 183 184 /* 185 * This function is based on vmxnet3_disable_intr() 186 */ 187 static void 188 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 189 { 190 int i; 191 192 PMD_INIT_FUNC_TRACE(); 193 194 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 195 for (i = 0; i < hw->num_intrs; i++) 196 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 197 } 198 199 static void 200 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 201 { 202 int i; 203 204 PMD_INIT_FUNC_TRACE(); 205 206 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 207 for (i = 0; i < hw->num_intrs; i++) 208 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 209 } 210 211 /* 212 * Gets tx data ring descriptor size. 213 */ 214 static uint16_t 215 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 216 { 217 uint16 txdata_desc_size; 218 219 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 220 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 221 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 222 223 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 224 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 225 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 226 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 227 } 228 229 /* 230 * It returns 0 on success. 231 */ 232 static int 233 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 234 { 235 struct rte_pci_device *pci_dev; 236 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 237 uint32_t mac_hi, mac_lo, ver; 238 struct rte_eth_link link; 239 240 PMD_INIT_FUNC_TRACE(); 241 242 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 243 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 244 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 245 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 246 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 247 248 /* 249 * for secondary processes, we don't initialize any further as primary 250 * has already done this work. 251 */ 252 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 253 return 0; 254 255 rte_eth_copy_pci_info(eth_dev, pci_dev); 256 257 /* Vendor and Device ID need to be set before init of shared code */ 258 hw->device_id = pci_dev->id.device_id; 259 hw->vendor_id = pci_dev->id.vendor_id; 260 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 261 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 262 263 hw->num_rx_queues = 1; 264 hw->num_tx_queues = 1; 265 hw->bufs_per_pkt = 1; 266 267 /* Check h/w version compatibility with driver. */ 268 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 269 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 270 271 if (ver & (1 << VMXNET3_REV_4)) { 272 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 273 1 << VMXNET3_REV_4); 274 hw->version = VMXNET3_REV_4 + 1; 275 } else if (ver & (1 << VMXNET3_REV_3)) { 276 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 277 1 << VMXNET3_REV_3); 278 hw->version = VMXNET3_REV_3 + 1; 279 } else if (ver & (1 << VMXNET3_REV_2)) { 280 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 281 1 << VMXNET3_REV_2); 282 hw->version = VMXNET3_REV_2 + 1; 283 } else if (ver & (1 << VMXNET3_REV_1)) { 284 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 285 1 << VMXNET3_REV_1); 286 hw->version = VMXNET3_REV_1 + 1; 287 } else { 288 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 289 return -EIO; 290 } 291 292 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 293 294 /* Check UPT version compatibility with driver. */ 295 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 296 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 297 if (ver & 0x1) 298 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 299 else { 300 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 301 return -EIO; 302 } 303 304 /* Getting MAC Address */ 305 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 306 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 307 memcpy(hw->perm_addr, &mac_lo, 4); 308 memcpy(hw->perm_addr + 4, &mac_hi, 2); 309 310 /* Allocate memory for storing MAC addresses */ 311 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 312 VMXNET3_MAX_MAC_ADDRS, 0); 313 if (eth_dev->data->mac_addrs == NULL) { 314 PMD_INIT_LOG(ERR, 315 "Failed to allocate %d bytes needed to store MAC addresses", 316 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 317 return -ENOMEM; 318 } 319 /* Copy the permanent MAC address */ 320 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 321 ð_dev->data->mac_addrs[0]); 322 323 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 324 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 325 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 326 327 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 328 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 329 330 /* Put device in Quiesce Mode */ 331 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 332 333 /* allow untagged pkts */ 334 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 335 336 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 337 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 338 339 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 340 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 341 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 342 hw->rxdata_desc_size); 343 344 /* clear shadow stats */ 345 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 346 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 347 348 /* clear snapshot stats */ 349 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 350 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 351 352 /* set the initial link status */ 353 memset(&link, 0, sizeof(link)); 354 link.link_duplex = ETH_LINK_FULL_DUPLEX; 355 link.link_speed = ETH_SPEED_NUM_10G; 356 link.link_autoneg = ETH_LINK_FIXED; 357 rte_eth_linkstatus_set(eth_dev, &link); 358 359 return 0; 360 } 361 362 static int 363 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 364 { 365 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 366 367 PMD_INIT_FUNC_TRACE(); 368 369 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 370 return 0; 371 372 if (hw->adapter_stopped == 0) { 373 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 374 return -EBUSY; 375 } 376 377 eth_dev->dev_ops = NULL; 378 eth_dev->rx_pkt_burst = NULL; 379 eth_dev->tx_pkt_burst = NULL; 380 eth_dev->tx_pkt_prepare = NULL; 381 382 return 0; 383 } 384 385 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 386 struct rte_pci_device *pci_dev) 387 { 388 return rte_eth_dev_pci_generic_probe(pci_dev, 389 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 390 } 391 392 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 393 { 394 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 395 } 396 397 static struct rte_pci_driver rte_vmxnet3_pmd = { 398 .id_table = pci_id_vmxnet3_map, 399 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 400 .probe = eth_vmxnet3_pci_probe, 401 .remove = eth_vmxnet3_pci_remove, 402 }; 403 404 static int 405 vmxnet3_dev_configure(struct rte_eth_dev *dev) 406 { 407 const struct rte_memzone *mz; 408 struct vmxnet3_hw *hw = dev->data->dev_private; 409 size_t size; 410 411 PMD_INIT_FUNC_TRACE(); 412 413 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 414 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 415 416 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 417 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 418 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 419 return -EINVAL; 420 } 421 422 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 423 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 424 return -EINVAL; 425 } 426 427 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 428 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 429 430 if (size > UINT16_MAX) 431 return -EINVAL; 432 433 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 434 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 435 436 /* 437 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 438 * on current socket 439 */ 440 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 441 "shared", rte_socket_id(), 8, 1); 442 443 if (mz == NULL) { 444 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 445 return -ENOMEM; 446 } 447 memset(mz->addr, 0, mz->len); 448 449 hw->shared = mz->addr; 450 hw->sharedPA = mz->iova; 451 452 /* 453 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 454 * on current socket. 455 * 456 * We cannot reuse this memzone from previous allocation as its size 457 * depends on the number of tx and rx queues, which could be different 458 * from one config to another. 459 */ 460 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 461 VMXNET3_QUEUE_DESC_ALIGN, 0); 462 if (mz == NULL) { 463 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 464 return -ENOMEM; 465 } 466 memset(mz->addr, 0, mz->len); 467 468 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 469 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 470 471 hw->queueDescPA = mz->iova; 472 hw->queue_desc_len = (uint16_t)size; 473 474 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 475 /* Allocate memory structure for UPT1_RSSConf and configure */ 476 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 477 "rss_conf", rte_socket_id(), 478 RTE_CACHE_LINE_SIZE, 1); 479 if (mz == NULL) { 480 PMD_INIT_LOG(ERR, 481 "ERROR: Creating rss_conf structure zone"); 482 return -ENOMEM; 483 } 484 memset(mz->addr, 0, mz->len); 485 486 hw->rss_conf = mz->addr; 487 hw->rss_confPA = mz->iova; 488 } 489 490 return 0; 491 } 492 493 static void 494 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 495 { 496 uint32_t val; 497 498 PMD_INIT_LOG(DEBUG, 499 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 500 addr[0], addr[1], addr[2], 501 addr[3], addr[4], addr[5]); 502 503 memcpy(&val, addr, 4); 504 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 505 506 memcpy(&val, addr + 4, 2); 507 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 508 } 509 510 static int 511 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 512 { 513 struct vmxnet3_hw *hw = dev->data->dev_private; 514 Vmxnet3_DriverShared *shared = hw->shared; 515 Vmxnet3_CmdInfo *cmdInfo; 516 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 517 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 518 uint32_t num, i, j, size; 519 520 if (hw->memRegsPA == 0) { 521 const struct rte_memzone *mz; 522 523 size = sizeof(Vmxnet3_MemRegs) + 524 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 525 sizeof(Vmxnet3_MemoryRegion); 526 527 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 528 1); 529 if (mz == NULL) { 530 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 531 return -ENOMEM; 532 } 533 memset(mz->addr, 0, mz->len); 534 hw->memRegs = mz->addr; 535 hw->memRegsPA = mz->iova; 536 } 537 538 num = hw->num_rx_queues; 539 540 for (i = 0; i < num; i++) { 541 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 542 543 mp[i] = rxq->mp; 544 index[i] = 1 << i; 545 } 546 547 /* 548 * The same mempool could be used by multiple queues. In such a case, 549 * remove duplicate mempool entries. Only one entry is kept with 550 * bitmask indicating queues that are using this mempool. 551 */ 552 for (i = 1; i < num; i++) { 553 for (j = 0; j < i; j++) { 554 if (mp[i] == mp[j]) { 555 mp[i] = NULL; 556 index[j] |= 1 << i; 557 break; 558 } 559 } 560 } 561 562 j = 0; 563 for (i = 0; i < num; i++) { 564 if (mp[i] == NULL) 565 continue; 566 567 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 568 569 mr->startPA = 570 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 571 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 572 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 573 mr->txQueueBits = index[i]; 574 mr->rxQueueBits = index[i]; 575 576 PMD_INIT_LOG(INFO, 577 "index: %u startPA: %" PRIu64 " length: %u, " 578 "rxBits: %x", 579 j, mr->startPA, mr->length, mr->rxQueueBits); 580 j++; 581 } 582 hw->memRegs->numRegs = j; 583 PMD_INIT_LOG(INFO, "numRegs: %u", j); 584 585 size = sizeof(Vmxnet3_MemRegs) + 586 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 587 588 cmdInfo = &shared->cu.cmdInfo; 589 cmdInfo->varConf.confVer = 1; 590 cmdInfo->varConf.confLen = size; 591 cmdInfo->varConf.confPA = hw->memRegsPA; 592 593 return 0; 594 } 595 596 static int 597 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 598 { 599 struct rte_eth_conf port_conf = dev->data->dev_conf; 600 struct vmxnet3_hw *hw = dev->data->dev_private; 601 uint32_t mtu = dev->data->mtu; 602 Vmxnet3_DriverShared *shared = hw->shared; 603 Vmxnet3_DSDevRead *devRead = &shared->devRead; 604 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 605 uint32_t i; 606 int ret; 607 608 hw->mtu = mtu; 609 610 shared->magic = VMXNET3_REV1_MAGIC; 611 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 612 613 /* Setting up Guest OS information */ 614 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 615 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 616 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 617 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 618 devRead->misc.driverInfo.uptVerSpt = 1; 619 620 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 621 devRead->misc.queueDescPA = hw->queueDescPA; 622 devRead->misc.queueDescLen = hw->queue_desc_len; 623 devRead->misc.numTxQueues = hw->num_tx_queues; 624 devRead->misc.numRxQueues = hw->num_rx_queues; 625 626 /* 627 * Set number of interrupts to 1 628 * PMD by default disables all the interrupts but this is MUST 629 * to activate device. It needs at least one interrupt for 630 * link events to handle 631 */ 632 hw->num_intrs = devRead->intrConf.numIntrs = 1; 633 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 634 635 for (i = 0; i < hw->num_tx_queues; i++) { 636 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 637 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 638 639 txq->shared = &hw->tqd_start[i]; 640 641 tqd->ctrl.txNumDeferred = 0; 642 tqd->ctrl.txThreshold = 1; 643 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 644 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 645 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 646 647 tqd->conf.txRingSize = txq->cmd_ring.size; 648 tqd->conf.compRingSize = txq->comp_ring.size; 649 tqd->conf.dataRingSize = txq->data_ring.size; 650 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 651 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 652 tqd->status.stopped = TRUE; 653 tqd->status.error = 0; 654 memset(&tqd->stats, 0, sizeof(tqd->stats)); 655 } 656 657 for (i = 0; i < hw->num_rx_queues; i++) { 658 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 659 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 660 661 rxq->shared = &hw->rqd_start[i]; 662 663 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 664 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 665 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 666 667 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 668 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 669 rqd->conf.compRingSize = rxq->comp_ring.size; 670 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 671 if (VMXNET3_VERSION_GE_3(hw)) { 672 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 673 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 674 } 675 rqd->status.stopped = TRUE; 676 rqd->status.error = 0; 677 memset(&rqd->stats, 0, sizeof(rqd->stats)); 678 } 679 680 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 681 devRead->rxFilterConf.rxMode = 0; 682 683 /* Setting up feature flags */ 684 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 685 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 686 687 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 688 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 689 devRead->misc.maxNumRxSG = 0; 690 } 691 692 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 693 ret = vmxnet3_rss_configure(dev); 694 if (ret != VMXNET3_SUCCESS) 695 return ret; 696 697 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 698 devRead->rssConfDesc.confVer = 1; 699 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 700 devRead->rssConfDesc.confPA = hw->rss_confPA; 701 } 702 703 ret = vmxnet3_dev_vlan_offload_set(dev, 704 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 705 if (ret) 706 return ret; 707 708 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 709 710 return VMXNET3_SUCCESS; 711 } 712 713 /* 714 * Configure device link speed and setup link. 715 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 716 * It returns 0 on success. 717 */ 718 static int 719 vmxnet3_dev_start(struct rte_eth_dev *dev) 720 { 721 int ret; 722 struct vmxnet3_hw *hw = dev->data->dev_private; 723 724 PMD_INIT_FUNC_TRACE(); 725 726 /* Save stats before it is reset by CMD_ACTIVATE */ 727 vmxnet3_hw_stats_save(hw); 728 729 ret = vmxnet3_setup_driver_shared(dev); 730 if (ret != VMXNET3_SUCCESS) 731 return ret; 732 733 /* check if lsc interrupt feature is enabled */ 734 if (dev->data->dev_conf.intr_conf.lsc) { 735 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 736 737 /* Setup interrupt callback */ 738 rte_intr_callback_register(&pci_dev->intr_handle, 739 vmxnet3_interrupt_handler, dev); 740 741 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 742 PMD_INIT_LOG(ERR, "interrupt enable failed"); 743 return -EIO; 744 } 745 } 746 747 /* Exchange shared data with device */ 748 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 749 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 750 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 751 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 752 753 /* Activate device by register write */ 754 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 755 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 756 757 if (ret != 0) { 758 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 759 return -EINVAL; 760 } 761 762 /* Setup memory region for rx buffers */ 763 ret = vmxnet3_dev_setup_memreg(dev); 764 if (ret == 0) { 765 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 766 VMXNET3_CMD_REGISTER_MEMREGS); 767 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 768 if (ret != 0) 769 PMD_INIT_LOG(DEBUG, 770 "Failed in setup memory region cmd\n"); 771 ret = 0; 772 } else { 773 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 774 } 775 776 if (VMXNET3_VERSION_GE_4(hw) && 777 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 778 /* Check for additional RSS */ 779 ret = vmxnet3_v4_rss_configure(dev); 780 if (ret != VMXNET3_SUCCESS) { 781 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 782 return ret; 783 } 784 } 785 786 /* Disable interrupts */ 787 vmxnet3_disable_intr(hw); 788 789 /* 790 * Load RX queues with blank mbufs and update next2fill index for device 791 * Update RxMode of the device 792 */ 793 ret = vmxnet3_dev_rxtx_init(dev); 794 if (ret != VMXNET3_SUCCESS) { 795 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 796 return ret; 797 } 798 799 hw->adapter_stopped = FALSE; 800 801 /* Setting proper Rx Mode and issue Rx Mode Update command */ 802 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 803 804 if (dev->data->dev_conf.intr_conf.lsc) { 805 vmxnet3_enable_intr(hw); 806 807 /* 808 * Update link state from device since this won't be 809 * done upon starting with lsc in use. This is done 810 * only after enabling interrupts to avoid any race 811 * where the link state could change without an 812 * interrupt being fired. 813 */ 814 __vmxnet3_dev_link_update(dev, 0); 815 } 816 817 return VMXNET3_SUCCESS; 818 } 819 820 /* 821 * Stop device: disable rx and tx functions to allow for reconfiguring. 822 */ 823 static void 824 vmxnet3_dev_stop(struct rte_eth_dev *dev) 825 { 826 struct rte_eth_link link; 827 struct vmxnet3_hw *hw = dev->data->dev_private; 828 829 PMD_INIT_FUNC_TRACE(); 830 831 if (hw->adapter_stopped == 1) { 832 PMD_INIT_LOG(DEBUG, "Device already stopped."); 833 return; 834 } 835 836 /* disable interrupts */ 837 vmxnet3_disable_intr(hw); 838 839 if (dev->data->dev_conf.intr_conf.lsc) { 840 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 841 842 rte_intr_disable(&pci_dev->intr_handle); 843 844 rte_intr_callback_unregister(&pci_dev->intr_handle, 845 vmxnet3_interrupt_handler, dev); 846 } 847 848 /* quiesce the device first */ 849 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 850 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 851 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 852 853 /* reset the device */ 854 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 855 PMD_INIT_LOG(DEBUG, "Device reset."); 856 857 vmxnet3_dev_clear_queues(dev); 858 859 /* Clear recorded link status */ 860 memset(&link, 0, sizeof(link)); 861 link.link_duplex = ETH_LINK_FULL_DUPLEX; 862 link.link_speed = ETH_SPEED_NUM_10G; 863 link.link_autoneg = ETH_LINK_FIXED; 864 rte_eth_linkstatus_set(dev, &link); 865 866 hw->adapter_stopped = 1; 867 } 868 869 static void 870 vmxnet3_free_queues(struct rte_eth_dev *dev) 871 { 872 int i; 873 874 PMD_INIT_FUNC_TRACE(); 875 876 for (i = 0; i < dev->data->nb_rx_queues; i++) { 877 void *rxq = dev->data->rx_queues[i]; 878 879 vmxnet3_dev_rx_queue_release(rxq); 880 } 881 dev->data->nb_rx_queues = 0; 882 883 for (i = 0; i < dev->data->nb_tx_queues; i++) { 884 void *txq = dev->data->tx_queues[i]; 885 886 vmxnet3_dev_tx_queue_release(txq); 887 } 888 dev->data->nb_tx_queues = 0; 889 } 890 891 /* 892 * Reset and stop device. 893 */ 894 static void 895 vmxnet3_dev_close(struct rte_eth_dev *dev) 896 { 897 PMD_INIT_FUNC_TRACE(); 898 899 vmxnet3_dev_stop(dev); 900 vmxnet3_free_queues(dev); 901 } 902 903 static void 904 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 905 struct UPT1_TxStats *res) 906 { 907 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 908 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 909 (h)->saved_tx_stats[(i)].f) 910 911 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 912 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 913 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 914 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 915 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 916 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 917 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 918 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 919 920 #undef VMXNET3_UPDATE_TX_STAT 921 } 922 923 static void 924 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 925 struct UPT1_RxStats *res) 926 { 927 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 928 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 929 (h)->saved_rx_stats[(i)].f) 930 931 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 932 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 933 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 934 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 935 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 936 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 937 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 938 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 939 940 #undef VMXNET3_UPDATE_RX_STAT 941 } 942 943 static void 944 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 945 struct UPT1_TxStats *res) 946 { 947 vmxnet3_hw_tx_stats_get(hw, q, res); 948 949 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 950 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 951 952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 953 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 954 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 955 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 956 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 957 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 958 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 959 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 960 961 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 962 } 963 964 static void 965 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 966 struct UPT1_RxStats *res) 967 { 968 vmxnet3_hw_rx_stats_get(hw, q, res); 969 970 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 971 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 972 973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 974 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 975 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 976 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 977 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 978 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 979 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 980 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 981 982 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 983 } 984 985 static void 986 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 987 { 988 unsigned int i; 989 990 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 991 992 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 993 994 for (i = 0; i < hw->num_tx_queues; i++) 995 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 996 for (i = 0; i < hw->num_rx_queues; i++) 997 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 998 } 999 1000 static int 1001 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 1002 struct rte_eth_xstat_name *xstats_names, 1003 unsigned int n) 1004 { 1005 unsigned int i, t, count = 0; 1006 unsigned int nstats = 1007 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1008 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1009 1010 if (!xstats_names || n < nstats) 1011 return nstats; 1012 1013 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1014 if (!dev->data->rx_queues[i]) 1015 continue; 1016 1017 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1018 snprintf(xstats_names[count].name, 1019 sizeof(xstats_names[count].name), 1020 "rx_q%u_%s", i, 1021 vmxnet3_rxq_stat_strings[t].name); 1022 count++; 1023 } 1024 } 1025 1026 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1027 if (!dev->data->tx_queues[i]) 1028 continue; 1029 1030 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1031 snprintf(xstats_names[count].name, 1032 sizeof(xstats_names[count].name), 1033 "tx_q%u_%s", i, 1034 vmxnet3_txq_stat_strings[t].name); 1035 count++; 1036 } 1037 } 1038 1039 return count; 1040 } 1041 1042 static int 1043 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1044 unsigned int n) 1045 { 1046 unsigned int i, t, count = 0; 1047 unsigned int nstats = 1048 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1049 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1050 1051 if (n < nstats) 1052 return nstats; 1053 1054 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1055 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1056 1057 if (rxq == NULL) 1058 continue; 1059 1060 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1061 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1062 vmxnet3_rxq_stat_strings[t].offset); 1063 xstats[count].id = count; 1064 count++; 1065 } 1066 } 1067 1068 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1069 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1070 1071 if (txq == NULL) 1072 continue; 1073 1074 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1075 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1076 vmxnet3_txq_stat_strings[t].offset); 1077 xstats[count].id = count; 1078 count++; 1079 } 1080 } 1081 1082 return count; 1083 } 1084 1085 static int 1086 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1087 { 1088 unsigned int i; 1089 struct vmxnet3_hw *hw = dev->data->dev_private; 1090 struct UPT1_TxStats txStats; 1091 struct UPT1_RxStats rxStats; 1092 1093 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1094 1095 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1096 for (i = 0; i < hw->num_tx_queues; i++) { 1097 vmxnet3_tx_stats_get(hw, i, &txStats); 1098 1099 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1100 txStats.mcastPktsTxOK + 1101 txStats.bcastPktsTxOK; 1102 1103 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1104 txStats.mcastBytesTxOK + 1105 txStats.bcastBytesTxOK; 1106 1107 stats->opackets += stats->q_opackets[i]; 1108 stats->obytes += stats->q_obytes[i]; 1109 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1110 } 1111 1112 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1113 for (i = 0; i < hw->num_rx_queues; i++) { 1114 vmxnet3_rx_stats_get(hw, i, &rxStats); 1115 1116 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1117 rxStats.mcastPktsRxOK + 1118 rxStats.bcastPktsRxOK; 1119 1120 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1121 rxStats.mcastBytesRxOK + 1122 rxStats.bcastBytesRxOK; 1123 1124 stats->ipackets += stats->q_ipackets[i]; 1125 stats->ibytes += stats->q_ibytes[i]; 1126 1127 stats->q_errors[i] = rxStats.pktsRxError; 1128 stats->ierrors += rxStats.pktsRxError; 1129 stats->imissed += rxStats.pktsRxOutOfBuf; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static int 1136 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1137 { 1138 unsigned int i; 1139 struct vmxnet3_hw *hw = dev->data->dev_private; 1140 struct UPT1_TxStats txStats = {0}; 1141 struct UPT1_RxStats rxStats = {0}; 1142 1143 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1144 1145 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1146 1147 for (i = 0; i < hw->num_tx_queues; i++) { 1148 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1149 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1150 sizeof(hw->snapshot_tx_stats[0])); 1151 } 1152 for (i = 0; i < hw->num_rx_queues; i++) { 1153 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1154 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1155 sizeof(hw->snapshot_rx_stats[0])); 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int 1162 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1163 struct rte_eth_dev_info *dev_info) 1164 { 1165 struct vmxnet3_hw *hw = dev->data->dev_private; 1166 1167 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1168 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1169 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1170 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1171 dev_info->min_mtu = VMXNET3_MIN_MTU; 1172 dev_info->max_mtu = VMXNET3_MAX_MTU; 1173 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1174 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1175 1176 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1177 1178 if (VMXNET3_VERSION_GE_4(hw)) { 1179 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1180 } 1181 1182 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1183 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1184 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1185 .nb_align = 1, 1186 }; 1187 1188 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1189 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1190 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1191 .nb_align = 1, 1192 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1193 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1194 }; 1195 1196 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1197 dev_info->rx_queue_offload_capa = 0; 1198 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1199 dev_info->tx_queue_offload_capa = 0; 1200 1201 return 0; 1202 } 1203 1204 static const uint32_t * 1205 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1206 { 1207 static const uint32_t ptypes[] = { 1208 RTE_PTYPE_L3_IPV4_EXT, 1209 RTE_PTYPE_L3_IPV4, 1210 RTE_PTYPE_UNKNOWN 1211 }; 1212 1213 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1214 return ptypes; 1215 return NULL; 1216 } 1217 1218 static int 1219 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu) 1220 { 1221 if (dev->data->dev_started) { 1222 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU", 1223 dev->data->port_id); 1224 return -EBUSY; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int 1231 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1232 { 1233 struct vmxnet3_hw *hw = dev->data->dev_private; 1234 1235 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1236 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1237 return 0; 1238 } 1239 1240 /* return 0 means link status changed, -1 means not changed */ 1241 static int 1242 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1243 __rte_unused int wait_to_complete) 1244 { 1245 struct vmxnet3_hw *hw = dev->data->dev_private; 1246 struct rte_eth_link link; 1247 uint32_t ret; 1248 1249 memset(&link, 0, sizeof(link)); 1250 1251 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1252 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1253 1254 if (ret & 0x1) 1255 link.link_status = ETH_LINK_UP; 1256 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1257 link.link_speed = ETH_SPEED_NUM_10G; 1258 link.link_autoneg = ETH_LINK_FIXED; 1259 1260 return rte_eth_linkstatus_set(dev, &link); 1261 } 1262 1263 static int 1264 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1265 { 1266 /* Link status doesn't change for stopped dev */ 1267 if (dev->data->dev_started == 0) 1268 return -1; 1269 1270 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1271 } 1272 1273 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1274 static void 1275 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1276 { 1277 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1278 1279 if (set) 1280 rxConf->rxMode = rxConf->rxMode | feature; 1281 else 1282 rxConf->rxMode = rxConf->rxMode & (~feature); 1283 1284 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1285 } 1286 1287 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1288 static int 1289 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1290 { 1291 struct vmxnet3_hw *hw = dev->data->dev_private; 1292 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1293 1294 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1295 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1296 1297 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1298 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1299 1300 return 0; 1301 } 1302 1303 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1304 static int 1305 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1306 { 1307 struct vmxnet3_hw *hw = dev->data->dev_private; 1308 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1309 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1310 1311 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1312 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1313 else 1314 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1315 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1316 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1317 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1318 1319 return 0; 1320 } 1321 1322 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1323 static int 1324 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1325 { 1326 struct vmxnet3_hw *hw = dev->data->dev_private; 1327 1328 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1329 1330 return 0; 1331 } 1332 1333 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1334 static int 1335 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1336 { 1337 struct vmxnet3_hw *hw = dev->data->dev_private; 1338 1339 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1340 1341 return 0; 1342 } 1343 1344 /* Enable/disable filter on vlan */ 1345 static int 1346 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1347 { 1348 struct vmxnet3_hw *hw = dev->data->dev_private; 1349 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1350 uint32_t *vf_table = rxConf->vfTable; 1351 1352 /* save state for restore */ 1353 if (on) 1354 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1355 else 1356 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1357 1358 /* don't change active filter if in promiscuous mode */ 1359 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1360 return 0; 1361 1362 /* set in hardware */ 1363 if (on) 1364 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1365 else 1366 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1367 1368 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1369 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1370 return 0; 1371 } 1372 1373 static int 1374 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1375 { 1376 struct vmxnet3_hw *hw = dev->data->dev_private; 1377 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1378 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1379 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1380 1381 if (mask & ETH_VLAN_STRIP_MASK) { 1382 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1383 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1384 else 1385 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1386 1387 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1388 VMXNET3_CMD_UPDATE_FEATURE); 1389 } 1390 1391 if (mask & ETH_VLAN_FILTER_MASK) { 1392 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1393 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1394 else 1395 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1396 1397 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1398 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1399 } 1400 1401 return 0; 1402 } 1403 1404 static void 1405 vmxnet3_process_events(struct rte_eth_dev *dev) 1406 { 1407 struct vmxnet3_hw *hw = dev->data->dev_private; 1408 uint32_t events = hw->shared->ecr; 1409 1410 if (!events) 1411 return; 1412 1413 /* 1414 * ECR bits when written with 1b are cleared. Hence write 1415 * events back to ECR so that the bits which were set will be reset. 1416 */ 1417 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1418 1419 /* Check if link state has changed */ 1420 if (events & VMXNET3_ECR_LINK) { 1421 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1422 if (vmxnet3_dev_link_update(dev, 0) == 0) 1423 _rte_eth_dev_callback_process(dev, 1424 RTE_ETH_EVENT_INTR_LSC, 1425 NULL); 1426 } 1427 1428 /* Check if there is an error on xmit/recv queues */ 1429 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1430 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1431 VMXNET3_CMD_GET_QUEUE_STATUS); 1432 1433 if (hw->tqd_start->status.stopped) 1434 PMD_DRV_LOG(ERR, "tq error 0x%x", 1435 hw->tqd_start->status.error); 1436 1437 if (hw->rqd_start->status.stopped) 1438 PMD_DRV_LOG(ERR, "rq error 0x%x", 1439 hw->rqd_start->status.error); 1440 1441 /* Reset the device */ 1442 /* Have to reset the device */ 1443 } 1444 1445 if (events & VMXNET3_ECR_DIC) 1446 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1447 1448 if (events & VMXNET3_ECR_DEBUG) 1449 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1450 } 1451 1452 static void 1453 vmxnet3_interrupt_handler(void *param) 1454 { 1455 struct rte_eth_dev *dev = param; 1456 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1457 1458 vmxnet3_process_events(dev); 1459 1460 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1461 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1462 } 1463 1464 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1465 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1466 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1467 1468 RTE_INIT(vmxnet3_init_log) 1469 { 1470 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1471 if (vmxnet3_logtype_init >= 0) 1472 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1473 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1474 if (vmxnet3_logtype_driver >= 0) 1475 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1476 } 1477