1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 60 DEV_RX_OFFLOAD_RSS_HASH) 61 62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 65 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 67 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 74 int wait_to_complete); 75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 76 int wait_to_complete); 77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 79 struct rte_eth_stats *stats); 80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 82 struct rte_eth_xstat_name *xstats, 83 unsigned int n); 84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 85 struct rte_eth_xstat *xstats, unsigned int n); 86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 87 struct rte_eth_dev_info *dev_info); 88 static const uint32_t * 89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 90 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 92 uint16_t vid, int on); 93 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 94 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 95 struct rte_ether_addr *mac_addr); 96 static void vmxnet3_interrupt_handler(void *param); 97 98 /* 99 * The set of PCI devices this driver supports 100 */ 101 #define VMWARE_PCI_VENDOR_ID 0x15AD 102 #define VMWARE_DEV_ID_VMXNET3 0x07B0 103 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 104 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 105 { .vendor_id = 0, /* sentinel */ }, 106 }; 107 108 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 109 .dev_configure = vmxnet3_dev_configure, 110 .dev_start = vmxnet3_dev_start, 111 .dev_stop = vmxnet3_dev_stop, 112 .dev_close = vmxnet3_dev_close, 113 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 114 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 115 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 116 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 117 .link_update = vmxnet3_dev_link_update, 118 .stats_get = vmxnet3_dev_stats_get, 119 .xstats_get_names = vmxnet3_dev_xstats_get_names, 120 .xstats_get = vmxnet3_dev_xstats_get, 121 .stats_reset = vmxnet3_dev_stats_reset, 122 .mac_addr_set = vmxnet3_mac_addr_set, 123 .dev_infos_get = vmxnet3_dev_info_get, 124 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 125 .mtu_set = vmxnet3_dev_mtu_set, 126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 129 .rx_queue_release = vmxnet3_dev_rx_queue_release, 130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 131 .tx_queue_release = vmxnet3_dev_tx_queue_release, 132 }; 133 134 struct vmxnet3_xstats_name_off { 135 char name[RTE_ETH_XSTATS_NAME_SIZE]; 136 unsigned int offset; 137 }; 138 139 /* tx_qX_ is prepended to the name string here */ 140 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 141 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 142 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 143 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 144 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 145 }; 146 147 /* rx_qX_ is prepended to the name string here */ 148 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 149 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 150 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 151 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 152 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 153 }; 154 155 static const struct rte_memzone * 156 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 157 const char *post_string, int socket_id, 158 uint16_t align, bool reuse) 159 { 160 char z_name[RTE_MEMZONE_NAMESIZE]; 161 const struct rte_memzone *mz; 162 163 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 164 dev->data->port_id, post_string); 165 166 mz = rte_memzone_lookup(z_name); 167 if (!reuse) { 168 if (mz) 169 rte_memzone_free(mz); 170 return rte_memzone_reserve_aligned(z_name, size, socket_id, 171 RTE_MEMZONE_IOVA_CONTIG, align); 172 } 173 174 if (mz) 175 return mz; 176 177 return rte_memzone_reserve_aligned(z_name, size, socket_id, 178 RTE_MEMZONE_IOVA_CONTIG, align); 179 } 180 181 /* 182 * This function is based on vmxnet3_disable_intr() 183 */ 184 static void 185 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 186 { 187 int i; 188 189 PMD_INIT_FUNC_TRACE(); 190 191 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 192 for (i = 0; i < hw->num_intrs; i++) 193 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 194 } 195 196 static void 197 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 198 { 199 int i; 200 201 PMD_INIT_FUNC_TRACE(); 202 203 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 204 for (i = 0; i < hw->num_intrs; i++) 205 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 206 } 207 208 /* 209 * Gets tx data ring descriptor size. 210 */ 211 static uint16_t 212 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 213 { 214 uint16 txdata_desc_size; 215 216 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 217 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 218 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 219 220 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 221 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 222 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 223 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 224 } 225 226 /* 227 * It returns 0 on success. 228 */ 229 static int 230 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 231 { 232 struct rte_pci_device *pci_dev; 233 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 234 uint32_t mac_hi, mac_lo, ver; 235 struct rte_eth_link link; 236 237 PMD_INIT_FUNC_TRACE(); 238 239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 243 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 244 245 /* 246 * for secondary processes, we don't initialize any further as primary 247 * has already done this work. 248 */ 249 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 250 return 0; 251 252 rte_eth_copy_pci_info(eth_dev, pci_dev); 253 254 /* Vendor and Device ID need to be set before init of shared code */ 255 hw->device_id = pci_dev->id.device_id; 256 hw->vendor_id = pci_dev->id.vendor_id; 257 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 258 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 259 260 hw->num_rx_queues = 1; 261 hw->num_tx_queues = 1; 262 hw->bufs_per_pkt = 1; 263 264 /* Check h/w version compatibility with driver. */ 265 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 266 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 267 268 if (ver & (1 << VMXNET3_REV_4)) { 269 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 270 1 << VMXNET3_REV_4); 271 hw->version = VMXNET3_REV_4 + 1; 272 } else if (ver & (1 << VMXNET3_REV_3)) { 273 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 274 1 << VMXNET3_REV_3); 275 hw->version = VMXNET3_REV_3 + 1; 276 } else if (ver & (1 << VMXNET3_REV_2)) { 277 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 278 1 << VMXNET3_REV_2); 279 hw->version = VMXNET3_REV_2 + 1; 280 } else if (ver & (1 << VMXNET3_REV_1)) { 281 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 282 1 << VMXNET3_REV_1); 283 hw->version = VMXNET3_REV_1 + 1; 284 } else { 285 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 286 return -EIO; 287 } 288 289 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 290 291 /* Check UPT version compatibility with driver. */ 292 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 293 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 294 if (ver & 0x1) 295 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 296 else { 297 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 298 return -EIO; 299 } 300 301 /* Getting MAC Address */ 302 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 303 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 304 memcpy(hw->perm_addr, &mac_lo, 4); 305 memcpy(hw->perm_addr + 4, &mac_hi, 2); 306 307 /* Allocate memory for storing MAC addresses */ 308 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 309 VMXNET3_MAX_MAC_ADDRS, 0); 310 if (eth_dev->data->mac_addrs == NULL) { 311 PMD_INIT_LOG(ERR, 312 "Failed to allocate %d bytes needed to store MAC addresses", 313 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 314 return -ENOMEM; 315 } 316 /* Copy the permanent MAC address */ 317 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 318 ð_dev->data->mac_addrs[0]); 319 320 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 321 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 322 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 323 324 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 325 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 326 327 /* Put device in Quiesce Mode */ 328 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 329 330 /* allow untagged pkts */ 331 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 332 333 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 334 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 335 336 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 337 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 338 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 339 hw->rxdata_desc_size); 340 341 /* clear shadow stats */ 342 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 343 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 344 345 /* clear snapshot stats */ 346 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 347 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 348 349 /* set the initial link status */ 350 memset(&link, 0, sizeof(link)); 351 link.link_duplex = ETH_LINK_FULL_DUPLEX; 352 link.link_speed = ETH_SPEED_NUM_10G; 353 link.link_autoneg = ETH_LINK_FIXED; 354 rte_eth_linkstatus_set(eth_dev, &link); 355 356 return 0; 357 } 358 359 static int 360 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 361 { 362 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 363 364 PMD_INIT_FUNC_TRACE(); 365 366 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 367 return 0; 368 369 if (hw->adapter_stopped == 0) { 370 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 371 return -EBUSY; 372 } 373 374 eth_dev->dev_ops = NULL; 375 eth_dev->rx_pkt_burst = NULL; 376 eth_dev->tx_pkt_burst = NULL; 377 eth_dev->tx_pkt_prepare = NULL; 378 379 return 0; 380 } 381 382 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 383 struct rte_pci_device *pci_dev) 384 { 385 return rte_eth_dev_pci_generic_probe(pci_dev, 386 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 387 } 388 389 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 390 { 391 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 392 } 393 394 static struct rte_pci_driver rte_vmxnet3_pmd = { 395 .id_table = pci_id_vmxnet3_map, 396 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 397 .probe = eth_vmxnet3_pci_probe, 398 .remove = eth_vmxnet3_pci_remove, 399 }; 400 401 static int 402 vmxnet3_dev_configure(struct rte_eth_dev *dev) 403 { 404 const struct rte_memzone *mz; 405 struct vmxnet3_hw *hw = dev->data->dev_private; 406 size_t size; 407 408 PMD_INIT_FUNC_TRACE(); 409 410 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 411 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 412 413 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 414 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 415 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 416 return -EINVAL; 417 } 418 419 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 420 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 421 return -EINVAL; 422 } 423 424 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 425 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 426 427 if (size > UINT16_MAX) 428 return -EINVAL; 429 430 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 431 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 432 433 /* 434 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 435 * on current socket 436 */ 437 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 438 "shared", rte_socket_id(), 8, 1); 439 440 if (mz == NULL) { 441 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 442 return -ENOMEM; 443 } 444 memset(mz->addr, 0, mz->len); 445 446 hw->shared = mz->addr; 447 hw->sharedPA = mz->iova; 448 449 /* 450 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 451 * on current socket. 452 * 453 * We cannot reuse this memzone from previous allocation as its size 454 * depends on the number of tx and rx queues, which could be different 455 * from one config to another. 456 */ 457 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 458 VMXNET3_QUEUE_DESC_ALIGN, 0); 459 if (mz == NULL) { 460 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 461 return -ENOMEM; 462 } 463 memset(mz->addr, 0, mz->len); 464 465 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 466 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 467 468 hw->queueDescPA = mz->iova; 469 hw->queue_desc_len = (uint16_t)size; 470 471 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 472 /* Allocate memory structure for UPT1_RSSConf and configure */ 473 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 474 "rss_conf", rte_socket_id(), 475 RTE_CACHE_LINE_SIZE, 1); 476 if (mz == NULL) { 477 PMD_INIT_LOG(ERR, 478 "ERROR: Creating rss_conf structure zone"); 479 return -ENOMEM; 480 } 481 memset(mz->addr, 0, mz->len); 482 483 hw->rss_conf = mz->addr; 484 hw->rss_confPA = mz->iova; 485 } 486 487 return 0; 488 } 489 490 static void 491 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 492 { 493 uint32_t val; 494 495 PMD_INIT_LOG(DEBUG, 496 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 497 addr[0], addr[1], addr[2], 498 addr[3], addr[4], addr[5]); 499 500 memcpy(&val, addr, 4); 501 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 502 503 memcpy(&val, addr + 4, 2); 504 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 505 } 506 507 static int 508 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 509 { 510 struct vmxnet3_hw *hw = dev->data->dev_private; 511 Vmxnet3_DriverShared *shared = hw->shared; 512 Vmxnet3_CmdInfo *cmdInfo; 513 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 514 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 515 uint32_t num, i, j, size; 516 517 if (hw->memRegsPA == 0) { 518 const struct rte_memzone *mz; 519 520 size = sizeof(Vmxnet3_MemRegs) + 521 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 522 sizeof(Vmxnet3_MemoryRegion); 523 524 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 525 1); 526 if (mz == NULL) { 527 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 528 return -ENOMEM; 529 } 530 memset(mz->addr, 0, mz->len); 531 hw->memRegs = mz->addr; 532 hw->memRegsPA = mz->iova; 533 } 534 535 num = hw->num_rx_queues; 536 537 for (i = 0; i < num; i++) { 538 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 539 540 mp[i] = rxq->mp; 541 index[i] = 1 << i; 542 } 543 544 /* 545 * The same mempool could be used by multiple queues. In such a case, 546 * remove duplicate mempool entries. Only one entry is kept with 547 * bitmask indicating queues that are using this mempool. 548 */ 549 for (i = 1; i < num; i++) { 550 for (j = 0; j < i; j++) { 551 if (mp[i] == mp[j]) { 552 mp[i] = NULL; 553 index[j] |= 1 << i; 554 break; 555 } 556 } 557 } 558 559 j = 0; 560 for (i = 0; i < num; i++) { 561 if (mp[i] == NULL) 562 continue; 563 564 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 565 566 mr->startPA = 567 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 568 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 569 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 570 mr->txQueueBits = index[i]; 571 mr->rxQueueBits = index[i]; 572 573 PMD_INIT_LOG(INFO, 574 "index: %u startPA: %" PRIu64 " length: %u, " 575 "rxBits: %x", 576 j, mr->startPA, mr->length, mr->rxQueueBits); 577 j++; 578 } 579 hw->memRegs->numRegs = j; 580 PMD_INIT_LOG(INFO, "numRegs: %u", j); 581 582 size = sizeof(Vmxnet3_MemRegs) + 583 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 584 585 cmdInfo = &shared->cu.cmdInfo; 586 cmdInfo->varConf.confVer = 1; 587 cmdInfo->varConf.confLen = size; 588 cmdInfo->varConf.confPA = hw->memRegsPA; 589 590 return 0; 591 } 592 593 static int 594 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 595 { 596 struct rte_eth_conf port_conf = dev->data->dev_conf; 597 struct vmxnet3_hw *hw = dev->data->dev_private; 598 uint32_t mtu = dev->data->mtu; 599 Vmxnet3_DriverShared *shared = hw->shared; 600 Vmxnet3_DSDevRead *devRead = &shared->devRead; 601 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 602 uint32_t i; 603 int ret; 604 605 hw->mtu = mtu; 606 607 shared->magic = VMXNET3_REV1_MAGIC; 608 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 609 610 /* Setting up Guest OS information */ 611 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 612 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 613 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 614 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 615 devRead->misc.driverInfo.uptVerSpt = 1; 616 617 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 618 devRead->misc.queueDescPA = hw->queueDescPA; 619 devRead->misc.queueDescLen = hw->queue_desc_len; 620 devRead->misc.numTxQueues = hw->num_tx_queues; 621 devRead->misc.numRxQueues = hw->num_rx_queues; 622 623 /* 624 * Set number of interrupts to 1 625 * PMD by default disables all the interrupts but this is MUST 626 * to activate device. It needs at least one interrupt for 627 * link events to handle 628 */ 629 hw->num_intrs = devRead->intrConf.numIntrs = 1; 630 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 631 632 for (i = 0; i < hw->num_tx_queues; i++) { 633 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 634 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 635 636 txq->shared = &hw->tqd_start[i]; 637 638 tqd->ctrl.txNumDeferred = 0; 639 tqd->ctrl.txThreshold = 1; 640 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 641 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 642 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 643 644 tqd->conf.txRingSize = txq->cmd_ring.size; 645 tqd->conf.compRingSize = txq->comp_ring.size; 646 tqd->conf.dataRingSize = txq->data_ring.size; 647 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 648 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 649 tqd->status.stopped = TRUE; 650 tqd->status.error = 0; 651 memset(&tqd->stats, 0, sizeof(tqd->stats)); 652 } 653 654 for (i = 0; i < hw->num_rx_queues; i++) { 655 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 656 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 657 658 rxq->shared = &hw->rqd_start[i]; 659 660 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 661 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 662 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 663 664 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 665 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 666 rqd->conf.compRingSize = rxq->comp_ring.size; 667 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 668 if (VMXNET3_VERSION_GE_3(hw)) { 669 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 670 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 671 } 672 rqd->status.stopped = TRUE; 673 rqd->status.error = 0; 674 memset(&rqd->stats, 0, sizeof(rqd->stats)); 675 } 676 677 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 678 devRead->rxFilterConf.rxMode = 0; 679 680 /* Setting up feature flags */ 681 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 682 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 683 684 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 685 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 686 devRead->misc.maxNumRxSG = 0; 687 } 688 689 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 690 ret = vmxnet3_rss_configure(dev); 691 if (ret != VMXNET3_SUCCESS) 692 return ret; 693 694 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 695 devRead->rssConfDesc.confVer = 1; 696 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 697 devRead->rssConfDesc.confPA = hw->rss_confPA; 698 } 699 700 ret = vmxnet3_dev_vlan_offload_set(dev, 701 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 702 if (ret) 703 return ret; 704 705 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 706 707 return VMXNET3_SUCCESS; 708 } 709 710 /* 711 * Configure device link speed and setup link. 712 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 713 * It returns 0 on success. 714 */ 715 static int 716 vmxnet3_dev_start(struct rte_eth_dev *dev) 717 { 718 int ret; 719 struct vmxnet3_hw *hw = dev->data->dev_private; 720 721 PMD_INIT_FUNC_TRACE(); 722 723 /* Save stats before it is reset by CMD_ACTIVATE */ 724 vmxnet3_hw_stats_save(hw); 725 726 ret = vmxnet3_setup_driver_shared(dev); 727 if (ret != VMXNET3_SUCCESS) 728 return ret; 729 730 /* check if lsc interrupt feature is enabled */ 731 if (dev->data->dev_conf.intr_conf.lsc) { 732 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 733 734 /* Setup interrupt callback */ 735 rte_intr_callback_register(&pci_dev->intr_handle, 736 vmxnet3_interrupt_handler, dev); 737 738 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 739 PMD_INIT_LOG(ERR, "interrupt enable failed"); 740 return -EIO; 741 } 742 } 743 744 /* Exchange shared data with device */ 745 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 746 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 747 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 748 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 749 750 /* Activate device by register write */ 751 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 752 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 753 754 if (ret != 0) { 755 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 756 return -EINVAL; 757 } 758 759 /* Setup memory region for rx buffers */ 760 ret = vmxnet3_dev_setup_memreg(dev); 761 if (ret == 0) { 762 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 763 VMXNET3_CMD_REGISTER_MEMREGS); 764 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 765 if (ret != 0) 766 PMD_INIT_LOG(DEBUG, 767 "Failed in setup memory region cmd\n"); 768 ret = 0; 769 } else { 770 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 771 } 772 773 if (VMXNET3_VERSION_GE_4(hw) && 774 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 775 /* Check for additional RSS */ 776 ret = vmxnet3_v4_rss_configure(dev); 777 if (ret != VMXNET3_SUCCESS) { 778 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 779 return ret; 780 } 781 } 782 783 /* Disable interrupts */ 784 vmxnet3_disable_intr(hw); 785 786 /* 787 * Load RX queues with blank mbufs and update next2fill index for device 788 * Update RxMode of the device 789 */ 790 ret = vmxnet3_dev_rxtx_init(dev); 791 if (ret != VMXNET3_SUCCESS) { 792 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 793 return ret; 794 } 795 796 hw->adapter_stopped = FALSE; 797 798 /* Setting proper Rx Mode and issue Rx Mode Update command */ 799 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 800 801 if (dev->data->dev_conf.intr_conf.lsc) { 802 vmxnet3_enable_intr(hw); 803 804 /* 805 * Update link state from device since this won't be 806 * done upon starting with lsc in use. This is done 807 * only after enabling interrupts to avoid any race 808 * where the link state could change without an 809 * interrupt being fired. 810 */ 811 __vmxnet3_dev_link_update(dev, 0); 812 } 813 814 return VMXNET3_SUCCESS; 815 } 816 817 /* 818 * Stop device: disable rx and tx functions to allow for reconfiguring. 819 */ 820 static void 821 vmxnet3_dev_stop(struct rte_eth_dev *dev) 822 { 823 struct rte_eth_link link; 824 struct vmxnet3_hw *hw = dev->data->dev_private; 825 826 PMD_INIT_FUNC_TRACE(); 827 828 if (hw->adapter_stopped == 1) { 829 PMD_INIT_LOG(DEBUG, "Device already stopped."); 830 return; 831 } 832 833 /* disable interrupts */ 834 vmxnet3_disable_intr(hw); 835 836 if (dev->data->dev_conf.intr_conf.lsc) { 837 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 838 839 rte_intr_disable(&pci_dev->intr_handle); 840 841 rte_intr_callback_unregister(&pci_dev->intr_handle, 842 vmxnet3_interrupt_handler, dev); 843 } 844 845 /* quiesce the device first */ 846 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 847 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 848 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 849 850 /* reset the device */ 851 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 852 PMD_INIT_LOG(DEBUG, "Device reset."); 853 854 vmxnet3_dev_clear_queues(dev); 855 856 /* Clear recorded link status */ 857 memset(&link, 0, sizeof(link)); 858 link.link_duplex = ETH_LINK_FULL_DUPLEX; 859 link.link_speed = ETH_SPEED_NUM_10G; 860 link.link_autoneg = ETH_LINK_FIXED; 861 rte_eth_linkstatus_set(dev, &link); 862 863 hw->adapter_stopped = 1; 864 } 865 866 static void 867 vmxnet3_free_queues(struct rte_eth_dev *dev) 868 { 869 int i; 870 871 PMD_INIT_FUNC_TRACE(); 872 873 for (i = 0; i < dev->data->nb_rx_queues; i++) { 874 void *rxq = dev->data->rx_queues[i]; 875 876 vmxnet3_dev_rx_queue_release(rxq); 877 } 878 dev->data->nb_rx_queues = 0; 879 880 for (i = 0; i < dev->data->nb_tx_queues; i++) { 881 void *txq = dev->data->tx_queues[i]; 882 883 vmxnet3_dev_tx_queue_release(txq); 884 } 885 dev->data->nb_tx_queues = 0; 886 } 887 888 /* 889 * Reset and stop device. 890 */ 891 static void 892 vmxnet3_dev_close(struct rte_eth_dev *dev) 893 { 894 PMD_INIT_FUNC_TRACE(); 895 896 vmxnet3_dev_stop(dev); 897 vmxnet3_free_queues(dev); 898 } 899 900 static void 901 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 902 struct UPT1_TxStats *res) 903 { 904 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 905 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 906 (h)->saved_tx_stats[(i)].f) 907 908 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 909 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 910 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 911 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 912 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 913 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 914 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 915 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 916 917 #undef VMXNET3_UPDATE_TX_STAT 918 } 919 920 static void 921 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 922 struct UPT1_RxStats *res) 923 { 924 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 925 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 926 (h)->saved_rx_stats[(i)].f) 927 928 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 929 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 930 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 931 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 932 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 933 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 934 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 935 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 936 937 #undef VMXNET3_UPDATE_RX_STAT 938 } 939 940 static void 941 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 942 struct UPT1_TxStats *res) 943 { 944 vmxnet3_hw_tx_stats_get(hw, q, res); 945 946 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 947 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 948 949 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 950 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 951 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 953 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 954 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 955 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 956 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 957 958 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 959 } 960 961 static void 962 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 963 struct UPT1_RxStats *res) 964 { 965 vmxnet3_hw_rx_stats_get(hw, q, res); 966 967 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 968 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 969 970 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 971 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 972 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 974 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 975 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 976 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 977 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 978 979 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 980 } 981 982 static void 983 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 984 { 985 unsigned int i; 986 987 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 988 989 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 990 991 for (i = 0; i < hw->num_tx_queues; i++) 992 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 993 for (i = 0; i < hw->num_rx_queues; i++) 994 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 995 } 996 997 static int 998 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 999 struct rte_eth_xstat_name *xstats_names, 1000 unsigned int n) 1001 { 1002 unsigned int i, t, count = 0; 1003 unsigned int nstats = 1004 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1005 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1006 1007 if (!xstats_names || n < nstats) 1008 return nstats; 1009 1010 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1011 if (!dev->data->rx_queues[i]) 1012 continue; 1013 1014 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1015 snprintf(xstats_names[count].name, 1016 sizeof(xstats_names[count].name), 1017 "rx_q%u_%s", i, 1018 vmxnet3_rxq_stat_strings[t].name); 1019 count++; 1020 } 1021 } 1022 1023 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1024 if (!dev->data->tx_queues[i]) 1025 continue; 1026 1027 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1028 snprintf(xstats_names[count].name, 1029 sizeof(xstats_names[count].name), 1030 "tx_q%u_%s", i, 1031 vmxnet3_txq_stat_strings[t].name); 1032 count++; 1033 } 1034 } 1035 1036 return count; 1037 } 1038 1039 static int 1040 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1041 unsigned int n) 1042 { 1043 unsigned int i, t, count = 0; 1044 unsigned int nstats = 1045 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1046 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1047 1048 if (n < nstats) 1049 return nstats; 1050 1051 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1052 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1053 1054 if (rxq == NULL) 1055 continue; 1056 1057 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1058 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1059 vmxnet3_rxq_stat_strings[t].offset); 1060 xstats[count].id = count; 1061 count++; 1062 } 1063 } 1064 1065 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1066 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1067 1068 if (txq == NULL) 1069 continue; 1070 1071 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1072 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1073 vmxnet3_txq_stat_strings[t].offset); 1074 xstats[count].id = count; 1075 count++; 1076 } 1077 } 1078 1079 return count; 1080 } 1081 1082 static int 1083 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1084 { 1085 unsigned int i; 1086 struct vmxnet3_hw *hw = dev->data->dev_private; 1087 struct UPT1_TxStats txStats; 1088 struct UPT1_RxStats rxStats; 1089 1090 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1091 1092 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1093 for (i = 0; i < hw->num_tx_queues; i++) { 1094 vmxnet3_tx_stats_get(hw, i, &txStats); 1095 1096 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1097 txStats.mcastPktsTxOK + 1098 txStats.bcastPktsTxOK; 1099 1100 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1101 txStats.mcastBytesTxOK + 1102 txStats.bcastBytesTxOK; 1103 1104 stats->opackets += stats->q_opackets[i]; 1105 stats->obytes += stats->q_obytes[i]; 1106 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1107 } 1108 1109 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1110 for (i = 0; i < hw->num_rx_queues; i++) { 1111 vmxnet3_rx_stats_get(hw, i, &rxStats); 1112 1113 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1114 rxStats.mcastPktsRxOK + 1115 rxStats.bcastPktsRxOK; 1116 1117 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1118 rxStats.mcastBytesRxOK + 1119 rxStats.bcastBytesRxOK; 1120 1121 stats->ipackets += stats->q_ipackets[i]; 1122 stats->ibytes += stats->q_ibytes[i]; 1123 1124 stats->q_errors[i] = rxStats.pktsRxError; 1125 stats->ierrors += rxStats.pktsRxError; 1126 stats->imissed += rxStats.pktsRxOutOfBuf; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int 1133 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1134 { 1135 unsigned int i; 1136 struct vmxnet3_hw *hw = dev->data->dev_private; 1137 struct UPT1_TxStats txStats = {0}; 1138 struct UPT1_RxStats rxStats = {0}; 1139 1140 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1141 1142 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1143 1144 for (i = 0; i < hw->num_tx_queues; i++) { 1145 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1146 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1147 sizeof(hw->snapshot_tx_stats[0])); 1148 } 1149 for (i = 0; i < hw->num_rx_queues; i++) { 1150 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1151 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1152 sizeof(hw->snapshot_rx_stats[0])); 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int 1159 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1160 struct rte_eth_dev_info *dev_info) 1161 { 1162 struct vmxnet3_hw *hw = dev->data->dev_private; 1163 1164 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1165 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1166 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1167 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1168 dev_info->min_mtu = VMXNET3_MIN_MTU; 1169 dev_info->max_mtu = VMXNET3_MAX_MTU; 1170 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1171 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1172 1173 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1174 1175 if (VMXNET3_VERSION_GE_4(hw)) { 1176 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1177 } 1178 1179 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1180 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1181 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1182 .nb_align = 1, 1183 }; 1184 1185 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1186 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1187 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1188 .nb_align = 1, 1189 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1190 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1191 }; 1192 1193 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1194 dev_info->rx_queue_offload_capa = 0; 1195 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1196 dev_info->tx_queue_offload_capa = 0; 1197 1198 return 0; 1199 } 1200 1201 static const uint32_t * 1202 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1203 { 1204 static const uint32_t ptypes[] = { 1205 RTE_PTYPE_L3_IPV4_EXT, 1206 RTE_PTYPE_L3_IPV4, 1207 RTE_PTYPE_UNKNOWN 1208 }; 1209 1210 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1211 return ptypes; 1212 return NULL; 1213 } 1214 1215 static int 1216 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu) 1217 { 1218 if (dev->data->dev_started) { 1219 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU", 1220 dev->data->port_id); 1221 return -EBUSY; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int 1228 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1229 { 1230 struct vmxnet3_hw *hw = dev->data->dev_private; 1231 1232 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1233 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1234 return 0; 1235 } 1236 1237 /* return 0 means link status changed, -1 means not changed */ 1238 static int 1239 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1240 __rte_unused int wait_to_complete) 1241 { 1242 struct vmxnet3_hw *hw = dev->data->dev_private; 1243 struct rte_eth_link link; 1244 uint32_t ret; 1245 1246 memset(&link, 0, sizeof(link)); 1247 1248 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1249 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1250 1251 if (ret & 0x1) 1252 link.link_status = ETH_LINK_UP; 1253 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1254 link.link_speed = ETH_SPEED_NUM_10G; 1255 link.link_autoneg = ETH_LINK_FIXED; 1256 1257 return rte_eth_linkstatus_set(dev, &link); 1258 } 1259 1260 static int 1261 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1262 { 1263 /* Link status doesn't change for stopped dev */ 1264 if (dev->data->dev_started == 0) 1265 return -1; 1266 1267 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1268 } 1269 1270 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1271 static void 1272 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1273 { 1274 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1275 1276 if (set) 1277 rxConf->rxMode = rxConf->rxMode | feature; 1278 else 1279 rxConf->rxMode = rxConf->rxMode & (~feature); 1280 1281 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1282 } 1283 1284 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1285 static int 1286 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1287 { 1288 struct vmxnet3_hw *hw = dev->data->dev_private; 1289 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1290 1291 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1292 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1293 1294 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1295 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1296 1297 return 0; 1298 } 1299 1300 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1301 static int 1302 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1303 { 1304 struct vmxnet3_hw *hw = dev->data->dev_private; 1305 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1306 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1307 1308 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1309 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1310 else 1311 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1312 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1313 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1314 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1315 1316 return 0; 1317 } 1318 1319 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1320 static int 1321 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1322 { 1323 struct vmxnet3_hw *hw = dev->data->dev_private; 1324 1325 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1326 1327 return 0; 1328 } 1329 1330 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1331 static int 1332 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1333 { 1334 struct vmxnet3_hw *hw = dev->data->dev_private; 1335 1336 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1337 1338 return 0; 1339 } 1340 1341 /* Enable/disable filter on vlan */ 1342 static int 1343 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1344 { 1345 struct vmxnet3_hw *hw = dev->data->dev_private; 1346 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1347 uint32_t *vf_table = rxConf->vfTable; 1348 1349 /* save state for restore */ 1350 if (on) 1351 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1352 else 1353 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1354 1355 /* don't change active filter if in promiscuous mode */ 1356 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1357 return 0; 1358 1359 /* set in hardware */ 1360 if (on) 1361 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1362 else 1363 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1364 1365 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1366 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1367 return 0; 1368 } 1369 1370 static int 1371 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1372 { 1373 struct vmxnet3_hw *hw = dev->data->dev_private; 1374 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1375 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1376 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1377 1378 if (mask & ETH_VLAN_STRIP_MASK) { 1379 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1380 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1381 else 1382 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1383 1384 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1385 VMXNET3_CMD_UPDATE_FEATURE); 1386 } 1387 1388 if (mask & ETH_VLAN_FILTER_MASK) { 1389 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1390 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1391 else 1392 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1393 1394 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1395 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1396 } 1397 1398 return 0; 1399 } 1400 1401 static void 1402 vmxnet3_process_events(struct rte_eth_dev *dev) 1403 { 1404 struct vmxnet3_hw *hw = dev->data->dev_private; 1405 uint32_t events = hw->shared->ecr; 1406 1407 if (!events) 1408 return; 1409 1410 /* 1411 * ECR bits when written with 1b are cleared. Hence write 1412 * events back to ECR so that the bits which were set will be reset. 1413 */ 1414 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1415 1416 /* Check if link state has changed */ 1417 if (events & VMXNET3_ECR_LINK) { 1418 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1419 if (vmxnet3_dev_link_update(dev, 0) == 0) 1420 rte_eth_dev_callback_process(dev, 1421 RTE_ETH_EVENT_INTR_LSC, 1422 NULL); 1423 } 1424 1425 /* Check if there is an error on xmit/recv queues */ 1426 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1427 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1428 VMXNET3_CMD_GET_QUEUE_STATUS); 1429 1430 if (hw->tqd_start->status.stopped) 1431 PMD_DRV_LOG(ERR, "tq error 0x%x", 1432 hw->tqd_start->status.error); 1433 1434 if (hw->rqd_start->status.stopped) 1435 PMD_DRV_LOG(ERR, "rq error 0x%x", 1436 hw->rqd_start->status.error); 1437 1438 /* Reset the device */ 1439 /* Have to reset the device */ 1440 } 1441 1442 if (events & VMXNET3_ECR_DIC) 1443 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1444 1445 if (events & VMXNET3_ECR_DEBUG) 1446 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1447 } 1448 1449 static void 1450 vmxnet3_interrupt_handler(void *param) 1451 { 1452 struct rte_eth_dev *dev = param; 1453 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1454 1455 vmxnet3_process_events(dev); 1456 1457 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1458 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1459 } 1460 1461 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1462 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1463 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1464 RTE_LOG_REGISTER(vmxnet3_logtype_init, pmd.net.vmxnet3.init, NOTICE); 1465 RTE_LOG_REGISTER(vmxnet3_logtype_driver, pmd.net.vmxnet3.driver, NOTICE); 1466