1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 60 DEV_RX_OFFLOAD_RSS_HASH) 61 62 int vmxnet3_segs_dynfield_offset = -1; 63 64 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 65 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 66 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 67 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 68 static int vmxnet3_dev_stop(struct rte_eth_dev *dev); 69 static int vmxnet3_dev_close(struct rte_eth_dev *dev); 70 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 71 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 73 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 74 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 75 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 76 int wait_to_complete); 77 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 78 int wait_to_complete); 79 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 80 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 81 struct rte_eth_stats *stats); 82 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 83 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 84 struct rte_eth_xstat_name *xstats, 85 unsigned int n); 86 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 87 struct rte_eth_xstat *xstats, unsigned int n); 88 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 89 struct rte_eth_dev_info *dev_info); 90 static const uint32_t * 91 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 92 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 93 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 94 uint16_t vid, int on); 95 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 96 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 97 struct rte_ether_addr *mac_addr); 98 static void vmxnet3_interrupt_handler(void *param); 99 100 /* 101 * The set of PCI devices this driver supports 102 */ 103 #define VMWARE_PCI_VENDOR_ID 0x15AD 104 #define VMWARE_DEV_ID_VMXNET3 0x07B0 105 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 106 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 107 { .vendor_id = 0, /* sentinel */ }, 108 }; 109 110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 111 .dev_configure = vmxnet3_dev_configure, 112 .dev_start = vmxnet3_dev_start, 113 .dev_stop = vmxnet3_dev_stop, 114 .dev_close = vmxnet3_dev_close, 115 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 116 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 117 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 118 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 119 .link_update = vmxnet3_dev_link_update, 120 .stats_get = vmxnet3_dev_stats_get, 121 .xstats_get_names = vmxnet3_dev_xstats_get_names, 122 .xstats_get = vmxnet3_dev_xstats_get, 123 .stats_reset = vmxnet3_dev_stats_reset, 124 .mac_addr_set = vmxnet3_mac_addr_set, 125 .dev_infos_get = vmxnet3_dev_info_get, 126 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 127 .mtu_set = vmxnet3_dev_mtu_set, 128 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 129 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 130 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 131 .rx_queue_release = vmxnet3_dev_rx_queue_release, 132 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 133 .tx_queue_release = vmxnet3_dev_tx_queue_release, 134 }; 135 136 struct vmxnet3_xstats_name_off { 137 char name[RTE_ETH_XSTATS_NAME_SIZE]; 138 unsigned int offset; 139 }; 140 141 /* tx_qX_ is prepended to the name string here */ 142 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 143 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 144 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 145 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 146 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 147 }; 148 149 /* rx_qX_ is prepended to the name string here */ 150 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 151 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 152 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 153 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 154 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 155 }; 156 157 static const struct rte_memzone * 158 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 159 const char *post_string, int socket_id, 160 uint16_t align, bool reuse) 161 { 162 char z_name[RTE_MEMZONE_NAMESIZE]; 163 const struct rte_memzone *mz; 164 165 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 166 dev->data->port_id, post_string); 167 168 mz = rte_memzone_lookup(z_name); 169 if (!reuse) { 170 if (mz) 171 rte_memzone_free(mz); 172 return rte_memzone_reserve_aligned(z_name, size, socket_id, 173 RTE_MEMZONE_IOVA_CONTIG, align); 174 } 175 176 if (mz) 177 return mz; 178 179 return rte_memzone_reserve_aligned(z_name, size, socket_id, 180 RTE_MEMZONE_IOVA_CONTIG, align); 181 } 182 183 /* 184 * This function is based on vmxnet3_disable_intr() 185 */ 186 static void 187 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 188 { 189 int i; 190 191 PMD_INIT_FUNC_TRACE(); 192 193 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 194 for (i = 0; i < hw->num_intrs; i++) 195 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 196 } 197 198 static void 199 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 200 { 201 int i; 202 203 PMD_INIT_FUNC_TRACE(); 204 205 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 206 for (i = 0; i < hw->num_intrs; i++) 207 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 208 } 209 210 /* 211 * Gets tx data ring descriptor size. 212 */ 213 static uint16_t 214 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 215 { 216 uint16 txdata_desc_size; 217 218 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 219 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 220 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 221 222 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 223 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 224 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 225 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 226 } 227 228 /* 229 * It returns 0 on success. 230 */ 231 static int 232 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 233 { 234 struct rte_pci_device *pci_dev; 235 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 236 uint32_t mac_hi, mac_lo, ver; 237 struct rte_eth_link link; 238 static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = { 239 .name = VMXNET3_SEGS_DYNFIELD_NAME, 240 .size = sizeof(vmxnet3_segs_dynfield_t), 241 .align = __alignof__(vmxnet3_segs_dynfield_t), 242 }; 243 244 PMD_INIT_FUNC_TRACE(); 245 246 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 247 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 248 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 249 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 250 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 251 252 /* extra mbuf field is required to guess MSS */ 253 vmxnet3_segs_dynfield_offset = 254 rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc); 255 if (vmxnet3_segs_dynfield_offset < 0) { 256 PMD_INIT_LOG(ERR, "Cannot register mbuf field."); 257 return -rte_errno; 258 } 259 260 /* 261 * for secondary processes, we don't initialize any further as primary 262 * has already done this work. 263 */ 264 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 265 return 0; 266 267 rte_eth_copy_pci_info(eth_dev, pci_dev); 268 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 269 270 /* Vendor and Device ID need to be set before init of shared code */ 271 hw->device_id = pci_dev->id.device_id; 272 hw->vendor_id = pci_dev->id.vendor_id; 273 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 274 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 275 276 hw->num_rx_queues = 1; 277 hw->num_tx_queues = 1; 278 hw->bufs_per_pkt = 1; 279 280 /* Check h/w version compatibility with driver. */ 281 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 282 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 283 284 if (ver & (1 << VMXNET3_REV_4)) { 285 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 286 1 << VMXNET3_REV_4); 287 hw->version = VMXNET3_REV_4 + 1; 288 } else if (ver & (1 << VMXNET3_REV_3)) { 289 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 290 1 << VMXNET3_REV_3); 291 hw->version = VMXNET3_REV_3 + 1; 292 } else if (ver & (1 << VMXNET3_REV_2)) { 293 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 294 1 << VMXNET3_REV_2); 295 hw->version = VMXNET3_REV_2 + 1; 296 } else if (ver & (1 << VMXNET3_REV_1)) { 297 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 298 1 << VMXNET3_REV_1); 299 hw->version = VMXNET3_REV_1 + 1; 300 } else { 301 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 302 return -EIO; 303 } 304 305 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 306 307 /* Check UPT version compatibility with driver. */ 308 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 309 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 310 if (ver & 0x1) 311 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 312 else { 313 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 314 return -EIO; 315 } 316 317 /* Getting MAC Address */ 318 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 319 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 320 memcpy(hw->perm_addr, &mac_lo, 4); 321 memcpy(hw->perm_addr + 4, &mac_hi, 2); 322 323 /* Allocate memory for storing MAC addresses */ 324 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 325 VMXNET3_MAX_MAC_ADDRS, 0); 326 if (eth_dev->data->mac_addrs == NULL) { 327 PMD_INIT_LOG(ERR, 328 "Failed to allocate %d bytes needed to store MAC addresses", 329 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 330 return -ENOMEM; 331 } 332 /* Copy the permanent MAC address */ 333 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 334 ð_dev->data->mac_addrs[0]); 335 336 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 337 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 338 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 339 340 /* Put device in Quiesce Mode */ 341 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 342 343 /* allow untagged pkts */ 344 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 345 346 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 347 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 348 349 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 350 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 351 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 352 hw->rxdata_desc_size); 353 354 /* clear shadow stats */ 355 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 356 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 357 358 /* clear snapshot stats */ 359 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 360 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 361 362 /* set the initial link status */ 363 memset(&link, 0, sizeof(link)); 364 link.link_duplex = ETH_LINK_FULL_DUPLEX; 365 link.link_speed = ETH_SPEED_NUM_10G; 366 link.link_autoneg = ETH_LINK_FIXED; 367 rte_eth_linkstatus_set(eth_dev, &link); 368 369 return 0; 370 } 371 372 static int 373 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 374 { 375 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 376 377 PMD_INIT_FUNC_TRACE(); 378 379 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 380 return 0; 381 382 if (hw->adapter_stopped == 0) { 383 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 384 return -EBUSY; 385 } 386 387 return 0; 388 } 389 390 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 391 struct rte_pci_device *pci_dev) 392 { 393 return rte_eth_dev_pci_generic_probe(pci_dev, 394 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 395 } 396 397 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 398 { 399 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 400 } 401 402 static struct rte_pci_driver rte_vmxnet3_pmd = { 403 .id_table = pci_id_vmxnet3_map, 404 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 405 .probe = eth_vmxnet3_pci_probe, 406 .remove = eth_vmxnet3_pci_remove, 407 }; 408 409 static int 410 vmxnet3_dev_configure(struct rte_eth_dev *dev) 411 { 412 const struct rte_memzone *mz; 413 struct vmxnet3_hw *hw = dev->data->dev_private; 414 size_t size; 415 416 PMD_INIT_FUNC_TRACE(); 417 418 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 419 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 420 421 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 422 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 423 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 424 return -EINVAL; 425 } 426 427 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 428 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 429 return -EINVAL; 430 } 431 432 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 433 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 434 435 if (size > UINT16_MAX) 436 return -EINVAL; 437 438 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 439 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 440 441 /* 442 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 443 * on current socket 444 */ 445 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 446 "shared", rte_socket_id(), 8, 1); 447 448 if (mz == NULL) { 449 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 450 return -ENOMEM; 451 } 452 memset(mz->addr, 0, mz->len); 453 454 hw->shared = mz->addr; 455 hw->sharedPA = mz->iova; 456 457 /* 458 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 459 * on current socket. 460 * 461 * We cannot reuse this memzone from previous allocation as its size 462 * depends on the number of tx and rx queues, which could be different 463 * from one config to another. 464 */ 465 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 466 VMXNET3_QUEUE_DESC_ALIGN, 0); 467 if (mz == NULL) { 468 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 469 return -ENOMEM; 470 } 471 memset(mz->addr, 0, mz->len); 472 473 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 474 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 475 476 hw->queueDescPA = mz->iova; 477 hw->queue_desc_len = (uint16_t)size; 478 479 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 480 /* Allocate memory structure for UPT1_RSSConf and configure */ 481 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 482 "rss_conf", rte_socket_id(), 483 RTE_CACHE_LINE_SIZE, 1); 484 if (mz == NULL) { 485 PMD_INIT_LOG(ERR, 486 "ERROR: Creating rss_conf structure zone"); 487 return -ENOMEM; 488 } 489 memset(mz->addr, 0, mz->len); 490 491 hw->rss_conf = mz->addr; 492 hw->rss_confPA = mz->iova; 493 } 494 495 return 0; 496 } 497 498 static void 499 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 500 { 501 uint32_t val; 502 503 PMD_INIT_LOG(DEBUG, 504 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 505 addr[0], addr[1], addr[2], 506 addr[3], addr[4], addr[5]); 507 508 memcpy(&val, addr, 4); 509 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 510 511 memcpy(&val, addr + 4, 2); 512 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 513 } 514 515 static int 516 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 517 { 518 struct vmxnet3_hw *hw = dev->data->dev_private; 519 Vmxnet3_DriverShared *shared = hw->shared; 520 Vmxnet3_CmdInfo *cmdInfo; 521 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 522 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 523 uint32_t num, i, j, size; 524 525 if (hw->memRegsPA == 0) { 526 const struct rte_memzone *mz; 527 528 size = sizeof(Vmxnet3_MemRegs) + 529 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 530 sizeof(Vmxnet3_MemoryRegion); 531 532 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 533 1); 534 if (mz == NULL) { 535 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 536 return -ENOMEM; 537 } 538 memset(mz->addr, 0, mz->len); 539 hw->memRegs = mz->addr; 540 hw->memRegsPA = mz->iova; 541 } 542 543 num = hw->num_rx_queues; 544 545 for (i = 0; i < num; i++) { 546 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 547 548 mp[i] = rxq->mp; 549 index[i] = 1 << i; 550 } 551 552 /* 553 * The same mempool could be used by multiple queues. In such a case, 554 * remove duplicate mempool entries. Only one entry is kept with 555 * bitmask indicating queues that are using this mempool. 556 */ 557 for (i = 1; i < num; i++) { 558 for (j = 0; j < i; j++) { 559 if (mp[i] == mp[j]) { 560 mp[i] = NULL; 561 index[j] |= 1 << i; 562 break; 563 } 564 } 565 } 566 567 j = 0; 568 for (i = 0; i < num; i++) { 569 if (mp[i] == NULL) 570 continue; 571 572 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 573 574 mr->startPA = 575 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 576 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 577 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 578 mr->txQueueBits = index[i]; 579 mr->rxQueueBits = index[i]; 580 581 PMD_INIT_LOG(INFO, 582 "index: %u startPA: %" PRIu64 " length: %u, " 583 "rxBits: %x", 584 j, mr->startPA, mr->length, mr->rxQueueBits); 585 j++; 586 } 587 hw->memRegs->numRegs = j; 588 PMD_INIT_LOG(INFO, "numRegs: %u", j); 589 590 size = sizeof(Vmxnet3_MemRegs) + 591 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 592 593 cmdInfo = &shared->cu.cmdInfo; 594 cmdInfo->varConf.confVer = 1; 595 cmdInfo->varConf.confLen = size; 596 cmdInfo->varConf.confPA = hw->memRegsPA; 597 598 return 0; 599 } 600 601 static int 602 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 603 { 604 struct rte_eth_conf port_conf = dev->data->dev_conf; 605 struct vmxnet3_hw *hw = dev->data->dev_private; 606 uint32_t mtu = dev->data->mtu; 607 Vmxnet3_DriverShared *shared = hw->shared; 608 Vmxnet3_DSDevRead *devRead = &shared->devRead; 609 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 610 uint32_t i; 611 int ret; 612 613 hw->mtu = mtu; 614 615 shared->magic = VMXNET3_REV1_MAGIC; 616 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 617 618 /* Setting up Guest OS information */ 619 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 620 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 621 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 622 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 623 devRead->misc.driverInfo.uptVerSpt = 1; 624 625 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 626 devRead->misc.queueDescPA = hw->queueDescPA; 627 devRead->misc.queueDescLen = hw->queue_desc_len; 628 devRead->misc.numTxQueues = hw->num_tx_queues; 629 devRead->misc.numRxQueues = hw->num_rx_queues; 630 631 /* 632 * Set number of interrupts to 1 633 * PMD by default disables all the interrupts but this is MUST 634 * to activate device. It needs at least one interrupt for 635 * link events to handle 636 */ 637 hw->num_intrs = devRead->intrConf.numIntrs = 1; 638 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 639 640 for (i = 0; i < hw->num_tx_queues; i++) { 641 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 642 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 643 644 txq->shared = &hw->tqd_start[i]; 645 646 tqd->ctrl.txNumDeferred = 0; 647 tqd->ctrl.txThreshold = 1; 648 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 649 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 650 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 651 652 tqd->conf.txRingSize = txq->cmd_ring.size; 653 tqd->conf.compRingSize = txq->comp_ring.size; 654 tqd->conf.dataRingSize = txq->data_ring.size; 655 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 656 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 657 tqd->status.stopped = TRUE; 658 tqd->status.error = 0; 659 memset(&tqd->stats, 0, sizeof(tqd->stats)); 660 } 661 662 for (i = 0; i < hw->num_rx_queues; i++) { 663 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 664 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 665 666 rxq->shared = &hw->rqd_start[i]; 667 668 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 669 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 670 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 671 672 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 673 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 674 rqd->conf.compRingSize = rxq->comp_ring.size; 675 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 676 if (VMXNET3_VERSION_GE_3(hw)) { 677 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 678 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 679 } 680 rqd->status.stopped = TRUE; 681 rqd->status.error = 0; 682 memset(&rqd->stats, 0, sizeof(rqd->stats)); 683 } 684 685 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 686 devRead->rxFilterConf.rxMode = 0; 687 688 /* Setting up feature flags */ 689 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 690 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 691 692 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 693 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 694 devRead->misc.maxNumRxSG = 0; 695 } 696 697 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 698 ret = vmxnet3_rss_configure(dev); 699 if (ret != VMXNET3_SUCCESS) 700 return ret; 701 702 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 703 devRead->rssConfDesc.confVer = 1; 704 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 705 devRead->rssConfDesc.confPA = hw->rss_confPA; 706 } 707 708 ret = vmxnet3_dev_vlan_offload_set(dev, 709 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 710 if (ret) 711 return ret; 712 713 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 714 715 return VMXNET3_SUCCESS; 716 } 717 718 /* 719 * Configure device link speed and setup link. 720 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 721 * It returns 0 on success. 722 */ 723 static int 724 vmxnet3_dev_start(struct rte_eth_dev *dev) 725 { 726 int ret; 727 struct vmxnet3_hw *hw = dev->data->dev_private; 728 729 PMD_INIT_FUNC_TRACE(); 730 731 /* Save stats before it is reset by CMD_ACTIVATE */ 732 vmxnet3_hw_stats_save(hw); 733 734 ret = vmxnet3_setup_driver_shared(dev); 735 if (ret != VMXNET3_SUCCESS) 736 return ret; 737 738 /* check if lsc interrupt feature is enabled */ 739 if (dev->data->dev_conf.intr_conf.lsc) { 740 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 741 742 /* Setup interrupt callback */ 743 rte_intr_callback_register(&pci_dev->intr_handle, 744 vmxnet3_interrupt_handler, dev); 745 746 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 747 PMD_INIT_LOG(ERR, "interrupt enable failed"); 748 return -EIO; 749 } 750 } 751 752 /* Exchange shared data with device */ 753 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 754 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 755 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 756 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 757 758 /* Activate device by register write */ 759 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 760 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 761 762 if (ret != 0) { 763 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 764 return -EINVAL; 765 } 766 767 /* Setup memory region for rx buffers */ 768 ret = vmxnet3_dev_setup_memreg(dev); 769 if (ret == 0) { 770 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 771 VMXNET3_CMD_REGISTER_MEMREGS); 772 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 773 if (ret != 0) 774 PMD_INIT_LOG(DEBUG, 775 "Failed in setup memory region cmd\n"); 776 ret = 0; 777 } else { 778 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 779 } 780 781 if (VMXNET3_VERSION_GE_4(hw) && 782 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 783 /* Check for additional RSS */ 784 ret = vmxnet3_v4_rss_configure(dev); 785 if (ret != VMXNET3_SUCCESS) { 786 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 787 return ret; 788 } 789 } 790 791 /* Disable interrupts */ 792 vmxnet3_disable_intr(hw); 793 794 /* 795 * Load RX queues with blank mbufs and update next2fill index for device 796 * Update RxMode of the device 797 */ 798 ret = vmxnet3_dev_rxtx_init(dev); 799 if (ret != VMXNET3_SUCCESS) { 800 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 801 return ret; 802 } 803 804 hw->adapter_stopped = FALSE; 805 806 /* Setting proper Rx Mode and issue Rx Mode Update command */ 807 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 808 809 if (dev->data->dev_conf.intr_conf.lsc) { 810 vmxnet3_enable_intr(hw); 811 812 /* 813 * Update link state from device since this won't be 814 * done upon starting with lsc in use. This is done 815 * only after enabling interrupts to avoid any race 816 * where the link state could change without an 817 * interrupt being fired. 818 */ 819 __vmxnet3_dev_link_update(dev, 0); 820 } 821 822 return VMXNET3_SUCCESS; 823 } 824 825 /* 826 * Stop device: disable rx and tx functions to allow for reconfiguring. 827 */ 828 static int 829 vmxnet3_dev_stop(struct rte_eth_dev *dev) 830 { 831 struct rte_eth_link link; 832 struct vmxnet3_hw *hw = dev->data->dev_private; 833 834 PMD_INIT_FUNC_TRACE(); 835 836 if (hw->adapter_stopped == 1) { 837 PMD_INIT_LOG(DEBUG, "Device already stopped."); 838 return 0; 839 } 840 841 /* disable interrupts */ 842 vmxnet3_disable_intr(hw); 843 844 if (dev->data->dev_conf.intr_conf.lsc) { 845 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 846 847 rte_intr_disable(&pci_dev->intr_handle); 848 849 rte_intr_callback_unregister(&pci_dev->intr_handle, 850 vmxnet3_interrupt_handler, dev); 851 } 852 853 /* quiesce the device first */ 854 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 855 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 856 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 857 858 /* reset the device */ 859 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 860 PMD_INIT_LOG(DEBUG, "Device reset."); 861 862 vmxnet3_dev_clear_queues(dev); 863 864 /* Clear recorded link status */ 865 memset(&link, 0, sizeof(link)); 866 link.link_duplex = ETH_LINK_FULL_DUPLEX; 867 link.link_speed = ETH_SPEED_NUM_10G; 868 link.link_autoneg = ETH_LINK_FIXED; 869 rte_eth_linkstatus_set(dev, &link); 870 871 hw->adapter_stopped = 1; 872 dev->data->dev_started = 0; 873 874 return 0; 875 } 876 877 static void 878 vmxnet3_free_queues(struct rte_eth_dev *dev) 879 { 880 int i; 881 882 PMD_INIT_FUNC_TRACE(); 883 884 for (i = 0; i < dev->data->nb_rx_queues; i++) { 885 void *rxq = dev->data->rx_queues[i]; 886 887 vmxnet3_dev_rx_queue_release(rxq); 888 } 889 dev->data->nb_rx_queues = 0; 890 891 for (i = 0; i < dev->data->nb_tx_queues; i++) { 892 void *txq = dev->data->tx_queues[i]; 893 894 vmxnet3_dev_tx_queue_release(txq); 895 } 896 dev->data->nb_tx_queues = 0; 897 } 898 899 /* 900 * Reset and stop device. 901 */ 902 static int 903 vmxnet3_dev_close(struct rte_eth_dev *dev) 904 { 905 int ret; 906 PMD_INIT_FUNC_TRACE(); 907 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 908 return 0; 909 910 ret = vmxnet3_dev_stop(dev); 911 vmxnet3_free_queues(dev); 912 913 return ret; 914 } 915 916 static void 917 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 918 struct UPT1_TxStats *res) 919 { 920 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 921 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 922 (h)->saved_tx_stats[(i)].f) 923 924 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 925 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 926 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 927 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 928 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 929 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 930 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 931 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 932 933 #undef VMXNET3_UPDATE_TX_STAT 934 } 935 936 static void 937 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 938 struct UPT1_RxStats *res) 939 { 940 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 941 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 942 (h)->saved_rx_stats[(i)].f) 943 944 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 945 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 946 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 947 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 948 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 949 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 950 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 951 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 952 953 #undef VMXNET3_UPDATE_RX_STAT 954 } 955 956 static void 957 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 958 struct UPT1_TxStats *res) 959 { 960 vmxnet3_hw_tx_stats_get(hw, q, res); 961 962 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 963 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 964 965 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 966 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 967 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 968 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 969 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 970 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 971 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 972 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 973 974 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 975 } 976 977 static void 978 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 979 struct UPT1_RxStats *res) 980 { 981 vmxnet3_hw_rx_stats_get(hw, q, res); 982 983 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 984 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 985 986 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 987 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 988 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 989 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 990 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 991 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 992 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 993 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 994 995 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 996 } 997 998 static void 999 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 1000 { 1001 unsigned int i; 1002 1003 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1004 1005 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1006 1007 for (i = 0; i < hw->num_tx_queues; i++) 1008 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 1009 for (i = 0; i < hw->num_rx_queues; i++) 1010 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 1011 } 1012 1013 static int 1014 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 1015 struct rte_eth_xstat_name *xstats_names, 1016 unsigned int n) 1017 { 1018 unsigned int i, t, count = 0; 1019 unsigned int nstats = 1020 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1021 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1022 1023 if (!xstats_names || n < nstats) 1024 return nstats; 1025 1026 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1027 if (!dev->data->rx_queues[i]) 1028 continue; 1029 1030 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1031 snprintf(xstats_names[count].name, 1032 sizeof(xstats_names[count].name), 1033 "rx_q%u_%s", i, 1034 vmxnet3_rxq_stat_strings[t].name); 1035 count++; 1036 } 1037 } 1038 1039 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1040 if (!dev->data->tx_queues[i]) 1041 continue; 1042 1043 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1044 snprintf(xstats_names[count].name, 1045 sizeof(xstats_names[count].name), 1046 "tx_q%u_%s", i, 1047 vmxnet3_txq_stat_strings[t].name); 1048 count++; 1049 } 1050 } 1051 1052 return count; 1053 } 1054 1055 static int 1056 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1057 unsigned int n) 1058 { 1059 unsigned int i, t, count = 0; 1060 unsigned int nstats = 1061 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1062 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1063 1064 if (n < nstats) 1065 return nstats; 1066 1067 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1068 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1069 1070 if (rxq == NULL) 1071 continue; 1072 1073 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1074 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1075 vmxnet3_rxq_stat_strings[t].offset); 1076 xstats[count].id = count; 1077 count++; 1078 } 1079 } 1080 1081 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1082 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1083 1084 if (txq == NULL) 1085 continue; 1086 1087 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1088 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1089 vmxnet3_txq_stat_strings[t].offset); 1090 xstats[count].id = count; 1091 count++; 1092 } 1093 } 1094 1095 return count; 1096 } 1097 1098 static int 1099 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1100 { 1101 unsigned int i; 1102 struct vmxnet3_hw *hw = dev->data->dev_private; 1103 struct UPT1_TxStats txStats; 1104 struct UPT1_RxStats rxStats; 1105 1106 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1107 1108 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1109 for (i = 0; i < hw->num_tx_queues; i++) { 1110 vmxnet3_tx_stats_get(hw, i, &txStats); 1111 1112 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1113 txStats.mcastPktsTxOK + 1114 txStats.bcastPktsTxOK; 1115 1116 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1117 txStats.mcastBytesTxOK + 1118 txStats.bcastBytesTxOK; 1119 1120 stats->opackets += stats->q_opackets[i]; 1121 stats->obytes += stats->q_obytes[i]; 1122 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1123 } 1124 1125 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1126 for (i = 0; i < hw->num_rx_queues; i++) { 1127 vmxnet3_rx_stats_get(hw, i, &rxStats); 1128 1129 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1130 rxStats.mcastPktsRxOK + 1131 rxStats.bcastPktsRxOK; 1132 1133 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1134 rxStats.mcastBytesRxOK + 1135 rxStats.bcastBytesRxOK; 1136 1137 stats->ipackets += stats->q_ipackets[i]; 1138 stats->ibytes += stats->q_ibytes[i]; 1139 1140 stats->q_errors[i] = rxStats.pktsRxError; 1141 stats->ierrors += rxStats.pktsRxError; 1142 stats->imissed += rxStats.pktsRxOutOfBuf; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int 1149 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1150 { 1151 unsigned int i; 1152 struct vmxnet3_hw *hw = dev->data->dev_private; 1153 struct UPT1_TxStats txStats = {0}; 1154 struct UPT1_RxStats rxStats = {0}; 1155 1156 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1157 1158 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1159 1160 for (i = 0; i < hw->num_tx_queues; i++) { 1161 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1162 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1163 sizeof(hw->snapshot_tx_stats[0])); 1164 } 1165 for (i = 0; i < hw->num_rx_queues; i++) { 1166 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1167 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1168 sizeof(hw->snapshot_rx_stats[0])); 1169 } 1170 1171 return 0; 1172 } 1173 1174 static int 1175 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1176 struct rte_eth_dev_info *dev_info) 1177 { 1178 struct vmxnet3_hw *hw = dev->data->dev_private; 1179 1180 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1181 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1182 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1183 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1184 dev_info->min_mtu = VMXNET3_MIN_MTU; 1185 dev_info->max_mtu = VMXNET3_MAX_MTU; 1186 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1187 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1188 1189 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1190 1191 if (VMXNET3_VERSION_GE_4(hw)) { 1192 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1193 } 1194 1195 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1196 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1197 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1198 .nb_align = 1, 1199 }; 1200 1201 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1202 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1203 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1204 .nb_align = 1, 1205 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1206 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1207 }; 1208 1209 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1210 dev_info->rx_queue_offload_capa = 0; 1211 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1212 dev_info->tx_queue_offload_capa = 0; 1213 1214 return 0; 1215 } 1216 1217 static const uint32_t * 1218 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1219 { 1220 static const uint32_t ptypes[] = { 1221 RTE_PTYPE_L3_IPV4_EXT, 1222 RTE_PTYPE_L3_IPV4, 1223 RTE_PTYPE_UNKNOWN 1224 }; 1225 1226 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1227 return ptypes; 1228 return NULL; 1229 } 1230 1231 static int 1232 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu) 1233 { 1234 if (dev->data->dev_started) { 1235 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU", 1236 dev->data->port_id); 1237 return -EBUSY; 1238 } 1239 1240 return 0; 1241 } 1242 1243 static int 1244 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1245 { 1246 struct vmxnet3_hw *hw = dev->data->dev_private; 1247 1248 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1249 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1250 return 0; 1251 } 1252 1253 /* return 0 means link status changed, -1 means not changed */ 1254 static int 1255 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1256 __rte_unused int wait_to_complete) 1257 { 1258 struct vmxnet3_hw *hw = dev->data->dev_private; 1259 struct rte_eth_link link; 1260 uint32_t ret; 1261 1262 memset(&link, 0, sizeof(link)); 1263 1264 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1265 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1266 1267 if (ret & 0x1) 1268 link.link_status = ETH_LINK_UP; 1269 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1270 link.link_speed = ETH_SPEED_NUM_10G; 1271 link.link_autoneg = ETH_LINK_FIXED; 1272 1273 return rte_eth_linkstatus_set(dev, &link); 1274 } 1275 1276 static int 1277 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1278 { 1279 /* Link status doesn't change for stopped dev */ 1280 if (dev->data->dev_started == 0) 1281 return -1; 1282 1283 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1284 } 1285 1286 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1287 static void 1288 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1289 { 1290 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1291 1292 if (set) 1293 rxConf->rxMode = rxConf->rxMode | feature; 1294 else 1295 rxConf->rxMode = rxConf->rxMode & (~feature); 1296 1297 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1298 } 1299 1300 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1301 static int 1302 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1303 { 1304 struct vmxnet3_hw *hw = dev->data->dev_private; 1305 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1306 1307 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1308 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1309 1310 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1311 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1312 1313 return 0; 1314 } 1315 1316 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1317 static int 1318 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1319 { 1320 struct vmxnet3_hw *hw = dev->data->dev_private; 1321 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1322 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1323 1324 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1325 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1326 else 1327 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1328 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1329 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1330 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1331 1332 return 0; 1333 } 1334 1335 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1336 static int 1337 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1338 { 1339 struct vmxnet3_hw *hw = dev->data->dev_private; 1340 1341 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1342 1343 return 0; 1344 } 1345 1346 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1347 static int 1348 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1349 { 1350 struct vmxnet3_hw *hw = dev->data->dev_private; 1351 1352 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1353 1354 return 0; 1355 } 1356 1357 /* Enable/disable filter on vlan */ 1358 static int 1359 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1360 { 1361 struct vmxnet3_hw *hw = dev->data->dev_private; 1362 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1363 uint32_t *vf_table = rxConf->vfTable; 1364 1365 /* save state for restore */ 1366 if (on) 1367 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1368 else 1369 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1370 1371 /* don't change active filter if in promiscuous mode */ 1372 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1373 return 0; 1374 1375 /* set in hardware */ 1376 if (on) 1377 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1378 else 1379 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1380 1381 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1382 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1383 return 0; 1384 } 1385 1386 static int 1387 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1388 { 1389 struct vmxnet3_hw *hw = dev->data->dev_private; 1390 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1391 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1392 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1393 1394 if (mask & ETH_VLAN_STRIP_MASK) { 1395 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1396 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1397 else 1398 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1399 1400 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1401 VMXNET3_CMD_UPDATE_FEATURE); 1402 } 1403 1404 if (mask & ETH_VLAN_FILTER_MASK) { 1405 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1406 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1407 else 1408 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1409 1410 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1411 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1412 } 1413 1414 return 0; 1415 } 1416 1417 static void 1418 vmxnet3_process_events(struct rte_eth_dev *dev) 1419 { 1420 struct vmxnet3_hw *hw = dev->data->dev_private; 1421 uint32_t events = hw->shared->ecr; 1422 1423 if (!events) 1424 return; 1425 1426 /* 1427 * ECR bits when written with 1b are cleared. Hence write 1428 * events back to ECR so that the bits which were set will be reset. 1429 */ 1430 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1431 1432 /* Check if link state has changed */ 1433 if (events & VMXNET3_ECR_LINK) { 1434 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1435 if (vmxnet3_dev_link_update(dev, 0) == 0) 1436 rte_eth_dev_callback_process(dev, 1437 RTE_ETH_EVENT_INTR_LSC, 1438 NULL); 1439 } 1440 1441 /* Check if there is an error on xmit/recv queues */ 1442 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1443 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1444 VMXNET3_CMD_GET_QUEUE_STATUS); 1445 1446 if (hw->tqd_start->status.stopped) 1447 PMD_DRV_LOG(ERR, "tq error 0x%x", 1448 hw->tqd_start->status.error); 1449 1450 if (hw->rqd_start->status.stopped) 1451 PMD_DRV_LOG(ERR, "rq error 0x%x", 1452 hw->rqd_start->status.error); 1453 1454 /* Reset the device */ 1455 /* Have to reset the device */ 1456 } 1457 1458 if (events & VMXNET3_ECR_DIC) 1459 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1460 1461 if (events & VMXNET3_ECR_DEBUG) 1462 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1463 } 1464 1465 static void 1466 vmxnet3_interrupt_handler(void *param) 1467 { 1468 struct rte_eth_dev *dev = param; 1469 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1470 1471 vmxnet3_process_events(dev); 1472 1473 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1474 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1475 } 1476 1477 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1478 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1479 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1480 RTE_LOG_REGISTER(vmxnet3_logtype_init, pmd.net.vmxnet3.init, NOTICE); 1481 RTE_LOG_REGISTER(vmxnet3_logtype_driver, pmd.net.vmxnet3.driver, NOTICE); 1482