1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <fcntl.h> 42 #include <inttypes.h> 43 #include <rte_byteorder.h> 44 #include <rte_common.h> 45 #include <rte_cycles.h> 46 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_eal.h> 56 #include <rte_alarm.h> 57 #include <rte_ether.h> 58 #include <rte_ethdev.h> 59 #include <rte_ethdev_pci.h> 60 #include <rte_atomic.h> 61 #include <rte_string_fns.h> 62 #include <rte_malloc.h> 63 #include <rte_dev.h> 64 65 #include "base/vmxnet3_defs.h" 66 67 #include "vmxnet3_ring.h" 68 #include "vmxnet3_logs.h" 69 #include "vmxnet3_ethdev.h" 70 71 #define PROCESS_SYS_EVENTS 0 72 73 #define VMXNET3_TX_MAX_SEG UINT8_MAX 74 75 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 76 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 77 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 78 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 79 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 80 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 81 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 82 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 83 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 84 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 85 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 86 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 87 int wait_to_complete); 88 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 89 int wait_to_complete); 90 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 91 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 92 struct rte_eth_stats *stats); 93 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 94 struct rte_eth_xstat_name *xstats, 95 unsigned int n); 96 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 97 struct rte_eth_xstat *xstats, unsigned int n); 98 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 99 struct rte_eth_dev_info *dev_info); 100 static const uint32_t * 101 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 102 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 103 uint16_t vid, int on); 104 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 105 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 106 struct ether_addr *mac_addr); 107 static void vmxnet3_interrupt_handler(void *param); 108 109 /* 110 * The set of PCI devices this driver supports 111 */ 112 #define VMWARE_PCI_VENDOR_ID 0x15AD 113 #define VMWARE_DEV_ID_VMXNET3 0x07B0 114 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 115 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 116 { .vendor_id = 0, /* sentinel */ }, 117 }; 118 119 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 120 .dev_configure = vmxnet3_dev_configure, 121 .dev_start = vmxnet3_dev_start, 122 .dev_stop = vmxnet3_dev_stop, 123 .dev_close = vmxnet3_dev_close, 124 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 125 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 126 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 127 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 128 .link_update = vmxnet3_dev_link_update, 129 .stats_get = vmxnet3_dev_stats_get, 130 .xstats_get_names = vmxnet3_dev_xstats_get_names, 131 .xstats_get = vmxnet3_dev_xstats_get, 132 .mac_addr_set = vmxnet3_mac_addr_set, 133 .dev_infos_get = vmxnet3_dev_info_get, 134 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 135 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 136 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 137 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 138 .rx_queue_release = vmxnet3_dev_rx_queue_release, 139 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 140 .tx_queue_release = vmxnet3_dev_tx_queue_release, 141 }; 142 143 struct vmxnet3_xstats_name_off { 144 char name[RTE_ETH_XSTATS_NAME_SIZE]; 145 unsigned int offset; 146 }; 147 148 /* tx_qX_ is prepended to the name string here */ 149 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 150 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 151 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 152 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 153 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 154 }; 155 156 /* rx_qX_ is prepended to the name string here */ 157 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 158 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 159 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 160 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 161 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 162 }; 163 164 static const struct rte_memzone * 165 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 166 const char *post_string, int socket_id, 167 uint16_t align, bool reuse) 168 { 169 char z_name[RTE_MEMZONE_NAMESIZE]; 170 const struct rte_memzone *mz; 171 172 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 173 dev->device->driver->name, dev->data->port_id, post_string); 174 175 mz = rte_memzone_lookup(z_name); 176 if (!reuse) { 177 if (mz) 178 rte_memzone_free(mz); 179 return rte_memzone_reserve_aligned(z_name, size, socket_id, 180 0, align); 181 } 182 183 if (mz) 184 return mz; 185 186 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align); 187 } 188 189 /** 190 * Atomically reads the link status information from global 191 * structure rte_eth_dev. 192 * 193 * @param dev 194 * - Pointer to the structure rte_eth_dev to read from. 195 * - Pointer to the buffer to be saved with the link status. 196 * 197 * @return 198 * - On success, zero. 199 * - On failure, negative value. 200 */ 201 202 static int 203 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev, 204 struct rte_eth_link *link) 205 { 206 struct rte_eth_link *dst = link; 207 struct rte_eth_link *src = &(dev->data->dev_link); 208 209 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 210 *(uint64_t *)src) == 0) 211 return -1; 212 213 return 0; 214 } 215 216 /** 217 * Atomically writes the link status information into global 218 * structure rte_eth_dev. 219 * 220 * @param dev 221 * - Pointer to the structure rte_eth_dev to write to. 222 * - Pointer to the buffer to be saved with the link status. 223 * 224 * @return 225 * - On success, zero. 226 * - On failure, negative value. 227 */ 228 static int 229 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev, 230 struct rte_eth_link *link) 231 { 232 struct rte_eth_link *dst = &(dev->data->dev_link); 233 struct rte_eth_link *src = link; 234 235 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 236 *(uint64_t *)src) == 0) 237 return -1; 238 239 return 0; 240 } 241 242 /* 243 * This function is based on vmxnet3_disable_intr() 244 */ 245 static void 246 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 247 { 248 int i; 249 250 PMD_INIT_FUNC_TRACE(); 251 252 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 253 for (i = 0; i < hw->num_intrs; i++) 254 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 255 } 256 257 static void 258 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 259 { 260 int i; 261 262 PMD_INIT_FUNC_TRACE(); 263 264 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 265 for (i = 0; i < hw->num_intrs; i++) 266 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 267 } 268 269 /* 270 * Gets tx data ring descriptor size. 271 */ 272 static uint16_t 273 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 274 { 275 uint16 txdata_desc_size; 276 277 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 278 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 279 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 280 281 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 282 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 283 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 284 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 285 } 286 287 /* 288 * It returns 0 on success. 289 */ 290 static int 291 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 292 { 293 struct rte_pci_device *pci_dev; 294 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 295 uint32_t mac_hi, mac_lo, ver; 296 297 PMD_INIT_FUNC_TRACE(); 298 299 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 300 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 301 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 302 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 303 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 304 305 /* 306 * for secondary processes, we don't initialize any further as primary 307 * has already done this work. 308 */ 309 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 310 return 0; 311 312 rte_eth_copy_pci_info(eth_dev, pci_dev); 313 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE; 314 315 /* Vendor and Device ID need to be set before init of shared code */ 316 hw->device_id = pci_dev->id.device_id; 317 hw->vendor_id = pci_dev->id.vendor_id; 318 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 319 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 320 321 hw->num_rx_queues = 1; 322 hw->num_tx_queues = 1; 323 hw->bufs_per_pkt = 1; 324 325 /* Check h/w version compatibility with driver. */ 326 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 327 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 328 329 if (ver & (1 << VMXNET3_REV_3)) { 330 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 331 1 << VMXNET3_REV_3); 332 hw->version = VMXNET3_REV_3 + 1; 333 } else if (ver & (1 << VMXNET3_REV_2)) { 334 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 335 1 << VMXNET3_REV_2); 336 hw->version = VMXNET3_REV_2 + 1; 337 } else if (ver & (1 << VMXNET3_REV_1)) { 338 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 339 1 << VMXNET3_REV_1); 340 hw->version = VMXNET3_REV_1 + 1; 341 } else { 342 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 343 return -EIO; 344 } 345 346 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 347 348 /* Check UPT version compatibility with driver. */ 349 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 350 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 351 if (ver & 0x1) 352 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 353 else { 354 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 355 return -EIO; 356 } 357 358 /* Getting MAC Address */ 359 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 360 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 361 memcpy(hw->perm_addr, &mac_lo, 4); 362 memcpy(hw->perm_addr + 4, &mac_hi, 2); 363 364 /* Allocate memory for storing MAC addresses */ 365 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 366 VMXNET3_MAX_MAC_ADDRS, 0); 367 if (eth_dev->data->mac_addrs == NULL) { 368 PMD_INIT_LOG(ERR, 369 "Failed to allocate %d bytes needed to store MAC addresses", 370 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 371 return -ENOMEM; 372 } 373 /* Copy the permanent MAC address */ 374 ether_addr_copy((struct ether_addr *) hw->perm_addr, 375 ð_dev->data->mac_addrs[0]); 376 377 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 378 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 379 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 380 381 /* Put device in Quiesce Mode */ 382 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 383 384 /* allow untagged pkts */ 385 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 386 387 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 388 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 389 390 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 391 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 392 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 393 hw->rxdata_desc_size); 394 395 /* clear shadow stats */ 396 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 397 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 398 399 return 0; 400 } 401 402 static int 403 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 404 { 405 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 406 407 PMD_INIT_FUNC_TRACE(); 408 409 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 410 return 0; 411 412 if (hw->adapter_stopped == 0) 413 vmxnet3_dev_close(eth_dev); 414 415 eth_dev->dev_ops = NULL; 416 eth_dev->rx_pkt_burst = NULL; 417 eth_dev->tx_pkt_burst = NULL; 418 eth_dev->tx_pkt_prepare = NULL; 419 420 rte_free(eth_dev->data->mac_addrs); 421 eth_dev->data->mac_addrs = NULL; 422 423 return 0; 424 } 425 426 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 427 struct rte_pci_device *pci_dev) 428 { 429 return rte_eth_dev_pci_generic_probe(pci_dev, 430 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 431 } 432 433 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 434 { 435 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 436 } 437 438 static struct rte_pci_driver rte_vmxnet3_pmd = { 439 .id_table = pci_id_vmxnet3_map, 440 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 441 .probe = eth_vmxnet3_pci_probe, 442 .remove = eth_vmxnet3_pci_remove, 443 }; 444 445 static int 446 vmxnet3_dev_configure(struct rte_eth_dev *dev) 447 { 448 const struct rte_memzone *mz; 449 struct vmxnet3_hw *hw = dev->data->dev_private; 450 size_t size; 451 452 PMD_INIT_FUNC_TRACE(); 453 454 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 455 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 456 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 457 return -EINVAL; 458 } 459 460 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 461 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 462 return -EINVAL; 463 } 464 465 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 466 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 467 468 if (size > UINT16_MAX) 469 return -EINVAL; 470 471 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 472 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 473 474 /* 475 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 476 * on current socket 477 */ 478 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 479 "shared", rte_socket_id(), 8, 1); 480 481 if (mz == NULL) { 482 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 483 return -ENOMEM; 484 } 485 memset(mz->addr, 0, mz->len); 486 487 hw->shared = mz->addr; 488 hw->sharedPA = mz->phys_addr; 489 490 /* 491 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 492 * on current socket. 493 * 494 * We cannot reuse this memzone from previous allocation as its size 495 * depends on the number of tx and rx queues, which could be different 496 * from one config to another. 497 */ 498 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 499 VMXNET3_QUEUE_DESC_ALIGN, 0); 500 if (mz == NULL) { 501 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 502 return -ENOMEM; 503 } 504 memset(mz->addr, 0, mz->len); 505 506 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 507 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 508 509 hw->queueDescPA = mz->phys_addr; 510 hw->queue_desc_len = (uint16_t)size; 511 512 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 513 /* Allocate memory structure for UPT1_RSSConf and configure */ 514 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 515 "rss_conf", rte_socket_id(), 516 RTE_CACHE_LINE_SIZE, 1); 517 if (mz == NULL) { 518 PMD_INIT_LOG(ERR, 519 "ERROR: Creating rss_conf structure zone"); 520 return -ENOMEM; 521 } 522 memset(mz->addr, 0, mz->len); 523 524 hw->rss_conf = mz->addr; 525 hw->rss_confPA = mz->phys_addr; 526 } 527 528 return 0; 529 } 530 531 static void 532 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 533 { 534 uint32_t val; 535 536 PMD_INIT_LOG(DEBUG, 537 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 538 addr[0], addr[1], addr[2], 539 addr[3], addr[4], addr[5]); 540 541 val = *(const uint32_t *)addr; 542 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 543 544 val = (addr[5] << 8) | addr[4]; 545 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 546 } 547 548 static int 549 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 550 { 551 struct vmxnet3_hw *hw = dev->data->dev_private; 552 Vmxnet3_DriverShared *shared = hw->shared; 553 Vmxnet3_CmdInfo *cmdInfo; 554 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 555 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 556 uint32_t num, i, j, size; 557 558 if (hw->memRegsPA == 0) { 559 const struct rte_memzone *mz; 560 561 size = sizeof(Vmxnet3_MemRegs) + 562 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 563 sizeof(Vmxnet3_MemoryRegion); 564 565 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 566 1); 567 if (mz == NULL) { 568 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 569 return -ENOMEM; 570 } 571 memset(mz->addr, 0, mz->len); 572 hw->memRegs = mz->addr; 573 hw->memRegsPA = mz->phys_addr; 574 } 575 576 num = hw->num_rx_queues; 577 578 for (i = 0; i < num; i++) { 579 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 580 581 mp[i] = rxq->mp; 582 index[i] = 1 << i; 583 } 584 585 /* 586 * The same mempool could be used by multiple queues. In such a case, 587 * remove duplicate mempool entries. Only one entry is kept with 588 * bitmask indicating queues that are using this mempool. 589 */ 590 for (i = 1; i < num; i++) { 591 for (j = 0; j < i; j++) { 592 if (mp[i] == mp[j]) { 593 mp[i] = NULL; 594 index[j] |= 1 << i; 595 break; 596 } 597 } 598 } 599 600 j = 0; 601 for (i = 0; i < num; i++) { 602 if (mp[i] == NULL) 603 continue; 604 605 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 606 607 mr->startPA = 608 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->phys_addr; 609 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 610 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 611 mr->txQueueBits = index[i]; 612 mr->rxQueueBits = index[i]; 613 614 PMD_INIT_LOG(INFO, 615 "index: %u startPA: %" PRIu64 " length: %u, " 616 "rxBits: %x", 617 j, mr->startPA, mr->length, mr->rxQueueBits); 618 j++; 619 } 620 hw->memRegs->numRegs = j; 621 PMD_INIT_LOG(INFO, "numRegs: %u", j); 622 623 size = sizeof(Vmxnet3_MemRegs) + 624 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 625 626 cmdInfo = &shared->cu.cmdInfo; 627 cmdInfo->varConf.confVer = 1; 628 cmdInfo->varConf.confLen = size; 629 cmdInfo->varConf.confPA = hw->memRegsPA; 630 631 return 0; 632 } 633 634 static int 635 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 636 { 637 struct rte_eth_conf port_conf = dev->data->dev_conf; 638 struct vmxnet3_hw *hw = dev->data->dev_private; 639 uint32_t mtu = dev->data->mtu; 640 Vmxnet3_DriverShared *shared = hw->shared; 641 Vmxnet3_DSDevRead *devRead = &shared->devRead; 642 uint32_t i; 643 int ret; 644 645 shared->magic = VMXNET3_REV1_MAGIC; 646 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 647 648 /* Setting up Guest OS information */ 649 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 650 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 651 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 652 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 653 devRead->misc.driverInfo.uptVerSpt = 1; 654 655 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 656 devRead->misc.queueDescPA = hw->queueDescPA; 657 devRead->misc.queueDescLen = hw->queue_desc_len; 658 devRead->misc.numTxQueues = hw->num_tx_queues; 659 devRead->misc.numRxQueues = hw->num_rx_queues; 660 661 /* 662 * Set number of interrupts to 1 663 * PMD by default disables all the interrupts but this is MUST 664 * to activate device. It needs at least one interrupt for 665 * link events to handle 666 */ 667 hw->num_intrs = devRead->intrConf.numIntrs = 1; 668 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 669 670 for (i = 0; i < hw->num_tx_queues; i++) { 671 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 672 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 673 674 tqd->ctrl.txNumDeferred = 0; 675 tqd->ctrl.txThreshold = 1; 676 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 677 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 678 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 679 680 tqd->conf.txRingSize = txq->cmd_ring.size; 681 tqd->conf.compRingSize = txq->comp_ring.size; 682 tqd->conf.dataRingSize = txq->data_ring.size; 683 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 684 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 685 tqd->status.stopped = TRUE; 686 tqd->status.error = 0; 687 memset(&tqd->stats, 0, sizeof(tqd->stats)); 688 } 689 690 for (i = 0; i < hw->num_rx_queues; i++) { 691 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 692 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 693 694 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 695 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 696 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 697 698 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 699 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 700 rqd->conf.compRingSize = rxq->comp_ring.size; 701 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 702 if (VMXNET3_VERSION_GE_3(hw)) { 703 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 704 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 705 } 706 rqd->status.stopped = TRUE; 707 rqd->status.error = 0; 708 memset(&rqd->stats, 0, sizeof(rqd->stats)); 709 } 710 711 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 712 devRead->rxFilterConf.rxMode = 0; 713 714 /* Setting up feature flags */ 715 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 716 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 717 718 if (dev->data->dev_conf.rxmode.enable_lro) { 719 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 720 devRead->misc.maxNumRxSG = 0; 721 } 722 723 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 724 ret = vmxnet3_rss_configure(dev); 725 if (ret != VMXNET3_SUCCESS) 726 return ret; 727 728 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 729 devRead->rssConfDesc.confVer = 1; 730 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 731 devRead->rssConfDesc.confPA = hw->rss_confPA; 732 } 733 734 vmxnet3_dev_vlan_offload_set(dev, 735 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 736 737 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 738 739 return VMXNET3_SUCCESS; 740 } 741 742 /* 743 * Configure device link speed and setup link. 744 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 745 * It returns 0 on success. 746 */ 747 static int 748 vmxnet3_dev_start(struct rte_eth_dev *dev) 749 { 750 int ret; 751 struct vmxnet3_hw *hw = dev->data->dev_private; 752 753 PMD_INIT_FUNC_TRACE(); 754 755 /* Save stats before it is reset by CMD_ACTIVATE */ 756 vmxnet3_hw_stats_save(hw); 757 758 ret = vmxnet3_setup_driver_shared(dev); 759 if (ret != VMXNET3_SUCCESS) 760 return ret; 761 762 /* check if lsc interrupt feature is enabled */ 763 if (dev->data->dev_conf.intr_conf.lsc) { 764 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 765 766 /* Setup interrupt callback */ 767 rte_intr_callback_register(&pci_dev->intr_handle, 768 vmxnet3_interrupt_handler, dev); 769 770 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 771 PMD_INIT_LOG(ERR, "interrupt enable failed"); 772 return -EIO; 773 } 774 } 775 776 /* Exchange shared data with device */ 777 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 778 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 779 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 780 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 781 782 /* Activate device by register write */ 783 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 784 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 785 786 if (ret != 0) { 787 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 788 return -EINVAL; 789 } 790 791 /* Setup memory region for rx buffers */ 792 ret = vmxnet3_dev_setup_memreg(dev); 793 if (ret == 0) { 794 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 795 VMXNET3_CMD_REGISTER_MEMREGS); 796 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 797 if (ret != 0) 798 PMD_INIT_LOG(DEBUG, 799 "Failed in setup memory region cmd\n"); 800 ret = 0; 801 } else { 802 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 803 } 804 805 /* Disable interrupts */ 806 vmxnet3_disable_intr(hw); 807 808 /* 809 * Load RX queues with blank mbufs and update next2fill index for device 810 * Update RxMode of the device 811 */ 812 ret = vmxnet3_dev_rxtx_init(dev); 813 if (ret != VMXNET3_SUCCESS) { 814 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 815 return ret; 816 } 817 818 hw->adapter_stopped = FALSE; 819 820 /* Setting proper Rx Mode and issue Rx Mode Update command */ 821 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 822 823 if (dev->data->dev_conf.intr_conf.lsc) { 824 vmxnet3_enable_intr(hw); 825 826 /* 827 * Update link state from device since this won't be 828 * done upon starting with lsc in use. This is done 829 * only after enabling interrupts to avoid any race 830 * where the link state could change without an 831 * interrupt being fired. 832 */ 833 __vmxnet3_dev_link_update(dev, 0); 834 } 835 836 return VMXNET3_SUCCESS; 837 } 838 839 /* 840 * Stop device: disable rx and tx functions to allow for reconfiguring. 841 */ 842 static void 843 vmxnet3_dev_stop(struct rte_eth_dev *dev) 844 { 845 struct rte_eth_link link; 846 struct vmxnet3_hw *hw = dev->data->dev_private; 847 848 PMD_INIT_FUNC_TRACE(); 849 850 if (hw->adapter_stopped == 1) { 851 PMD_INIT_LOG(DEBUG, "Device already closed."); 852 return; 853 } 854 855 /* disable interrupts */ 856 vmxnet3_disable_intr(hw); 857 858 if (dev->data->dev_conf.intr_conf.lsc) { 859 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 860 861 rte_intr_disable(&pci_dev->intr_handle); 862 863 rte_intr_callback_unregister(&pci_dev->intr_handle, 864 vmxnet3_interrupt_handler, dev); 865 } 866 867 /* quiesce the device first */ 868 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 869 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 870 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 871 872 /* reset the device */ 873 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 874 PMD_INIT_LOG(DEBUG, "Device reset."); 875 hw->adapter_stopped = 0; 876 877 vmxnet3_dev_clear_queues(dev); 878 879 /* Clear recorded link status */ 880 memset(&link, 0, sizeof(link)); 881 vmxnet3_dev_atomic_write_link_status(dev, &link); 882 } 883 884 /* 885 * Reset and stop device. 886 */ 887 static void 888 vmxnet3_dev_close(struct rte_eth_dev *dev) 889 { 890 struct vmxnet3_hw *hw = dev->data->dev_private; 891 892 PMD_INIT_FUNC_TRACE(); 893 894 vmxnet3_dev_stop(dev); 895 hw->adapter_stopped = 1; 896 } 897 898 static void 899 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 900 struct UPT1_TxStats *res) 901 { 902 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 903 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 904 (h)->saved_tx_stats[(i)].f) 905 906 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 907 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 908 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 909 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 910 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 911 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 912 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 913 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 914 915 #undef VMXNET3_UPDATE_TX_STAT 916 } 917 918 static void 919 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 920 struct UPT1_RxStats *res) 921 { 922 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 923 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 924 (h)->saved_rx_stats[(i)].f) 925 926 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 927 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 928 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 929 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 930 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 931 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 932 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 933 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 934 935 #undef VMXNET3_UPDATE_RX_STATS 936 } 937 938 static void 939 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 940 { 941 unsigned int i; 942 943 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 944 945 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 946 947 for (i = 0; i < hw->num_tx_queues; i++) 948 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 949 for (i = 0; i < hw->num_rx_queues; i++) 950 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 951 } 952 953 static int 954 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 955 struct rte_eth_xstat_name *xstats_names, 956 unsigned int n) 957 { 958 unsigned int i, t, count = 0; 959 unsigned int nstats = 960 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 961 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 962 963 if (!xstats_names || n < nstats) 964 return nstats; 965 966 for (i = 0; i < dev->data->nb_rx_queues; i++) { 967 if (!dev->data->rx_queues[i]) 968 continue; 969 970 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 971 snprintf(xstats_names[count].name, 972 sizeof(xstats_names[count].name), 973 "rx_q%u_%s", i, 974 vmxnet3_rxq_stat_strings[t].name); 975 count++; 976 } 977 } 978 979 for (i = 0; i < dev->data->nb_tx_queues; i++) { 980 if (!dev->data->tx_queues[i]) 981 continue; 982 983 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 984 snprintf(xstats_names[count].name, 985 sizeof(xstats_names[count].name), 986 "tx_q%u_%s", i, 987 vmxnet3_txq_stat_strings[t].name); 988 count++; 989 } 990 } 991 992 return count; 993 } 994 995 static int 996 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 997 unsigned int n) 998 { 999 unsigned int i, t, count = 0; 1000 unsigned int nstats = 1001 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1002 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1003 1004 if (n < nstats) 1005 return nstats; 1006 1007 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1008 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1009 1010 if (rxq == NULL) 1011 continue; 1012 1013 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1014 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1015 vmxnet3_rxq_stat_strings[t].offset); 1016 xstats[count].id = count; 1017 count++; 1018 } 1019 } 1020 1021 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1022 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1023 1024 if (txq == NULL) 1025 continue; 1026 1027 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1028 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1029 vmxnet3_txq_stat_strings[t].offset); 1030 xstats[count].id = count; 1031 count++; 1032 } 1033 } 1034 1035 return count; 1036 } 1037 1038 static void 1039 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1040 { 1041 unsigned int i; 1042 struct vmxnet3_hw *hw = dev->data->dev_private; 1043 struct UPT1_TxStats txStats; 1044 struct UPT1_RxStats rxStats; 1045 1046 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1047 1048 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1049 for (i = 0; i < hw->num_tx_queues; i++) { 1050 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1051 1052 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1053 txStats.mcastPktsTxOK + 1054 txStats.bcastPktsTxOK; 1055 1056 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1057 txStats.mcastBytesTxOK + 1058 txStats.bcastBytesTxOK; 1059 1060 stats->opackets += stats->q_opackets[i]; 1061 stats->obytes += stats->q_obytes[i]; 1062 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1063 } 1064 1065 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1066 for (i = 0; i < hw->num_rx_queues; i++) { 1067 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1068 1069 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1070 rxStats.mcastPktsRxOK + 1071 rxStats.bcastPktsRxOK; 1072 1073 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1074 rxStats.mcastBytesRxOK + 1075 rxStats.bcastBytesRxOK; 1076 1077 stats->ipackets += stats->q_ipackets[i]; 1078 stats->ibytes += stats->q_ibytes[i]; 1079 1080 stats->q_errors[i] = rxStats.pktsRxError; 1081 stats->ierrors += rxStats.pktsRxError; 1082 stats->rx_nombuf += rxStats.pktsRxOutOfBuf; 1083 } 1084 } 1085 1086 static void 1087 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1088 struct rte_eth_dev_info *dev_info) 1089 { 1090 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1091 1092 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1093 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1094 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1095 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1096 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1097 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1098 1099 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 1100 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1101 1102 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1103 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1104 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1105 .nb_align = 1, 1106 }; 1107 1108 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1109 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1110 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1111 .nb_align = 1, 1112 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1113 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1114 }; 1115 1116 dev_info->rx_offload_capa = 1117 DEV_RX_OFFLOAD_VLAN_STRIP | 1118 DEV_RX_OFFLOAD_UDP_CKSUM | 1119 DEV_RX_OFFLOAD_TCP_CKSUM | 1120 DEV_RX_OFFLOAD_TCP_LRO; 1121 1122 dev_info->tx_offload_capa = 1123 DEV_TX_OFFLOAD_VLAN_INSERT | 1124 DEV_TX_OFFLOAD_TCP_CKSUM | 1125 DEV_TX_OFFLOAD_UDP_CKSUM | 1126 DEV_TX_OFFLOAD_TCP_TSO; 1127 } 1128 1129 static const uint32_t * 1130 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1131 { 1132 static const uint32_t ptypes[] = { 1133 RTE_PTYPE_L3_IPV4_EXT, 1134 RTE_PTYPE_L3_IPV4, 1135 RTE_PTYPE_UNKNOWN 1136 }; 1137 1138 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1139 return ptypes; 1140 return NULL; 1141 } 1142 1143 static void 1144 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1145 { 1146 struct vmxnet3_hw *hw = dev->data->dev_private; 1147 1148 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1149 } 1150 1151 /* return 0 means link status changed, -1 means not changed */ 1152 static int 1153 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1154 __rte_unused int wait_to_complete) 1155 { 1156 struct vmxnet3_hw *hw = dev->data->dev_private; 1157 struct rte_eth_link old = { 0 }, link; 1158 uint32_t ret; 1159 1160 memset(&link, 0, sizeof(link)); 1161 vmxnet3_dev_atomic_read_link_status(dev, &old); 1162 1163 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1164 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1165 1166 if (ret & 0x1) { 1167 link.link_status = ETH_LINK_UP; 1168 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1169 link.link_speed = ETH_SPEED_NUM_10G; 1170 link.link_autoneg = ETH_LINK_SPEED_FIXED; 1171 } 1172 1173 vmxnet3_dev_atomic_write_link_status(dev, &link); 1174 1175 return (old.link_status == link.link_status) ? -1 : 0; 1176 } 1177 1178 static int 1179 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1180 { 1181 /* Link status doesn't change for stopped dev */ 1182 if (dev->data->dev_started == 0) 1183 return -1; 1184 1185 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1186 } 1187 1188 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1189 static void 1190 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1191 { 1192 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1193 1194 if (set) 1195 rxConf->rxMode = rxConf->rxMode | feature; 1196 else 1197 rxConf->rxMode = rxConf->rxMode & (~feature); 1198 1199 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1200 } 1201 1202 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1203 static void 1204 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1205 { 1206 struct vmxnet3_hw *hw = dev->data->dev_private; 1207 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1208 1209 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1210 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1211 1212 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1213 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1214 } 1215 1216 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1217 static void 1218 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1219 { 1220 struct vmxnet3_hw *hw = dev->data->dev_private; 1221 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1222 1223 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1224 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1225 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1226 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1227 } 1228 1229 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1230 static void 1231 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1232 { 1233 struct vmxnet3_hw *hw = dev->data->dev_private; 1234 1235 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1236 } 1237 1238 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1239 static void 1240 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1241 { 1242 struct vmxnet3_hw *hw = dev->data->dev_private; 1243 1244 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1245 } 1246 1247 /* Enable/disable filter on vlan */ 1248 static int 1249 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1250 { 1251 struct vmxnet3_hw *hw = dev->data->dev_private; 1252 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1253 uint32_t *vf_table = rxConf->vfTable; 1254 1255 /* save state for restore */ 1256 if (on) 1257 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1258 else 1259 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1260 1261 /* don't change active filter if in promiscuous mode */ 1262 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1263 return 0; 1264 1265 /* set in hardware */ 1266 if (on) 1267 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1268 else 1269 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1270 1271 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1272 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1273 return 0; 1274 } 1275 1276 static void 1277 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1278 { 1279 struct vmxnet3_hw *hw = dev->data->dev_private; 1280 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1281 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1282 1283 if (mask & ETH_VLAN_STRIP_MASK) { 1284 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1285 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1286 else 1287 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1288 1289 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1290 VMXNET3_CMD_UPDATE_FEATURE); 1291 } 1292 1293 if (mask & ETH_VLAN_FILTER_MASK) { 1294 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1295 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1296 else 1297 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1298 1299 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1300 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1301 } 1302 } 1303 1304 static void 1305 vmxnet3_process_events(struct rte_eth_dev *dev) 1306 { 1307 struct vmxnet3_hw *hw = dev->data->dev_private; 1308 uint32_t events = hw->shared->ecr; 1309 1310 if (!events) 1311 return; 1312 1313 /* 1314 * ECR bits when written with 1b are cleared. Hence write 1315 * events back to ECR so that the bits which were set will be reset. 1316 */ 1317 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1318 1319 /* Check if link state has changed */ 1320 if (events & VMXNET3_ECR_LINK) { 1321 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1322 if (vmxnet3_dev_link_update(dev, 0) == 0) 1323 _rte_eth_dev_callback_process(dev, 1324 RTE_ETH_EVENT_INTR_LSC, 1325 NULL, NULL); 1326 } 1327 1328 /* Check if there is an error on xmit/recv queues */ 1329 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1330 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1331 VMXNET3_CMD_GET_QUEUE_STATUS); 1332 1333 if (hw->tqd_start->status.stopped) 1334 PMD_DRV_LOG(ERR, "tq error 0x%x", 1335 hw->tqd_start->status.error); 1336 1337 if (hw->rqd_start->status.stopped) 1338 PMD_DRV_LOG(ERR, "rq error 0x%x", 1339 hw->rqd_start->status.error); 1340 1341 /* Reset the device */ 1342 /* Have to reset the device */ 1343 } 1344 1345 if (events & VMXNET3_ECR_DIC) 1346 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1347 1348 if (events & VMXNET3_ECR_DEBUG) 1349 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1350 } 1351 1352 static void 1353 vmxnet3_interrupt_handler(void *param) 1354 { 1355 struct rte_eth_dev *dev = param; 1356 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1357 1358 vmxnet3_process_events(dev); 1359 1360 if (rte_intr_enable(&pci_dev->intr_handle) < 0) 1361 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1362 } 1363 1364 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1365 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1366 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1367