1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <fcntl.h> 42 #include <inttypes.h> 43 #include <rte_byteorder.h> 44 #include <rte_common.h> 45 #include <rte_cycles.h> 46 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_eal.h> 56 #include <rte_alarm.h> 57 #include <rte_ether.h> 58 #include <rte_ethdev.h> 59 #include <rte_atomic.h> 60 #include <rte_string_fns.h> 61 #include <rte_malloc.h> 62 #include <rte_dev.h> 63 64 #include "base/vmxnet3_defs.h" 65 66 #include "vmxnet3_ring.h" 67 #include "vmxnet3_logs.h" 68 #include "vmxnet3_ethdev.h" 69 70 #define PROCESS_SYS_EVENTS 0 71 72 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 73 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 74 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 75 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 76 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 77 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 78 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 79 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 80 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 81 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 82 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 83 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 84 int wait_to_complete); 85 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 86 struct rte_eth_stats *stats); 87 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 88 struct rte_eth_dev_info *dev_info); 89 static const uint32_t * 90 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 92 uint16_t vid, int on); 93 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 94 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 95 struct ether_addr *mac_addr); 96 97 #if PROCESS_SYS_EVENTS == 1 98 static void vmxnet3_process_events(struct vmxnet3_hw *); 99 #endif 100 /* 101 * The set of PCI devices this driver supports 102 */ 103 #define VMWARE_PCI_VENDOR_ID 0x15AD 104 #define VMWARE_DEV_ID_VMXNET3 0x07B0 105 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 106 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 107 { .vendor_id = 0, /* sentinel */ }, 108 }; 109 110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 111 .dev_configure = vmxnet3_dev_configure, 112 .dev_start = vmxnet3_dev_start, 113 .dev_stop = vmxnet3_dev_stop, 114 .dev_close = vmxnet3_dev_close, 115 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 116 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 117 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 118 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 119 .link_update = vmxnet3_dev_link_update, 120 .stats_get = vmxnet3_dev_stats_get, 121 .mac_addr_set = vmxnet3_mac_addr_set, 122 .dev_infos_get = vmxnet3_dev_info_get, 123 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 124 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 125 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 126 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 127 .rx_queue_release = vmxnet3_dev_rx_queue_release, 128 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 129 .tx_queue_release = vmxnet3_dev_tx_queue_release, 130 }; 131 132 static const struct rte_memzone * 133 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 134 const char *post_string, int socket_id, 135 uint16_t align, bool reuse) 136 { 137 char z_name[RTE_MEMZONE_NAMESIZE]; 138 const struct rte_memzone *mz; 139 140 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 141 dev->driver->pci_drv.driver.name, dev->data->port_id, post_string); 142 143 mz = rte_memzone_lookup(z_name); 144 if (!reuse) { 145 if (mz) 146 rte_memzone_free(mz); 147 return rte_memzone_reserve_aligned(z_name, size, socket_id, 148 0, align); 149 } 150 151 if (mz) 152 return mz; 153 154 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align); 155 } 156 157 /** 158 * Atomically reads the link status information from global 159 * structure rte_eth_dev. 160 * 161 * @param dev 162 * - Pointer to the structure rte_eth_dev to read from. 163 * - Pointer to the buffer to be saved with the link status. 164 * 165 * @return 166 * - On success, zero. 167 * - On failure, negative value. 168 */ 169 170 static int 171 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev, 172 struct rte_eth_link *link) 173 { 174 struct rte_eth_link *dst = link; 175 struct rte_eth_link *src = &(dev->data->dev_link); 176 177 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 178 *(uint64_t *)src) == 0) 179 return -1; 180 181 return 0; 182 } 183 184 /** 185 * Atomically writes the link status information into global 186 * structure rte_eth_dev. 187 * 188 * @param dev 189 * - Pointer to the structure rte_eth_dev to write to. 190 * - Pointer to the buffer to be saved with the link status. 191 * 192 * @return 193 * - On success, zero. 194 * - On failure, negative value. 195 */ 196 static int 197 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev, 198 struct rte_eth_link *link) 199 { 200 struct rte_eth_link *dst = &(dev->data->dev_link); 201 struct rte_eth_link *src = link; 202 203 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 204 *(uint64_t *)src) == 0) 205 return -1; 206 207 return 0; 208 } 209 210 /* 211 * This function is based on vmxnet3_disable_intr() 212 */ 213 static void 214 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 215 { 216 int i; 217 218 PMD_INIT_FUNC_TRACE(); 219 220 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 221 for (i = 0; i < VMXNET3_MAX_INTRS; i++) 222 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 223 } 224 225 /* 226 * It returns 0 on success. 227 */ 228 static int 229 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 230 { 231 struct rte_pci_device *pci_dev; 232 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 233 uint32_t mac_hi, mac_lo, ver; 234 235 PMD_INIT_FUNC_TRACE(); 236 237 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 238 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 239 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 240 pci_dev = eth_dev->pci_dev; 241 242 /* 243 * for secondary processes, we don't initialize any further as primary 244 * has already done this work. 245 */ 246 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 247 return 0; 248 249 rte_eth_copy_pci_info(eth_dev, pci_dev); 250 251 /* Vendor and Device ID need to be set before init of shared code */ 252 hw->device_id = pci_dev->id.device_id; 253 hw->vendor_id = pci_dev->id.vendor_id; 254 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 255 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 256 257 hw->num_rx_queues = 1; 258 hw->num_tx_queues = 1; 259 hw->bufs_per_pkt = 1; 260 261 /* Check h/w version compatibility with driver. */ 262 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 263 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 264 if (ver & 0x1) 265 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1); 266 else { 267 PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1"); 268 return -EIO; 269 } 270 271 /* Check UPT version compatibility with driver. */ 272 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 273 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 274 if (ver & 0x1) 275 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 276 else { 277 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 278 return -EIO; 279 } 280 281 /* Getting MAC Address */ 282 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 283 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 284 memcpy(hw->perm_addr, &mac_lo, 4); 285 memcpy(hw->perm_addr + 4, &mac_hi, 2); 286 287 /* Allocate memory for storing MAC addresses */ 288 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 289 VMXNET3_MAX_MAC_ADDRS, 0); 290 if (eth_dev->data->mac_addrs == NULL) { 291 PMD_INIT_LOG(ERR, 292 "Failed to allocate %d bytes needed to store MAC addresses", 293 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 294 return -ENOMEM; 295 } 296 /* Copy the permanent MAC address */ 297 ether_addr_copy((struct ether_addr *) hw->perm_addr, 298 ð_dev->data->mac_addrs[0]); 299 300 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 301 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 302 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 303 304 /* Put device in Quiesce Mode */ 305 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 306 307 /* allow untagged pkts */ 308 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 309 310 return 0; 311 } 312 313 static int 314 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 315 { 316 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 317 318 PMD_INIT_FUNC_TRACE(); 319 320 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 321 return 0; 322 323 if (hw->adapter_stopped == 0) 324 vmxnet3_dev_close(eth_dev); 325 326 eth_dev->dev_ops = NULL; 327 eth_dev->rx_pkt_burst = NULL; 328 eth_dev->tx_pkt_burst = NULL; 329 330 rte_free(eth_dev->data->mac_addrs); 331 eth_dev->data->mac_addrs = NULL; 332 333 return 0; 334 } 335 336 static struct eth_driver rte_vmxnet3_pmd = { 337 .pci_drv = { 338 .id_table = pci_id_vmxnet3_map, 339 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE, 340 .probe = rte_eth_dev_pci_probe, 341 .remove = rte_eth_dev_pci_remove, 342 }, 343 .eth_dev_init = eth_vmxnet3_dev_init, 344 .eth_dev_uninit = eth_vmxnet3_dev_uninit, 345 .dev_private_size = sizeof(struct vmxnet3_hw), 346 }; 347 348 static int 349 vmxnet3_dev_configure(struct rte_eth_dev *dev) 350 { 351 const struct rte_memzone *mz; 352 struct vmxnet3_hw *hw = dev->data->dev_private; 353 size_t size; 354 355 PMD_INIT_FUNC_TRACE(); 356 357 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 358 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 359 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 360 return -EINVAL; 361 } 362 363 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 364 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 365 return -EINVAL; 366 } 367 368 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 369 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 370 371 if (size > UINT16_MAX) 372 return -EINVAL; 373 374 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 375 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 376 377 /* 378 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 379 * on current socket 380 */ 381 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 382 "shared", rte_socket_id(), 8, 1); 383 384 if (mz == NULL) { 385 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 386 return -ENOMEM; 387 } 388 memset(mz->addr, 0, mz->len); 389 390 hw->shared = mz->addr; 391 hw->sharedPA = mz->phys_addr; 392 393 /* 394 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 395 * on current socket. 396 * 397 * We cannot reuse this memzone from previous allocation as its size 398 * depends on the number of tx and rx queues, which could be different 399 * from one config to another. 400 */ 401 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 402 VMXNET3_QUEUE_DESC_ALIGN, 0); 403 if (mz == NULL) { 404 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 405 return -ENOMEM; 406 } 407 memset(mz->addr, 0, mz->len); 408 409 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 410 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 411 412 hw->queueDescPA = mz->phys_addr; 413 hw->queue_desc_len = (uint16_t)size; 414 415 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 416 /* Allocate memory structure for UPT1_RSSConf and configure */ 417 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 418 "rss_conf", rte_socket_id(), 419 RTE_CACHE_LINE_SIZE, 1); 420 if (mz == NULL) { 421 PMD_INIT_LOG(ERR, 422 "ERROR: Creating rss_conf structure zone"); 423 return -ENOMEM; 424 } 425 memset(mz->addr, 0, mz->len); 426 427 hw->rss_conf = mz->addr; 428 hw->rss_confPA = mz->phys_addr; 429 } 430 431 return 0; 432 } 433 434 static void 435 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 436 { 437 uint32_t val; 438 439 PMD_INIT_LOG(DEBUG, 440 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 441 addr[0], addr[1], addr[2], 442 addr[3], addr[4], addr[5]); 443 444 val = *(const uint32_t *)addr; 445 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 446 447 val = (addr[5] << 8) | addr[4]; 448 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 449 } 450 451 static int 452 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 453 { 454 struct rte_eth_conf port_conf = dev->data->dev_conf; 455 struct vmxnet3_hw *hw = dev->data->dev_private; 456 uint32_t mtu = dev->data->mtu; 457 Vmxnet3_DriverShared *shared = hw->shared; 458 Vmxnet3_DSDevRead *devRead = &shared->devRead; 459 uint32_t i; 460 int ret; 461 462 shared->magic = VMXNET3_REV1_MAGIC; 463 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 464 465 /* Setting up Guest OS information */ 466 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 467 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 468 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 469 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 470 devRead->misc.driverInfo.uptVerSpt = 1; 471 472 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 473 devRead->misc.queueDescPA = hw->queueDescPA; 474 devRead->misc.queueDescLen = hw->queue_desc_len; 475 devRead->misc.numTxQueues = hw->num_tx_queues; 476 devRead->misc.numRxQueues = hw->num_rx_queues; 477 478 /* 479 * Set number of interrupts to 1 480 * PMD disables all the interrupts but this is MUST to activate device 481 * It needs at least one interrupt for link events to handle 482 * So we'll disable it later after device activation if needed 483 */ 484 devRead->intrConf.numIntrs = 1; 485 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 486 487 for (i = 0; i < hw->num_tx_queues; i++) { 488 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 489 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 490 491 tqd->ctrl.txNumDeferred = 0; 492 tqd->ctrl.txThreshold = 1; 493 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 494 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 495 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 496 497 tqd->conf.txRingSize = txq->cmd_ring.size; 498 tqd->conf.compRingSize = txq->comp_ring.size; 499 tqd->conf.dataRingSize = txq->data_ring.size; 500 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 501 tqd->status.stopped = TRUE; 502 tqd->status.error = 0; 503 memset(&tqd->stats, 0, sizeof(tqd->stats)); 504 } 505 506 for (i = 0; i < hw->num_rx_queues; i++) { 507 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 508 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 509 510 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 511 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 512 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 513 514 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 515 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 516 rqd->conf.compRingSize = rxq->comp_ring.size; 517 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 518 rqd->status.stopped = TRUE; 519 rqd->status.error = 0; 520 memset(&rqd->stats, 0, sizeof(rqd->stats)); 521 } 522 523 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 524 devRead->rxFilterConf.rxMode = 0; 525 526 /* Setting up feature flags */ 527 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 528 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 529 530 if (dev->data->dev_conf.rxmode.enable_lro) { 531 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 532 devRead->misc.maxNumRxSG = 0; 533 } 534 535 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 536 ret = vmxnet3_rss_configure(dev); 537 if (ret != VMXNET3_SUCCESS) 538 return ret; 539 540 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 541 devRead->rssConfDesc.confVer = 1; 542 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 543 devRead->rssConfDesc.confPA = hw->rss_confPA; 544 } 545 546 vmxnet3_dev_vlan_offload_set(dev, 547 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 548 549 vmxnet3_write_mac(hw, hw->perm_addr); 550 551 return VMXNET3_SUCCESS; 552 } 553 554 /* 555 * Configure device link speed and setup link. 556 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 557 * It returns 0 on success. 558 */ 559 static int 560 vmxnet3_dev_start(struct rte_eth_dev *dev) 561 { 562 int ret; 563 struct vmxnet3_hw *hw = dev->data->dev_private; 564 565 PMD_INIT_FUNC_TRACE(); 566 567 ret = vmxnet3_setup_driver_shared(dev); 568 if (ret != VMXNET3_SUCCESS) 569 return ret; 570 571 /* Exchange shared data with device */ 572 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 573 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 574 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 575 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 576 577 /* Activate device by register write */ 578 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 579 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 580 581 if (ret != 0) { 582 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 583 return -EINVAL; 584 } 585 586 /* Disable interrupts */ 587 vmxnet3_disable_intr(hw); 588 589 /* 590 * Load RX queues with blank mbufs and update next2fill index for device 591 * Update RxMode of the device 592 */ 593 ret = vmxnet3_dev_rxtx_init(dev); 594 if (ret != VMXNET3_SUCCESS) { 595 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 596 return ret; 597 } 598 599 /* Setting proper Rx Mode and issue Rx Mode Update command */ 600 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 601 602 /* 603 * Don't need to handle events for now 604 */ 605 #if PROCESS_SYS_EVENTS == 1 606 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR); 607 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events); 608 vmxnet3_process_events(hw); 609 #endif 610 return VMXNET3_SUCCESS; 611 } 612 613 /* 614 * Stop device: disable rx and tx functions to allow for reconfiguring. 615 */ 616 static void 617 vmxnet3_dev_stop(struct rte_eth_dev *dev) 618 { 619 struct rte_eth_link link; 620 struct vmxnet3_hw *hw = dev->data->dev_private; 621 622 PMD_INIT_FUNC_TRACE(); 623 624 if (hw->adapter_stopped == 1) { 625 PMD_INIT_LOG(DEBUG, "Device already closed."); 626 return; 627 } 628 629 /* disable interrupts */ 630 vmxnet3_disable_intr(hw); 631 632 /* quiesce the device first */ 633 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 634 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 635 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 636 637 /* reset the device */ 638 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 639 PMD_INIT_LOG(DEBUG, "Device reset."); 640 hw->adapter_stopped = 0; 641 642 vmxnet3_dev_clear_queues(dev); 643 644 /* Clear recorded link status */ 645 memset(&link, 0, sizeof(link)); 646 vmxnet3_dev_atomic_write_link_status(dev, &link); 647 } 648 649 /* 650 * Reset and stop device. 651 */ 652 static void 653 vmxnet3_dev_close(struct rte_eth_dev *dev) 654 { 655 struct vmxnet3_hw *hw = dev->data->dev_private; 656 657 PMD_INIT_FUNC_TRACE(); 658 659 vmxnet3_dev_stop(dev); 660 hw->adapter_stopped = 1; 661 } 662 663 static void 664 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 665 { 666 unsigned int i; 667 struct vmxnet3_hw *hw = dev->data->dev_private; 668 669 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 670 671 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 672 for (i = 0; i < hw->num_tx_queues; i++) { 673 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats; 674 675 stats->q_opackets[i] = txStats->ucastPktsTxOK + 676 txStats->mcastPktsTxOK + 677 txStats->bcastPktsTxOK; 678 stats->q_obytes[i] = txStats->ucastBytesTxOK + 679 txStats->mcastBytesTxOK + 680 txStats->bcastBytesTxOK; 681 682 stats->opackets += stats->q_opackets[i]; 683 stats->obytes += stats->q_obytes[i]; 684 stats->oerrors += txStats->pktsTxError + txStats->pktsTxDiscard; 685 } 686 687 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 688 for (i = 0; i < hw->num_rx_queues; i++) { 689 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats; 690 691 stats->q_ipackets[i] = rxStats->ucastPktsRxOK + 692 rxStats->mcastPktsRxOK + 693 rxStats->bcastPktsRxOK; 694 695 stats->q_ibytes[i] = rxStats->ucastBytesRxOK + 696 rxStats->mcastBytesRxOK + 697 rxStats->bcastBytesRxOK; 698 699 stats->ipackets += stats->q_ipackets[i]; 700 stats->ibytes += stats->q_ibytes[i]; 701 702 stats->q_errors[i] = rxStats->pktsRxError; 703 stats->ierrors += rxStats->pktsRxError; 704 stats->rx_nombuf += rxStats->pktsRxOutOfBuf; 705 } 706 } 707 708 static void 709 vmxnet3_dev_info_get(__rte_unused struct rte_eth_dev *dev, 710 struct rte_eth_dev_info *dev_info) 711 { 712 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 713 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 714 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 715 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 716 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 717 718 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 719 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 720 721 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 722 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 723 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 724 .nb_align = 1, 725 }; 726 727 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 728 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 729 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 730 .nb_align = 1, 731 }; 732 733 dev_info->rx_offload_capa = 734 DEV_RX_OFFLOAD_VLAN_STRIP | 735 DEV_RX_OFFLOAD_UDP_CKSUM | 736 DEV_RX_OFFLOAD_TCP_CKSUM | 737 DEV_RX_OFFLOAD_TCP_LRO; 738 739 dev_info->tx_offload_capa = 740 DEV_TX_OFFLOAD_VLAN_INSERT | 741 DEV_TX_OFFLOAD_TCP_CKSUM | 742 DEV_TX_OFFLOAD_UDP_CKSUM | 743 DEV_TX_OFFLOAD_TCP_TSO; 744 } 745 746 static const uint32_t * 747 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 748 { 749 static const uint32_t ptypes[] = { 750 RTE_PTYPE_L3_IPV4_EXT, 751 RTE_PTYPE_L3_IPV4, 752 RTE_PTYPE_UNKNOWN 753 }; 754 755 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 756 return ptypes; 757 return NULL; 758 } 759 760 static void 761 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 762 { 763 struct vmxnet3_hw *hw = dev->data->dev_private; 764 765 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 766 } 767 768 /* return 0 means link status changed, -1 means not changed */ 769 static int 770 vmxnet3_dev_link_update(struct rte_eth_dev *dev, 771 __rte_unused int wait_to_complete) 772 { 773 struct vmxnet3_hw *hw = dev->data->dev_private; 774 struct rte_eth_link old, link; 775 uint32_t ret; 776 777 /* Link status doesn't change for stopped dev */ 778 if (dev->data->dev_started == 0) 779 return -1; 780 781 memset(&link, 0, sizeof(link)); 782 vmxnet3_dev_atomic_read_link_status(dev, &old); 783 784 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 785 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 786 787 if (ret & 0x1) { 788 link.link_status = ETH_LINK_UP; 789 link.link_duplex = ETH_LINK_FULL_DUPLEX; 790 link.link_speed = ETH_SPEED_NUM_10G; 791 link.link_autoneg = ETH_LINK_SPEED_FIXED; 792 } 793 794 vmxnet3_dev_atomic_write_link_status(dev, &link); 795 796 return (old.link_status == link.link_status) ? -1 : 0; 797 } 798 799 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 800 static void 801 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 802 { 803 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 804 805 if (set) 806 rxConf->rxMode = rxConf->rxMode | feature; 807 else 808 rxConf->rxMode = rxConf->rxMode & (~feature); 809 810 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 811 } 812 813 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 814 static void 815 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 816 { 817 struct vmxnet3_hw *hw = dev->data->dev_private; 818 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 819 820 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 821 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 822 823 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 824 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 825 } 826 827 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 828 static void 829 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 830 { 831 struct vmxnet3_hw *hw = dev->data->dev_private; 832 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 833 834 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 835 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 836 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 837 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 838 } 839 840 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 841 static void 842 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 843 { 844 struct vmxnet3_hw *hw = dev->data->dev_private; 845 846 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 847 } 848 849 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 850 static void 851 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 852 { 853 struct vmxnet3_hw *hw = dev->data->dev_private; 854 855 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 856 } 857 858 /* Enable/disable filter on vlan */ 859 static int 860 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 861 { 862 struct vmxnet3_hw *hw = dev->data->dev_private; 863 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 864 uint32_t *vf_table = rxConf->vfTable; 865 866 /* save state for restore */ 867 if (on) 868 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 869 else 870 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 871 872 /* don't change active filter if in promiscuous mode */ 873 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 874 return 0; 875 876 /* set in hardware */ 877 if (on) 878 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 879 else 880 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 881 882 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 883 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 884 return 0; 885 } 886 887 static void 888 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 889 { 890 struct vmxnet3_hw *hw = dev->data->dev_private; 891 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 892 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 893 894 if (mask & ETH_VLAN_STRIP_MASK) { 895 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 896 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 897 else 898 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 899 900 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 901 VMXNET3_CMD_UPDATE_FEATURE); 902 } 903 904 if (mask & ETH_VLAN_FILTER_MASK) { 905 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 906 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 907 else 908 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 909 910 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 911 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 912 } 913 } 914 915 #if PROCESS_SYS_EVENTS == 1 916 static void 917 vmxnet3_process_events(struct vmxnet3_hw *hw) 918 { 919 uint32_t events = hw->shared->ecr; 920 921 if (!events) { 922 PMD_INIT_LOG(ERR, "No events to process"); 923 return; 924 } 925 926 /* 927 * ECR bits when written with 1b are cleared. Hence write 928 * events back to ECR so that the bits which were set will be reset. 929 */ 930 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 931 932 /* Check if link state has changed */ 933 if (events & VMXNET3_ECR_LINK) 934 PMD_INIT_LOG(ERR, 935 "Process events in %s(): VMXNET3_ECR_LINK event", 936 __func__); 937 938 /* Check if there is an error on xmit/recv queues */ 939 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 940 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 941 VMXNET3_CMD_GET_QUEUE_STATUS); 942 943 if (hw->tqd_start->status.stopped) 944 PMD_INIT_LOG(ERR, "tq error 0x%x", 945 hw->tqd_start->status.error); 946 947 if (hw->rqd_start->status.stopped) 948 PMD_INIT_LOG(ERR, "rq error 0x%x", 949 hw->rqd_start->status.error); 950 951 /* Reset the device */ 952 /* Have to reset the device */ 953 } 954 955 if (events & VMXNET3_ECR_DIC) 956 PMD_INIT_LOG(ERR, "Device implementation change event."); 957 958 if (events & VMXNET3_ECR_DEBUG) 959 PMD_INIT_LOG(ERR, "Debug event generated by device."); 960 } 961 #endif 962 963 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd.pci_drv); 964 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 965 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio"); 966