1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 60 DEV_RX_OFFLOAD_RSS_HASH) 61 62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 65 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 67 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 74 int wait_to_complete); 75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 76 int wait_to_complete); 77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 79 struct rte_eth_stats *stats); 80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 82 struct rte_eth_xstat_name *xstats, 83 unsigned int n); 84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 85 struct rte_eth_xstat *xstats, unsigned int n); 86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 87 struct rte_eth_dev_info *dev_info); 88 static const uint32_t * 89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 90 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 91 uint16_t vid, int on); 92 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 93 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 94 struct rte_ether_addr *mac_addr); 95 static void vmxnet3_interrupt_handler(void *param); 96 97 int vmxnet3_logtype_init; 98 int vmxnet3_logtype_driver; 99 100 /* 101 * The set of PCI devices this driver supports 102 */ 103 #define VMWARE_PCI_VENDOR_ID 0x15AD 104 #define VMWARE_DEV_ID_VMXNET3 0x07B0 105 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 106 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 107 { .vendor_id = 0, /* sentinel */ }, 108 }; 109 110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 111 .dev_configure = vmxnet3_dev_configure, 112 .dev_start = vmxnet3_dev_start, 113 .dev_stop = vmxnet3_dev_stop, 114 .dev_close = vmxnet3_dev_close, 115 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 116 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 117 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 118 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 119 .link_update = vmxnet3_dev_link_update, 120 .stats_get = vmxnet3_dev_stats_get, 121 .xstats_get_names = vmxnet3_dev_xstats_get_names, 122 .xstats_get = vmxnet3_dev_xstats_get, 123 .stats_reset = vmxnet3_dev_stats_reset, 124 .mac_addr_set = vmxnet3_mac_addr_set, 125 .dev_infos_get = vmxnet3_dev_info_get, 126 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 127 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 128 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 129 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 130 .rx_queue_release = vmxnet3_dev_rx_queue_release, 131 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 132 .tx_queue_release = vmxnet3_dev_tx_queue_release, 133 }; 134 135 struct vmxnet3_xstats_name_off { 136 char name[RTE_ETH_XSTATS_NAME_SIZE]; 137 unsigned int offset; 138 }; 139 140 /* tx_qX_ is prepended to the name string here */ 141 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 142 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 143 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 144 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 145 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 146 }; 147 148 /* rx_qX_ is prepended to the name string here */ 149 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 150 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 151 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 152 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 153 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 154 }; 155 156 static const struct rte_memzone * 157 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 158 const char *post_string, int socket_id, 159 uint16_t align, bool reuse) 160 { 161 char z_name[RTE_MEMZONE_NAMESIZE]; 162 const struct rte_memzone *mz; 163 164 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 165 dev->data->port_id, post_string); 166 167 mz = rte_memzone_lookup(z_name); 168 if (!reuse) { 169 if (mz) 170 rte_memzone_free(mz); 171 return rte_memzone_reserve_aligned(z_name, size, socket_id, 172 RTE_MEMZONE_IOVA_CONTIG, align); 173 } 174 175 if (mz) 176 return mz; 177 178 return rte_memzone_reserve_aligned(z_name, size, socket_id, 179 RTE_MEMZONE_IOVA_CONTIG, align); 180 } 181 182 /* 183 * This function is based on vmxnet3_disable_intr() 184 */ 185 static void 186 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 187 { 188 int i; 189 190 PMD_INIT_FUNC_TRACE(); 191 192 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 193 for (i = 0; i < hw->num_intrs; i++) 194 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 195 } 196 197 static void 198 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 199 { 200 int i; 201 202 PMD_INIT_FUNC_TRACE(); 203 204 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 205 for (i = 0; i < hw->num_intrs; i++) 206 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 207 } 208 209 /* 210 * Gets tx data ring descriptor size. 211 */ 212 static uint16_t 213 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 214 { 215 uint16 txdata_desc_size; 216 217 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 218 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 219 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 220 221 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 222 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 223 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 224 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 225 } 226 227 /* 228 * It returns 0 on success. 229 */ 230 static int 231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 232 { 233 struct rte_pci_device *pci_dev; 234 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 235 uint32_t mac_hi, mac_lo, ver; 236 struct rte_eth_link link; 237 238 PMD_INIT_FUNC_TRACE(); 239 240 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 241 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 242 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 243 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 244 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 245 246 /* 247 * for secondary processes, we don't initialize any further as primary 248 * has already done this work. 249 */ 250 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 251 return 0; 252 253 rte_eth_copy_pci_info(eth_dev, pci_dev); 254 255 /* Vendor and Device ID need to be set before init of shared code */ 256 hw->device_id = pci_dev->id.device_id; 257 hw->vendor_id = pci_dev->id.vendor_id; 258 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 259 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 260 261 hw->num_rx_queues = 1; 262 hw->num_tx_queues = 1; 263 hw->bufs_per_pkt = 1; 264 265 /* Check h/w version compatibility with driver. */ 266 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 267 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 268 269 if (ver & (1 << VMXNET3_REV_4)) { 270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 271 1 << VMXNET3_REV_4); 272 hw->version = VMXNET3_REV_4 + 1; 273 } else if (ver & (1 << VMXNET3_REV_3)) { 274 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 275 1 << VMXNET3_REV_3); 276 hw->version = VMXNET3_REV_3 + 1; 277 } else if (ver & (1 << VMXNET3_REV_2)) { 278 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 279 1 << VMXNET3_REV_2); 280 hw->version = VMXNET3_REV_2 + 1; 281 } else if (ver & (1 << VMXNET3_REV_1)) { 282 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 283 1 << VMXNET3_REV_1); 284 hw->version = VMXNET3_REV_1 + 1; 285 } else { 286 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 287 return -EIO; 288 } 289 290 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 291 292 /* Check UPT version compatibility with driver. */ 293 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 294 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 295 if (ver & 0x1) 296 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 297 else { 298 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 299 return -EIO; 300 } 301 302 /* Getting MAC Address */ 303 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 304 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 305 memcpy(hw->perm_addr, &mac_lo, 4); 306 memcpy(hw->perm_addr + 4, &mac_hi, 2); 307 308 /* Allocate memory for storing MAC addresses */ 309 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 310 VMXNET3_MAX_MAC_ADDRS, 0); 311 if (eth_dev->data->mac_addrs == NULL) { 312 PMD_INIT_LOG(ERR, 313 "Failed to allocate %d bytes needed to store MAC addresses", 314 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 315 return -ENOMEM; 316 } 317 /* Copy the permanent MAC address */ 318 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 319 ð_dev->data->mac_addrs[0]); 320 321 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 322 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 323 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 324 325 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 326 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 327 328 /* Put device in Quiesce Mode */ 329 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 330 331 /* allow untagged pkts */ 332 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 333 334 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 335 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 336 337 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 338 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 339 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 340 hw->rxdata_desc_size); 341 342 /* clear shadow stats */ 343 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 344 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 345 346 /* clear snapshot stats */ 347 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 348 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 349 350 /* set the initial link status */ 351 memset(&link, 0, sizeof(link)); 352 link.link_duplex = ETH_LINK_FULL_DUPLEX; 353 link.link_speed = ETH_SPEED_NUM_10G; 354 link.link_autoneg = ETH_LINK_FIXED; 355 rte_eth_linkstatus_set(eth_dev, &link); 356 357 return 0; 358 } 359 360 static int 361 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 362 { 363 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 364 365 PMD_INIT_FUNC_TRACE(); 366 367 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 368 return 0; 369 370 if (hw->adapter_stopped == 0) { 371 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 372 return -EBUSY; 373 } 374 375 eth_dev->dev_ops = NULL; 376 eth_dev->rx_pkt_burst = NULL; 377 eth_dev->tx_pkt_burst = NULL; 378 eth_dev->tx_pkt_prepare = NULL; 379 380 return 0; 381 } 382 383 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 384 struct rte_pci_device *pci_dev) 385 { 386 return rte_eth_dev_pci_generic_probe(pci_dev, 387 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 388 } 389 390 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 391 { 392 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 393 } 394 395 static struct rte_pci_driver rte_vmxnet3_pmd = { 396 .id_table = pci_id_vmxnet3_map, 397 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 398 .probe = eth_vmxnet3_pci_probe, 399 .remove = eth_vmxnet3_pci_remove, 400 }; 401 402 static int 403 vmxnet3_dev_configure(struct rte_eth_dev *dev) 404 { 405 const struct rte_memzone *mz; 406 struct vmxnet3_hw *hw = dev->data->dev_private; 407 size_t size; 408 409 PMD_INIT_FUNC_TRACE(); 410 411 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 412 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 413 414 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 415 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 416 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 417 return -EINVAL; 418 } 419 420 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 421 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 422 return -EINVAL; 423 } 424 425 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 426 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 427 428 if (size > UINT16_MAX) 429 return -EINVAL; 430 431 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 432 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 433 434 /* 435 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 436 * on current socket 437 */ 438 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 439 "shared", rte_socket_id(), 8, 1); 440 441 if (mz == NULL) { 442 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 443 return -ENOMEM; 444 } 445 memset(mz->addr, 0, mz->len); 446 447 hw->shared = mz->addr; 448 hw->sharedPA = mz->iova; 449 450 /* 451 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 452 * on current socket. 453 * 454 * We cannot reuse this memzone from previous allocation as its size 455 * depends on the number of tx and rx queues, which could be different 456 * from one config to another. 457 */ 458 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 459 VMXNET3_QUEUE_DESC_ALIGN, 0); 460 if (mz == NULL) { 461 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 462 return -ENOMEM; 463 } 464 memset(mz->addr, 0, mz->len); 465 466 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 467 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 468 469 hw->queueDescPA = mz->iova; 470 hw->queue_desc_len = (uint16_t)size; 471 472 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 473 /* Allocate memory structure for UPT1_RSSConf and configure */ 474 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 475 "rss_conf", rte_socket_id(), 476 RTE_CACHE_LINE_SIZE, 1); 477 if (mz == NULL) { 478 PMD_INIT_LOG(ERR, 479 "ERROR: Creating rss_conf structure zone"); 480 return -ENOMEM; 481 } 482 memset(mz->addr, 0, mz->len); 483 484 hw->rss_conf = mz->addr; 485 hw->rss_confPA = mz->iova; 486 } 487 488 return 0; 489 } 490 491 static void 492 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 493 { 494 uint32_t val; 495 496 PMD_INIT_LOG(DEBUG, 497 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 498 addr[0], addr[1], addr[2], 499 addr[3], addr[4], addr[5]); 500 501 memcpy(&val, addr, 4); 502 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 503 504 memcpy(&val, addr + 4, 2); 505 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 506 } 507 508 static int 509 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 510 { 511 struct vmxnet3_hw *hw = dev->data->dev_private; 512 Vmxnet3_DriverShared *shared = hw->shared; 513 Vmxnet3_CmdInfo *cmdInfo; 514 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 515 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 516 uint32_t num, i, j, size; 517 518 if (hw->memRegsPA == 0) { 519 const struct rte_memzone *mz; 520 521 size = sizeof(Vmxnet3_MemRegs) + 522 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 523 sizeof(Vmxnet3_MemoryRegion); 524 525 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 526 1); 527 if (mz == NULL) { 528 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 529 return -ENOMEM; 530 } 531 memset(mz->addr, 0, mz->len); 532 hw->memRegs = mz->addr; 533 hw->memRegsPA = mz->iova; 534 } 535 536 num = hw->num_rx_queues; 537 538 for (i = 0; i < num; i++) { 539 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 540 541 mp[i] = rxq->mp; 542 index[i] = 1 << i; 543 } 544 545 /* 546 * The same mempool could be used by multiple queues. In such a case, 547 * remove duplicate mempool entries. Only one entry is kept with 548 * bitmask indicating queues that are using this mempool. 549 */ 550 for (i = 1; i < num; i++) { 551 for (j = 0; j < i; j++) { 552 if (mp[i] == mp[j]) { 553 mp[i] = NULL; 554 index[j] |= 1 << i; 555 break; 556 } 557 } 558 } 559 560 j = 0; 561 for (i = 0; i < num; i++) { 562 if (mp[i] == NULL) 563 continue; 564 565 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 566 567 mr->startPA = 568 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 569 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 570 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 571 mr->txQueueBits = index[i]; 572 mr->rxQueueBits = index[i]; 573 574 PMD_INIT_LOG(INFO, 575 "index: %u startPA: %" PRIu64 " length: %u, " 576 "rxBits: %x", 577 j, mr->startPA, mr->length, mr->rxQueueBits); 578 j++; 579 } 580 hw->memRegs->numRegs = j; 581 PMD_INIT_LOG(INFO, "numRegs: %u", j); 582 583 size = sizeof(Vmxnet3_MemRegs) + 584 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 585 586 cmdInfo = &shared->cu.cmdInfo; 587 cmdInfo->varConf.confVer = 1; 588 cmdInfo->varConf.confLen = size; 589 cmdInfo->varConf.confPA = hw->memRegsPA; 590 591 return 0; 592 } 593 594 static int 595 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 596 { 597 struct rte_eth_conf port_conf = dev->data->dev_conf; 598 struct vmxnet3_hw *hw = dev->data->dev_private; 599 uint32_t mtu = dev->data->mtu; 600 Vmxnet3_DriverShared *shared = hw->shared; 601 Vmxnet3_DSDevRead *devRead = &shared->devRead; 602 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 603 uint32_t i; 604 int ret; 605 606 hw->mtu = mtu; 607 608 shared->magic = VMXNET3_REV1_MAGIC; 609 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 610 611 /* Setting up Guest OS information */ 612 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 613 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 614 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 615 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 616 devRead->misc.driverInfo.uptVerSpt = 1; 617 618 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 619 devRead->misc.queueDescPA = hw->queueDescPA; 620 devRead->misc.queueDescLen = hw->queue_desc_len; 621 devRead->misc.numTxQueues = hw->num_tx_queues; 622 devRead->misc.numRxQueues = hw->num_rx_queues; 623 624 /* 625 * Set number of interrupts to 1 626 * PMD by default disables all the interrupts but this is MUST 627 * to activate device. It needs at least one interrupt for 628 * link events to handle 629 */ 630 hw->num_intrs = devRead->intrConf.numIntrs = 1; 631 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 632 633 for (i = 0; i < hw->num_tx_queues; i++) { 634 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 635 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 636 637 txq->shared = &hw->tqd_start[i]; 638 639 tqd->ctrl.txNumDeferred = 0; 640 tqd->ctrl.txThreshold = 1; 641 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 642 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 643 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 644 645 tqd->conf.txRingSize = txq->cmd_ring.size; 646 tqd->conf.compRingSize = txq->comp_ring.size; 647 tqd->conf.dataRingSize = txq->data_ring.size; 648 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 649 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 650 tqd->status.stopped = TRUE; 651 tqd->status.error = 0; 652 memset(&tqd->stats, 0, sizeof(tqd->stats)); 653 } 654 655 for (i = 0; i < hw->num_rx_queues; i++) { 656 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 657 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 658 659 rxq->shared = &hw->rqd_start[i]; 660 661 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 662 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 663 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 664 665 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 666 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 667 rqd->conf.compRingSize = rxq->comp_ring.size; 668 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 669 if (VMXNET3_VERSION_GE_3(hw)) { 670 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 671 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 672 } 673 rqd->status.stopped = TRUE; 674 rqd->status.error = 0; 675 memset(&rqd->stats, 0, sizeof(rqd->stats)); 676 } 677 678 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 679 devRead->rxFilterConf.rxMode = 0; 680 681 /* Setting up feature flags */ 682 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 683 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 684 685 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 686 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 687 devRead->misc.maxNumRxSG = 0; 688 } 689 690 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 691 ret = vmxnet3_rss_configure(dev); 692 if (ret != VMXNET3_SUCCESS) 693 return ret; 694 695 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 696 devRead->rssConfDesc.confVer = 1; 697 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 698 devRead->rssConfDesc.confPA = hw->rss_confPA; 699 } 700 701 ret = vmxnet3_dev_vlan_offload_set(dev, 702 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 703 if (ret) 704 return ret; 705 706 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 707 708 return VMXNET3_SUCCESS; 709 } 710 711 /* 712 * Configure device link speed and setup link. 713 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 714 * It returns 0 on success. 715 */ 716 static int 717 vmxnet3_dev_start(struct rte_eth_dev *dev) 718 { 719 int ret; 720 struct vmxnet3_hw *hw = dev->data->dev_private; 721 722 PMD_INIT_FUNC_TRACE(); 723 724 /* Save stats before it is reset by CMD_ACTIVATE */ 725 vmxnet3_hw_stats_save(hw); 726 727 ret = vmxnet3_setup_driver_shared(dev); 728 if (ret != VMXNET3_SUCCESS) 729 return ret; 730 731 /* check if lsc interrupt feature is enabled */ 732 if (dev->data->dev_conf.intr_conf.lsc) { 733 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 734 735 /* Setup interrupt callback */ 736 rte_intr_callback_register(&pci_dev->intr_handle, 737 vmxnet3_interrupt_handler, dev); 738 739 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 740 PMD_INIT_LOG(ERR, "interrupt enable failed"); 741 return -EIO; 742 } 743 } 744 745 /* Exchange shared data with device */ 746 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 747 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 748 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 749 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 750 751 /* Activate device by register write */ 752 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 753 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 754 755 if (ret != 0) { 756 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 757 return -EINVAL; 758 } 759 760 /* Setup memory region for rx buffers */ 761 ret = vmxnet3_dev_setup_memreg(dev); 762 if (ret == 0) { 763 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 764 VMXNET3_CMD_REGISTER_MEMREGS); 765 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 766 if (ret != 0) 767 PMD_INIT_LOG(DEBUG, 768 "Failed in setup memory region cmd\n"); 769 ret = 0; 770 } else { 771 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 772 } 773 774 if (VMXNET3_VERSION_GE_4(hw) && 775 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 776 /* Check for additional RSS */ 777 ret = vmxnet3_v4_rss_configure(dev); 778 if (ret != VMXNET3_SUCCESS) { 779 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 780 return ret; 781 } 782 } 783 784 /* Disable interrupts */ 785 vmxnet3_disable_intr(hw); 786 787 /* 788 * Load RX queues with blank mbufs and update next2fill index for device 789 * Update RxMode of the device 790 */ 791 ret = vmxnet3_dev_rxtx_init(dev); 792 if (ret != VMXNET3_SUCCESS) { 793 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 794 return ret; 795 } 796 797 hw->adapter_stopped = FALSE; 798 799 /* Setting proper Rx Mode and issue Rx Mode Update command */ 800 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 801 802 if (dev->data->dev_conf.intr_conf.lsc) { 803 vmxnet3_enable_intr(hw); 804 805 /* 806 * Update link state from device since this won't be 807 * done upon starting with lsc in use. This is done 808 * only after enabling interrupts to avoid any race 809 * where the link state could change without an 810 * interrupt being fired. 811 */ 812 __vmxnet3_dev_link_update(dev, 0); 813 } 814 815 return VMXNET3_SUCCESS; 816 } 817 818 /* 819 * Stop device: disable rx and tx functions to allow for reconfiguring. 820 */ 821 static void 822 vmxnet3_dev_stop(struct rte_eth_dev *dev) 823 { 824 struct rte_eth_link link; 825 struct vmxnet3_hw *hw = dev->data->dev_private; 826 827 PMD_INIT_FUNC_TRACE(); 828 829 if (hw->adapter_stopped == 1) { 830 PMD_INIT_LOG(DEBUG, "Device already stopped."); 831 return; 832 } 833 834 /* disable interrupts */ 835 vmxnet3_disable_intr(hw); 836 837 if (dev->data->dev_conf.intr_conf.lsc) { 838 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 839 840 rte_intr_disable(&pci_dev->intr_handle); 841 842 rte_intr_callback_unregister(&pci_dev->intr_handle, 843 vmxnet3_interrupt_handler, dev); 844 } 845 846 /* quiesce the device first */ 847 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 848 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 849 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 850 851 /* reset the device */ 852 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 853 PMD_INIT_LOG(DEBUG, "Device reset."); 854 855 vmxnet3_dev_clear_queues(dev); 856 857 /* Clear recorded link status */ 858 memset(&link, 0, sizeof(link)); 859 link.link_duplex = ETH_LINK_FULL_DUPLEX; 860 link.link_speed = ETH_SPEED_NUM_10G; 861 link.link_autoneg = ETH_LINK_FIXED; 862 rte_eth_linkstatus_set(dev, &link); 863 864 hw->adapter_stopped = 1; 865 } 866 867 static void 868 vmxnet3_free_queues(struct rte_eth_dev *dev) 869 { 870 int i; 871 872 PMD_INIT_FUNC_TRACE(); 873 874 for (i = 0; i < dev->data->nb_rx_queues; i++) { 875 void *rxq = dev->data->rx_queues[i]; 876 877 vmxnet3_dev_rx_queue_release(rxq); 878 } 879 dev->data->nb_rx_queues = 0; 880 881 for (i = 0; i < dev->data->nb_tx_queues; i++) { 882 void *txq = dev->data->tx_queues[i]; 883 884 vmxnet3_dev_tx_queue_release(txq); 885 } 886 dev->data->nb_tx_queues = 0; 887 } 888 889 /* 890 * Reset and stop device. 891 */ 892 static void 893 vmxnet3_dev_close(struct rte_eth_dev *dev) 894 { 895 PMD_INIT_FUNC_TRACE(); 896 897 vmxnet3_dev_stop(dev); 898 vmxnet3_free_queues(dev); 899 } 900 901 static void 902 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 903 struct UPT1_TxStats *res) 904 { 905 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 906 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 907 (h)->saved_tx_stats[(i)].f) 908 909 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 910 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 911 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 912 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 913 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 914 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 915 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 916 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 917 918 #undef VMXNET3_UPDATE_TX_STAT 919 } 920 921 static void 922 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 923 struct UPT1_RxStats *res) 924 { 925 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 926 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 927 (h)->saved_rx_stats[(i)].f) 928 929 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 930 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 931 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 932 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 933 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 934 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 935 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 936 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 937 938 #undef VMXNET3_UPDATE_RX_STAT 939 } 940 941 static void 942 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 943 struct UPT1_TxStats *res) 944 { 945 vmxnet3_hw_tx_stats_get(hw, q, res); 946 947 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 948 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 949 950 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 951 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 953 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 954 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 955 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 956 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 957 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 958 959 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 960 } 961 962 static void 963 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 964 struct UPT1_RxStats *res) 965 { 966 vmxnet3_hw_rx_stats_get(hw, q, res); 967 968 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 969 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 970 971 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 972 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 974 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 975 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 976 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 977 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 978 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 979 980 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 981 } 982 983 static void 984 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 985 { 986 unsigned int i; 987 988 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 989 990 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 991 992 for (i = 0; i < hw->num_tx_queues; i++) 993 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 994 for (i = 0; i < hw->num_rx_queues; i++) 995 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 996 } 997 998 static int 999 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 1000 struct rte_eth_xstat_name *xstats_names, 1001 unsigned int n) 1002 { 1003 unsigned int i, t, count = 0; 1004 unsigned int nstats = 1005 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1006 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1007 1008 if (!xstats_names || n < nstats) 1009 return nstats; 1010 1011 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1012 if (!dev->data->rx_queues[i]) 1013 continue; 1014 1015 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1016 snprintf(xstats_names[count].name, 1017 sizeof(xstats_names[count].name), 1018 "rx_q%u_%s", i, 1019 vmxnet3_rxq_stat_strings[t].name); 1020 count++; 1021 } 1022 } 1023 1024 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1025 if (!dev->data->tx_queues[i]) 1026 continue; 1027 1028 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1029 snprintf(xstats_names[count].name, 1030 sizeof(xstats_names[count].name), 1031 "tx_q%u_%s", i, 1032 vmxnet3_txq_stat_strings[t].name); 1033 count++; 1034 } 1035 } 1036 1037 return count; 1038 } 1039 1040 static int 1041 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1042 unsigned int n) 1043 { 1044 unsigned int i, t, count = 0; 1045 unsigned int nstats = 1046 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1047 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1048 1049 if (n < nstats) 1050 return nstats; 1051 1052 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1053 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1054 1055 if (rxq == NULL) 1056 continue; 1057 1058 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1059 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1060 vmxnet3_rxq_stat_strings[t].offset); 1061 xstats[count].id = count; 1062 count++; 1063 } 1064 } 1065 1066 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1067 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1068 1069 if (txq == NULL) 1070 continue; 1071 1072 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1073 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1074 vmxnet3_txq_stat_strings[t].offset); 1075 xstats[count].id = count; 1076 count++; 1077 } 1078 } 1079 1080 return count; 1081 } 1082 1083 static int 1084 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1085 { 1086 unsigned int i; 1087 struct vmxnet3_hw *hw = dev->data->dev_private; 1088 struct UPT1_TxStats txStats; 1089 struct UPT1_RxStats rxStats; 1090 1091 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1092 1093 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1094 for (i = 0; i < hw->num_tx_queues; i++) { 1095 vmxnet3_tx_stats_get(hw, i, &txStats); 1096 1097 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1098 txStats.mcastPktsTxOK + 1099 txStats.bcastPktsTxOK; 1100 1101 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1102 txStats.mcastBytesTxOK + 1103 txStats.bcastBytesTxOK; 1104 1105 stats->opackets += stats->q_opackets[i]; 1106 stats->obytes += stats->q_obytes[i]; 1107 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1108 } 1109 1110 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1111 for (i = 0; i < hw->num_rx_queues; i++) { 1112 vmxnet3_rx_stats_get(hw, i, &rxStats); 1113 1114 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1115 rxStats.mcastPktsRxOK + 1116 rxStats.bcastPktsRxOK; 1117 1118 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1119 rxStats.mcastBytesRxOK + 1120 rxStats.bcastBytesRxOK; 1121 1122 stats->ipackets += stats->q_ipackets[i]; 1123 stats->ibytes += stats->q_ibytes[i]; 1124 1125 stats->q_errors[i] = rxStats.pktsRxError; 1126 stats->ierrors += rxStats.pktsRxError; 1127 stats->imissed += rxStats.pktsRxOutOfBuf; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static int 1134 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1135 { 1136 unsigned int i; 1137 struct vmxnet3_hw *hw = dev->data->dev_private; 1138 struct UPT1_TxStats txStats = {0}; 1139 struct UPT1_RxStats rxStats = {0}; 1140 1141 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1142 1143 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1144 1145 for (i = 0; i < hw->num_tx_queues; i++) { 1146 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1147 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1148 sizeof(hw->snapshot_tx_stats[0])); 1149 } 1150 for (i = 0; i < hw->num_rx_queues; i++) { 1151 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1152 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1153 sizeof(hw->snapshot_rx_stats[0])); 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int 1160 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1161 struct rte_eth_dev_info *dev_info) 1162 { 1163 struct vmxnet3_hw *hw = dev->data->dev_private; 1164 1165 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1166 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1167 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1168 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1169 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1170 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1171 1172 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1173 1174 if (VMXNET3_VERSION_GE_4(hw)) { 1175 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1176 } 1177 1178 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1179 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1180 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1181 .nb_align = 1, 1182 }; 1183 1184 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1185 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1186 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1187 .nb_align = 1, 1188 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1189 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1190 }; 1191 1192 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1193 dev_info->rx_queue_offload_capa = 0; 1194 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1195 dev_info->tx_queue_offload_capa = 0; 1196 1197 return 0; 1198 } 1199 1200 static const uint32_t * 1201 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1202 { 1203 static const uint32_t ptypes[] = { 1204 RTE_PTYPE_L3_IPV4_EXT, 1205 RTE_PTYPE_L3_IPV4, 1206 RTE_PTYPE_UNKNOWN 1207 }; 1208 1209 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1210 return ptypes; 1211 return NULL; 1212 } 1213 1214 static int 1215 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1216 { 1217 struct vmxnet3_hw *hw = dev->data->dev_private; 1218 1219 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1220 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1221 return 0; 1222 } 1223 1224 /* return 0 means link status changed, -1 means not changed */ 1225 static int 1226 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1227 __rte_unused int wait_to_complete) 1228 { 1229 struct vmxnet3_hw *hw = dev->data->dev_private; 1230 struct rte_eth_link link; 1231 uint32_t ret; 1232 1233 memset(&link, 0, sizeof(link)); 1234 1235 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1236 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1237 1238 if (ret & 0x1) 1239 link.link_status = ETH_LINK_UP; 1240 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1241 link.link_speed = ETH_SPEED_NUM_10G; 1242 link.link_autoneg = ETH_LINK_FIXED; 1243 1244 return rte_eth_linkstatus_set(dev, &link); 1245 } 1246 1247 static int 1248 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1249 { 1250 /* Link status doesn't change for stopped dev */ 1251 if (dev->data->dev_started == 0) 1252 return -1; 1253 1254 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1255 } 1256 1257 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1258 static void 1259 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1260 { 1261 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1262 1263 if (set) 1264 rxConf->rxMode = rxConf->rxMode | feature; 1265 else 1266 rxConf->rxMode = rxConf->rxMode & (~feature); 1267 1268 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1269 } 1270 1271 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1272 static int 1273 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1274 { 1275 struct vmxnet3_hw *hw = dev->data->dev_private; 1276 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1277 1278 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1279 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1280 1281 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1282 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1283 1284 return 0; 1285 } 1286 1287 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1288 static int 1289 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1290 { 1291 struct vmxnet3_hw *hw = dev->data->dev_private; 1292 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1293 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1294 1295 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1296 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1297 else 1298 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1299 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1300 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1301 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1302 1303 return 0; 1304 } 1305 1306 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1307 static int 1308 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1309 { 1310 struct vmxnet3_hw *hw = dev->data->dev_private; 1311 1312 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1313 1314 return 0; 1315 } 1316 1317 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1318 static int 1319 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1320 { 1321 struct vmxnet3_hw *hw = dev->data->dev_private; 1322 1323 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1324 1325 return 0; 1326 } 1327 1328 /* Enable/disable filter on vlan */ 1329 static int 1330 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1331 { 1332 struct vmxnet3_hw *hw = dev->data->dev_private; 1333 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1334 uint32_t *vf_table = rxConf->vfTable; 1335 1336 /* save state for restore */ 1337 if (on) 1338 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1339 else 1340 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1341 1342 /* don't change active filter if in promiscuous mode */ 1343 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1344 return 0; 1345 1346 /* set in hardware */ 1347 if (on) 1348 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1349 else 1350 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1351 1352 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1353 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1354 return 0; 1355 } 1356 1357 static int 1358 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1359 { 1360 struct vmxnet3_hw *hw = dev->data->dev_private; 1361 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1362 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1363 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1364 1365 if (mask & ETH_VLAN_STRIP_MASK) { 1366 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1367 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1368 else 1369 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1370 1371 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1372 VMXNET3_CMD_UPDATE_FEATURE); 1373 } 1374 1375 if (mask & ETH_VLAN_FILTER_MASK) { 1376 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1377 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1378 else 1379 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1380 1381 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1382 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1383 } 1384 1385 return 0; 1386 } 1387 1388 static void 1389 vmxnet3_process_events(struct rte_eth_dev *dev) 1390 { 1391 struct vmxnet3_hw *hw = dev->data->dev_private; 1392 uint32_t events = hw->shared->ecr; 1393 1394 if (!events) 1395 return; 1396 1397 /* 1398 * ECR bits when written with 1b are cleared. Hence write 1399 * events back to ECR so that the bits which were set will be reset. 1400 */ 1401 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1402 1403 /* Check if link state has changed */ 1404 if (events & VMXNET3_ECR_LINK) { 1405 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1406 if (vmxnet3_dev_link_update(dev, 0) == 0) 1407 _rte_eth_dev_callback_process(dev, 1408 RTE_ETH_EVENT_INTR_LSC, 1409 NULL); 1410 } 1411 1412 /* Check if there is an error on xmit/recv queues */ 1413 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1414 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1415 VMXNET3_CMD_GET_QUEUE_STATUS); 1416 1417 if (hw->tqd_start->status.stopped) 1418 PMD_DRV_LOG(ERR, "tq error 0x%x", 1419 hw->tqd_start->status.error); 1420 1421 if (hw->rqd_start->status.stopped) 1422 PMD_DRV_LOG(ERR, "rq error 0x%x", 1423 hw->rqd_start->status.error); 1424 1425 /* Reset the device */ 1426 /* Have to reset the device */ 1427 } 1428 1429 if (events & VMXNET3_ECR_DIC) 1430 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1431 1432 if (events & VMXNET3_ECR_DEBUG) 1433 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1434 } 1435 1436 static void 1437 vmxnet3_interrupt_handler(void *param) 1438 { 1439 struct rte_eth_dev *dev = param; 1440 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1441 1442 vmxnet3_process_events(dev); 1443 1444 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1445 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1446 } 1447 1448 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1449 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1450 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1451 1452 RTE_INIT(vmxnet3_init_log) 1453 { 1454 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1455 if (vmxnet3_logtype_init >= 0) 1456 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1457 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1458 if (vmxnet3_logtype_driver >= 0) 1459 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1460 } 1461