1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <fcntl.h> 42 #include <inttypes.h> 43 #include <rte_byteorder.h> 44 #include <rte_common.h> 45 #include <rte_cycles.h> 46 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_eal.h> 56 #include <rte_alarm.h> 57 #include <rte_ether.h> 58 #include <rte_ethdev.h> 59 #include <rte_ethdev_pci.h> 60 #include <rte_atomic.h> 61 #include <rte_string_fns.h> 62 #include <rte_malloc.h> 63 #include <rte_dev.h> 64 65 #include "base/vmxnet3_defs.h" 66 67 #include "vmxnet3_ring.h" 68 #include "vmxnet3_logs.h" 69 #include "vmxnet3_ethdev.h" 70 71 #define PROCESS_SYS_EVENTS 0 72 73 #define VMXNET3_TX_MAX_SEG UINT8_MAX 74 75 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 76 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 77 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 78 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 79 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 80 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 81 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 82 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 83 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 84 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 85 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 86 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 87 int wait_to_complete); 88 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 89 struct rte_eth_stats *stats); 90 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 91 struct rte_eth_dev_info *dev_info); 92 static const uint32_t * 93 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 94 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 95 uint16_t vid, int on); 96 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 97 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 98 struct ether_addr *mac_addr); 99 100 #if PROCESS_SYS_EVENTS == 1 101 static void vmxnet3_process_events(struct vmxnet3_hw *); 102 #endif 103 /* 104 * The set of PCI devices this driver supports 105 */ 106 #define VMWARE_PCI_VENDOR_ID 0x15AD 107 #define VMWARE_DEV_ID_VMXNET3 0x07B0 108 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 109 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 110 { .vendor_id = 0, /* sentinel */ }, 111 }; 112 113 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 114 .dev_configure = vmxnet3_dev_configure, 115 .dev_start = vmxnet3_dev_start, 116 .dev_stop = vmxnet3_dev_stop, 117 .dev_close = vmxnet3_dev_close, 118 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 119 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 120 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 121 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 122 .link_update = vmxnet3_dev_link_update, 123 .stats_get = vmxnet3_dev_stats_get, 124 .mac_addr_set = vmxnet3_mac_addr_set, 125 .dev_infos_get = vmxnet3_dev_info_get, 126 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 127 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 128 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 129 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 130 .rx_queue_release = vmxnet3_dev_rx_queue_release, 131 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 132 .tx_queue_release = vmxnet3_dev_tx_queue_release, 133 }; 134 135 static const struct rte_memzone * 136 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 137 const char *post_string, int socket_id, 138 uint16_t align, bool reuse) 139 { 140 char z_name[RTE_MEMZONE_NAMESIZE]; 141 const struct rte_memzone *mz; 142 143 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 144 dev->data->drv_name, dev->data->port_id, post_string); 145 146 mz = rte_memzone_lookup(z_name); 147 if (!reuse) { 148 if (mz) 149 rte_memzone_free(mz); 150 return rte_memzone_reserve_aligned(z_name, size, socket_id, 151 0, align); 152 } 153 154 if (mz) 155 return mz; 156 157 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align); 158 } 159 160 /** 161 * Atomically reads the link status information from global 162 * structure rte_eth_dev. 163 * 164 * @param dev 165 * - Pointer to the structure rte_eth_dev to read from. 166 * - Pointer to the buffer to be saved with the link status. 167 * 168 * @return 169 * - On success, zero. 170 * - On failure, negative value. 171 */ 172 173 static int 174 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev, 175 struct rte_eth_link *link) 176 { 177 struct rte_eth_link *dst = link; 178 struct rte_eth_link *src = &(dev->data->dev_link); 179 180 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 181 *(uint64_t *)src) == 0) 182 return -1; 183 184 return 0; 185 } 186 187 /** 188 * Atomically writes the link status information into global 189 * structure rte_eth_dev. 190 * 191 * @param dev 192 * - Pointer to the structure rte_eth_dev to write to. 193 * - Pointer to the buffer to be saved with the link status. 194 * 195 * @return 196 * - On success, zero. 197 * - On failure, negative value. 198 */ 199 static int 200 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev, 201 struct rte_eth_link *link) 202 { 203 struct rte_eth_link *dst = &(dev->data->dev_link); 204 struct rte_eth_link *src = link; 205 206 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 207 *(uint64_t *)src) == 0) 208 return -1; 209 210 return 0; 211 } 212 213 /* 214 * This function is based on vmxnet3_disable_intr() 215 */ 216 static void 217 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 218 { 219 int i; 220 221 PMD_INIT_FUNC_TRACE(); 222 223 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 224 for (i = 0; i < VMXNET3_MAX_INTRS; i++) 225 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 226 } 227 228 /* 229 * Gets tx data ring descriptor size. 230 */ 231 static uint16_t 232 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 233 { 234 uint16 txdata_desc_size; 235 236 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 237 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 238 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 239 240 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 241 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 242 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 243 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 244 } 245 246 /* 247 * It returns 0 on success. 248 */ 249 static int 250 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 251 { 252 struct rte_pci_device *pci_dev; 253 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 254 uint32_t mac_hi, mac_lo, ver; 255 256 PMD_INIT_FUNC_TRACE(); 257 258 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 259 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 260 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 261 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 262 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 263 264 /* 265 * for secondary processes, we don't initialize any further as primary 266 * has already done this work. 267 */ 268 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 269 return 0; 270 271 rte_eth_copy_pci_info(eth_dev, pci_dev); 272 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE; 273 274 /* Vendor and Device ID need to be set before init of shared code */ 275 hw->device_id = pci_dev->id.device_id; 276 hw->vendor_id = pci_dev->id.vendor_id; 277 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 278 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 279 280 hw->num_rx_queues = 1; 281 hw->num_tx_queues = 1; 282 hw->bufs_per_pkt = 1; 283 284 /* Check h/w version compatibility with driver. */ 285 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 286 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 287 288 if (ver & (1 << VMXNET3_REV_3)) { 289 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 290 1 << VMXNET3_REV_3); 291 hw->version = VMXNET3_REV_3 + 1; 292 } else if (ver & (1 << VMXNET3_REV_2)) { 293 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 294 1 << VMXNET3_REV_2); 295 hw->version = VMXNET3_REV_2 + 1; 296 } else if (ver & (1 << VMXNET3_REV_1)) { 297 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 298 1 << VMXNET3_REV_1); 299 hw->version = VMXNET3_REV_1 + 1; 300 } else { 301 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 302 return -EIO; 303 } 304 305 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 306 307 /* Check UPT version compatibility with driver. */ 308 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 309 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 310 if (ver & 0x1) 311 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 312 else { 313 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 314 return -EIO; 315 } 316 317 /* Getting MAC Address */ 318 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 319 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 320 memcpy(hw->perm_addr, &mac_lo, 4); 321 memcpy(hw->perm_addr + 4, &mac_hi, 2); 322 323 /* Allocate memory for storing MAC addresses */ 324 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 325 VMXNET3_MAX_MAC_ADDRS, 0); 326 if (eth_dev->data->mac_addrs == NULL) { 327 PMD_INIT_LOG(ERR, 328 "Failed to allocate %d bytes needed to store MAC addresses", 329 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 330 return -ENOMEM; 331 } 332 /* Copy the permanent MAC address */ 333 ether_addr_copy((struct ether_addr *) hw->perm_addr, 334 ð_dev->data->mac_addrs[0]); 335 336 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 337 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 338 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 339 340 /* Put device in Quiesce Mode */ 341 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 342 343 /* allow untagged pkts */ 344 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 345 346 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 347 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 348 349 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 350 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 351 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 352 hw->rxdata_desc_size); 353 354 return 0; 355 } 356 357 static int 358 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 359 { 360 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 361 362 PMD_INIT_FUNC_TRACE(); 363 364 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 365 return 0; 366 367 if (hw->adapter_stopped == 0) 368 vmxnet3_dev_close(eth_dev); 369 370 eth_dev->dev_ops = NULL; 371 eth_dev->rx_pkt_burst = NULL; 372 eth_dev->tx_pkt_burst = NULL; 373 eth_dev->tx_pkt_prepare = NULL; 374 375 rte_free(eth_dev->data->mac_addrs); 376 eth_dev->data->mac_addrs = NULL; 377 378 return 0; 379 } 380 381 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 382 struct rte_pci_device *pci_dev) 383 { 384 return rte_eth_dev_pci_generic_probe(pci_dev, 385 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 386 } 387 388 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 389 { 390 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 391 } 392 393 static struct rte_pci_driver rte_vmxnet3_pmd = { 394 .id_table = pci_id_vmxnet3_map, 395 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 396 .probe = eth_vmxnet3_pci_probe, 397 .remove = eth_vmxnet3_pci_remove, 398 }; 399 400 static int 401 vmxnet3_dev_configure(struct rte_eth_dev *dev) 402 { 403 const struct rte_memzone *mz; 404 struct vmxnet3_hw *hw = dev->data->dev_private; 405 size_t size; 406 407 PMD_INIT_FUNC_TRACE(); 408 409 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 410 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 411 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 412 return -EINVAL; 413 } 414 415 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 416 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 417 return -EINVAL; 418 } 419 420 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 421 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 422 423 if (size > UINT16_MAX) 424 return -EINVAL; 425 426 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 427 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 428 429 /* 430 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 431 * on current socket 432 */ 433 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 434 "shared", rte_socket_id(), 8, 1); 435 436 if (mz == NULL) { 437 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 438 return -ENOMEM; 439 } 440 memset(mz->addr, 0, mz->len); 441 442 hw->shared = mz->addr; 443 hw->sharedPA = mz->phys_addr; 444 445 /* 446 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 447 * on current socket. 448 * 449 * We cannot reuse this memzone from previous allocation as its size 450 * depends on the number of tx and rx queues, which could be different 451 * from one config to another. 452 */ 453 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 454 VMXNET3_QUEUE_DESC_ALIGN, 0); 455 if (mz == NULL) { 456 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 457 return -ENOMEM; 458 } 459 memset(mz->addr, 0, mz->len); 460 461 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 462 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 463 464 hw->queueDescPA = mz->phys_addr; 465 hw->queue_desc_len = (uint16_t)size; 466 467 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 468 /* Allocate memory structure for UPT1_RSSConf and configure */ 469 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 470 "rss_conf", rte_socket_id(), 471 RTE_CACHE_LINE_SIZE, 1); 472 if (mz == NULL) { 473 PMD_INIT_LOG(ERR, 474 "ERROR: Creating rss_conf structure zone"); 475 return -ENOMEM; 476 } 477 memset(mz->addr, 0, mz->len); 478 479 hw->rss_conf = mz->addr; 480 hw->rss_confPA = mz->phys_addr; 481 } 482 483 return 0; 484 } 485 486 static void 487 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 488 { 489 uint32_t val; 490 491 PMD_INIT_LOG(DEBUG, 492 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 493 addr[0], addr[1], addr[2], 494 addr[3], addr[4], addr[5]); 495 496 val = *(const uint32_t *)addr; 497 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 498 499 val = (addr[5] << 8) | addr[4]; 500 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 501 } 502 503 static int 504 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 505 { 506 struct vmxnet3_hw *hw = dev->data->dev_private; 507 Vmxnet3_DriverShared *shared = hw->shared; 508 Vmxnet3_CmdInfo *cmdInfo; 509 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 510 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 511 uint32_t num, i, j, size; 512 513 if (hw->memRegsPA == 0) { 514 const struct rte_memzone *mz; 515 516 size = sizeof(Vmxnet3_MemRegs) + 517 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 518 sizeof(Vmxnet3_MemoryRegion); 519 520 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 521 1); 522 if (mz == NULL) { 523 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 524 return -ENOMEM; 525 } 526 memset(mz->addr, 0, mz->len); 527 hw->memRegs = mz->addr; 528 hw->memRegsPA = mz->phys_addr; 529 } 530 531 num = hw->num_rx_queues; 532 533 for (i = 0; i < num; i++) { 534 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 535 536 mp[i] = rxq->mp; 537 index[i] = 1 << i; 538 } 539 540 /* 541 * The same mempool could be used by multiple queues. In such a case, 542 * remove duplicate mempool entries. Only one entry is kept with 543 * bitmask indicating queues that are using this mempool. 544 */ 545 for (i = 1; i < num; i++) { 546 for (j = 0; j < i; j++) { 547 if (mp[i] == mp[j]) { 548 mp[i] = NULL; 549 index[j] |= 1 << i; 550 break; 551 } 552 } 553 } 554 555 j = 0; 556 for (i = 0; i < num; i++) { 557 if (mp[i] == NULL) 558 continue; 559 560 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 561 562 mr->startPA = 563 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->phys_addr; 564 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 565 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 566 mr->txQueueBits = index[i]; 567 mr->rxQueueBits = index[i]; 568 569 PMD_INIT_LOG(INFO, 570 "index: %u startPA: %" PRIu64 " length: %u, " 571 "rxBits: %x", 572 j, mr->startPA, mr->length, mr->rxQueueBits); 573 j++; 574 } 575 hw->memRegs->numRegs = j; 576 PMD_INIT_LOG(INFO, "numRegs: %u", j); 577 578 size = sizeof(Vmxnet3_MemRegs) + 579 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 580 581 cmdInfo = &shared->cu.cmdInfo; 582 cmdInfo->varConf.confVer = 1; 583 cmdInfo->varConf.confLen = size; 584 cmdInfo->varConf.confPA = hw->memRegsPA; 585 586 return 0; 587 } 588 589 static int 590 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 591 { 592 struct rte_eth_conf port_conf = dev->data->dev_conf; 593 struct vmxnet3_hw *hw = dev->data->dev_private; 594 uint32_t mtu = dev->data->mtu; 595 Vmxnet3_DriverShared *shared = hw->shared; 596 Vmxnet3_DSDevRead *devRead = &shared->devRead; 597 uint32_t i; 598 int ret; 599 600 shared->magic = VMXNET3_REV1_MAGIC; 601 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 602 603 /* Setting up Guest OS information */ 604 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 605 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 606 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 607 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 608 devRead->misc.driverInfo.uptVerSpt = 1; 609 610 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 611 devRead->misc.queueDescPA = hw->queueDescPA; 612 devRead->misc.queueDescLen = hw->queue_desc_len; 613 devRead->misc.numTxQueues = hw->num_tx_queues; 614 devRead->misc.numRxQueues = hw->num_rx_queues; 615 616 /* 617 * Set number of interrupts to 1 618 * PMD disables all the interrupts but this is MUST to activate device 619 * It needs at least one interrupt for link events to handle 620 * So we'll disable it later after device activation if needed 621 */ 622 devRead->intrConf.numIntrs = 1; 623 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 624 625 for (i = 0; i < hw->num_tx_queues; i++) { 626 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 627 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 628 629 tqd->ctrl.txNumDeferred = 0; 630 tqd->ctrl.txThreshold = 1; 631 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 632 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 633 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 634 635 tqd->conf.txRingSize = txq->cmd_ring.size; 636 tqd->conf.compRingSize = txq->comp_ring.size; 637 tqd->conf.dataRingSize = txq->data_ring.size; 638 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 639 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 640 tqd->status.stopped = TRUE; 641 tqd->status.error = 0; 642 memset(&tqd->stats, 0, sizeof(tqd->stats)); 643 } 644 645 for (i = 0; i < hw->num_rx_queues; i++) { 646 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 647 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 648 649 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 650 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 651 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 652 653 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 654 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 655 rqd->conf.compRingSize = rxq->comp_ring.size; 656 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 657 if (VMXNET3_VERSION_GE_3(hw)) { 658 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 659 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 660 } 661 rqd->status.stopped = TRUE; 662 rqd->status.error = 0; 663 memset(&rqd->stats, 0, sizeof(rqd->stats)); 664 } 665 666 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 667 devRead->rxFilterConf.rxMode = 0; 668 669 /* Setting up feature flags */ 670 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 671 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 672 673 if (dev->data->dev_conf.rxmode.enable_lro) { 674 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 675 devRead->misc.maxNumRxSG = 0; 676 } 677 678 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 679 ret = vmxnet3_rss_configure(dev); 680 if (ret != VMXNET3_SUCCESS) 681 return ret; 682 683 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 684 devRead->rssConfDesc.confVer = 1; 685 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 686 devRead->rssConfDesc.confPA = hw->rss_confPA; 687 } 688 689 vmxnet3_dev_vlan_offload_set(dev, 690 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 691 692 vmxnet3_write_mac(hw, hw->perm_addr); 693 694 return VMXNET3_SUCCESS; 695 } 696 697 /* 698 * Configure device link speed and setup link. 699 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 700 * It returns 0 on success. 701 */ 702 static int 703 vmxnet3_dev_start(struct rte_eth_dev *dev) 704 { 705 int ret; 706 struct vmxnet3_hw *hw = dev->data->dev_private; 707 708 PMD_INIT_FUNC_TRACE(); 709 710 ret = vmxnet3_setup_driver_shared(dev); 711 if (ret != VMXNET3_SUCCESS) 712 return ret; 713 714 /* Exchange shared data with device */ 715 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 716 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 717 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 718 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 719 720 /* Activate device by register write */ 721 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 722 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 723 724 if (ret != 0) { 725 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 726 return -EINVAL; 727 } 728 729 /* Setup memory region for rx buffers */ 730 ret = vmxnet3_dev_setup_memreg(dev); 731 if (ret == 0) { 732 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 733 VMXNET3_CMD_REGISTER_MEMREGS); 734 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 735 if (ret != 0) 736 PMD_INIT_LOG(DEBUG, 737 "Failed in setup memory region cmd\n"); 738 ret = 0; 739 } else { 740 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 741 } 742 743 /* Disable interrupts */ 744 vmxnet3_disable_intr(hw); 745 746 /* 747 * Load RX queues with blank mbufs and update next2fill index for device 748 * Update RxMode of the device 749 */ 750 ret = vmxnet3_dev_rxtx_init(dev); 751 if (ret != VMXNET3_SUCCESS) { 752 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 753 return ret; 754 } 755 756 hw->adapter_stopped = FALSE; 757 758 /* Setting proper Rx Mode and issue Rx Mode Update command */ 759 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 760 761 /* 762 * Don't need to handle events for now 763 */ 764 #if PROCESS_SYS_EVENTS == 1 765 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR); 766 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events); 767 vmxnet3_process_events(hw); 768 #endif 769 return VMXNET3_SUCCESS; 770 } 771 772 /* 773 * Stop device: disable rx and tx functions to allow for reconfiguring. 774 */ 775 static void 776 vmxnet3_dev_stop(struct rte_eth_dev *dev) 777 { 778 struct rte_eth_link link; 779 struct vmxnet3_hw *hw = dev->data->dev_private; 780 781 PMD_INIT_FUNC_TRACE(); 782 783 if (hw->adapter_stopped == 1) { 784 PMD_INIT_LOG(DEBUG, "Device already closed."); 785 return; 786 } 787 788 /* disable interrupts */ 789 vmxnet3_disable_intr(hw); 790 791 /* quiesce the device first */ 792 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 793 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 794 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 795 796 /* reset the device */ 797 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 798 PMD_INIT_LOG(DEBUG, "Device reset."); 799 hw->adapter_stopped = 0; 800 801 vmxnet3_dev_clear_queues(dev); 802 803 /* Clear recorded link status */ 804 memset(&link, 0, sizeof(link)); 805 vmxnet3_dev_atomic_write_link_status(dev, &link); 806 } 807 808 /* 809 * Reset and stop device. 810 */ 811 static void 812 vmxnet3_dev_close(struct rte_eth_dev *dev) 813 { 814 struct vmxnet3_hw *hw = dev->data->dev_private; 815 816 PMD_INIT_FUNC_TRACE(); 817 818 vmxnet3_dev_stop(dev); 819 hw->adapter_stopped = 1; 820 } 821 822 static void 823 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 824 { 825 unsigned int i; 826 struct vmxnet3_hw *hw = dev->data->dev_private; 827 828 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 829 830 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 831 for (i = 0; i < hw->num_tx_queues; i++) { 832 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats; 833 834 stats->q_opackets[i] = txStats->ucastPktsTxOK + 835 txStats->mcastPktsTxOK + 836 txStats->bcastPktsTxOK; 837 stats->q_obytes[i] = txStats->ucastBytesTxOK + 838 txStats->mcastBytesTxOK + 839 txStats->bcastBytesTxOK; 840 841 stats->opackets += stats->q_opackets[i]; 842 stats->obytes += stats->q_obytes[i]; 843 stats->oerrors += txStats->pktsTxError + txStats->pktsTxDiscard; 844 } 845 846 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 847 for (i = 0; i < hw->num_rx_queues; i++) { 848 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats; 849 850 stats->q_ipackets[i] = rxStats->ucastPktsRxOK + 851 rxStats->mcastPktsRxOK + 852 rxStats->bcastPktsRxOK; 853 854 stats->q_ibytes[i] = rxStats->ucastBytesRxOK + 855 rxStats->mcastBytesRxOK + 856 rxStats->bcastBytesRxOK; 857 858 stats->ipackets += stats->q_ipackets[i]; 859 stats->ibytes += stats->q_ibytes[i]; 860 861 stats->q_errors[i] = rxStats->pktsRxError; 862 stats->ierrors += rxStats->pktsRxError; 863 stats->rx_nombuf += rxStats->pktsRxOutOfBuf; 864 } 865 } 866 867 static void 868 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 869 struct rte_eth_dev_info *dev_info) 870 { 871 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device); 872 873 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 874 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 875 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 876 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 877 dev_info->speed_capa = ETH_LINK_SPEED_10G; 878 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 879 880 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 881 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 882 883 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 884 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 885 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 886 .nb_align = 1, 887 }; 888 889 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 890 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 891 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 892 .nb_align = 1, 893 .nb_seg_max = VMXNET3_TX_MAX_SEG, 894 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 895 }; 896 897 dev_info->rx_offload_capa = 898 DEV_RX_OFFLOAD_VLAN_STRIP | 899 DEV_RX_OFFLOAD_UDP_CKSUM | 900 DEV_RX_OFFLOAD_TCP_CKSUM | 901 DEV_RX_OFFLOAD_TCP_LRO; 902 903 dev_info->tx_offload_capa = 904 DEV_TX_OFFLOAD_VLAN_INSERT | 905 DEV_TX_OFFLOAD_TCP_CKSUM | 906 DEV_TX_OFFLOAD_UDP_CKSUM | 907 DEV_TX_OFFLOAD_TCP_TSO; 908 } 909 910 static const uint32_t * 911 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 912 { 913 static const uint32_t ptypes[] = { 914 RTE_PTYPE_L3_IPV4_EXT, 915 RTE_PTYPE_L3_IPV4, 916 RTE_PTYPE_UNKNOWN 917 }; 918 919 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 920 return ptypes; 921 return NULL; 922 } 923 924 static void 925 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 926 { 927 struct vmxnet3_hw *hw = dev->data->dev_private; 928 929 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 930 } 931 932 /* return 0 means link status changed, -1 means not changed */ 933 static int 934 vmxnet3_dev_link_update(struct rte_eth_dev *dev, 935 __rte_unused int wait_to_complete) 936 { 937 struct vmxnet3_hw *hw = dev->data->dev_private; 938 struct rte_eth_link old, link; 939 uint32_t ret; 940 941 /* Link status doesn't change for stopped dev */ 942 if (dev->data->dev_started == 0) 943 return -1; 944 945 memset(&link, 0, sizeof(link)); 946 vmxnet3_dev_atomic_read_link_status(dev, &old); 947 948 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 949 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 950 951 if (ret & 0x1) { 952 link.link_status = ETH_LINK_UP; 953 link.link_duplex = ETH_LINK_FULL_DUPLEX; 954 link.link_speed = ETH_SPEED_NUM_10G; 955 link.link_autoneg = ETH_LINK_SPEED_FIXED; 956 } 957 958 vmxnet3_dev_atomic_write_link_status(dev, &link); 959 960 return (old.link_status == link.link_status) ? -1 : 0; 961 } 962 963 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 964 static void 965 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 966 { 967 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 968 969 if (set) 970 rxConf->rxMode = rxConf->rxMode | feature; 971 else 972 rxConf->rxMode = rxConf->rxMode & (~feature); 973 974 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 975 } 976 977 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 978 static void 979 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 980 { 981 struct vmxnet3_hw *hw = dev->data->dev_private; 982 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 983 984 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 985 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 986 987 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 988 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 989 } 990 991 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 992 static void 993 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 994 { 995 struct vmxnet3_hw *hw = dev->data->dev_private; 996 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 997 998 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 999 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1000 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1001 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1002 } 1003 1004 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1005 static void 1006 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1007 { 1008 struct vmxnet3_hw *hw = dev->data->dev_private; 1009 1010 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1011 } 1012 1013 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1014 static void 1015 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1016 { 1017 struct vmxnet3_hw *hw = dev->data->dev_private; 1018 1019 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1020 } 1021 1022 /* Enable/disable filter on vlan */ 1023 static int 1024 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1025 { 1026 struct vmxnet3_hw *hw = dev->data->dev_private; 1027 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1028 uint32_t *vf_table = rxConf->vfTable; 1029 1030 /* save state for restore */ 1031 if (on) 1032 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1033 else 1034 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1035 1036 /* don't change active filter if in promiscuous mode */ 1037 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1038 return 0; 1039 1040 /* set in hardware */ 1041 if (on) 1042 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1043 else 1044 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1045 1046 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1047 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1048 return 0; 1049 } 1050 1051 static void 1052 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1053 { 1054 struct vmxnet3_hw *hw = dev->data->dev_private; 1055 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1056 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1057 1058 if (mask & ETH_VLAN_STRIP_MASK) { 1059 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1060 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1061 else 1062 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1063 1064 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1065 VMXNET3_CMD_UPDATE_FEATURE); 1066 } 1067 1068 if (mask & ETH_VLAN_FILTER_MASK) { 1069 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1070 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1071 else 1072 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1073 1074 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1075 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1076 } 1077 } 1078 1079 #if PROCESS_SYS_EVENTS == 1 1080 static void 1081 vmxnet3_process_events(struct vmxnet3_hw *hw) 1082 { 1083 uint32_t events = hw->shared->ecr; 1084 1085 if (!events) { 1086 PMD_INIT_LOG(ERR, "No events to process"); 1087 return; 1088 } 1089 1090 /* 1091 * ECR bits when written with 1b are cleared. Hence write 1092 * events back to ECR so that the bits which were set will be reset. 1093 */ 1094 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1095 1096 /* Check if link state has changed */ 1097 if (events & VMXNET3_ECR_LINK) 1098 PMD_INIT_LOG(ERR, 1099 "Process events in %s(): VMXNET3_ECR_LINK event", 1100 __func__); 1101 1102 /* Check if there is an error on xmit/recv queues */ 1103 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1104 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1105 VMXNET3_CMD_GET_QUEUE_STATUS); 1106 1107 if (hw->tqd_start->status.stopped) 1108 PMD_INIT_LOG(ERR, "tq error 0x%x", 1109 hw->tqd_start->status.error); 1110 1111 if (hw->rqd_start->status.stopped) 1112 PMD_INIT_LOG(ERR, "rq error 0x%x", 1113 hw->rqd_start->status.error); 1114 1115 /* Reset the device */ 1116 /* Have to reset the device */ 1117 } 1118 1119 if (events & VMXNET3_ECR_DIC) 1120 PMD_INIT_LOG(ERR, "Device implementation change event."); 1121 1122 if (events & VMXNET3_ECR_DEBUG) 1123 PMD_INIT_LOG(ERR, "Debug event generated by device."); 1124 } 1125 #endif 1126 1127 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1128 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1129 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio"); 1130