1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_atomic.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_memzone.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <rte_ethdev.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_string_fns.h> 33 #include <rte_malloc.h> 34 #include <rte_dev.h> 35 36 #include "base/vmxnet3_defs.h" 37 38 #include "vmxnet3_ring.h" 39 #include "vmxnet3_logs.h" 40 #include "vmxnet3_ethdev.h" 41 42 #define PROCESS_SYS_EVENTS 0 43 44 #define VMXNET3_TX_MAX_SEG UINT8_MAX 45 46 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 47 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 48 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 49 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 50 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 51 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 52 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 53 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 54 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 55 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 56 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 57 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 58 int wait_to_complete); 59 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 60 int wait_to_complete); 61 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 62 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 63 struct rte_eth_stats *stats); 64 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 65 struct rte_eth_xstat_name *xstats, 66 unsigned int n); 67 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 68 struct rte_eth_xstat *xstats, unsigned int n); 69 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 70 struct rte_eth_dev_info *dev_info); 71 static const uint32_t * 72 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 73 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 74 uint16_t vid, int on); 75 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 76 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 77 struct ether_addr *mac_addr); 78 static void vmxnet3_interrupt_handler(void *param); 79 80 /* 81 * The set of PCI devices this driver supports 82 */ 83 #define VMWARE_PCI_VENDOR_ID 0x15AD 84 #define VMWARE_DEV_ID_VMXNET3 0x07B0 85 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 86 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 91 .dev_configure = vmxnet3_dev_configure, 92 .dev_start = vmxnet3_dev_start, 93 .dev_stop = vmxnet3_dev_stop, 94 .dev_close = vmxnet3_dev_close, 95 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 96 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 97 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 98 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 99 .link_update = vmxnet3_dev_link_update, 100 .stats_get = vmxnet3_dev_stats_get, 101 .xstats_get_names = vmxnet3_dev_xstats_get_names, 102 .xstats_get = vmxnet3_dev_xstats_get, 103 .mac_addr_set = vmxnet3_mac_addr_set, 104 .dev_infos_get = vmxnet3_dev_info_get, 105 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 106 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 107 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 108 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 109 .rx_queue_release = vmxnet3_dev_rx_queue_release, 110 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 111 .tx_queue_release = vmxnet3_dev_tx_queue_release, 112 }; 113 114 struct vmxnet3_xstats_name_off { 115 char name[RTE_ETH_XSTATS_NAME_SIZE]; 116 unsigned int offset; 117 }; 118 119 /* tx_qX_ is prepended to the name string here */ 120 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 121 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 122 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 123 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 124 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 125 }; 126 127 /* rx_qX_ is prepended to the name string here */ 128 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 129 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 130 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 131 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 132 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 133 }; 134 135 static const struct rte_memzone * 136 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 137 const char *post_string, int socket_id, 138 uint16_t align, bool reuse) 139 { 140 char z_name[RTE_MEMZONE_NAMESIZE]; 141 const struct rte_memzone *mz; 142 143 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 144 dev->device->driver->name, dev->data->port_id, post_string); 145 146 mz = rte_memzone_lookup(z_name); 147 if (!reuse) { 148 if (mz) 149 rte_memzone_free(mz); 150 return rte_memzone_reserve_aligned(z_name, size, socket_id, 151 0, align); 152 } 153 154 if (mz) 155 return mz; 156 157 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align); 158 } 159 160 /** 161 * Atomically reads the link status information from global 162 * structure rte_eth_dev. 163 * 164 * @param dev 165 * - Pointer to the structure rte_eth_dev to read from. 166 * - Pointer to the buffer to be saved with the link status. 167 * 168 * @return 169 * - On success, zero. 170 * - On failure, negative value. 171 */ 172 173 static int 174 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev, 175 struct rte_eth_link *link) 176 { 177 struct rte_eth_link *dst = link; 178 struct rte_eth_link *src = &(dev->data->dev_link); 179 180 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 181 *(uint64_t *)src) == 0) 182 return -1; 183 184 return 0; 185 } 186 187 /** 188 * Atomically writes the link status information into global 189 * structure rte_eth_dev. 190 * 191 * @param dev 192 * - Pointer to the structure rte_eth_dev to write to. 193 * - Pointer to the buffer to be saved with the link status. 194 * 195 * @return 196 * - On success, zero. 197 * - On failure, negative value. 198 */ 199 static int 200 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev, 201 struct rte_eth_link *link) 202 { 203 struct rte_eth_link *dst = &(dev->data->dev_link); 204 struct rte_eth_link *src = link; 205 206 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 207 *(uint64_t *)src) == 0) 208 return -1; 209 210 return 0; 211 } 212 213 /* 214 * This function is based on vmxnet3_disable_intr() 215 */ 216 static void 217 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 218 { 219 int i; 220 221 PMD_INIT_FUNC_TRACE(); 222 223 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 224 for (i = 0; i < hw->num_intrs; i++) 225 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 226 } 227 228 static void 229 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 230 { 231 int i; 232 233 PMD_INIT_FUNC_TRACE(); 234 235 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 236 for (i = 0; i < hw->num_intrs; i++) 237 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 238 } 239 240 /* 241 * Gets tx data ring descriptor size. 242 */ 243 static uint16_t 244 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 245 { 246 uint16 txdata_desc_size; 247 248 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 249 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 250 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 251 252 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 253 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 254 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 255 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 256 } 257 258 /* 259 * It returns 0 on success. 260 */ 261 static int 262 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 263 { 264 struct rte_pci_device *pci_dev; 265 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 266 uint32_t mac_hi, mac_lo, ver; 267 268 PMD_INIT_FUNC_TRACE(); 269 270 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 271 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 272 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 273 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 274 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 275 276 /* 277 * for secondary processes, we don't initialize any further as primary 278 * has already done this work. 279 */ 280 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 281 return 0; 282 283 rte_eth_copy_pci_info(eth_dev, pci_dev); 284 285 /* Vendor and Device ID need to be set before init of shared code */ 286 hw->device_id = pci_dev->id.device_id; 287 hw->vendor_id = pci_dev->id.vendor_id; 288 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 289 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 290 291 hw->num_rx_queues = 1; 292 hw->num_tx_queues = 1; 293 hw->bufs_per_pkt = 1; 294 295 /* Check h/w version compatibility with driver. */ 296 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 297 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 298 299 if (ver & (1 << VMXNET3_REV_3)) { 300 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 301 1 << VMXNET3_REV_3); 302 hw->version = VMXNET3_REV_3 + 1; 303 } else if (ver & (1 << VMXNET3_REV_2)) { 304 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 305 1 << VMXNET3_REV_2); 306 hw->version = VMXNET3_REV_2 + 1; 307 } else if (ver & (1 << VMXNET3_REV_1)) { 308 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 309 1 << VMXNET3_REV_1); 310 hw->version = VMXNET3_REV_1 + 1; 311 } else { 312 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 313 return -EIO; 314 } 315 316 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 317 318 /* Check UPT version compatibility with driver. */ 319 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 320 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 321 if (ver & 0x1) 322 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 323 else { 324 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 325 return -EIO; 326 } 327 328 /* Getting MAC Address */ 329 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 330 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 331 memcpy(hw->perm_addr, &mac_lo, 4); 332 memcpy(hw->perm_addr + 4, &mac_hi, 2); 333 334 /* Allocate memory for storing MAC addresses */ 335 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 336 VMXNET3_MAX_MAC_ADDRS, 0); 337 if (eth_dev->data->mac_addrs == NULL) { 338 PMD_INIT_LOG(ERR, 339 "Failed to allocate %d bytes needed to store MAC addresses", 340 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 341 return -ENOMEM; 342 } 343 /* Copy the permanent MAC address */ 344 ether_addr_copy((struct ether_addr *) hw->perm_addr, 345 ð_dev->data->mac_addrs[0]); 346 347 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 348 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 349 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 350 351 /* Put device in Quiesce Mode */ 352 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 353 354 /* allow untagged pkts */ 355 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 356 357 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 358 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 359 360 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 361 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 362 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 363 hw->rxdata_desc_size); 364 365 /* clear shadow stats */ 366 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 367 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 368 369 return 0; 370 } 371 372 static int 373 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 374 { 375 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 376 377 PMD_INIT_FUNC_TRACE(); 378 379 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 380 return 0; 381 382 if (hw->adapter_stopped == 0) 383 vmxnet3_dev_close(eth_dev); 384 385 eth_dev->dev_ops = NULL; 386 eth_dev->rx_pkt_burst = NULL; 387 eth_dev->tx_pkt_burst = NULL; 388 eth_dev->tx_pkt_prepare = NULL; 389 390 rte_free(eth_dev->data->mac_addrs); 391 eth_dev->data->mac_addrs = NULL; 392 393 return 0; 394 } 395 396 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 397 struct rte_pci_device *pci_dev) 398 { 399 return rte_eth_dev_pci_generic_probe(pci_dev, 400 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 401 } 402 403 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 404 { 405 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 406 } 407 408 static struct rte_pci_driver rte_vmxnet3_pmd = { 409 .id_table = pci_id_vmxnet3_map, 410 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 411 .probe = eth_vmxnet3_pci_probe, 412 .remove = eth_vmxnet3_pci_remove, 413 }; 414 415 static int 416 vmxnet3_dev_configure(struct rte_eth_dev *dev) 417 { 418 const struct rte_memzone *mz; 419 struct vmxnet3_hw *hw = dev->data->dev_private; 420 size_t size; 421 422 PMD_INIT_FUNC_TRACE(); 423 424 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 425 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 426 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 427 return -EINVAL; 428 } 429 430 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 431 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 432 return -EINVAL; 433 } 434 435 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 436 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 437 438 if (size > UINT16_MAX) 439 return -EINVAL; 440 441 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 442 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 443 444 /* 445 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 446 * on current socket 447 */ 448 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 449 "shared", rte_socket_id(), 8, 1); 450 451 if (mz == NULL) { 452 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 453 return -ENOMEM; 454 } 455 memset(mz->addr, 0, mz->len); 456 457 hw->shared = mz->addr; 458 hw->sharedPA = mz->iova; 459 460 /* 461 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 462 * on current socket. 463 * 464 * We cannot reuse this memzone from previous allocation as its size 465 * depends on the number of tx and rx queues, which could be different 466 * from one config to another. 467 */ 468 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 469 VMXNET3_QUEUE_DESC_ALIGN, 0); 470 if (mz == NULL) { 471 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 472 return -ENOMEM; 473 } 474 memset(mz->addr, 0, mz->len); 475 476 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 477 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 478 479 hw->queueDescPA = mz->iova; 480 hw->queue_desc_len = (uint16_t)size; 481 482 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 483 /* Allocate memory structure for UPT1_RSSConf and configure */ 484 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 485 "rss_conf", rte_socket_id(), 486 RTE_CACHE_LINE_SIZE, 1); 487 if (mz == NULL) { 488 PMD_INIT_LOG(ERR, 489 "ERROR: Creating rss_conf structure zone"); 490 return -ENOMEM; 491 } 492 memset(mz->addr, 0, mz->len); 493 494 hw->rss_conf = mz->addr; 495 hw->rss_confPA = mz->iova; 496 } 497 498 return 0; 499 } 500 501 static void 502 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 503 { 504 uint32_t val; 505 506 PMD_INIT_LOG(DEBUG, 507 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 508 addr[0], addr[1], addr[2], 509 addr[3], addr[4], addr[5]); 510 511 memcpy(&val, addr, 4); 512 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 513 514 memcpy(&val, addr + 4, 2); 515 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 516 } 517 518 static int 519 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 520 { 521 struct vmxnet3_hw *hw = dev->data->dev_private; 522 Vmxnet3_DriverShared *shared = hw->shared; 523 Vmxnet3_CmdInfo *cmdInfo; 524 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 525 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 526 uint32_t num, i, j, size; 527 528 if (hw->memRegsPA == 0) { 529 const struct rte_memzone *mz; 530 531 size = sizeof(Vmxnet3_MemRegs) + 532 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 533 sizeof(Vmxnet3_MemoryRegion); 534 535 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 536 1); 537 if (mz == NULL) { 538 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 539 return -ENOMEM; 540 } 541 memset(mz->addr, 0, mz->len); 542 hw->memRegs = mz->addr; 543 hw->memRegsPA = mz->iova; 544 } 545 546 num = hw->num_rx_queues; 547 548 for (i = 0; i < num; i++) { 549 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 550 551 mp[i] = rxq->mp; 552 index[i] = 1 << i; 553 } 554 555 /* 556 * The same mempool could be used by multiple queues. In such a case, 557 * remove duplicate mempool entries. Only one entry is kept with 558 * bitmask indicating queues that are using this mempool. 559 */ 560 for (i = 1; i < num; i++) { 561 for (j = 0; j < i; j++) { 562 if (mp[i] == mp[j]) { 563 mp[i] = NULL; 564 index[j] |= 1 << i; 565 break; 566 } 567 } 568 } 569 570 j = 0; 571 for (i = 0; i < num; i++) { 572 if (mp[i] == NULL) 573 continue; 574 575 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 576 577 mr->startPA = 578 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 579 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 580 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 581 mr->txQueueBits = index[i]; 582 mr->rxQueueBits = index[i]; 583 584 PMD_INIT_LOG(INFO, 585 "index: %u startPA: %" PRIu64 " length: %u, " 586 "rxBits: %x", 587 j, mr->startPA, mr->length, mr->rxQueueBits); 588 j++; 589 } 590 hw->memRegs->numRegs = j; 591 PMD_INIT_LOG(INFO, "numRegs: %u", j); 592 593 size = sizeof(Vmxnet3_MemRegs) + 594 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 595 596 cmdInfo = &shared->cu.cmdInfo; 597 cmdInfo->varConf.confVer = 1; 598 cmdInfo->varConf.confLen = size; 599 cmdInfo->varConf.confPA = hw->memRegsPA; 600 601 return 0; 602 } 603 604 static int 605 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 606 { 607 struct rte_eth_conf port_conf = dev->data->dev_conf; 608 struct vmxnet3_hw *hw = dev->data->dev_private; 609 uint32_t mtu = dev->data->mtu; 610 Vmxnet3_DriverShared *shared = hw->shared; 611 Vmxnet3_DSDevRead *devRead = &shared->devRead; 612 uint32_t i; 613 int ret; 614 615 shared->magic = VMXNET3_REV1_MAGIC; 616 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 617 618 /* Setting up Guest OS information */ 619 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 620 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 621 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 622 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 623 devRead->misc.driverInfo.uptVerSpt = 1; 624 625 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 626 devRead->misc.queueDescPA = hw->queueDescPA; 627 devRead->misc.queueDescLen = hw->queue_desc_len; 628 devRead->misc.numTxQueues = hw->num_tx_queues; 629 devRead->misc.numRxQueues = hw->num_rx_queues; 630 631 /* 632 * Set number of interrupts to 1 633 * PMD by default disables all the interrupts but this is MUST 634 * to activate device. It needs at least one interrupt for 635 * link events to handle 636 */ 637 hw->num_intrs = devRead->intrConf.numIntrs = 1; 638 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 639 640 for (i = 0; i < hw->num_tx_queues; i++) { 641 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 642 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 643 644 tqd->ctrl.txNumDeferred = 0; 645 tqd->ctrl.txThreshold = 1; 646 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 647 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 648 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 649 650 tqd->conf.txRingSize = txq->cmd_ring.size; 651 tqd->conf.compRingSize = txq->comp_ring.size; 652 tqd->conf.dataRingSize = txq->data_ring.size; 653 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 654 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 655 tqd->status.stopped = TRUE; 656 tqd->status.error = 0; 657 memset(&tqd->stats, 0, sizeof(tqd->stats)); 658 } 659 660 for (i = 0; i < hw->num_rx_queues; i++) { 661 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 662 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 663 664 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 665 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 666 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 667 668 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 669 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 670 rqd->conf.compRingSize = rxq->comp_ring.size; 671 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 672 if (VMXNET3_VERSION_GE_3(hw)) { 673 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 674 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 675 } 676 rqd->status.stopped = TRUE; 677 rqd->status.error = 0; 678 memset(&rqd->stats, 0, sizeof(rqd->stats)); 679 } 680 681 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 682 devRead->rxFilterConf.rxMode = 0; 683 684 /* Setting up feature flags */ 685 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 686 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 687 688 if (dev->data->dev_conf.rxmode.enable_lro) { 689 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 690 devRead->misc.maxNumRxSG = 0; 691 } 692 693 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 694 ret = vmxnet3_rss_configure(dev); 695 if (ret != VMXNET3_SUCCESS) 696 return ret; 697 698 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 699 devRead->rssConfDesc.confVer = 1; 700 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 701 devRead->rssConfDesc.confPA = hw->rss_confPA; 702 } 703 704 ret = vmxnet3_dev_vlan_offload_set(dev, 705 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 706 if (ret) 707 return ret; 708 709 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 710 711 return VMXNET3_SUCCESS; 712 } 713 714 /* 715 * Configure device link speed and setup link. 716 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 717 * It returns 0 on success. 718 */ 719 static int 720 vmxnet3_dev_start(struct rte_eth_dev *dev) 721 { 722 int ret; 723 struct vmxnet3_hw *hw = dev->data->dev_private; 724 725 PMD_INIT_FUNC_TRACE(); 726 727 /* Save stats before it is reset by CMD_ACTIVATE */ 728 vmxnet3_hw_stats_save(hw); 729 730 ret = vmxnet3_setup_driver_shared(dev); 731 if (ret != VMXNET3_SUCCESS) 732 return ret; 733 734 /* check if lsc interrupt feature is enabled */ 735 if (dev->data->dev_conf.intr_conf.lsc) { 736 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 737 738 /* Setup interrupt callback */ 739 rte_intr_callback_register(&pci_dev->intr_handle, 740 vmxnet3_interrupt_handler, dev); 741 742 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 743 PMD_INIT_LOG(ERR, "interrupt enable failed"); 744 return -EIO; 745 } 746 } 747 748 /* Exchange shared data with device */ 749 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 750 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 751 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 752 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 753 754 /* Activate device by register write */ 755 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 756 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 757 758 if (ret != 0) { 759 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 760 return -EINVAL; 761 } 762 763 /* Setup memory region for rx buffers */ 764 ret = vmxnet3_dev_setup_memreg(dev); 765 if (ret == 0) { 766 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 767 VMXNET3_CMD_REGISTER_MEMREGS); 768 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 769 if (ret != 0) 770 PMD_INIT_LOG(DEBUG, 771 "Failed in setup memory region cmd\n"); 772 ret = 0; 773 } else { 774 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 775 } 776 777 /* Disable interrupts */ 778 vmxnet3_disable_intr(hw); 779 780 /* 781 * Load RX queues with blank mbufs and update next2fill index for device 782 * Update RxMode of the device 783 */ 784 ret = vmxnet3_dev_rxtx_init(dev); 785 if (ret != VMXNET3_SUCCESS) { 786 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 787 return ret; 788 } 789 790 hw->adapter_stopped = FALSE; 791 792 /* Setting proper Rx Mode and issue Rx Mode Update command */ 793 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 794 795 if (dev->data->dev_conf.intr_conf.lsc) { 796 vmxnet3_enable_intr(hw); 797 798 /* 799 * Update link state from device since this won't be 800 * done upon starting with lsc in use. This is done 801 * only after enabling interrupts to avoid any race 802 * where the link state could change without an 803 * interrupt being fired. 804 */ 805 __vmxnet3_dev_link_update(dev, 0); 806 } 807 808 return VMXNET3_SUCCESS; 809 } 810 811 /* 812 * Stop device: disable rx and tx functions to allow for reconfiguring. 813 */ 814 static void 815 vmxnet3_dev_stop(struct rte_eth_dev *dev) 816 { 817 struct rte_eth_link link; 818 struct vmxnet3_hw *hw = dev->data->dev_private; 819 820 PMD_INIT_FUNC_TRACE(); 821 822 if (hw->adapter_stopped == 1) { 823 PMD_INIT_LOG(DEBUG, "Device already closed."); 824 return; 825 } 826 827 /* disable interrupts */ 828 vmxnet3_disable_intr(hw); 829 830 if (dev->data->dev_conf.intr_conf.lsc) { 831 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 832 833 rte_intr_disable(&pci_dev->intr_handle); 834 835 rte_intr_callback_unregister(&pci_dev->intr_handle, 836 vmxnet3_interrupt_handler, dev); 837 } 838 839 /* quiesce the device first */ 840 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 841 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 842 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 843 844 /* reset the device */ 845 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 846 PMD_INIT_LOG(DEBUG, "Device reset."); 847 hw->adapter_stopped = 0; 848 849 vmxnet3_dev_clear_queues(dev); 850 851 /* Clear recorded link status */ 852 memset(&link, 0, sizeof(link)); 853 vmxnet3_dev_atomic_write_link_status(dev, &link); 854 } 855 856 /* 857 * Reset and stop device. 858 */ 859 static void 860 vmxnet3_dev_close(struct rte_eth_dev *dev) 861 { 862 struct vmxnet3_hw *hw = dev->data->dev_private; 863 864 PMD_INIT_FUNC_TRACE(); 865 866 vmxnet3_dev_stop(dev); 867 hw->adapter_stopped = 1; 868 } 869 870 static void 871 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 872 struct UPT1_TxStats *res) 873 { 874 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 875 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 876 (h)->saved_tx_stats[(i)].f) 877 878 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 879 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 880 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 881 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 882 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 883 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 884 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 885 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 886 887 #undef VMXNET3_UPDATE_TX_STAT 888 } 889 890 static void 891 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 892 struct UPT1_RxStats *res) 893 { 894 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 895 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 896 (h)->saved_rx_stats[(i)].f) 897 898 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 899 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 900 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 901 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 902 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 903 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 904 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 905 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 906 907 #undef VMXNET3_UPDATE_RX_STATS 908 } 909 910 static void 911 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 912 { 913 unsigned int i; 914 915 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 916 917 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 918 919 for (i = 0; i < hw->num_tx_queues; i++) 920 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 921 for (i = 0; i < hw->num_rx_queues; i++) 922 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 923 } 924 925 static int 926 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 927 struct rte_eth_xstat_name *xstats_names, 928 unsigned int n) 929 { 930 unsigned int i, t, count = 0; 931 unsigned int nstats = 932 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 933 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 934 935 if (!xstats_names || n < nstats) 936 return nstats; 937 938 for (i = 0; i < dev->data->nb_rx_queues; i++) { 939 if (!dev->data->rx_queues[i]) 940 continue; 941 942 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 943 snprintf(xstats_names[count].name, 944 sizeof(xstats_names[count].name), 945 "rx_q%u_%s", i, 946 vmxnet3_rxq_stat_strings[t].name); 947 count++; 948 } 949 } 950 951 for (i = 0; i < dev->data->nb_tx_queues; i++) { 952 if (!dev->data->tx_queues[i]) 953 continue; 954 955 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 956 snprintf(xstats_names[count].name, 957 sizeof(xstats_names[count].name), 958 "tx_q%u_%s", i, 959 vmxnet3_txq_stat_strings[t].name); 960 count++; 961 } 962 } 963 964 return count; 965 } 966 967 static int 968 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 969 unsigned int n) 970 { 971 unsigned int i, t, count = 0; 972 unsigned int nstats = 973 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 974 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 975 976 if (n < nstats) 977 return nstats; 978 979 for (i = 0; i < dev->data->nb_rx_queues; i++) { 980 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 981 982 if (rxq == NULL) 983 continue; 984 985 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 986 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 987 vmxnet3_rxq_stat_strings[t].offset); 988 xstats[count].id = count; 989 count++; 990 } 991 } 992 993 for (i = 0; i < dev->data->nb_tx_queues; i++) { 994 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 995 996 if (txq == NULL) 997 continue; 998 999 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1000 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1001 vmxnet3_txq_stat_strings[t].offset); 1002 xstats[count].id = count; 1003 count++; 1004 } 1005 } 1006 1007 return count; 1008 } 1009 1010 static int 1011 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1012 { 1013 unsigned int i; 1014 struct vmxnet3_hw *hw = dev->data->dev_private; 1015 struct UPT1_TxStats txStats; 1016 struct UPT1_RxStats rxStats; 1017 1018 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1019 1020 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1021 for (i = 0; i < hw->num_tx_queues; i++) { 1022 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1023 1024 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1025 txStats.mcastPktsTxOK + 1026 txStats.bcastPktsTxOK; 1027 1028 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1029 txStats.mcastBytesTxOK + 1030 txStats.bcastBytesTxOK; 1031 1032 stats->opackets += stats->q_opackets[i]; 1033 stats->obytes += stats->q_obytes[i]; 1034 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1035 } 1036 1037 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1038 for (i = 0; i < hw->num_rx_queues; i++) { 1039 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1040 1041 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1042 rxStats.mcastPktsRxOK + 1043 rxStats.bcastPktsRxOK; 1044 1045 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1046 rxStats.mcastBytesRxOK + 1047 rxStats.bcastBytesRxOK; 1048 1049 stats->ipackets += stats->q_ipackets[i]; 1050 stats->ibytes += stats->q_ibytes[i]; 1051 1052 stats->q_errors[i] = rxStats.pktsRxError; 1053 stats->ierrors += rxStats.pktsRxError; 1054 stats->rx_nombuf += rxStats.pktsRxOutOfBuf; 1055 } 1056 1057 return 0; 1058 } 1059 1060 static void 1061 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1062 struct rte_eth_dev_info *dev_info) 1063 { 1064 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1065 1066 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1067 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1068 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1069 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1070 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1071 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1072 1073 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 1074 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1075 1076 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1077 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1078 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1079 .nb_align = 1, 1080 }; 1081 1082 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1083 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1084 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1085 .nb_align = 1, 1086 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1087 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1088 }; 1089 1090 dev_info->rx_offload_capa = 1091 DEV_RX_OFFLOAD_VLAN_STRIP | 1092 DEV_RX_OFFLOAD_UDP_CKSUM | 1093 DEV_RX_OFFLOAD_TCP_CKSUM | 1094 DEV_RX_OFFLOAD_TCP_LRO; 1095 1096 dev_info->tx_offload_capa = 1097 DEV_TX_OFFLOAD_VLAN_INSERT | 1098 DEV_TX_OFFLOAD_TCP_CKSUM | 1099 DEV_TX_OFFLOAD_UDP_CKSUM | 1100 DEV_TX_OFFLOAD_TCP_TSO; 1101 } 1102 1103 static const uint32_t * 1104 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1105 { 1106 static const uint32_t ptypes[] = { 1107 RTE_PTYPE_L3_IPV4_EXT, 1108 RTE_PTYPE_L3_IPV4, 1109 RTE_PTYPE_UNKNOWN 1110 }; 1111 1112 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1113 return ptypes; 1114 return NULL; 1115 } 1116 1117 static void 1118 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1119 { 1120 struct vmxnet3_hw *hw = dev->data->dev_private; 1121 1122 ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr)); 1123 ether_addr_copy(mac_addr, &dev->data->mac_addrs[0]); 1124 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1125 } 1126 1127 /* return 0 means link status changed, -1 means not changed */ 1128 static int 1129 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1130 __rte_unused int wait_to_complete) 1131 { 1132 struct vmxnet3_hw *hw = dev->data->dev_private; 1133 struct rte_eth_link old = { 0 }, link; 1134 uint32_t ret; 1135 1136 memset(&link, 0, sizeof(link)); 1137 vmxnet3_dev_atomic_read_link_status(dev, &old); 1138 1139 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1140 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1141 1142 if (ret & 0x1) { 1143 link.link_status = ETH_LINK_UP; 1144 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1145 link.link_speed = ETH_SPEED_NUM_10G; 1146 link.link_autoneg = ETH_LINK_SPEED_FIXED; 1147 } 1148 1149 vmxnet3_dev_atomic_write_link_status(dev, &link); 1150 1151 return (old.link_status == link.link_status) ? -1 : 0; 1152 } 1153 1154 static int 1155 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1156 { 1157 /* Link status doesn't change for stopped dev */ 1158 if (dev->data->dev_started == 0) 1159 return -1; 1160 1161 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1162 } 1163 1164 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1165 static void 1166 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1167 { 1168 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1169 1170 if (set) 1171 rxConf->rxMode = rxConf->rxMode | feature; 1172 else 1173 rxConf->rxMode = rxConf->rxMode & (~feature); 1174 1175 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1176 } 1177 1178 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1179 static void 1180 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1181 { 1182 struct vmxnet3_hw *hw = dev->data->dev_private; 1183 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1184 1185 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1186 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1187 1188 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1189 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1190 } 1191 1192 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1193 static void 1194 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1195 { 1196 struct vmxnet3_hw *hw = dev->data->dev_private; 1197 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1198 1199 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1200 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1201 else 1202 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1203 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1204 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1205 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1206 } 1207 1208 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1209 static void 1210 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1211 { 1212 struct vmxnet3_hw *hw = dev->data->dev_private; 1213 1214 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1215 } 1216 1217 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1218 static void 1219 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1220 { 1221 struct vmxnet3_hw *hw = dev->data->dev_private; 1222 1223 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1224 } 1225 1226 /* Enable/disable filter on vlan */ 1227 static int 1228 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1229 { 1230 struct vmxnet3_hw *hw = dev->data->dev_private; 1231 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1232 uint32_t *vf_table = rxConf->vfTable; 1233 1234 /* save state for restore */ 1235 if (on) 1236 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1237 else 1238 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1239 1240 /* don't change active filter if in promiscuous mode */ 1241 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1242 return 0; 1243 1244 /* set in hardware */ 1245 if (on) 1246 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1247 else 1248 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1249 1250 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1251 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1252 return 0; 1253 } 1254 1255 static int 1256 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1257 { 1258 struct vmxnet3_hw *hw = dev->data->dev_private; 1259 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1260 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1261 1262 if (mask & ETH_VLAN_STRIP_MASK) { 1263 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1264 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1265 else 1266 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1267 1268 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1269 VMXNET3_CMD_UPDATE_FEATURE); 1270 } 1271 1272 if (mask & ETH_VLAN_FILTER_MASK) { 1273 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1274 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1275 else 1276 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1277 1278 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1279 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1280 } 1281 1282 return 0; 1283 } 1284 1285 static void 1286 vmxnet3_process_events(struct rte_eth_dev *dev) 1287 { 1288 struct vmxnet3_hw *hw = dev->data->dev_private; 1289 uint32_t events = hw->shared->ecr; 1290 1291 if (!events) 1292 return; 1293 1294 /* 1295 * ECR bits when written with 1b are cleared. Hence write 1296 * events back to ECR so that the bits which were set will be reset. 1297 */ 1298 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1299 1300 /* Check if link state has changed */ 1301 if (events & VMXNET3_ECR_LINK) { 1302 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1303 if (vmxnet3_dev_link_update(dev, 0) == 0) 1304 _rte_eth_dev_callback_process(dev, 1305 RTE_ETH_EVENT_INTR_LSC, 1306 NULL, NULL); 1307 } 1308 1309 /* Check if there is an error on xmit/recv queues */ 1310 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1311 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1312 VMXNET3_CMD_GET_QUEUE_STATUS); 1313 1314 if (hw->tqd_start->status.stopped) 1315 PMD_DRV_LOG(ERR, "tq error 0x%x", 1316 hw->tqd_start->status.error); 1317 1318 if (hw->rqd_start->status.stopped) 1319 PMD_DRV_LOG(ERR, "rq error 0x%x", 1320 hw->rqd_start->status.error); 1321 1322 /* Reset the device */ 1323 /* Have to reset the device */ 1324 } 1325 1326 if (events & VMXNET3_ECR_DIC) 1327 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1328 1329 if (events & VMXNET3_ECR_DEBUG) 1330 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1331 } 1332 1333 static void 1334 vmxnet3_interrupt_handler(void *param) 1335 { 1336 struct rte_eth_dev *dev = param; 1337 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1338 1339 vmxnet3_process_events(dev); 1340 1341 if (rte_intr_enable(&pci_dev->intr_handle) < 0) 1342 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1343 } 1344 1345 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1346 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1347 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1348