1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 46 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 47 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 48 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 49 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 50 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 51 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 52 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 53 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 54 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 55 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 56 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 57 int wait_to_complete); 58 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 59 int wait_to_complete); 60 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 61 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 62 struct rte_eth_stats *stats); 63 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 64 struct rte_eth_xstat_name *xstats, 65 unsigned int n); 66 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 67 struct rte_eth_xstat *xstats, unsigned int n); 68 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, 69 struct rte_eth_dev_info *dev_info); 70 static const uint32_t * 71 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 73 uint16_t vid, int on); 74 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 75 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 76 struct ether_addr *mac_addr); 77 static void vmxnet3_interrupt_handler(void *param); 78 79 int vmxnet3_logtype_init; 80 int vmxnet3_logtype_driver; 81 82 /* 83 * The set of PCI devices this driver supports 84 */ 85 #define VMWARE_PCI_VENDOR_ID 0x15AD 86 #define VMWARE_DEV_ID_VMXNET3 0x07B0 87 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 88 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 89 { .vendor_id = 0, /* sentinel */ }, 90 }; 91 92 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 93 .dev_configure = vmxnet3_dev_configure, 94 .dev_start = vmxnet3_dev_start, 95 .dev_stop = vmxnet3_dev_stop, 96 .dev_close = vmxnet3_dev_close, 97 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 98 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 99 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 100 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 101 .link_update = vmxnet3_dev_link_update, 102 .stats_get = vmxnet3_dev_stats_get, 103 .xstats_get_names = vmxnet3_dev_xstats_get_names, 104 .xstats_get = vmxnet3_dev_xstats_get, 105 .mac_addr_set = vmxnet3_mac_addr_set, 106 .dev_infos_get = vmxnet3_dev_info_get, 107 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 108 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 109 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 110 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 111 .rx_queue_release = vmxnet3_dev_rx_queue_release, 112 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 113 .tx_queue_release = vmxnet3_dev_tx_queue_release, 114 }; 115 116 struct vmxnet3_xstats_name_off { 117 char name[RTE_ETH_XSTATS_NAME_SIZE]; 118 unsigned int offset; 119 }; 120 121 /* tx_qX_ is prepended to the name string here */ 122 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 123 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 124 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 125 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 126 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 127 }; 128 129 /* rx_qX_ is prepended to the name string here */ 130 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 131 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 132 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 133 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 134 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 135 }; 136 137 static const struct rte_memzone * 138 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 139 const char *post_string, int socket_id, 140 uint16_t align, bool reuse) 141 { 142 char z_name[RTE_MEMZONE_NAMESIZE]; 143 const struct rte_memzone *mz; 144 145 snprintf(z_name, sizeof(z_name), "%s_%d_%s", 146 dev->device->driver->name, dev->data->port_id, post_string); 147 148 mz = rte_memzone_lookup(z_name); 149 if (!reuse) { 150 if (mz) 151 rte_memzone_free(mz); 152 return rte_memzone_reserve_aligned(z_name, size, socket_id, 153 0, align); 154 } 155 156 if (mz) 157 return mz; 158 159 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align); 160 } 161 162 /* 163 * This function is based on vmxnet3_disable_intr() 164 */ 165 static void 166 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 167 { 168 int i; 169 170 PMD_INIT_FUNC_TRACE(); 171 172 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 173 for (i = 0; i < hw->num_intrs; i++) 174 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 175 } 176 177 static void 178 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 179 { 180 int i; 181 182 PMD_INIT_FUNC_TRACE(); 183 184 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 185 for (i = 0; i < hw->num_intrs; i++) 186 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 187 } 188 189 /* 190 * Gets tx data ring descriptor size. 191 */ 192 static uint16_t 193 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 194 { 195 uint16 txdata_desc_size; 196 197 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 198 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 199 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 200 201 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 202 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 203 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 204 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 205 } 206 207 /* 208 * It returns 0 on success. 209 */ 210 static int 211 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 212 { 213 struct rte_pci_device *pci_dev; 214 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 215 uint32_t mac_hi, mac_lo, ver; 216 struct rte_eth_link link; 217 218 PMD_INIT_FUNC_TRACE(); 219 220 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 221 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 222 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 223 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 224 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 225 226 /* 227 * for secondary processes, we don't initialize any further as primary 228 * has already done this work. 229 */ 230 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 231 return 0; 232 233 rte_eth_copy_pci_info(eth_dev, pci_dev); 234 235 /* Vendor and Device ID need to be set before init of shared code */ 236 hw->device_id = pci_dev->id.device_id; 237 hw->vendor_id = pci_dev->id.vendor_id; 238 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 239 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 240 241 hw->num_rx_queues = 1; 242 hw->num_tx_queues = 1; 243 hw->bufs_per_pkt = 1; 244 245 /* Check h/w version compatibility with driver. */ 246 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 247 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 248 249 if (ver & (1 << VMXNET3_REV_3)) { 250 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 251 1 << VMXNET3_REV_3); 252 hw->version = VMXNET3_REV_3 + 1; 253 } else if (ver & (1 << VMXNET3_REV_2)) { 254 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 255 1 << VMXNET3_REV_2); 256 hw->version = VMXNET3_REV_2 + 1; 257 } else if (ver & (1 << VMXNET3_REV_1)) { 258 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 259 1 << VMXNET3_REV_1); 260 hw->version = VMXNET3_REV_1 + 1; 261 } else { 262 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 263 return -EIO; 264 } 265 266 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 267 268 /* Check UPT version compatibility with driver. */ 269 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 270 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 271 if (ver & 0x1) 272 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 273 else { 274 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 275 return -EIO; 276 } 277 278 /* Getting MAC Address */ 279 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 280 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 281 memcpy(hw->perm_addr, &mac_lo, 4); 282 memcpy(hw->perm_addr + 4, &mac_hi, 2); 283 284 /* Allocate memory for storing MAC addresses */ 285 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN * 286 VMXNET3_MAX_MAC_ADDRS, 0); 287 if (eth_dev->data->mac_addrs == NULL) { 288 PMD_INIT_LOG(ERR, 289 "Failed to allocate %d bytes needed to store MAC addresses", 290 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 291 return -ENOMEM; 292 } 293 /* Copy the permanent MAC address */ 294 ether_addr_copy((struct ether_addr *) hw->perm_addr, 295 ð_dev->data->mac_addrs[0]); 296 297 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 298 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 299 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 300 301 /* Put device in Quiesce Mode */ 302 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 303 304 /* allow untagged pkts */ 305 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 306 307 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 308 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 309 310 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 311 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 312 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 313 hw->rxdata_desc_size); 314 315 /* clear shadow stats */ 316 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 317 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 318 319 /* set the initial link status */ 320 memset(&link, 0, sizeof(link)); 321 link.link_duplex = ETH_LINK_FULL_DUPLEX; 322 link.link_speed = ETH_SPEED_NUM_10G; 323 link.link_autoneg = ETH_LINK_FIXED; 324 rte_eth_linkstatus_set(eth_dev, &link); 325 326 return 0; 327 } 328 329 static int 330 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 331 { 332 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 333 334 PMD_INIT_FUNC_TRACE(); 335 336 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 337 return 0; 338 339 if (hw->adapter_stopped == 0) 340 vmxnet3_dev_close(eth_dev); 341 342 eth_dev->dev_ops = NULL; 343 eth_dev->rx_pkt_burst = NULL; 344 eth_dev->tx_pkt_burst = NULL; 345 eth_dev->tx_pkt_prepare = NULL; 346 347 rte_free(eth_dev->data->mac_addrs); 348 eth_dev->data->mac_addrs = NULL; 349 350 return 0; 351 } 352 353 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 354 struct rte_pci_device *pci_dev) 355 { 356 return rte_eth_dev_pci_generic_probe(pci_dev, 357 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 358 } 359 360 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 361 { 362 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 363 } 364 365 static struct rte_pci_driver rte_vmxnet3_pmd = { 366 .id_table = pci_id_vmxnet3_map, 367 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 368 .probe = eth_vmxnet3_pci_probe, 369 .remove = eth_vmxnet3_pci_remove, 370 }; 371 372 static int 373 vmxnet3_dev_configure(struct rte_eth_dev *dev) 374 { 375 const struct rte_memzone *mz; 376 struct vmxnet3_hw *hw = dev->data->dev_private; 377 size_t size; 378 379 PMD_INIT_FUNC_TRACE(); 380 381 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 382 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 383 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 384 return -EINVAL; 385 } 386 387 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 388 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 389 return -EINVAL; 390 } 391 392 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 393 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 394 395 if (size > UINT16_MAX) 396 return -EINVAL; 397 398 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 399 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 400 401 /* 402 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 403 * on current socket 404 */ 405 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 406 "shared", rte_socket_id(), 8, 1); 407 408 if (mz == NULL) { 409 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 410 return -ENOMEM; 411 } 412 memset(mz->addr, 0, mz->len); 413 414 hw->shared = mz->addr; 415 hw->sharedPA = mz->iova; 416 417 /* 418 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 419 * on current socket. 420 * 421 * We cannot reuse this memzone from previous allocation as its size 422 * depends on the number of tx and rx queues, which could be different 423 * from one config to another. 424 */ 425 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 426 VMXNET3_QUEUE_DESC_ALIGN, 0); 427 if (mz == NULL) { 428 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 429 return -ENOMEM; 430 } 431 memset(mz->addr, 0, mz->len); 432 433 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 434 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 435 436 hw->queueDescPA = mz->iova; 437 hw->queue_desc_len = (uint16_t)size; 438 439 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 440 /* Allocate memory structure for UPT1_RSSConf and configure */ 441 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 442 "rss_conf", rte_socket_id(), 443 RTE_CACHE_LINE_SIZE, 1); 444 if (mz == NULL) { 445 PMD_INIT_LOG(ERR, 446 "ERROR: Creating rss_conf structure zone"); 447 return -ENOMEM; 448 } 449 memset(mz->addr, 0, mz->len); 450 451 hw->rss_conf = mz->addr; 452 hw->rss_confPA = mz->iova; 453 } 454 455 return 0; 456 } 457 458 static void 459 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 460 { 461 uint32_t val; 462 463 PMD_INIT_LOG(DEBUG, 464 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 465 addr[0], addr[1], addr[2], 466 addr[3], addr[4], addr[5]); 467 468 memcpy(&val, addr, 4); 469 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 470 471 memcpy(&val, addr + 4, 2); 472 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 473 } 474 475 static int 476 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 477 { 478 struct vmxnet3_hw *hw = dev->data->dev_private; 479 Vmxnet3_DriverShared *shared = hw->shared; 480 Vmxnet3_CmdInfo *cmdInfo; 481 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 482 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 483 uint32_t num, i, j, size; 484 485 if (hw->memRegsPA == 0) { 486 const struct rte_memzone *mz; 487 488 size = sizeof(Vmxnet3_MemRegs) + 489 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 490 sizeof(Vmxnet3_MemoryRegion); 491 492 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 493 1); 494 if (mz == NULL) { 495 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 496 return -ENOMEM; 497 } 498 memset(mz->addr, 0, mz->len); 499 hw->memRegs = mz->addr; 500 hw->memRegsPA = mz->iova; 501 } 502 503 num = hw->num_rx_queues; 504 505 for (i = 0; i < num; i++) { 506 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 507 508 mp[i] = rxq->mp; 509 index[i] = 1 << i; 510 } 511 512 /* 513 * The same mempool could be used by multiple queues. In such a case, 514 * remove duplicate mempool entries. Only one entry is kept with 515 * bitmask indicating queues that are using this mempool. 516 */ 517 for (i = 1; i < num; i++) { 518 for (j = 0; j < i; j++) { 519 if (mp[i] == mp[j]) { 520 mp[i] = NULL; 521 index[j] |= 1 << i; 522 break; 523 } 524 } 525 } 526 527 j = 0; 528 for (i = 0; i < num; i++) { 529 if (mp[i] == NULL) 530 continue; 531 532 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 533 534 mr->startPA = 535 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 536 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 537 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 538 mr->txQueueBits = index[i]; 539 mr->rxQueueBits = index[i]; 540 541 PMD_INIT_LOG(INFO, 542 "index: %u startPA: %" PRIu64 " length: %u, " 543 "rxBits: %x", 544 j, mr->startPA, mr->length, mr->rxQueueBits); 545 j++; 546 } 547 hw->memRegs->numRegs = j; 548 PMD_INIT_LOG(INFO, "numRegs: %u", j); 549 550 size = sizeof(Vmxnet3_MemRegs) + 551 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 552 553 cmdInfo = &shared->cu.cmdInfo; 554 cmdInfo->varConf.confVer = 1; 555 cmdInfo->varConf.confLen = size; 556 cmdInfo->varConf.confPA = hw->memRegsPA; 557 558 return 0; 559 } 560 561 static int 562 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 563 { 564 struct rte_eth_conf port_conf = dev->data->dev_conf; 565 struct vmxnet3_hw *hw = dev->data->dev_private; 566 uint32_t mtu = dev->data->mtu; 567 Vmxnet3_DriverShared *shared = hw->shared; 568 Vmxnet3_DSDevRead *devRead = &shared->devRead; 569 uint32_t i; 570 int ret; 571 572 shared->magic = VMXNET3_REV1_MAGIC; 573 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 574 575 /* Setting up Guest OS information */ 576 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 577 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 578 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 579 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 580 devRead->misc.driverInfo.uptVerSpt = 1; 581 582 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 583 devRead->misc.queueDescPA = hw->queueDescPA; 584 devRead->misc.queueDescLen = hw->queue_desc_len; 585 devRead->misc.numTxQueues = hw->num_tx_queues; 586 devRead->misc.numRxQueues = hw->num_rx_queues; 587 588 /* 589 * Set number of interrupts to 1 590 * PMD by default disables all the interrupts but this is MUST 591 * to activate device. It needs at least one interrupt for 592 * link events to handle 593 */ 594 hw->num_intrs = devRead->intrConf.numIntrs = 1; 595 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 596 597 for (i = 0; i < hw->num_tx_queues; i++) { 598 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 599 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 600 601 txq->shared = &hw->tqd_start[i]; 602 603 tqd->ctrl.txNumDeferred = 0; 604 tqd->ctrl.txThreshold = 1; 605 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 606 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 607 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 608 609 tqd->conf.txRingSize = txq->cmd_ring.size; 610 tqd->conf.compRingSize = txq->comp_ring.size; 611 tqd->conf.dataRingSize = txq->data_ring.size; 612 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 613 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 614 tqd->status.stopped = TRUE; 615 tqd->status.error = 0; 616 memset(&tqd->stats, 0, sizeof(tqd->stats)); 617 } 618 619 for (i = 0; i < hw->num_rx_queues; i++) { 620 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 621 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 622 623 rxq->shared = &hw->rqd_start[i]; 624 625 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 626 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 627 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 628 629 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 630 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 631 rqd->conf.compRingSize = rxq->comp_ring.size; 632 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 633 if (VMXNET3_VERSION_GE_3(hw)) { 634 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 635 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 636 } 637 rqd->status.stopped = TRUE; 638 rqd->status.error = 0; 639 memset(&rqd->stats, 0, sizeof(rqd->stats)); 640 } 641 642 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 643 devRead->rxFilterConf.rxMode = 0; 644 645 /* Setting up feature flags */ 646 if (dev->data->dev_conf.rxmode.hw_ip_checksum) 647 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 648 649 if (dev->data->dev_conf.rxmode.enable_lro) { 650 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 651 devRead->misc.maxNumRxSG = 0; 652 } 653 654 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 655 ret = vmxnet3_rss_configure(dev); 656 if (ret != VMXNET3_SUCCESS) 657 return ret; 658 659 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 660 devRead->rssConfDesc.confVer = 1; 661 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 662 devRead->rssConfDesc.confPA = hw->rss_confPA; 663 } 664 665 ret = vmxnet3_dev_vlan_offload_set(dev, 666 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 667 if (ret) 668 return ret; 669 670 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 671 672 return VMXNET3_SUCCESS; 673 } 674 675 /* 676 * Configure device link speed and setup link. 677 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 678 * It returns 0 on success. 679 */ 680 static int 681 vmxnet3_dev_start(struct rte_eth_dev *dev) 682 { 683 int ret; 684 struct vmxnet3_hw *hw = dev->data->dev_private; 685 686 PMD_INIT_FUNC_TRACE(); 687 688 /* Save stats before it is reset by CMD_ACTIVATE */ 689 vmxnet3_hw_stats_save(hw); 690 691 ret = vmxnet3_setup_driver_shared(dev); 692 if (ret != VMXNET3_SUCCESS) 693 return ret; 694 695 /* check if lsc interrupt feature is enabled */ 696 if (dev->data->dev_conf.intr_conf.lsc) { 697 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 698 699 /* Setup interrupt callback */ 700 rte_intr_callback_register(&pci_dev->intr_handle, 701 vmxnet3_interrupt_handler, dev); 702 703 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 704 PMD_INIT_LOG(ERR, "interrupt enable failed"); 705 return -EIO; 706 } 707 } 708 709 /* Exchange shared data with device */ 710 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 711 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 712 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 713 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 714 715 /* Activate device by register write */ 716 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 717 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 718 719 if (ret != 0) { 720 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 721 return -EINVAL; 722 } 723 724 /* Setup memory region for rx buffers */ 725 ret = vmxnet3_dev_setup_memreg(dev); 726 if (ret == 0) { 727 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 728 VMXNET3_CMD_REGISTER_MEMREGS); 729 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 730 if (ret != 0) 731 PMD_INIT_LOG(DEBUG, 732 "Failed in setup memory region cmd\n"); 733 ret = 0; 734 } else { 735 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 736 } 737 738 /* Disable interrupts */ 739 vmxnet3_disable_intr(hw); 740 741 /* 742 * Load RX queues with blank mbufs and update next2fill index for device 743 * Update RxMode of the device 744 */ 745 ret = vmxnet3_dev_rxtx_init(dev); 746 if (ret != VMXNET3_SUCCESS) { 747 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 748 return ret; 749 } 750 751 hw->adapter_stopped = FALSE; 752 753 /* Setting proper Rx Mode and issue Rx Mode Update command */ 754 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 755 756 if (dev->data->dev_conf.intr_conf.lsc) { 757 vmxnet3_enable_intr(hw); 758 759 /* 760 * Update link state from device since this won't be 761 * done upon starting with lsc in use. This is done 762 * only after enabling interrupts to avoid any race 763 * where the link state could change without an 764 * interrupt being fired. 765 */ 766 __vmxnet3_dev_link_update(dev, 0); 767 } 768 769 return VMXNET3_SUCCESS; 770 } 771 772 /* 773 * Stop device: disable rx and tx functions to allow for reconfiguring. 774 */ 775 static void 776 vmxnet3_dev_stop(struct rte_eth_dev *dev) 777 { 778 struct rte_eth_link link; 779 struct vmxnet3_hw *hw = dev->data->dev_private; 780 781 PMD_INIT_FUNC_TRACE(); 782 783 if (hw->adapter_stopped == 1) { 784 PMD_INIT_LOG(DEBUG, "Device already closed."); 785 return; 786 } 787 788 /* disable interrupts */ 789 vmxnet3_disable_intr(hw); 790 791 if (dev->data->dev_conf.intr_conf.lsc) { 792 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 793 794 rte_intr_disable(&pci_dev->intr_handle); 795 796 rte_intr_callback_unregister(&pci_dev->intr_handle, 797 vmxnet3_interrupt_handler, dev); 798 } 799 800 /* quiesce the device first */ 801 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 802 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 803 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 804 805 /* reset the device */ 806 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 807 PMD_INIT_LOG(DEBUG, "Device reset."); 808 hw->adapter_stopped = 0; 809 810 vmxnet3_dev_clear_queues(dev); 811 812 /* Clear recorded link status */ 813 memset(&link, 0, sizeof(link)); 814 link.link_duplex = ETH_LINK_FULL_DUPLEX; 815 link.link_speed = ETH_SPEED_NUM_10G; 816 link.link_autoneg = ETH_LINK_FIXED; 817 rte_eth_linkstatus_set(dev, &link); 818 } 819 820 /* 821 * Reset and stop device. 822 */ 823 static void 824 vmxnet3_dev_close(struct rte_eth_dev *dev) 825 { 826 struct vmxnet3_hw *hw = dev->data->dev_private; 827 828 PMD_INIT_FUNC_TRACE(); 829 830 vmxnet3_dev_stop(dev); 831 hw->adapter_stopped = 1; 832 } 833 834 static void 835 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 836 struct UPT1_TxStats *res) 837 { 838 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 839 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 840 (h)->saved_tx_stats[(i)].f) 841 842 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 843 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 844 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 845 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 846 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 847 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 848 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 849 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 850 851 #undef VMXNET3_UPDATE_TX_STAT 852 } 853 854 static void 855 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 856 struct UPT1_RxStats *res) 857 { 858 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 859 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 860 (h)->saved_rx_stats[(i)].f) 861 862 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 863 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 864 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 865 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 866 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 867 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 868 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 869 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 870 871 #undef VMXNET3_UPDATE_RX_STATS 872 } 873 874 static void 875 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 876 { 877 unsigned int i; 878 879 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 880 881 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 882 883 for (i = 0; i < hw->num_tx_queues; i++) 884 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 885 for (i = 0; i < hw->num_rx_queues; i++) 886 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 887 } 888 889 static int 890 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 891 struct rte_eth_xstat_name *xstats_names, 892 unsigned int n) 893 { 894 unsigned int i, t, count = 0; 895 unsigned int nstats = 896 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 897 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 898 899 if (!xstats_names || n < nstats) 900 return nstats; 901 902 for (i = 0; i < dev->data->nb_rx_queues; i++) { 903 if (!dev->data->rx_queues[i]) 904 continue; 905 906 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 907 snprintf(xstats_names[count].name, 908 sizeof(xstats_names[count].name), 909 "rx_q%u_%s", i, 910 vmxnet3_rxq_stat_strings[t].name); 911 count++; 912 } 913 } 914 915 for (i = 0; i < dev->data->nb_tx_queues; i++) { 916 if (!dev->data->tx_queues[i]) 917 continue; 918 919 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 920 snprintf(xstats_names[count].name, 921 sizeof(xstats_names[count].name), 922 "tx_q%u_%s", i, 923 vmxnet3_txq_stat_strings[t].name); 924 count++; 925 } 926 } 927 928 return count; 929 } 930 931 static int 932 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 933 unsigned int n) 934 { 935 unsigned int i, t, count = 0; 936 unsigned int nstats = 937 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 938 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 939 940 if (n < nstats) 941 return nstats; 942 943 for (i = 0; i < dev->data->nb_rx_queues; i++) { 944 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 945 946 if (rxq == NULL) 947 continue; 948 949 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 950 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 951 vmxnet3_rxq_stat_strings[t].offset); 952 xstats[count].id = count; 953 count++; 954 } 955 } 956 957 for (i = 0; i < dev->data->nb_tx_queues; i++) { 958 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 959 960 if (txq == NULL) 961 continue; 962 963 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 964 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 965 vmxnet3_txq_stat_strings[t].offset); 966 xstats[count].id = count; 967 count++; 968 } 969 } 970 971 return count; 972 } 973 974 static int 975 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 976 { 977 unsigned int i; 978 struct vmxnet3_hw *hw = dev->data->dev_private; 979 struct UPT1_TxStats txStats; 980 struct UPT1_RxStats rxStats; 981 982 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 983 984 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 985 for (i = 0; i < hw->num_tx_queues; i++) { 986 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 987 988 stats->q_opackets[i] = txStats.ucastPktsTxOK + 989 txStats.mcastPktsTxOK + 990 txStats.bcastPktsTxOK; 991 992 stats->q_obytes[i] = txStats.ucastBytesTxOK + 993 txStats.mcastBytesTxOK + 994 txStats.bcastBytesTxOK; 995 996 stats->opackets += stats->q_opackets[i]; 997 stats->obytes += stats->q_obytes[i]; 998 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 999 } 1000 1001 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1002 for (i = 0; i < hw->num_rx_queues; i++) { 1003 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1004 1005 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1006 rxStats.mcastPktsRxOK + 1007 rxStats.bcastPktsRxOK; 1008 1009 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1010 rxStats.mcastBytesRxOK + 1011 rxStats.bcastBytesRxOK; 1012 1013 stats->ipackets += stats->q_ipackets[i]; 1014 stats->ibytes += stats->q_ibytes[i]; 1015 1016 stats->q_errors[i] = rxStats.pktsRxError; 1017 stats->ierrors += rxStats.pktsRxError; 1018 stats->rx_nombuf += rxStats.pktsRxOutOfBuf; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static void 1025 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1026 struct rte_eth_dev_info *dev_info) 1027 { 1028 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1029 1030 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1031 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1032 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1033 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1034 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1035 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1036 1037 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP; 1038 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1039 1040 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1041 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1042 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1043 .nb_align = 1, 1044 }; 1045 1046 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1047 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1048 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1049 .nb_align = 1, 1050 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1051 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1052 }; 1053 1054 dev_info->rx_offload_capa = 1055 DEV_RX_OFFLOAD_VLAN_STRIP | 1056 DEV_RX_OFFLOAD_UDP_CKSUM | 1057 DEV_RX_OFFLOAD_TCP_CKSUM | 1058 DEV_RX_OFFLOAD_TCP_LRO; 1059 1060 dev_info->tx_offload_capa = 1061 DEV_TX_OFFLOAD_VLAN_INSERT | 1062 DEV_TX_OFFLOAD_TCP_CKSUM | 1063 DEV_TX_OFFLOAD_UDP_CKSUM | 1064 DEV_TX_OFFLOAD_TCP_TSO; 1065 } 1066 1067 static const uint32_t * 1068 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1069 { 1070 static const uint32_t ptypes[] = { 1071 RTE_PTYPE_L3_IPV4_EXT, 1072 RTE_PTYPE_L3_IPV4, 1073 RTE_PTYPE_UNKNOWN 1074 }; 1075 1076 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1077 return ptypes; 1078 return NULL; 1079 } 1080 1081 static void 1082 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) 1083 { 1084 struct vmxnet3_hw *hw = dev->data->dev_private; 1085 1086 ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr)); 1087 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1088 } 1089 1090 /* return 0 means link status changed, -1 means not changed */ 1091 static int 1092 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1093 __rte_unused int wait_to_complete) 1094 { 1095 struct vmxnet3_hw *hw = dev->data->dev_private; 1096 struct rte_eth_link link; 1097 uint32_t ret; 1098 1099 memset(&link, 0, sizeof(link)); 1100 1101 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1102 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1103 1104 if (ret & 0x1) 1105 link.link_status = ETH_LINK_UP; 1106 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1107 link.link_speed = ETH_SPEED_NUM_10G; 1108 link.link_autoneg = ETH_LINK_AUTONEG; 1109 1110 return rte_eth_linkstatus_set(dev, &link); 1111 } 1112 1113 static int 1114 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1115 { 1116 /* Link status doesn't change for stopped dev */ 1117 if (dev->data->dev_started == 0) 1118 return -1; 1119 1120 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1121 } 1122 1123 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1124 static void 1125 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1126 { 1127 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1128 1129 if (set) 1130 rxConf->rxMode = rxConf->rxMode | feature; 1131 else 1132 rxConf->rxMode = rxConf->rxMode & (~feature); 1133 1134 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1135 } 1136 1137 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1138 static void 1139 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1140 { 1141 struct vmxnet3_hw *hw = dev->data->dev_private; 1142 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1143 1144 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1145 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1146 1147 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1148 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1149 } 1150 1151 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1152 static void 1153 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1154 { 1155 struct vmxnet3_hw *hw = dev->data->dev_private; 1156 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1157 1158 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1159 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1160 else 1161 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1162 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1163 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1164 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1165 } 1166 1167 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1168 static void 1169 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1170 { 1171 struct vmxnet3_hw *hw = dev->data->dev_private; 1172 1173 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1174 } 1175 1176 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1177 static void 1178 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1179 { 1180 struct vmxnet3_hw *hw = dev->data->dev_private; 1181 1182 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1183 } 1184 1185 /* Enable/disable filter on vlan */ 1186 static int 1187 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1188 { 1189 struct vmxnet3_hw *hw = dev->data->dev_private; 1190 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1191 uint32_t *vf_table = rxConf->vfTable; 1192 1193 /* save state for restore */ 1194 if (on) 1195 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1196 else 1197 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1198 1199 /* don't change active filter if in promiscuous mode */ 1200 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1201 return 0; 1202 1203 /* set in hardware */ 1204 if (on) 1205 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1206 else 1207 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1208 1209 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1210 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1211 return 0; 1212 } 1213 1214 static int 1215 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1216 { 1217 struct vmxnet3_hw *hw = dev->data->dev_private; 1218 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1219 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1220 1221 if (mask & ETH_VLAN_STRIP_MASK) { 1222 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1223 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1224 else 1225 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1226 1227 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1228 VMXNET3_CMD_UPDATE_FEATURE); 1229 } 1230 1231 if (mask & ETH_VLAN_FILTER_MASK) { 1232 if (dev->data->dev_conf.rxmode.hw_vlan_filter) 1233 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1234 else 1235 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1236 1237 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1238 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static void 1245 vmxnet3_process_events(struct rte_eth_dev *dev) 1246 { 1247 struct vmxnet3_hw *hw = dev->data->dev_private; 1248 uint32_t events = hw->shared->ecr; 1249 1250 if (!events) 1251 return; 1252 1253 /* 1254 * ECR bits when written with 1b are cleared. Hence write 1255 * events back to ECR so that the bits which were set will be reset. 1256 */ 1257 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1258 1259 /* Check if link state has changed */ 1260 if (events & VMXNET3_ECR_LINK) { 1261 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1262 if (vmxnet3_dev_link_update(dev, 0) == 0) 1263 _rte_eth_dev_callback_process(dev, 1264 RTE_ETH_EVENT_INTR_LSC, 1265 NULL); 1266 } 1267 1268 /* Check if there is an error on xmit/recv queues */ 1269 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1271 VMXNET3_CMD_GET_QUEUE_STATUS); 1272 1273 if (hw->tqd_start->status.stopped) 1274 PMD_DRV_LOG(ERR, "tq error 0x%x", 1275 hw->tqd_start->status.error); 1276 1277 if (hw->rqd_start->status.stopped) 1278 PMD_DRV_LOG(ERR, "rq error 0x%x", 1279 hw->rqd_start->status.error); 1280 1281 /* Reset the device */ 1282 /* Have to reset the device */ 1283 } 1284 1285 if (events & VMXNET3_ECR_DIC) 1286 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1287 1288 if (events & VMXNET3_ECR_DEBUG) 1289 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1290 } 1291 1292 static void 1293 vmxnet3_interrupt_handler(void *param) 1294 { 1295 struct rte_eth_dev *dev = param; 1296 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1297 1298 vmxnet3_process_events(dev); 1299 1300 if (rte_intr_enable(&pci_dev->intr_handle) < 0) 1301 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1302 } 1303 1304 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1305 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1306 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1307 1308 RTE_INIT(vmxnet3_init_log); 1309 static void 1310 vmxnet3_init_log(void) 1311 { 1312 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1313 if (vmxnet3_logtype_init >= 0) 1314 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1315 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1316 if (vmxnet3_logtype_driver >= 0) 1317 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1318 } 1319