1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define PROCESS_SYS_EVENTS 0 42 43 #define VMXNET3_TX_MAX_SEG UINT8_MAX 44 45 #define VMXNET3_TX_OFFLOAD_CAP \ 46 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 47 DEV_TX_OFFLOAD_TCP_CKSUM | \ 48 DEV_TX_OFFLOAD_UDP_CKSUM | \ 49 DEV_TX_OFFLOAD_TCP_TSO | \ 50 DEV_TX_OFFLOAD_MULTI_SEGS) 51 52 #define VMXNET3_RX_OFFLOAD_CAP \ 53 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 54 DEV_RX_OFFLOAD_VLAN_FILTER | \ 55 DEV_RX_OFFLOAD_SCATTER | \ 56 DEV_RX_OFFLOAD_UDP_CKSUM | \ 57 DEV_RX_OFFLOAD_TCP_CKSUM | \ 58 DEV_RX_OFFLOAD_TCP_LRO | \ 59 DEV_RX_OFFLOAD_JUMBO_FRAME) 60 61 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 62 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 63 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 64 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 65 static void vmxnet3_dev_stop(struct rte_eth_dev *dev); 66 static void vmxnet3_dev_close(struct rte_eth_dev *dev); 67 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 68 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 69 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 70 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 72 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 73 int wait_to_complete); 74 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 75 int wait_to_complete); 76 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 77 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 78 struct rte_eth_stats *stats); 79 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 80 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 81 struct rte_eth_xstat_name *xstats, 82 unsigned int n); 83 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 84 struct rte_eth_xstat *xstats, unsigned int n); 85 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 86 struct rte_eth_dev_info *dev_info); 87 static const uint32_t * 88 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 89 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 90 uint16_t vid, int on); 91 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 92 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 93 struct rte_ether_addr *mac_addr); 94 static void vmxnet3_interrupt_handler(void *param); 95 96 int vmxnet3_logtype_init; 97 int vmxnet3_logtype_driver; 98 99 /* 100 * The set of PCI devices this driver supports 101 */ 102 #define VMWARE_PCI_VENDOR_ID 0x15AD 103 #define VMWARE_DEV_ID_VMXNET3 0x07B0 104 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 105 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 106 { .vendor_id = 0, /* sentinel */ }, 107 }; 108 109 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 110 .dev_configure = vmxnet3_dev_configure, 111 .dev_start = vmxnet3_dev_start, 112 .dev_stop = vmxnet3_dev_stop, 113 .dev_close = vmxnet3_dev_close, 114 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 115 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 116 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 117 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 118 .link_update = vmxnet3_dev_link_update, 119 .stats_get = vmxnet3_dev_stats_get, 120 .xstats_get_names = vmxnet3_dev_xstats_get_names, 121 .xstats_get = vmxnet3_dev_xstats_get, 122 .stats_reset = vmxnet3_dev_stats_reset, 123 .mac_addr_set = vmxnet3_mac_addr_set, 124 .dev_infos_get = vmxnet3_dev_info_get, 125 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 129 .rx_queue_release = vmxnet3_dev_rx_queue_release, 130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 131 .tx_queue_release = vmxnet3_dev_tx_queue_release, 132 }; 133 134 struct vmxnet3_xstats_name_off { 135 char name[RTE_ETH_XSTATS_NAME_SIZE]; 136 unsigned int offset; 137 }; 138 139 /* tx_qX_ is prepended to the name string here */ 140 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 141 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 142 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 143 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 144 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 145 }; 146 147 /* rx_qX_ is prepended to the name string here */ 148 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 149 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 150 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 151 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 152 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 153 }; 154 155 static const struct rte_memzone * 156 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 157 const char *post_string, int socket_id, 158 uint16_t align, bool reuse) 159 { 160 char z_name[RTE_MEMZONE_NAMESIZE]; 161 const struct rte_memzone *mz; 162 163 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 164 dev->data->port_id, post_string); 165 166 mz = rte_memzone_lookup(z_name); 167 if (!reuse) { 168 if (mz) 169 rte_memzone_free(mz); 170 return rte_memzone_reserve_aligned(z_name, size, socket_id, 171 RTE_MEMZONE_IOVA_CONTIG, align); 172 } 173 174 if (mz) 175 return mz; 176 177 return rte_memzone_reserve_aligned(z_name, size, socket_id, 178 RTE_MEMZONE_IOVA_CONTIG, align); 179 } 180 181 /* 182 * This function is based on vmxnet3_disable_intr() 183 */ 184 static void 185 vmxnet3_disable_intr(struct vmxnet3_hw *hw) 186 { 187 int i; 188 189 PMD_INIT_FUNC_TRACE(); 190 191 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 192 for (i = 0; i < hw->num_intrs; i++) 193 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1); 194 } 195 196 static void 197 vmxnet3_enable_intr(struct vmxnet3_hw *hw) 198 { 199 int i; 200 201 PMD_INIT_FUNC_TRACE(); 202 203 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL; 204 for (i = 0; i < hw->num_intrs; i++) 205 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0); 206 } 207 208 /* 209 * Gets tx data ring descriptor size. 210 */ 211 static uint16_t 212 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 213 { 214 uint16 txdata_desc_size; 215 216 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 217 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 218 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 219 220 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 221 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 222 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 223 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 224 } 225 226 /* 227 * It returns 0 on success. 228 */ 229 static int 230 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 231 { 232 struct rte_pci_device *pci_dev; 233 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 234 uint32_t mac_hi, mac_lo, ver; 235 struct rte_eth_link link; 236 237 PMD_INIT_FUNC_TRACE(); 238 239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 243 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 244 245 /* 246 * for secondary processes, we don't initialize any further as primary 247 * has already done this work. 248 */ 249 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 250 return 0; 251 252 rte_eth_copy_pci_info(eth_dev, pci_dev); 253 254 /* Vendor and Device ID need to be set before init of shared code */ 255 hw->device_id = pci_dev->id.device_id; 256 hw->vendor_id = pci_dev->id.vendor_id; 257 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 258 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 259 260 hw->num_rx_queues = 1; 261 hw->num_tx_queues = 1; 262 hw->bufs_per_pkt = 1; 263 264 /* Check h/w version compatibility with driver. */ 265 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 266 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 267 268 if (ver & (1 << VMXNET3_REV_4)) { 269 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 270 1 << VMXNET3_REV_4); 271 hw->version = VMXNET3_REV_4 + 1; 272 } else if (ver & (1 << VMXNET3_REV_3)) { 273 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 274 1 << VMXNET3_REV_3); 275 hw->version = VMXNET3_REV_3 + 1; 276 } else if (ver & (1 << VMXNET3_REV_2)) { 277 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 278 1 << VMXNET3_REV_2); 279 hw->version = VMXNET3_REV_2 + 1; 280 } else if (ver & (1 << VMXNET3_REV_1)) { 281 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 282 1 << VMXNET3_REV_1); 283 hw->version = VMXNET3_REV_1 + 1; 284 } else { 285 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 286 return -EIO; 287 } 288 289 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version); 290 291 /* Check UPT version compatibility with driver. */ 292 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 293 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 294 if (ver & 0x1) 295 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 296 else { 297 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 298 return -EIO; 299 } 300 301 /* Getting MAC Address */ 302 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 303 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 304 memcpy(hw->perm_addr, &mac_lo, 4); 305 memcpy(hw->perm_addr + 4, &mac_hi, 2); 306 307 /* Allocate memory for storing MAC addresses */ 308 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 309 VMXNET3_MAX_MAC_ADDRS, 0); 310 if (eth_dev->data->mac_addrs == NULL) { 311 PMD_INIT_LOG(ERR, 312 "Failed to allocate %d bytes needed to store MAC addresses", 313 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 314 return -ENOMEM; 315 } 316 /* Copy the permanent MAC address */ 317 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 318 ð_dev->data->mac_addrs[0]); 319 320 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 321 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 322 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 323 324 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 325 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 326 327 /* Put device in Quiesce Mode */ 328 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 329 330 /* allow untagged pkts */ 331 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 332 333 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 334 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 335 336 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 337 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 338 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 339 hw->rxdata_desc_size); 340 341 /* clear shadow stats */ 342 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 343 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 344 345 /* clear snapshot stats */ 346 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 347 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 348 349 /* set the initial link status */ 350 memset(&link, 0, sizeof(link)); 351 link.link_duplex = ETH_LINK_FULL_DUPLEX; 352 link.link_speed = ETH_SPEED_NUM_10G; 353 link.link_autoneg = ETH_LINK_FIXED; 354 rte_eth_linkstatus_set(eth_dev, &link); 355 356 return 0; 357 } 358 359 static int 360 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 361 { 362 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 363 364 PMD_INIT_FUNC_TRACE(); 365 366 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 367 return 0; 368 369 if (hw->adapter_stopped == 0) { 370 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 371 return -EBUSY; 372 } 373 374 eth_dev->dev_ops = NULL; 375 eth_dev->rx_pkt_burst = NULL; 376 eth_dev->tx_pkt_burst = NULL; 377 eth_dev->tx_pkt_prepare = NULL; 378 379 return 0; 380 } 381 382 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 383 struct rte_pci_device *pci_dev) 384 { 385 return rte_eth_dev_pci_generic_probe(pci_dev, 386 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 387 } 388 389 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 390 { 391 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 392 } 393 394 static struct rte_pci_driver rte_vmxnet3_pmd = { 395 .id_table = pci_id_vmxnet3_map, 396 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 397 .probe = eth_vmxnet3_pci_probe, 398 .remove = eth_vmxnet3_pci_remove, 399 }; 400 401 static int 402 vmxnet3_dev_configure(struct rte_eth_dev *dev) 403 { 404 const struct rte_memzone *mz; 405 struct vmxnet3_hw *hw = dev->data->dev_private; 406 size_t size; 407 408 PMD_INIT_FUNC_TRACE(); 409 410 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 411 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 412 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 413 return -EINVAL; 414 } 415 416 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 417 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 418 return -EINVAL; 419 } 420 421 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 422 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 423 424 if (size > UINT16_MAX) 425 return -EINVAL; 426 427 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 428 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 429 430 /* 431 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 432 * on current socket 433 */ 434 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 435 "shared", rte_socket_id(), 8, 1); 436 437 if (mz == NULL) { 438 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 439 return -ENOMEM; 440 } 441 memset(mz->addr, 0, mz->len); 442 443 hw->shared = mz->addr; 444 hw->sharedPA = mz->iova; 445 446 /* 447 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 448 * on current socket. 449 * 450 * We cannot reuse this memzone from previous allocation as its size 451 * depends on the number of tx and rx queues, which could be different 452 * from one config to another. 453 */ 454 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 455 VMXNET3_QUEUE_DESC_ALIGN, 0); 456 if (mz == NULL) { 457 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 458 return -ENOMEM; 459 } 460 memset(mz->addr, 0, mz->len); 461 462 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 463 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 464 465 hw->queueDescPA = mz->iova; 466 hw->queue_desc_len = (uint16_t)size; 467 468 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 469 /* Allocate memory structure for UPT1_RSSConf and configure */ 470 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 471 "rss_conf", rte_socket_id(), 472 RTE_CACHE_LINE_SIZE, 1); 473 if (mz == NULL) { 474 PMD_INIT_LOG(ERR, 475 "ERROR: Creating rss_conf structure zone"); 476 return -ENOMEM; 477 } 478 memset(mz->addr, 0, mz->len); 479 480 hw->rss_conf = mz->addr; 481 hw->rss_confPA = mz->iova; 482 } 483 484 return 0; 485 } 486 487 static void 488 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 489 { 490 uint32_t val; 491 492 PMD_INIT_LOG(DEBUG, 493 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", 494 addr[0], addr[1], addr[2], 495 addr[3], addr[4], addr[5]); 496 497 memcpy(&val, addr, 4); 498 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 499 500 memcpy(&val, addr + 4, 2); 501 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 502 } 503 504 static int 505 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 506 { 507 struct vmxnet3_hw *hw = dev->data->dev_private; 508 Vmxnet3_DriverShared *shared = hw->shared; 509 Vmxnet3_CmdInfo *cmdInfo; 510 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 511 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 512 uint32_t num, i, j, size; 513 514 if (hw->memRegsPA == 0) { 515 const struct rte_memzone *mz; 516 517 size = sizeof(Vmxnet3_MemRegs) + 518 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 519 sizeof(Vmxnet3_MemoryRegion); 520 521 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 522 1); 523 if (mz == NULL) { 524 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 525 return -ENOMEM; 526 } 527 memset(mz->addr, 0, mz->len); 528 hw->memRegs = mz->addr; 529 hw->memRegsPA = mz->iova; 530 } 531 532 num = hw->num_rx_queues; 533 534 for (i = 0; i < num; i++) { 535 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 536 537 mp[i] = rxq->mp; 538 index[i] = 1 << i; 539 } 540 541 /* 542 * The same mempool could be used by multiple queues. In such a case, 543 * remove duplicate mempool entries. Only one entry is kept with 544 * bitmask indicating queues that are using this mempool. 545 */ 546 for (i = 1; i < num; i++) { 547 for (j = 0; j < i; j++) { 548 if (mp[i] == mp[j]) { 549 mp[i] = NULL; 550 index[j] |= 1 << i; 551 break; 552 } 553 } 554 } 555 556 j = 0; 557 for (i = 0; i < num; i++) { 558 if (mp[i] == NULL) 559 continue; 560 561 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 562 563 mr->startPA = 564 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 565 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 566 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 567 mr->txQueueBits = index[i]; 568 mr->rxQueueBits = index[i]; 569 570 PMD_INIT_LOG(INFO, 571 "index: %u startPA: %" PRIu64 " length: %u, " 572 "rxBits: %x", 573 j, mr->startPA, mr->length, mr->rxQueueBits); 574 j++; 575 } 576 hw->memRegs->numRegs = j; 577 PMD_INIT_LOG(INFO, "numRegs: %u", j); 578 579 size = sizeof(Vmxnet3_MemRegs) + 580 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 581 582 cmdInfo = &shared->cu.cmdInfo; 583 cmdInfo->varConf.confVer = 1; 584 cmdInfo->varConf.confLen = size; 585 cmdInfo->varConf.confPA = hw->memRegsPA; 586 587 return 0; 588 } 589 590 static int 591 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 592 { 593 struct rte_eth_conf port_conf = dev->data->dev_conf; 594 struct vmxnet3_hw *hw = dev->data->dev_private; 595 uint32_t mtu = dev->data->mtu; 596 Vmxnet3_DriverShared *shared = hw->shared; 597 Vmxnet3_DSDevRead *devRead = &shared->devRead; 598 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 599 uint32_t i; 600 int ret; 601 602 hw->mtu = mtu; 603 604 shared->magic = VMXNET3_REV1_MAGIC; 605 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 606 607 /* Setting up Guest OS information */ 608 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 609 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 610 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 611 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 612 devRead->misc.driverInfo.uptVerSpt = 1; 613 614 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 615 devRead->misc.queueDescPA = hw->queueDescPA; 616 devRead->misc.queueDescLen = hw->queue_desc_len; 617 devRead->misc.numTxQueues = hw->num_tx_queues; 618 devRead->misc.numRxQueues = hw->num_rx_queues; 619 620 /* 621 * Set number of interrupts to 1 622 * PMD by default disables all the interrupts but this is MUST 623 * to activate device. It needs at least one interrupt for 624 * link events to handle 625 */ 626 hw->num_intrs = devRead->intrConf.numIntrs = 1; 627 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL; 628 629 for (i = 0; i < hw->num_tx_queues; i++) { 630 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 631 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 632 633 txq->shared = &hw->tqd_start[i]; 634 635 tqd->ctrl.txNumDeferred = 0; 636 tqd->ctrl.txThreshold = 1; 637 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 638 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 639 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 640 641 tqd->conf.txRingSize = txq->cmd_ring.size; 642 tqd->conf.compRingSize = txq->comp_ring.size; 643 tqd->conf.dataRingSize = txq->data_ring.size; 644 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 645 tqd->conf.intrIdx = txq->comp_ring.intr_idx; 646 tqd->status.stopped = TRUE; 647 tqd->status.error = 0; 648 memset(&tqd->stats, 0, sizeof(tqd->stats)); 649 } 650 651 for (i = 0; i < hw->num_rx_queues; i++) { 652 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 653 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 654 655 rxq->shared = &hw->rqd_start[i]; 656 657 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 658 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 659 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 660 661 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 662 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 663 rqd->conf.compRingSize = rxq->comp_ring.size; 664 rqd->conf.intrIdx = rxq->comp_ring.intr_idx; 665 if (VMXNET3_VERSION_GE_3(hw)) { 666 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA; 667 rqd->conf.rxDataRingDescSize = rxq->data_desc_size; 668 } 669 rqd->status.stopped = TRUE; 670 rqd->status.error = 0; 671 memset(&rqd->stats, 0, sizeof(rqd->stats)); 672 } 673 674 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 675 devRead->rxFilterConf.rxMode = 0; 676 677 /* Setting up feature flags */ 678 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 679 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 680 681 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 682 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 683 devRead->misc.maxNumRxSG = 0; 684 } 685 686 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 687 ret = vmxnet3_rss_configure(dev); 688 if (ret != VMXNET3_SUCCESS) 689 return ret; 690 691 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 692 devRead->rssConfDesc.confVer = 1; 693 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 694 devRead->rssConfDesc.confPA = hw->rss_confPA; 695 } 696 697 ret = vmxnet3_dev_vlan_offload_set(dev, 698 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 699 if (ret) 700 return ret; 701 702 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 703 704 return VMXNET3_SUCCESS; 705 } 706 707 /* 708 * Configure device link speed and setup link. 709 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 710 * It returns 0 on success. 711 */ 712 static int 713 vmxnet3_dev_start(struct rte_eth_dev *dev) 714 { 715 int ret; 716 struct vmxnet3_hw *hw = dev->data->dev_private; 717 718 PMD_INIT_FUNC_TRACE(); 719 720 /* Save stats before it is reset by CMD_ACTIVATE */ 721 vmxnet3_hw_stats_save(hw); 722 723 ret = vmxnet3_setup_driver_shared(dev); 724 if (ret != VMXNET3_SUCCESS) 725 return ret; 726 727 /* check if lsc interrupt feature is enabled */ 728 if (dev->data->dev_conf.intr_conf.lsc) { 729 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 730 731 /* Setup interrupt callback */ 732 rte_intr_callback_register(&pci_dev->intr_handle, 733 vmxnet3_interrupt_handler, dev); 734 735 if (rte_intr_enable(&pci_dev->intr_handle) < 0) { 736 PMD_INIT_LOG(ERR, "interrupt enable failed"); 737 return -EIO; 738 } 739 } 740 741 /* Exchange shared data with device */ 742 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 743 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 744 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 745 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 746 747 /* Activate device by register write */ 748 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 749 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 750 751 if (ret != 0) { 752 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 753 return -EINVAL; 754 } 755 756 /* Setup memory region for rx buffers */ 757 ret = vmxnet3_dev_setup_memreg(dev); 758 if (ret == 0) { 759 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 760 VMXNET3_CMD_REGISTER_MEMREGS); 761 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 762 if (ret != 0) 763 PMD_INIT_LOG(DEBUG, 764 "Failed in setup memory region cmd\n"); 765 ret = 0; 766 } else { 767 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 768 } 769 770 if (VMXNET3_VERSION_GE_4(hw)) { 771 /* Check for additional RSS */ 772 ret = vmxnet3_v4_rss_configure(dev); 773 if (ret != VMXNET3_SUCCESS) { 774 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 775 return ret; 776 } 777 } 778 779 /* Disable interrupts */ 780 vmxnet3_disable_intr(hw); 781 782 /* 783 * Load RX queues with blank mbufs and update next2fill index for device 784 * Update RxMode of the device 785 */ 786 ret = vmxnet3_dev_rxtx_init(dev); 787 if (ret != VMXNET3_SUCCESS) { 788 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 789 return ret; 790 } 791 792 hw->adapter_stopped = FALSE; 793 794 /* Setting proper Rx Mode and issue Rx Mode Update command */ 795 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 796 797 if (dev->data->dev_conf.intr_conf.lsc) { 798 vmxnet3_enable_intr(hw); 799 800 /* 801 * Update link state from device since this won't be 802 * done upon starting with lsc in use. This is done 803 * only after enabling interrupts to avoid any race 804 * where the link state could change without an 805 * interrupt being fired. 806 */ 807 __vmxnet3_dev_link_update(dev, 0); 808 } 809 810 return VMXNET3_SUCCESS; 811 } 812 813 /* 814 * Stop device: disable rx and tx functions to allow for reconfiguring. 815 */ 816 static void 817 vmxnet3_dev_stop(struct rte_eth_dev *dev) 818 { 819 struct rte_eth_link link; 820 struct vmxnet3_hw *hw = dev->data->dev_private; 821 822 PMD_INIT_FUNC_TRACE(); 823 824 if (hw->adapter_stopped == 1) { 825 PMD_INIT_LOG(DEBUG, "Device already stopped."); 826 return; 827 } 828 829 /* disable interrupts */ 830 vmxnet3_disable_intr(hw); 831 832 if (dev->data->dev_conf.intr_conf.lsc) { 833 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 834 835 rte_intr_disable(&pci_dev->intr_handle); 836 837 rte_intr_callback_unregister(&pci_dev->intr_handle, 838 vmxnet3_interrupt_handler, dev); 839 } 840 841 /* quiesce the device first */ 842 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 843 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 844 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 845 846 /* reset the device */ 847 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 848 PMD_INIT_LOG(DEBUG, "Device reset."); 849 850 vmxnet3_dev_clear_queues(dev); 851 852 /* Clear recorded link status */ 853 memset(&link, 0, sizeof(link)); 854 link.link_duplex = ETH_LINK_FULL_DUPLEX; 855 link.link_speed = ETH_SPEED_NUM_10G; 856 link.link_autoneg = ETH_LINK_FIXED; 857 rte_eth_linkstatus_set(dev, &link); 858 859 hw->adapter_stopped = 1; 860 } 861 862 static void 863 vmxnet3_free_queues(struct rte_eth_dev *dev) 864 { 865 int i; 866 867 PMD_INIT_FUNC_TRACE(); 868 869 for (i = 0; i < dev->data->nb_rx_queues; i++) { 870 void *rxq = dev->data->rx_queues[i]; 871 872 vmxnet3_dev_rx_queue_release(rxq); 873 } 874 dev->data->nb_rx_queues = 0; 875 876 for (i = 0; i < dev->data->nb_tx_queues; i++) { 877 void *txq = dev->data->tx_queues[i]; 878 879 vmxnet3_dev_tx_queue_release(txq); 880 } 881 dev->data->nb_tx_queues = 0; 882 } 883 884 /* 885 * Reset and stop device. 886 */ 887 static void 888 vmxnet3_dev_close(struct rte_eth_dev *dev) 889 { 890 PMD_INIT_FUNC_TRACE(); 891 892 vmxnet3_dev_stop(dev); 893 vmxnet3_free_queues(dev); 894 } 895 896 static void 897 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 898 struct UPT1_TxStats *res) 899 { 900 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 901 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 902 (h)->saved_tx_stats[(i)].f) 903 904 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 905 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 906 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 907 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 908 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 909 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 910 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 911 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 912 913 #undef VMXNET3_UPDATE_TX_STAT 914 } 915 916 static void 917 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 918 struct UPT1_RxStats *res) 919 { 920 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 921 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 922 (h)->saved_rx_stats[(i)].f) 923 924 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 925 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 926 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 927 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 928 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 929 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 930 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 931 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 932 933 #undef VMXNET3_UPDATE_RX_STAT 934 } 935 936 static void 937 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 938 struct UPT1_TxStats *res) 939 { 940 vmxnet3_hw_tx_stats_get(hw, q, res); 941 942 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 943 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 944 945 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 946 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 947 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 948 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 949 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 950 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 951 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 953 954 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 955 } 956 957 static void 958 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 959 struct UPT1_RxStats *res) 960 { 961 vmxnet3_hw_rx_stats_get(hw, q, res); 962 963 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 964 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 965 966 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 967 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 968 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 969 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 970 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 971 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 972 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 974 975 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 976 } 977 978 static void 979 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 980 { 981 unsigned int i; 982 983 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 984 985 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 986 987 for (i = 0; i < hw->num_tx_queues; i++) 988 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 989 for (i = 0; i < hw->num_rx_queues; i++) 990 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 991 } 992 993 static int 994 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 995 struct rte_eth_xstat_name *xstats_names, 996 unsigned int n) 997 { 998 unsigned int i, t, count = 0; 999 unsigned int nstats = 1000 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1001 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1002 1003 if (!xstats_names || n < nstats) 1004 return nstats; 1005 1006 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1007 if (!dev->data->rx_queues[i]) 1008 continue; 1009 1010 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1011 snprintf(xstats_names[count].name, 1012 sizeof(xstats_names[count].name), 1013 "rx_q%u_%s", i, 1014 vmxnet3_rxq_stat_strings[t].name); 1015 count++; 1016 } 1017 } 1018 1019 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1020 if (!dev->data->tx_queues[i]) 1021 continue; 1022 1023 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1024 snprintf(xstats_names[count].name, 1025 sizeof(xstats_names[count].name), 1026 "tx_q%u_%s", i, 1027 vmxnet3_txq_stat_strings[t].name); 1028 count++; 1029 } 1030 } 1031 1032 return count; 1033 } 1034 1035 static int 1036 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1037 unsigned int n) 1038 { 1039 unsigned int i, t, count = 0; 1040 unsigned int nstats = 1041 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1042 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1043 1044 if (n < nstats) 1045 return nstats; 1046 1047 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1048 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1049 1050 if (rxq == NULL) 1051 continue; 1052 1053 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1054 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1055 vmxnet3_rxq_stat_strings[t].offset); 1056 xstats[count].id = count; 1057 count++; 1058 } 1059 } 1060 1061 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1062 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1063 1064 if (txq == NULL) 1065 continue; 1066 1067 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1068 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1069 vmxnet3_txq_stat_strings[t].offset); 1070 xstats[count].id = count; 1071 count++; 1072 } 1073 } 1074 1075 return count; 1076 } 1077 1078 static int 1079 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1080 { 1081 unsigned int i; 1082 struct vmxnet3_hw *hw = dev->data->dev_private; 1083 struct UPT1_TxStats txStats; 1084 struct UPT1_RxStats rxStats; 1085 1086 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1087 1088 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1089 for (i = 0; i < hw->num_tx_queues; i++) { 1090 vmxnet3_tx_stats_get(hw, i, &txStats); 1091 1092 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1093 txStats.mcastPktsTxOK + 1094 txStats.bcastPktsTxOK; 1095 1096 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1097 txStats.mcastBytesTxOK + 1098 txStats.bcastBytesTxOK; 1099 1100 stats->opackets += stats->q_opackets[i]; 1101 stats->obytes += stats->q_obytes[i]; 1102 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1103 } 1104 1105 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1106 for (i = 0; i < hw->num_rx_queues; i++) { 1107 vmxnet3_rx_stats_get(hw, i, &rxStats); 1108 1109 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1110 rxStats.mcastPktsRxOK + 1111 rxStats.bcastPktsRxOK; 1112 1113 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1114 rxStats.mcastBytesRxOK + 1115 rxStats.bcastBytesRxOK; 1116 1117 stats->ipackets += stats->q_ipackets[i]; 1118 stats->ibytes += stats->q_ibytes[i]; 1119 1120 stats->q_errors[i] = rxStats.pktsRxError; 1121 stats->ierrors += rxStats.pktsRxError; 1122 stats->imissed += rxStats.pktsRxOutOfBuf; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int 1129 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1130 { 1131 unsigned int i; 1132 struct vmxnet3_hw *hw = dev->data->dev_private; 1133 struct UPT1_TxStats txStats = {0}; 1134 struct UPT1_RxStats rxStats = {0}; 1135 1136 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1137 1138 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1139 1140 for (i = 0; i < hw->num_tx_queues; i++) { 1141 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1142 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1143 sizeof(hw->snapshot_tx_stats[0])); 1144 } 1145 for (i = 0; i < hw->num_rx_queues; i++) { 1146 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1147 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1148 sizeof(hw->snapshot_rx_stats[0])); 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int 1155 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1156 struct rte_eth_dev_info *dev_info) 1157 { 1158 struct vmxnet3_hw *hw = dev->data->dev_private; 1159 1160 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1161 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1162 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1163 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1164 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1165 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1166 1167 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1168 1169 if (VMXNET3_VERSION_GE_4(hw)) { 1170 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1171 } 1172 1173 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1174 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1175 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1176 .nb_align = 1, 1177 }; 1178 1179 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1180 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1181 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1182 .nb_align = 1, 1183 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1184 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1185 }; 1186 1187 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1188 dev_info->rx_queue_offload_capa = 0; 1189 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1190 dev_info->tx_queue_offload_capa = 0; 1191 1192 return 0; 1193 } 1194 1195 static const uint32_t * 1196 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1197 { 1198 static const uint32_t ptypes[] = { 1199 RTE_PTYPE_L3_IPV4_EXT, 1200 RTE_PTYPE_L3_IPV4, 1201 RTE_PTYPE_UNKNOWN 1202 }; 1203 1204 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1205 return ptypes; 1206 return NULL; 1207 } 1208 1209 static int 1210 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1211 { 1212 struct vmxnet3_hw *hw = dev->data->dev_private; 1213 1214 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1215 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1216 return 0; 1217 } 1218 1219 /* return 0 means link status changed, -1 means not changed */ 1220 static int 1221 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1222 __rte_unused int wait_to_complete) 1223 { 1224 struct vmxnet3_hw *hw = dev->data->dev_private; 1225 struct rte_eth_link link; 1226 uint32_t ret; 1227 1228 memset(&link, 0, sizeof(link)); 1229 1230 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1231 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1232 1233 if (ret & 0x1) 1234 link.link_status = ETH_LINK_UP; 1235 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1236 link.link_speed = ETH_SPEED_NUM_10G; 1237 link.link_autoneg = ETH_LINK_FIXED; 1238 1239 return rte_eth_linkstatus_set(dev, &link); 1240 } 1241 1242 static int 1243 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1244 { 1245 /* Link status doesn't change for stopped dev */ 1246 if (dev->data->dev_started == 0) 1247 return -1; 1248 1249 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1250 } 1251 1252 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1253 static void 1254 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1255 { 1256 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1257 1258 if (set) 1259 rxConf->rxMode = rxConf->rxMode | feature; 1260 else 1261 rxConf->rxMode = rxConf->rxMode & (~feature); 1262 1263 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1264 } 1265 1266 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1267 static int 1268 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1269 { 1270 struct vmxnet3_hw *hw = dev->data->dev_private; 1271 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1272 1273 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1274 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1275 1276 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1277 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1278 1279 return 0; 1280 } 1281 1282 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1283 static int 1284 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1285 { 1286 struct vmxnet3_hw *hw = dev->data->dev_private; 1287 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1288 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1289 1290 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1291 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1292 else 1293 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1294 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1295 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1296 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1297 1298 return 0; 1299 } 1300 1301 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1302 static int 1303 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1304 { 1305 struct vmxnet3_hw *hw = dev->data->dev_private; 1306 1307 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1308 1309 return 0; 1310 } 1311 1312 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1313 static int 1314 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1315 { 1316 struct vmxnet3_hw *hw = dev->data->dev_private; 1317 1318 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1319 1320 return 0; 1321 } 1322 1323 /* Enable/disable filter on vlan */ 1324 static int 1325 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1326 { 1327 struct vmxnet3_hw *hw = dev->data->dev_private; 1328 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1329 uint32_t *vf_table = rxConf->vfTable; 1330 1331 /* save state for restore */ 1332 if (on) 1333 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1334 else 1335 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1336 1337 /* don't change active filter if in promiscuous mode */ 1338 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1339 return 0; 1340 1341 /* set in hardware */ 1342 if (on) 1343 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1344 else 1345 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1346 1347 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1348 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1349 return 0; 1350 } 1351 1352 static int 1353 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1354 { 1355 struct vmxnet3_hw *hw = dev->data->dev_private; 1356 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1357 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1358 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1359 1360 if (mask & ETH_VLAN_STRIP_MASK) { 1361 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1362 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1363 else 1364 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1365 1366 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1367 VMXNET3_CMD_UPDATE_FEATURE); 1368 } 1369 1370 if (mask & ETH_VLAN_FILTER_MASK) { 1371 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1372 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1373 else 1374 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1375 1376 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1377 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1378 } 1379 1380 return 0; 1381 } 1382 1383 static void 1384 vmxnet3_process_events(struct rte_eth_dev *dev) 1385 { 1386 struct vmxnet3_hw *hw = dev->data->dev_private; 1387 uint32_t events = hw->shared->ecr; 1388 1389 if (!events) 1390 return; 1391 1392 /* 1393 * ECR bits when written with 1b are cleared. Hence write 1394 * events back to ECR so that the bits which were set will be reset. 1395 */ 1396 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1397 1398 /* Check if link state has changed */ 1399 if (events & VMXNET3_ECR_LINK) { 1400 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1401 if (vmxnet3_dev_link_update(dev, 0) == 0) 1402 _rte_eth_dev_callback_process(dev, 1403 RTE_ETH_EVENT_INTR_LSC, 1404 NULL); 1405 } 1406 1407 /* Check if there is an error on xmit/recv queues */ 1408 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1409 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1410 VMXNET3_CMD_GET_QUEUE_STATUS); 1411 1412 if (hw->tqd_start->status.stopped) 1413 PMD_DRV_LOG(ERR, "tq error 0x%x", 1414 hw->tqd_start->status.error); 1415 1416 if (hw->rqd_start->status.stopped) 1417 PMD_DRV_LOG(ERR, "rq error 0x%x", 1418 hw->rqd_start->status.error); 1419 1420 /* Reset the device */ 1421 /* Have to reset the device */ 1422 } 1423 1424 if (events & VMXNET3_ECR_DIC) 1425 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1426 1427 if (events & VMXNET3_ECR_DEBUG) 1428 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1429 } 1430 1431 static void 1432 vmxnet3_interrupt_handler(void *param) 1433 { 1434 struct rte_eth_dev *dev = param; 1435 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); 1436 1437 vmxnet3_process_events(dev); 1438 1439 if (rte_intr_ack(&pci_dev->intr_handle) < 0) 1440 PMD_DRV_LOG(ERR, "interrupt enable failed"); 1441 } 1442 1443 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1444 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1445 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1446 1447 RTE_INIT(vmxnet3_init_log) 1448 { 1449 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init"); 1450 if (vmxnet3_logtype_init >= 0) 1451 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE); 1452 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver"); 1453 if (vmxnet3_logtype_driver >= 0) 1454 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE); 1455 } 1456