1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <fcntl.h> 13 #include <inttypes.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_memzone.h> 26 #include <rte_eal.h> 27 #include <rte_alarm.h> 28 #include <rte_ether.h> 29 #include <ethdev_driver.h> 30 #include <ethdev_pci.h> 31 #include <rte_string_fns.h> 32 #include <rte_malloc.h> 33 #include <rte_dev.h> 34 35 #include "base/vmxnet3_defs.h" 36 37 #include "vmxnet3_ring.h" 38 #include "vmxnet3_logs.h" 39 #include "vmxnet3_ethdev.h" 40 41 #define VMXNET3_TX_MAX_SEG UINT8_MAX 42 43 #define VMXNET3_TX_OFFLOAD_CAP \ 44 (DEV_TX_OFFLOAD_VLAN_INSERT | \ 45 DEV_TX_OFFLOAD_TCP_CKSUM | \ 46 DEV_TX_OFFLOAD_UDP_CKSUM | \ 47 DEV_TX_OFFLOAD_TCP_TSO | \ 48 DEV_TX_OFFLOAD_MULTI_SEGS) 49 50 #define VMXNET3_RX_OFFLOAD_CAP \ 51 (DEV_RX_OFFLOAD_VLAN_STRIP | \ 52 DEV_RX_OFFLOAD_VLAN_FILTER | \ 53 DEV_RX_OFFLOAD_SCATTER | \ 54 DEV_RX_OFFLOAD_UDP_CKSUM | \ 55 DEV_RX_OFFLOAD_TCP_CKSUM | \ 56 DEV_RX_OFFLOAD_TCP_LRO | \ 57 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 58 DEV_RX_OFFLOAD_RSS_HASH) 59 60 int vmxnet3_segs_dynfield_offset = -1; 61 62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev); 63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev); 64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev); 65 static int vmxnet3_dev_start(struct rte_eth_dev *dev); 66 static int vmxnet3_dev_stop(struct rte_eth_dev *dev); 67 static int vmxnet3_dev_close(struct rte_eth_dev *dev); 68 static int vmxnet3_dev_reset(struct rte_eth_dev *dev); 69 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set); 70 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev); 71 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev); 72 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev); 73 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev); 74 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 75 int wait_to_complete); 76 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev, 77 int wait_to_complete); 78 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw); 79 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev, 80 struct rte_eth_stats *stats); 81 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev); 82 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 83 struct rte_eth_xstat_name *xstats, 84 unsigned int n); 85 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, 86 struct rte_eth_xstat *xstats, unsigned int n); 87 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev, 88 struct rte_eth_dev_info *dev_info); 89 static const uint32_t * 90 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev); 91 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 92 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, 93 uint16_t vid, int on); 94 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 95 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev, 96 struct rte_ether_addr *mac_addr); 97 static void vmxnet3_process_events(struct rte_eth_dev *dev); 98 static void vmxnet3_interrupt_handler(void *param); 99 static int vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 100 uint16_t queue_id); 101 static int vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 102 uint16_t queue_id); 103 104 /* 105 * The set of PCI devices this driver supports 106 */ 107 #define VMWARE_PCI_VENDOR_ID 0x15AD 108 #define VMWARE_DEV_ID_VMXNET3 0x07B0 109 static const struct rte_pci_id pci_id_vmxnet3_map[] = { 110 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) }, 111 { .vendor_id = 0, /* sentinel */ }, 112 }; 113 114 static const struct eth_dev_ops vmxnet3_eth_dev_ops = { 115 .dev_configure = vmxnet3_dev_configure, 116 .dev_start = vmxnet3_dev_start, 117 .dev_stop = vmxnet3_dev_stop, 118 .dev_close = vmxnet3_dev_close, 119 .dev_reset = vmxnet3_dev_reset, 120 .promiscuous_enable = vmxnet3_dev_promiscuous_enable, 121 .promiscuous_disable = vmxnet3_dev_promiscuous_disable, 122 .allmulticast_enable = vmxnet3_dev_allmulticast_enable, 123 .allmulticast_disable = vmxnet3_dev_allmulticast_disable, 124 .link_update = vmxnet3_dev_link_update, 125 .stats_get = vmxnet3_dev_stats_get, 126 .xstats_get_names = vmxnet3_dev_xstats_get_names, 127 .xstats_get = vmxnet3_dev_xstats_get, 128 .stats_reset = vmxnet3_dev_stats_reset, 129 .mac_addr_set = vmxnet3_mac_addr_set, 130 .dev_infos_get = vmxnet3_dev_info_get, 131 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get, 132 .mtu_set = vmxnet3_dev_mtu_set, 133 .vlan_filter_set = vmxnet3_dev_vlan_filter_set, 134 .vlan_offload_set = vmxnet3_dev_vlan_offload_set, 135 .rx_queue_setup = vmxnet3_dev_rx_queue_setup, 136 .rx_queue_release = vmxnet3_dev_rx_queue_release, 137 .tx_queue_setup = vmxnet3_dev_tx_queue_setup, 138 .tx_queue_release = vmxnet3_dev_tx_queue_release, 139 .rx_queue_intr_enable = vmxnet3_dev_rx_queue_intr_enable, 140 .rx_queue_intr_disable = vmxnet3_dev_rx_queue_intr_disable, 141 }; 142 143 struct vmxnet3_xstats_name_off { 144 char name[RTE_ETH_XSTATS_NAME_SIZE]; 145 unsigned int offset; 146 }; 147 148 /* tx_qX_ is prepended to the name string here */ 149 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = { 150 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)}, 151 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)}, 152 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)}, 153 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)}, 154 }; 155 156 /* rx_qX_ is prepended to the name string here */ 157 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = { 158 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)}, 159 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)}, 160 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)}, 161 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)}, 162 }; 163 164 static const struct rte_memzone * 165 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size, 166 const char *post_string, int socket_id, 167 uint16_t align, bool reuse) 168 { 169 char z_name[RTE_MEMZONE_NAMESIZE]; 170 const struct rte_memzone *mz; 171 172 snprintf(z_name, sizeof(z_name), "eth_p%d_%s", 173 dev->data->port_id, post_string); 174 175 mz = rte_memzone_lookup(z_name); 176 if (!reuse) { 177 if (mz) 178 rte_memzone_free(mz); 179 return rte_memzone_reserve_aligned(z_name, size, socket_id, 180 RTE_MEMZONE_IOVA_CONTIG, align); 181 } 182 183 if (mz) 184 return mz; 185 186 return rte_memzone_reserve_aligned(z_name, size, socket_id, 187 RTE_MEMZONE_IOVA_CONTIG, align); 188 } 189 190 /* 191 * Enable the given interrupt 192 */ 193 static void 194 vmxnet3_enable_intr(struct vmxnet3_hw *hw, unsigned int intr_idx) 195 { 196 PMD_INIT_FUNC_TRACE(); 197 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + intr_idx * 8, 0); 198 } 199 200 /* 201 * Disable the given interrupt 202 */ 203 static void 204 vmxnet3_disable_intr(struct vmxnet3_hw *hw, unsigned int intr_idx) 205 { 206 PMD_INIT_FUNC_TRACE(); 207 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + intr_idx * 8, 1); 208 } 209 210 /* 211 * Enable all intrs used by the device 212 */ 213 static void 214 vmxnet3_enable_all_intrs(struct vmxnet3_hw *hw) 215 { 216 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 217 218 PMD_INIT_FUNC_TRACE(); 219 220 devRead->intrConf.intrCtrl &= rte_cpu_to_le_32(~VMXNET3_IC_DISABLE_ALL); 221 222 if (hw->intr.lsc_only) { 223 vmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx); 224 } else { 225 int i; 226 227 for (i = 0; i < hw->intr.num_intrs; i++) 228 vmxnet3_enable_intr(hw, i); 229 } 230 } 231 232 /* 233 * Disable all intrs used by the device 234 */ 235 static void 236 vmxnet3_disable_all_intrs(struct vmxnet3_hw *hw) 237 { 238 int i; 239 240 PMD_INIT_FUNC_TRACE(); 241 242 hw->shared->devRead.intrConf.intrCtrl |= 243 rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL); 244 for (i = 0; i < hw->num_intrs; i++) 245 vmxnet3_disable_intr(hw, i); 246 } 247 248 /* 249 * Gets tx data ring descriptor size. 250 */ 251 static uint16_t 252 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) 253 { 254 uint16 txdata_desc_size; 255 256 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 257 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 258 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 259 260 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE || 261 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE || 262 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ? 263 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; 264 } 265 266 /* 267 * It returns 0 on success. 268 */ 269 static int 270 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) 271 { 272 struct rte_pci_device *pci_dev; 273 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 274 uint32_t mac_hi, mac_lo, ver; 275 struct rte_eth_link link; 276 static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = { 277 .name = VMXNET3_SEGS_DYNFIELD_NAME, 278 .size = sizeof(vmxnet3_segs_dynfield_t), 279 .align = __alignof__(vmxnet3_segs_dynfield_t), 280 }; 281 282 PMD_INIT_FUNC_TRACE(); 283 284 eth_dev->dev_ops = &vmxnet3_eth_dev_ops; 285 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts; 286 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts; 287 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts; 288 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 289 290 /* extra mbuf field is required to guess MSS */ 291 vmxnet3_segs_dynfield_offset = 292 rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc); 293 if (vmxnet3_segs_dynfield_offset < 0) { 294 PMD_INIT_LOG(ERR, "Cannot register mbuf field."); 295 return -rte_errno; 296 } 297 298 /* 299 * for secondary processes, we don't initialize any further as primary 300 * has already done this work. 301 */ 302 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 303 return 0; 304 305 rte_eth_copy_pci_info(eth_dev, pci_dev); 306 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 307 308 /* Vendor and Device ID need to be set before init of shared code */ 309 hw->device_id = pci_dev->id.device_id; 310 hw->vendor_id = pci_dev->id.vendor_id; 311 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr; 312 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr; 313 314 hw->num_rx_queues = 1; 315 hw->num_tx_queues = 1; 316 hw->bufs_per_pkt = 1; 317 318 /* Check h/w version compatibility with driver. */ 319 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); 320 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver); 321 322 if (ver & (1 << VMXNET3_REV_4)) { 323 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 324 1 << VMXNET3_REV_4); 325 hw->version = VMXNET3_REV_4 + 1; 326 } else if (ver & (1 << VMXNET3_REV_3)) { 327 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 328 1 << VMXNET3_REV_3); 329 hw->version = VMXNET3_REV_3 + 1; 330 } else if (ver & (1 << VMXNET3_REV_2)) { 331 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 332 1 << VMXNET3_REV_2); 333 hw->version = VMXNET3_REV_2 + 1; 334 } else if (ver & (1 << VMXNET3_REV_1)) { 335 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 336 1 << VMXNET3_REV_1); 337 hw->version = VMXNET3_REV_1 + 1; 338 } else { 339 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver); 340 return -EIO; 341 } 342 343 PMD_INIT_LOG(INFO, "Using device v%d", hw->version); 344 345 /* Check UPT version compatibility with driver. */ 346 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS); 347 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver); 348 if (ver & 0x1) 349 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1); 350 else { 351 PMD_INIT_LOG(ERR, "Incompatible UPT version."); 352 return -EIO; 353 } 354 355 /* Getting MAC Address */ 356 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); 357 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); 358 memcpy(hw->perm_addr, &mac_lo, 4); 359 memcpy(hw->perm_addr + 4, &mac_hi, 2); 360 361 /* Allocate memory for storing MAC addresses */ 362 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN * 363 VMXNET3_MAX_MAC_ADDRS, 0); 364 if (eth_dev->data->mac_addrs == NULL) { 365 PMD_INIT_LOG(ERR, 366 "Failed to allocate %d bytes needed to store MAC addresses", 367 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS); 368 return -ENOMEM; 369 } 370 /* Copy the permanent MAC address */ 371 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr, 372 ð_dev->data->mac_addrs[0]); 373 374 PMD_INIT_LOG(DEBUG, "MAC Address : " RTE_ETHER_ADDR_PRT_FMT, 375 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2], 376 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]); 377 378 /* Put device in Quiesce Mode */ 379 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 380 381 /* allow untagged pkts */ 382 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); 383 384 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 385 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc); 386 387 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ? 388 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 389 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) == 390 hw->rxdata_desc_size); 391 392 /* clear shadow stats */ 393 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats)); 394 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats)); 395 396 /* clear snapshot stats */ 397 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats)); 398 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats)); 399 400 /* set the initial link status */ 401 memset(&link, 0, sizeof(link)); 402 link.link_duplex = ETH_LINK_FULL_DUPLEX; 403 link.link_speed = ETH_SPEED_NUM_10G; 404 link.link_autoneg = ETH_LINK_FIXED; 405 rte_eth_linkstatus_set(eth_dev, &link); 406 407 return 0; 408 } 409 410 static int 411 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev) 412 { 413 struct vmxnet3_hw *hw = eth_dev->data->dev_private; 414 415 PMD_INIT_FUNC_TRACE(); 416 417 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 418 return 0; 419 420 if (hw->adapter_stopped == 0) { 421 PMD_INIT_LOG(DEBUG, "Device has not been closed."); 422 return -EBUSY; 423 } 424 425 return 0; 426 } 427 428 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 429 struct rte_pci_device *pci_dev) 430 { 431 return rte_eth_dev_pci_generic_probe(pci_dev, 432 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init); 433 } 434 435 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev) 436 { 437 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit); 438 } 439 440 static struct rte_pci_driver rte_vmxnet3_pmd = { 441 .id_table = pci_id_vmxnet3_map, 442 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 443 .probe = eth_vmxnet3_pci_probe, 444 .remove = eth_vmxnet3_pci_remove, 445 }; 446 447 static void 448 vmxnet3_alloc_intr_resources(struct rte_eth_dev *dev) 449 { 450 struct vmxnet3_hw *hw = dev->data->dev_private; 451 uint32_t cfg; 452 int nvec = 1; /* for link event */ 453 454 /* intr settings */ 455 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 456 VMXNET3_CMD_GET_CONF_INTR); 457 cfg = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 458 hw->intr.type = cfg & 0x3; 459 hw->intr.mask_mode = (cfg >> 2) & 0x3; 460 461 if (hw->intr.type == VMXNET3_IT_AUTO) 462 hw->intr.type = VMXNET3_IT_MSIX; 463 464 if (hw->intr.type == VMXNET3_IT_MSIX) { 465 /* only support shared tx/rx intr */ 466 if (hw->num_tx_queues != hw->num_rx_queues) 467 goto msix_err; 468 469 nvec += hw->num_rx_queues; 470 hw->intr.num_intrs = nvec; 471 return; 472 } 473 474 msix_err: 475 /* the tx/rx queue interrupt will be disabled */ 476 hw->intr.num_intrs = 2; 477 hw->intr.lsc_only = TRUE; 478 PMD_INIT_LOG(INFO, "Enabled MSI-X with %d vectors", hw->intr.num_intrs); 479 } 480 481 static int 482 vmxnet3_dev_configure(struct rte_eth_dev *dev) 483 { 484 const struct rte_memzone *mz; 485 struct vmxnet3_hw *hw = dev->data->dev_private; 486 size_t size; 487 488 PMD_INIT_FUNC_TRACE(); 489 490 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 491 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 492 493 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES || 494 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) { 495 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported"); 496 return -EINVAL; 497 } 498 499 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) { 500 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2"); 501 return -EINVAL; 502 } 503 504 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 505 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc); 506 507 if (size > UINT16_MAX) 508 return -EINVAL; 509 510 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues; 511 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues; 512 513 /* 514 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead 515 * on current socket 516 */ 517 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared), 518 "shared", rte_socket_id(), 8, 1); 519 520 if (mz == NULL) { 521 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone"); 522 return -ENOMEM; 523 } 524 memset(mz->addr, 0, mz->len); 525 526 hw->shared = mz->addr; 527 hw->sharedPA = mz->iova; 528 529 /* 530 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc 531 * on current socket. 532 * 533 * We cannot reuse this memzone from previous allocation as its size 534 * depends on the number of tx and rx queues, which could be different 535 * from one config to another. 536 */ 537 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(), 538 VMXNET3_QUEUE_DESC_ALIGN, 0); 539 if (mz == NULL) { 540 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone"); 541 return -ENOMEM; 542 } 543 memset(mz->addr, 0, mz->len); 544 545 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr; 546 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues); 547 548 hw->queueDescPA = mz->iova; 549 hw->queue_desc_len = (uint16_t)size; 550 551 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 552 /* Allocate memory structure for UPT1_RSSConf and configure */ 553 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), 554 "rss_conf", rte_socket_id(), 555 RTE_CACHE_LINE_SIZE, 1); 556 if (mz == NULL) { 557 PMD_INIT_LOG(ERR, 558 "ERROR: Creating rss_conf structure zone"); 559 return -ENOMEM; 560 } 561 memset(mz->addr, 0, mz->len); 562 563 hw->rss_conf = mz->addr; 564 hw->rss_confPA = mz->iova; 565 } 566 567 vmxnet3_alloc_intr_resources(dev); 568 569 return 0; 570 } 571 572 static void 573 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr) 574 { 575 uint32_t val; 576 577 PMD_INIT_LOG(DEBUG, 578 "Writing MAC Address : " RTE_ETHER_ADDR_PRT_FMT, 579 addr[0], addr[1], addr[2], 580 addr[3], addr[4], addr[5]); 581 582 memcpy(&val, addr, 4); 583 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val); 584 585 memcpy(&val, addr + 4, 2); 586 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val); 587 } 588 589 /* 590 * Configure the hardware to generate MSI-X interrupts. 591 * If setting up MSIx fails, try setting up MSI (only 1 interrupt vector 592 * which will be disabled to allow lsc to work). 593 * 594 * Returns 0 on success and -1 otherwise. 595 */ 596 static int 597 vmxnet3_configure_msix(struct rte_eth_dev *dev) 598 { 599 struct vmxnet3_hw *hw = dev->data->dev_private; 600 struct rte_intr_handle *intr_handle = dev->intr_handle; 601 uint16_t intr_vector; 602 int i; 603 604 hw->intr.event_intr_idx = 0; 605 606 /* only vfio-pci driver can support interrupt mode. */ 607 if (!rte_intr_cap_multiple(intr_handle) || 608 dev->data->dev_conf.intr_conf.rxq == 0) 609 return -1; 610 611 intr_vector = dev->data->nb_rx_queues; 612 if (intr_vector > VMXNET3_MAX_RX_QUEUES) { 613 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 614 VMXNET3_MAX_RX_QUEUES); 615 return -ENOTSUP; 616 } 617 618 if (rte_intr_efd_enable(intr_handle, intr_vector)) { 619 PMD_INIT_LOG(ERR, "Failed to enable fastpath event fd"); 620 return -1; 621 } 622 623 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 624 intr_handle->intr_vec = 625 rte_zmalloc("intr_vec", 626 dev->data->nb_rx_queues * sizeof(int), 0); 627 if (intr_handle->intr_vec == NULL) { 628 PMD_INIT_LOG(ERR, "Failed to allocate %d Rx queues intr_vec", 629 dev->data->nb_rx_queues); 630 rte_intr_efd_disable(intr_handle); 631 return -ENOMEM; 632 } 633 } 634 635 if (!rte_intr_allow_others(intr_handle) && 636 dev->data->dev_conf.intr_conf.lsc != 0) { 637 PMD_INIT_LOG(ERR, "not enough intr vector to support both Rx interrupt and LSC"); 638 rte_free(intr_handle->intr_vec); 639 intr_handle->intr_vec = NULL; 640 rte_intr_efd_disable(intr_handle); 641 return -1; 642 } 643 644 /* if we cannot allocate one MSI-X vector per queue, don't enable 645 * interrupt mode. 646 */ 647 if (hw->intr.num_intrs != (intr_handle->nb_efd + 1)) { 648 PMD_INIT_LOG(ERR, "Device configured with %d Rx intr vectors, expecting %d", 649 hw->intr.num_intrs, intr_handle->nb_efd + 1); 650 rte_free(intr_handle->intr_vec); 651 intr_handle->intr_vec = NULL; 652 rte_intr_efd_disable(intr_handle); 653 return -1; 654 } 655 656 for (i = 0; i < dev->data->nb_rx_queues; i++) 657 intr_handle->intr_vec[i] = i + 1; 658 659 for (i = 0; i < hw->intr.num_intrs; i++) 660 hw->intr.mod_levels[i] = UPT1_IML_ADAPTIVE; 661 662 PMD_INIT_LOG(INFO, "intr type %u, mode %u, %u vectors allocated", 663 hw->intr.type, hw->intr.mask_mode, hw->intr.num_intrs); 664 665 return 0; 666 } 667 668 static int 669 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev) 670 { 671 struct vmxnet3_hw *hw = dev->data->dev_private; 672 Vmxnet3_DriverShared *shared = hw->shared; 673 Vmxnet3_CmdInfo *cmdInfo; 674 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES]; 675 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES]; 676 uint32_t num, i, j, size; 677 678 if (hw->memRegsPA == 0) { 679 const struct rte_memzone *mz; 680 681 size = sizeof(Vmxnet3_MemRegs) + 682 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) * 683 sizeof(Vmxnet3_MemoryRegion); 684 685 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8, 686 1); 687 if (mz == NULL) { 688 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone"); 689 return -ENOMEM; 690 } 691 memset(mz->addr, 0, mz->len); 692 hw->memRegs = mz->addr; 693 hw->memRegsPA = mz->iova; 694 } 695 696 num = hw->num_rx_queues; 697 698 for (i = 0; i < num; i++) { 699 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 700 701 mp[i] = rxq->mp; 702 index[i] = 1 << i; 703 } 704 705 /* 706 * The same mempool could be used by multiple queues. In such a case, 707 * remove duplicate mempool entries. Only one entry is kept with 708 * bitmask indicating queues that are using this mempool. 709 */ 710 for (i = 1; i < num; i++) { 711 for (j = 0; j < i; j++) { 712 if (mp[i] == mp[j]) { 713 mp[i] = NULL; 714 index[j] |= 1 << i; 715 break; 716 } 717 } 718 } 719 720 j = 0; 721 for (i = 0; i < num; i++) { 722 if (mp[i] == NULL) 723 continue; 724 725 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j]; 726 727 mr->startPA = 728 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova; 729 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ? 730 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX; 731 mr->txQueueBits = index[i]; 732 mr->rxQueueBits = index[i]; 733 734 PMD_INIT_LOG(INFO, 735 "index: %u startPA: %" PRIu64 " length: %u, " 736 "rxBits: %x", 737 j, mr->startPA, mr->length, mr->rxQueueBits); 738 j++; 739 } 740 hw->memRegs->numRegs = j; 741 PMD_INIT_LOG(INFO, "numRegs: %u", j); 742 743 size = sizeof(Vmxnet3_MemRegs) + 744 (j - 1) * sizeof(Vmxnet3_MemoryRegion); 745 746 cmdInfo = &shared->cu.cmdInfo; 747 cmdInfo->varConf.confVer = 1; 748 cmdInfo->varConf.confLen = size; 749 cmdInfo->varConf.confPA = hw->memRegsPA; 750 751 return 0; 752 } 753 754 static int 755 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) 756 { 757 struct rte_eth_conf port_conf = dev->data->dev_conf; 758 struct vmxnet3_hw *hw = dev->data->dev_private; 759 struct rte_intr_handle *intr_handle = dev->intr_handle; 760 uint32_t mtu = dev->data->mtu; 761 Vmxnet3_DriverShared *shared = hw->shared; 762 Vmxnet3_DSDevRead *devRead = &shared->devRead; 763 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 764 uint32_t i; 765 int ret; 766 767 hw->mtu = mtu; 768 769 shared->magic = VMXNET3_REV1_MAGIC; 770 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; 771 772 /* Setting up Guest OS information */ 773 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ? 774 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64; 775 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 776 devRead->misc.driverInfo.vmxnet3RevSpt = 1; 777 devRead->misc.driverInfo.uptVerSpt = 1; 778 779 devRead->misc.mtu = rte_le_to_cpu_32(mtu); 780 devRead->misc.queueDescPA = hw->queueDescPA; 781 devRead->misc.queueDescLen = hw->queue_desc_len; 782 devRead->misc.numTxQueues = hw->num_tx_queues; 783 devRead->misc.numRxQueues = hw->num_rx_queues; 784 785 for (i = 0; i < hw->num_tx_queues; i++) { 786 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i]; 787 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i]; 788 789 txq->shared = &hw->tqd_start[i]; 790 791 tqd->ctrl.txNumDeferred = 0; 792 tqd->ctrl.txThreshold = 1; 793 tqd->conf.txRingBasePA = txq->cmd_ring.basePA; 794 tqd->conf.compRingBasePA = txq->comp_ring.basePA; 795 tqd->conf.dataRingBasePA = txq->data_ring.basePA; 796 797 tqd->conf.txRingSize = txq->cmd_ring.size; 798 tqd->conf.compRingSize = txq->comp_ring.size; 799 tqd->conf.dataRingSize = txq->data_ring.size; 800 tqd->conf.txDataRingDescSize = txq->txdata_desc_size; 801 802 if (hw->intr.lsc_only) 803 tqd->conf.intrIdx = 1; 804 else 805 tqd->conf.intrIdx = intr_handle->intr_vec[i]; 806 tqd->status.stopped = TRUE; 807 tqd->status.error = 0; 808 memset(&tqd->stats, 0, sizeof(tqd->stats)); 809 } 810 811 for (i = 0; i < hw->num_rx_queues; i++) { 812 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i]; 813 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i]; 814 815 rxq->shared = &hw->rqd_start[i]; 816 817 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA; 818 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA; 819 rqd->conf.compRingBasePA = rxq->comp_ring.basePA; 820 821 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size; 822 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size; 823 rqd->conf.compRingSize = rxq->comp_ring.size; 824 825 if (hw->intr.lsc_only) 826 rqd->conf.intrIdx = 1; 827 else 828 rqd->conf.intrIdx = intr_handle->intr_vec[i]; 829 rqd->status.stopped = TRUE; 830 rqd->status.error = 0; 831 memset(&rqd->stats, 0, sizeof(rqd->stats)); 832 } 833 834 /* intr settings */ 835 devRead->intrConf.autoMask = hw->intr.mask_mode == VMXNET3_IMM_AUTO; 836 devRead->intrConf.numIntrs = hw->intr.num_intrs; 837 for (i = 0; i < hw->intr.num_intrs; i++) 838 devRead->intrConf.modLevels[i] = hw->intr.mod_levels[i]; 839 840 devRead->intrConf.eventIntrIdx = hw->intr.event_intr_idx; 841 devRead->intrConf.intrCtrl |= rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL); 842 843 /* RxMode set to 0 of VMXNET3_RXM_xxx */ 844 devRead->rxFilterConf.rxMode = 0; 845 846 /* Setting up feature flags */ 847 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM) 848 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM; 849 850 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) { 851 devRead->misc.uptFeatures |= VMXNET3_F_LRO; 852 devRead->misc.maxNumRxSG = 0; 853 } 854 855 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 856 ret = vmxnet3_rss_configure(dev); 857 if (ret != VMXNET3_SUCCESS) 858 return ret; 859 860 devRead->misc.uptFeatures |= VMXNET3_F_RSS; 861 devRead->rssConfDesc.confVer = 1; 862 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf); 863 devRead->rssConfDesc.confPA = hw->rss_confPA; 864 } 865 866 ret = vmxnet3_dev_vlan_offload_set(dev, 867 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 868 if (ret) 869 return ret; 870 871 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes); 872 873 return VMXNET3_SUCCESS; 874 } 875 876 /* 877 * Configure device link speed and setup link. 878 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail 879 * It returns 0 on success. 880 */ 881 static int 882 vmxnet3_dev_start(struct rte_eth_dev *dev) 883 { 884 int ret; 885 struct vmxnet3_hw *hw = dev->data->dev_private; 886 887 PMD_INIT_FUNC_TRACE(); 888 889 /* Save stats before it is reset by CMD_ACTIVATE */ 890 vmxnet3_hw_stats_save(hw); 891 892 /* configure MSI-X */ 893 ret = vmxnet3_configure_msix(dev); 894 if (ret < 0) { 895 /* revert to lsc only */ 896 hw->intr.num_intrs = 2; 897 hw->intr.lsc_only = TRUE; 898 } 899 900 ret = vmxnet3_setup_driver_shared(dev); 901 if (ret != VMXNET3_SUCCESS) 902 return ret; 903 904 /* Exchange shared data with device */ 905 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 906 VMXNET3_GET_ADDR_LO(hw->sharedPA)); 907 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 908 VMXNET3_GET_ADDR_HI(hw->sharedPA)); 909 910 /* Activate device by register write */ 911 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV); 912 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 913 914 if (ret != 0) { 915 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL"); 916 return -EINVAL; 917 } 918 919 /* Setup memory region for rx buffers */ 920 ret = vmxnet3_dev_setup_memreg(dev); 921 if (ret == 0) { 922 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 923 VMXNET3_CMD_REGISTER_MEMREGS); 924 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 925 if (ret != 0) 926 PMD_INIT_LOG(DEBUG, 927 "Failed in setup memory region cmd\n"); 928 ret = 0; 929 } else { 930 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n"); 931 } 932 933 if (VMXNET3_VERSION_GE_4(hw) && 934 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { 935 /* Check for additional RSS */ 936 ret = vmxnet3_v4_rss_configure(dev); 937 if (ret != VMXNET3_SUCCESS) { 938 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS"); 939 return ret; 940 } 941 } 942 943 /* 944 * Load RX queues with blank mbufs and update next2fill index for device 945 * Update RxMode of the device 946 */ 947 ret = vmxnet3_dev_rxtx_init(dev); 948 if (ret != VMXNET3_SUCCESS) { 949 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL"); 950 return ret; 951 } 952 953 hw->adapter_stopped = FALSE; 954 955 /* Setting proper Rx Mode and issue Rx Mode Update command */ 956 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1); 957 958 /* Setup interrupt callback */ 959 rte_intr_callback_register(dev->intr_handle, 960 vmxnet3_interrupt_handler, dev); 961 962 if (rte_intr_enable(dev->intr_handle) < 0) { 963 PMD_INIT_LOG(ERR, "interrupt enable failed"); 964 return -EIO; 965 } 966 967 /* enable all intrs */ 968 vmxnet3_enable_all_intrs(hw); 969 970 vmxnet3_process_events(dev); 971 972 /* 973 * Update link state from device since this won't be 974 * done upon starting with lsc in use. This is done 975 * only after enabling interrupts to avoid any race 976 * where the link state could change without an 977 * interrupt being fired. 978 */ 979 __vmxnet3_dev_link_update(dev, 0); 980 981 return VMXNET3_SUCCESS; 982 } 983 984 /* 985 * Stop device: disable rx and tx functions to allow for reconfiguring. 986 */ 987 static int 988 vmxnet3_dev_stop(struct rte_eth_dev *dev) 989 { 990 struct rte_eth_link link; 991 struct vmxnet3_hw *hw = dev->data->dev_private; 992 struct rte_intr_handle *intr_handle = dev->intr_handle; 993 int ret; 994 995 PMD_INIT_FUNC_TRACE(); 996 997 if (hw->adapter_stopped == 1) { 998 PMD_INIT_LOG(DEBUG, "Device already stopped."); 999 return 0; 1000 } 1001 1002 do { 1003 /* Unregister has lock to make sure there is no running cb. 1004 * This has to happen first since vmxnet3_interrupt_handler 1005 * reenables interrupts by calling vmxnet3_enable_intr 1006 */ 1007 ret = rte_intr_callback_unregister(intr_handle, 1008 vmxnet3_interrupt_handler, 1009 (void *)-1); 1010 } while (ret == -EAGAIN); 1011 1012 if (ret < 0) 1013 PMD_DRV_LOG(ERR, "Error attempting to unregister intr cb: %d", 1014 ret); 1015 1016 PMD_INIT_LOG(DEBUG, "Disabled %d intr callbacks", ret); 1017 1018 /* disable interrupts */ 1019 vmxnet3_disable_all_intrs(hw); 1020 1021 rte_intr_disable(intr_handle); 1022 1023 /* Clean datapath event and queue/vector mapping */ 1024 rte_intr_efd_disable(intr_handle); 1025 if (intr_handle->intr_vec != NULL) { 1026 rte_free(intr_handle->intr_vec); 1027 intr_handle->intr_vec = NULL; 1028 } 1029 1030 /* quiesce the device first */ 1031 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); 1032 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0); 1033 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0); 1034 1035 /* reset the device */ 1036 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 1037 PMD_INIT_LOG(DEBUG, "Device reset."); 1038 1039 vmxnet3_dev_clear_queues(dev); 1040 1041 /* Clear recorded link status */ 1042 memset(&link, 0, sizeof(link)); 1043 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1044 link.link_speed = ETH_SPEED_NUM_10G; 1045 link.link_autoneg = ETH_LINK_FIXED; 1046 rte_eth_linkstatus_set(dev, &link); 1047 1048 hw->adapter_stopped = 1; 1049 dev->data->dev_started = 0; 1050 1051 return 0; 1052 } 1053 1054 static void 1055 vmxnet3_free_queues(struct rte_eth_dev *dev) 1056 { 1057 int i; 1058 1059 PMD_INIT_FUNC_TRACE(); 1060 1061 for (i = 0; i < dev->data->nb_rx_queues; i++) 1062 vmxnet3_dev_rx_queue_release(dev, i); 1063 dev->data->nb_rx_queues = 0; 1064 1065 for (i = 0; i < dev->data->nb_tx_queues; i++) 1066 vmxnet3_dev_tx_queue_release(dev, i); 1067 dev->data->nb_tx_queues = 0; 1068 } 1069 1070 /* 1071 * Reset and stop device. 1072 */ 1073 static int 1074 vmxnet3_dev_close(struct rte_eth_dev *dev) 1075 { 1076 int ret; 1077 PMD_INIT_FUNC_TRACE(); 1078 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1079 return 0; 1080 1081 ret = vmxnet3_dev_stop(dev); 1082 vmxnet3_free_queues(dev); 1083 1084 return ret; 1085 } 1086 1087 static int 1088 vmxnet3_dev_reset(struct rte_eth_dev *dev) 1089 { 1090 int ret; 1091 1092 ret = eth_vmxnet3_dev_uninit(dev); 1093 if (ret) 1094 return ret; 1095 ret = eth_vmxnet3_dev_init(dev); 1096 return ret; 1097 } 1098 1099 static void 1100 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 1101 struct UPT1_TxStats *res) 1102 { 1103 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \ 1104 ((r)->f = (h)->tqd_start[(i)].stats.f + \ 1105 (h)->saved_tx_stats[(i)].f) 1106 1107 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res); 1108 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res); 1109 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res); 1110 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res); 1111 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res); 1112 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res); 1113 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res); 1114 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res); 1115 1116 #undef VMXNET3_UPDATE_TX_STAT 1117 } 1118 1119 static void 1120 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 1121 struct UPT1_RxStats *res) 1122 { 1123 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \ 1124 ((r)->f = (h)->rqd_start[(i)].stats.f + \ 1125 (h)->saved_rx_stats[(i)].f) 1126 1127 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res); 1128 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res); 1129 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res); 1130 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res); 1131 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res); 1132 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res); 1133 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res); 1134 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res); 1135 1136 #undef VMXNET3_UPDATE_RX_STAT 1137 } 1138 1139 static void 1140 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 1141 struct UPT1_TxStats *res) 1142 { 1143 vmxnet3_hw_tx_stats_get(hw, q, res); 1144 1145 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \ 1146 ((r)->f -= (h)->snapshot_tx_stats[(i)].f) 1147 1148 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res); 1149 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res); 1150 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res); 1151 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res); 1152 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res); 1153 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res); 1154 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res); 1155 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res); 1156 1157 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT 1158 } 1159 1160 static void 1161 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q, 1162 struct UPT1_RxStats *res) 1163 { 1164 vmxnet3_hw_rx_stats_get(hw, q, res); 1165 1166 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \ 1167 ((r)->f -= (h)->snapshot_rx_stats[(i)].f) 1168 1169 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res); 1170 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res); 1171 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res); 1172 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res); 1173 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res); 1174 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res); 1175 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res); 1176 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res); 1177 1178 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT 1179 } 1180 1181 static void 1182 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw) 1183 { 1184 unsigned int i; 1185 1186 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1187 1188 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1189 1190 for (i = 0; i < hw->num_tx_queues; i++) 1191 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]); 1192 for (i = 0; i < hw->num_rx_queues; i++) 1193 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]); 1194 } 1195 1196 static int 1197 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev, 1198 struct rte_eth_xstat_name *xstats_names, 1199 unsigned int n) 1200 { 1201 unsigned int i, t, count = 0; 1202 unsigned int nstats = 1203 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1204 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1205 1206 if (!xstats_names || n < nstats) 1207 return nstats; 1208 1209 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1210 if (!dev->data->rx_queues[i]) 1211 continue; 1212 1213 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1214 snprintf(xstats_names[count].name, 1215 sizeof(xstats_names[count].name), 1216 "rx_q%u_%s", i, 1217 vmxnet3_rxq_stat_strings[t].name); 1218 count++; 1219 } 1220 } 1221 1222 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1223 if (!dev->data->tx_queues[i]) 1224 continue; 1225 1226 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1227 snprintf(xstats_names[count].name, 1228 sizeof(xstats_names[count].name), 1229 "tx_q%u_%s", i, 1230 vmxnet3_txq_stat_strings[t].name); 1231 count++; 1232 } 1233 } 1234 1235 return count; 1236 } 1237 1238 static int 1239 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1240 unsigned int n) 1241 { 1242 unsigned int i, t, count = 0; 1243 unsigned int nstats = 1244 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) + 1245 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings); 1246 1247 if (n < nstats) 1248 return nstats; 1249 1250 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1251 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i]; 1252 1253 if (rxq == NULL) 1254 continue; 1255 1256 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) { 1257 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) + 1258 vmxnet3_rxq_stat_strings[t].offset); 1259 xstats[count].id = count; 1260 count++; 1261 } 1262 } 1263 1264 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1265 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i]; 1266 1267 if (txq == NULL) 1268 continue; 1269 1270 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) { 1271 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) + 1272 vmxnet3_txq_stat_strings[t].offset); 1273 xstats[count].id = count; 1274 count++; 1275 } 1276 } 1277 1278 return count; 1279 } 1280 1281 static int 1282 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1283 { 1284 unsigned int i; 1285 struct vmxnet3_hw *hw = dev->data->dev_private; 1286 struct UPT1_TxStats txStats; 1287 struct UPT1_RxStats rxStats; 1288 1289 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1290 1291 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1292 for (i = 0; i < hw->num_tx_queues; i++) { 1293 vmxnet3_tx_stats_get(hw, i, &txStats); 1294 1295 stats->q_opackets[i] = txStats.ucastPktsTxOK + 1296 txStats.mcastPktsTxOK + 1297 txStats.bcastPktsTxOK; 1298 1299 stats->q_obytes[i] = txStats.ucastBytesTxOK + 1300 txStats.mcastBytesTxOK + 1301 txStats.bcastBytesTxOK; 1302 1303 stats->opackets += stats->q_opackets[i]; 1304 stats->obytes += stats->q_obytes[i]; 1305 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard; 1306 } 1307 1308 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES); 1309 for (i = 0; i < hw->num_rx_queues; i++) { 1310 vmxnet3_rx_stats_get(hw, i, &rxStats); 1311 1312 stats->q_ipackets[i] = rxStats.ucastPktsRxOK + 1313 rxStats.mcastPktsRxOK + 1314 rxStats.bcastPktsRxOK; 1315 1316 stats->q_ibytes[i] = rxStats.ucastBytesRxOK + 1317 rxStats.mcastBytesRxOK + 1318 rxStats.bcastBytesRxOK; 1319 1320 stats->ipackets += stats->q_ipackets[i]; 1321 stats->ibytes += stats->q_ibytes[i]; 1322 1323 stats->q_errors[i] = rxStats.pktsRxError; 1324 stats->ierrors += rxStats.pktsRxError; 1325 stats->imissed += rxStats.pktsRxOutOfBuf; 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int 1332 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev) 1333 { 1334 unsigned int i; 1335 struct vmxnet3_hw *hw = dev->data->dev_private; 1336 struct UPT1_TxStats txStats = {0}; 1337 struct UPT1_RxStats rxStats = {0}; 1338 1339 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS); 1340 1341 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES); 1342 1343 for (i = 0; i < hw->num_tx_queues; i++) { 1344 vmxnet3_hw_tx_stats_get(hw, i, &txStats); 1345 memcpy(&hw->snapshot_tx_stats[i], &txStats, 1346 sizeof(hw->snapshot_tx_stats[0])); 1347 } 1348 for (i = 0; i < hw->num_rx_queues; i++) { 1349 vmxnet3_hw_rx_stats_get(hw, i, &rxStats); 1350 memcpy(&hw->snapshot_rx_stats[i], &rxStats, 1351 sizeof(hw->snapshot_rx_stats[0])); 1352 } 1353 1354 return 0; 1355 } 1356 1357 static int 1358 vmxnet3_dev_info_get(struct rte_eth_dev *dev, 1359 struct rte_eth_dev_info *dev_info) 1360 { 1361 struct vmxnet3_hw *hw = dev->data->dev_private; 1362 1363 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES; 1364 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES; 1365 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM; 1366 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */ 1367 dev_info->min_mtu = VMXNET3_MIN_MTU; 1368 dev_info->max_mtu = VMXNET3_MAX_MTU; 1369 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1370 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS; 1371 1372 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL; 1373 1374 if (VMXNET3_VERSION_GE_4(hw)) { 1375 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK; 1376 } 1377 1378 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1379 .nb_max = VMXNET3_RX_RING_MAX_SIZE, 1380 .nb_min = VMXNET3_DEF_RX_RING_SIZE, 1381 .nb_align = 1, 1382 }; 1383 1384 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1385 .nb_max = VMXNET3_TX_RING_MAX_SIZE, 1386 .nb_min = VMXNET3_DEF_TX_RING_SIZE, 1387 .nb_align = 1, 1388 .nb_seg_max = VMXNET3_TX_MAX_SEG, 1389 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT, 1390 }; 1391 1392 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP; 1393 dev_info->rx_queue_offload_capa = 0; 1394 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP; 1395 dev_info->tx_queue_offload_capa = 0; 1396 1397 return 0; 1398 } 1399 1400 static const uint32_t * 1401 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1402 { 1403 static const uint32_t ptypes[] = { 1404 RTE_PTYPE_L3_IPV4_EXT, 1405 RTE_PTYPE_L3_IPV4, 1406 RTE_PTYPE_UNKNOWN 1407 }; 1408 1409 if (dev->rx_pkt_burst == vmxnet3_recv_pkts) 1410 return ptypes; 1411 return NULL; 1412 } 1413 1414 static int 1415 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu) 1416 { 1417 if (dev->data->dev_started) { 1418 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU", 1419 dev->data->port_id); 1420 return -EBUSY; 1421 } 1422 1423 return 0; 1424 } 1425 1426 static int 1427 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1428 { 1429 struct vmxnet3_hw *hw = dev->data->dev_private; 1430 1431 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr)); 1432 vmxnet3_write_mac(hw, mac_addr->addr_bytes); 1433 return 0; 1434 } 1435 1436 /* return 0 means link status changed, -1 means not changed */ 1437 static int 1438 __vmxnet3_dev_link_update(struct rte_eth_dev *dev, 1439 __rte_unused int wait_to_complete) 1440 { 1441 struct vmxnet3_hw *hw = dev->data->dev_private; 1442 struct rte_eth_link link; 1443 uint32_t ret; 1444 1445 memset(&link, 0, sizeof(link)); 1446 1447 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 1448 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); 1449 1450 if (ret & 0x1) 1451 link.link_status = ETH_LINK_UP; 1452 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1453 link.link_speed = ETH_SPEED_NUM_10G; 1454 link.link_autoneg = ETH_LINK_FIXED; 1455 1456 return rte_eth_linkstatus_set(dev, &link); 1457 } 1458 1459 static int 1460 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1461 { 1462 /* Link status doesn't change for stopped dev */ 1463 if (dev->data->dev_started == 0) 1464 return -1; 1465 1466 return __vmxnet3_dev_link_update(dev, wait_to_complete); 1467 } 1468 1469 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */ 1470 static void 1471 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) 1472 { 1473 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1474 1475 if (set) 1476 rxConf->rxMode = rxConf->rxMode | feature; 1477 else 1478 rxConf->rxMode = rxConf->rxMode & (~feature); 1479 1480 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE); 1481 } 1482 1483 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1484 static int 1485 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev) 1486 { 1487 struct vmxnet3_hw *hw = dev->data->dev_private; 1488 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1489 1490 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE); 1491 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1); 1492 1493 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1494 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1495 1496 return 0; 1497 } 1498 1499 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */ 1500 static int 1501 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev) 1502 { 1503 struct vmxnet3_hw *hw = dev->data->dev_private; 1504 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable; 1505 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1506 1507 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1508 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1509 else 1510 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1511 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0); 1512 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1513 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1514 1515 return 0; 1516 } 1517 1518 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1519 static int 1520 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev) 1521 { 1522 struct vmxnet3_hw *hw = dev->data->dev_private; 1523 1524 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1); 1525 1526 return 0; 1527 } 1528 1529 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */ 1530 static int 1531 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev) 1532 { 1533 struct vmxnet3_hw *hw = dev->data->dev_private; 1534 1535 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0); 1536 1537 return 0; 1538 } 1539 1540 /* Enable/disable filter on vlan */ 1541 static int 1542 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1543 { 1544 struct vmxnet3_hw *hw = dev->data->dev_private; 1545 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf; 1546 uint32_t *vf_table = rxConf->vfTable; 1547 1548 /* save state for restore */ 1549 if (on) 1550 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1551 else 1552 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid); 1553 1554 /* don't change active filter if in promiscuous mode */ 1555 if (rxConf->rxMode & VMXNET3_RXM_PROMISC) 1556 return 0; 1557 1558 /* set in hardware */ 1559 if (on) 1560 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid); 1561 else 1562 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid); 1563 1564 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1565 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1566 return 0; 1567 } 1568 1569 static int 1570 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1571 { 1572 struct vmxnet3_hw *hw = dev->data->dev_private; 1573 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1574 uint32_t *vf_table = devRead->rxFilterConf.vfTable; 1575 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1576 1577 if (mask & ETH_VLAN_STRIP_MASK) { 1578 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1579 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 1580 else 1581 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; 1582 1583 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1584 VMXNET3_CMD_UPDATE_FEATURE); 1585 } 1586 1587 if (mask & ETH_VLAN_FILTER_MASK) { 1588 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1589 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); 1590 else 1591 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); 1592 1593 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1594 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1595 } 1596 1597 return 0; 1598 } 1599 1600 static void 1601 vmxnet3_process_events(struct rte_eth_dev *dev) 1602 { 1603 struct vmxnet3_hw *hw = dev->data->dev_private; 1604 uint32_t events = hw->shared->ecr; 1605 1606 if (!events) 1607 return; 1608 1609 /* 1610 * ECR bits when written with 1b are cleared. Hence write 1611 * events back to ECR so that the bits which were set will be reset. 1612 */ 1613 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events); 1614 1615 /* Check if link state has changed */ 1616 if (events & VMXNET3_ECR_LINK) { 1617 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event"); 1618 if (vmxnet3_dev_link_update(dev, 0) == 0) 1619 rte_eth_dev_callback_process(dev, 1620 RTE_ETH_EVENT_INTR_LSC, 1621 NULL); 1622 } 1623 1624 /* Check if there is an error on xmit/recv queues */ 1625 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 1626 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, 1627 VMXNET3_CMD_GET_QUEUE_STATUS); 1628 1629 if (hw->tqd_start->status.stopped) 1630 PMD_DRV_LOG(ERR, "tq error 0x%x", 1631 hw->tqd_start->status.error); 1632 1633 if (hw->rqd_start->status.stopped) 1634 PMD_DRV_LOG(ERR, "rq error 0x%x", 1635 hw->rqd_start->status.error); 1636 1637 /* Reset the device */ 1638 /* Have to reset the device */ 1639 } 1640 1641 if (events & VMXNET3_ECR_DIC) 1642 PMD_DRV_LOG(DEBUG, "Device implementation change event."); 1643 1644 if (events & VMXNET3_ECR_DEBUG) 1645 PMD_DRV_LOG(DEBUG, "Debug event generated by device."); 1646 } 1647 1648 static void 1649 vmxnet3_interrupt_handler(void *param) 1650 { 1651 struct rte_eth_dev *dev = param; 1652 struct vmxnet3_hw *hw = dev->data->dev_private; 1653 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; 1654 uint32_t events; 1655 1656 PMD_INIT_FUNC_TRACE(); 1657 vmxnet3_disable_intr(hw, devRead->intrConf.eventIntrIdx); 1658 1659 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR); 1660 if (events == 0) 1661 goto done; 1662 1663 RTE_LOG(DEBUG, PMD, "Reading events: 0x%X", events); 1664 vmxnet3_process_events(dev); 1665 done: 1666 vmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx); 1667 } 1668 1669 static int 1670 vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 1671 { 1672 struct vmxnet3_hw *hw = dev->data->dev_private; 1673 1674 vmxnet3_enable_intr(hw, dev->intr_handle->intr_vec[queue_id]); 1675 1676 return 0; 1677 } 1678 1679 static int 1680 vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 1681 { 1682 struct vmxnet3_hw *hw = dev->data->dev_private; 1683 1684 vmxnet3_disable_intr(hw, dev->intr_handle->intr_vec[queue_id]); 1685 1686 return 0; 1687 } 1688 1689 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd); 1690 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map); 1691 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci"); 1692 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_init, init, NOTICE); 1693 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_driver, driver, NOTICE); 1694