1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2007 VMware, Inc. All rights reserved. 3 */ 4 5 /* 6 * vmxnet3_defs.h -- 7 * 8 * Definitions shared by device emulation and guest drivers for 9 * VMXNET3 NIC 10 */ 11 12 #ifndef _VMXNET3_DEFS_H_ 13 #define _VMXNET3_DEFS_H_ 14 15 #include "vmxnet3_osdep.h" 16 #include "upt1_defs.h" 17 18 /* all registers are 32 bit wide */ 19 /* BAR 1 */ 20 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */ 21 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */ 22 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */ 23 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */ 24 #define VMXNET3_REG_CMD 0x20 /* Command */ 25 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */ 26 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ 27 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ 28 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ 29 30 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ 31 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ 32 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */ 33 34 /* BAR 0 */ 35 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */ 36 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */ 37 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ 38 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ 39 40 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 41 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 42 43 /* 44 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at 45 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region: 46 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE--> 47 * ------------------------------------------------------------------------- 48 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table | 49 * ------------------------------------------------------------------------- 50 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" 51 */ 52 #define VMXNET3_PHYSMEM_PAGES 4 53 54 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 55 #define VMXNET3_REG_ALIGN_MASK 0x7 56 57 /* I/O Mapped access to registers */ 58 #define VMXNET3_IO_TYPE_PT 0 59 #define VMXNET3_IO_TYPE_VD 1 60 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 61 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 62 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 63 64 #ifndef __le16 65 #define __le16 uint16 66 #endif 67 #ifndef __le32 68 #define __le32 uint32 69 #endif 70 #ifndef __le64 71 #define __le64 uint64 72 #endif 73 74 typedef enum { 75 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 76 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 77 VMXNET3_CMD_QUIESCE_DEV, 78 VMXNET3_CMD_RESET_DEV, 79 VMXNET3_CMD_UPDATE_RX_MODE, 80 VMXNET3_CMD_UPDATE_MAC_FILTERS, 81 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 82 VMXNET3_CMD_UPDATE_RSSIDT, 83 VMXNET3_CMD_UPDATE_IML, 84 VMXNET3_CMD_UPDATE_PMCFG, 85 VMXNET3_CMD_UPDATE_FEATURE, 86 VMXNET3_CMD_STOP_EMULATION, 87 VMXNET3_CMD_LOAD_PLUGIN, 88 VMXNET3_CMD_ACTIVATE_VF, 89 VMXNET3_CMD_RESERVED3, 90 VMXNET3_CMD_RESERVED4, 91 VMXNET3_CMD_REGISTER_MEMREGS, 92 VMXNET3_CMD_SET_RSS_FIELDS, 93 94 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 95 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 96 VMXNET3_CMD_GET_STATS, 97 VMXNET3_CMD_GET_LINK, 98 VMXNET3_CMD_GET_PERM_MAC_LO, 99 VMXNET3_CMD_GET_PERM_MAC_HI, 100 VMXNET3_CMD_GET_DID_LO, 101 VMXNET3_CMD_GET_DID_HI, 102 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 103 VMXNET3_CMD_GET_CONF_INTR, 104 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO, 105 VMXNET3_CMD_GET_TXDATA_DESC_SIZE, 106 VMXNET3_CMD_RESERVED5, 107 } Vmxnet3_Cmd; 108 109 /* Adaptive Ring Info Flags */ 110 #define VMXNET3_DISABLE_ADAPTIVE_RING 1 111 112 /* 113 * Little Endian layout of bitfields - 114 * Byte 0 : 7.....len.....0 115 * Byte 1 : rsvd gen 13.len.8 116 * Byte 2 : 5.msscof.0 ext1 dtype 117 * Byte 3 : 13...msscof...6 118 * 119 * Big Endian layout of bitfields - 120 * Byte 0: 13...msscof...6 121 * Byte 1 : 5.msscof.0 ext1 dtype 122 * Byte 2 : rsvd gen 13.len.8 123 * Byte 3 : 7.....len.....0 124 * 125 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 126 * the bit fields correctly. And cpu_to_le32 will convert bitfields 127 * bit fields written by big endian driver to format required by device. 128 */ 129 130 typedef 131 #include "vmware_pack_begin.h" 132 struct Vmxnet3_TxDesc { 133 __le64 addr; 134 135 #ifdef __BIG_ENDIAN_BITFIELD 136 uint32 msscof:14; /* MSS, checksum offset, flags */ 137 uint32 ext1:1; 138 uint32 dtype:1; /* descriptor type */ 139 uint32 rsvd:1; 140 uint32 gen:1; /* generation bit */ 141 uint32 len:14; 142 #else 143 uint32 len:14; 144 uint32 gen:1; /* generation bit */ 145 uint32 rsvd:1; 146 uint32 dtype:1; /* descriptor type */ 147 uint32 ext1:1; 148 uint32 msscof:14; /* MSS, checksum offset, flags */ 149 #endif /* __BIG_ENDIAN_BITFIELD */ 150 151 #ifdef __BIG_ENDIAN_BITFIELD 152 uint32 tci:16; /* Tag to Insert */ 153 uint32 ti:1; /* VLAN Tag Insertion */ 154 uint32 ext2:1; 155 uint32 cq:1; /* completion request */ 156 uint32 eop:1; /* End Of Packet */ 157 uint32 om:2; /* offload mode */ 158 uint32 hlen:10; /* header len */ 159 #else 160 uint32 hlen:10; /* header len */ 161 uint32 om:2; /* offload mode */ 162 uint32 eop:1; /* End Of Packet */ 163 uint32 cq:1; /* completion request */ 164 uint32 ext2:1; 165 uint32 ti:1; /* VLAN Tag Insertion */ 166 uint32 tci:16; /* Tag to Insert */ 167 #endif /* __BIG_ENDIAN_BITFIELD */ 168 } 169 #include "vmware_pack_end.h" 170 Vmxnet3_TxDesc; 171 172 /* TxDesc.OM values */ 173 #define VMXNET3_OM_NONE 0 174 #define VMXNET3_OM_CSUM 2 175 #define VMXNET3_OM_TSO 3 176 177 /* fields in TxDesc we access w/o using bit fields */ 178 #define VMXNET3_TXD_EOP_SHIFT 12 179 #define VMXNET3_TXD_CQ_SHIFT 13 180 #define VMXNET3_TXD_GEN_SHIFT 14 181 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 182 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 183 184 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 185 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 186 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 187 188 #define VMXNET3_TXD_GEN_SIZE 1 189 #define VMXNET3_TXD_EOP_SIZE 1 190 191 #define VMXNET3_HDR_COPY_SIZE 128 192 193 typedef 194 #include "vmware_pack_begin.h" 195 struct Vmxnet3_TxDataDesc { 196 uint8 data[VMXNET3_HDR_COPY_SIZE]; 197 } 198 #include "vmware_pack_end.h" 199 Vmxnet3_TxDataDesc; 200 201 #define VMXNET3_TCD_GEN_SHIFT 31 202 #define VMXNET3_TCD_GEN_SIZE 1 203 #define VMXNET3_TCD_TXIDX_SHIFT 0 204 #define VMXNET3_TCD_TXIDX_SIZE 12 205 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 206 207 typedef 208 #include "vmware_pack_begin.h" 209 struct Vmxnet3_TxCompDesc { 210 uint32 txdIdx:12; /* Index of the EOP TxDesc */ 211 uint32 ext1:20; 212 213 __le32 ext2; 214 __le32 ext3; 215 216 uint32 rsvd:24; 217 uint32 type:7; /* completion type */ 218 uint32 gen:1; /* generation bit */ 219 } 220 #include "vmware_pack_end.h" 221 Vmxnet3_TxCompDesc; 222 223 typedef 224 #include "vmware_pack_begin.h" 225 struct Vmxnet3_RxDesc { 226 __le64 addr; 227 228 #ifdef __BIG_ENDIAN_BITFIELD 229 uint32 gen:1; /* Generation bit */ 230 uint32 rsvd:15; 231 uint32 dtype:1; /* Descriptor type */ 232 uint32 btype:1; /* Buffer Type */ 233 uint32 len:14; 234 #else 235 uint32 len:14; 236 uint32 btype:1; /* Buffer Type */ 237 uint32 dtype:1; /* Descriptor type */ 238 uint32 rsvd:15; 239 uint32 gen:1; /* Generation bit */ 240 #endif 241 __le32 ext1; 242 } 243 #include "vmware_pack_end.h" 244 Vmxnet3_RxDesc; 245 246 /* values of RXD.BTYPE */ 247 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 248 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 249 250 /* fields in RxDesc we access w/o using bit fields */ 251 #define VMXNET3_RXD_BTYPE_SHIFT 14 252 #define VMXNET3_RXD_GEN_SHIFT 31 253 254 typedef 255 #include "vmware_pack_begin.h" 256 struct Vmxnet3_RxCompDesc { 257 #ifdef __BIG_ENDIAN_BITFIELD 258 uint32 ext2:1; 259 uint32 cnc:1; /* Checksum Not Calculated */ 260 uint32 rssType:4; /* RSS hash type used */ 261 uint32 rqID:10; /* rx queue/ring ID */ 262 uint32 sop:1; /* Start of Packet */ 263 uint32 eop:1; /* End of Packet */ 264 uint32 ext1:2; 265 uint32 rxdIdx:12; /* Index of the RxDesc */ 266 #else 267 uint32 rxdIdx:12; /* Index of the RxDesc */ 268 uint32 ext1:2; 269 uint32 eop:1; /* End of Packet */ 270 uint32 sop:1; /* Start of Packet */ 271 uint32 rqID:10; /* rx queue/ring ID */ 272 uint32 rssType:4; /* RSS hash type used */ 273 uint32 cnc:1; /* Checksum Not Calculated */ 274 uint32 ext2:1; 275 #endif /* __BIG_ENDIAN_BITFIELD */ 276 277 __le32 rssHash; /* RSS hash value */ 278 279 #ifdef __BIG_ENDIAN_BITFIELD 280 uint32 tci:16; /* Tag stripped */ 281 uint32 ts:1; /* Tag is stripped */ 282 uint32 err:1; /* Error */ 283 uint32 len:14; /* data length */ 284 #else 285 uint32 len:14; /* data length */ 286 uint32 err:1; /* Error */ 287 uint32 ts:1; /* Tag is stripped */ 288 uint32 tci:16; /* Tag stripped */ 289 #endif /* __BIG_ENDIAN_BITFIELD */ 290 291 292 #ifdef __BIG_ENDIAN_BITFIELD 293 uint32 gen:1; /* generation bit */ 294 uint32 type:7; /* completion type */ 295 uint32 fcs:1; /* Frame CRC correct */ 296 uint32 frg:1; /* IP Fragment */ 297 uint32 v4:1; /* IPv4 */ 298 uint32 v6:1; /* IPv6 */ 299 uint32 ipc:1; /* IP Checksum Correct */ 300 uint32 tcp:1; /* TCP packet */ 301 uint32 udp:1; /* UDP packet */ 302 uint32 tuc:1; /* TCP/UDP Checksum Correct */ 303 uint32 csum:16; 304 #else 305 uint32 csum:16; 306 uint32 tuc:1; /* TCP/UDP Checksum Correct */ 307 uint32 udp:1; /* UDP packet */ 308 uint32 tcp:1; /* TCP packet */ 309 uint32 ipc:1; /* IP Checksum Correct */ 310 uint32 v6:1; /* IPv6 */ 311 uint32 v4:1; /* IPv4 */ 312 uint32 frg:1; /* IP Fragment */ 313 uint32 fcs:1; /* Frame CRC correct */ 314 uint32 type:7; /* completion type */ 315 uint32 gen:1; /* generation bit */ 316 #endif /* __BIG_ENDIAN_BITFIELD */ 317 } 318 #include "vmware_pack_end.h" 319 Vmxnet3_RxCompDesc; 320 321 typedef 322 #include "vmware_pack_begin.h" 323 struct Vmxnet3_RxCompDescExt { 324 __le32 dword1; 325 uint8 segCnt; /* Number of aggregated packets */ 326 uint8 dupAckCnt; /* Number of duplicate Acks */ 327 __le16 tsDelta; /* TCP timestamp difference */ 328 __le32 dword2; 329 #ifdef __BIG_ENDIAN_BITFIELD 330 uint32 gen : 1; /* generation bit */ 331 uint32 type : 7; /* completion type */ 332 uint32 fcs : 1; /* Frame CRC correct */ 333 uint32 frg : 1; /* IP Fragment */ 334 uint32 v4 : 1; /* IPv4 */ 335 uint32 v6 : 1; /* IPv6 */ 336 uint32 ipc : 1; /* IP Checksum Correct */ 337 uint32 tcp : 1; /* TCP packet */ 338 uint32 udp : 1; /* UDP packet */ 339 uint32 tuc : 1; /* TCP/UDP Checksum Correct */ 340 uint32 mss : 16; 341 #else 342 uint32 mss : 16; 343 uint32 tuc : 1; /* TCP/UDP Checksum Correct */ 344 uint32 udp : 1; /* UDP packet */ 345 uint32 tcp : 1; /* TCP packet */ 346 uint32 ipc : 1; /* IP Checksum Correct */ 347 uint32 v6 : 1; /* IPv6 */ 348 uint32 v4 : 1; /* IPv4 */ 349 uint32 frg : 1; /* IP Fragment */ 350 uint32 fcs : 1; /* Frame CRC correct */ 351 uint32 type : 7; /* completion type */ 352 uint32 gen : 1; /* generation bit */ 353 #endif /* __BIG_ENDIAN_BITFIELD */ 354 } 355 #include "vmware_pack_end.h" 356 Vmxnet3_RxCompDescExt; 357 358 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 359 #define VMXNET3_RCD_TUC_SHIFT 16 360 #define VMXNET3_RCD_IPC_SHIFT 19 361 362 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 363 #define VMXNET3_RCD_TYPE_SHIFT 56 364 #define VMXNET3_RCD_GEN_SHIFT 63 365 366 /* csum OK for TCP/UDP pkts over IP */ 367 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT) 368 369 /* value of RxCompDesc.rssType */ 370 #define VMXNET3_RCD_RSS_TYPE_NONE 0 371 #define VMXNET3_RCD_RSS_TYPE_IPV4 1 372 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 373 #define VMXNET3_RCD_RSS_TYPE_IPV6 3 374 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 375 376 /* a union for accessing all cmd/completion descriptors */ 377 typedef union Vmxnet3_GenericDesc { 378 __le64 qword[2]; 379 __le32 dword[4]; 380 __le16 word[8]; 381 Vmxnet3_TxDesc txd; 382 Vmxnet3_RxDesc rxd; 383 Vmxnet3_TxCompDesc tcd; 384 Vmxnet3_RxCompDesc rcd; 385 Vmxnet3_RxCompDescExt rcdExt; 386 } Vmxnet3_GenericDesc; 387 388 #define VMXNET3_INIT_GEN 1 389 390 /* Max size of a single tx buffer */ 391 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 392 393 /* # of tx desc needed for a tx buffer size */ 394 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE) 395 396 /* max # of tx descs for a non-tso pkt */ 397 #define VMXNET3_MAX_TXD_PER_PKT 16 398 399 /* Max size of a single rx buffer */ 400 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 401 /* Minimum size of a type 0 buffer */ 402 #define VMXNET3_MIN_T0_BUF_SIZE 128 403 #define VMXNET3_MAX_CSUM_OFFSET 1024 404 405 /* Ring base address alignment */ 406 #define VMXNET3_RING_BA_ALIGN 512 407 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 408 409 /* Ring size must be a multiple of 32 */ 410 #define VMXNET3_RING_SIZE_ALIGN 32 411 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 412 413 /* Tx Data Ring buffer size must be a multiple of 64 */ 414 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 415 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) 416 417 /* Rx Data Ring buffer size must be a multiple of 64 */ 418 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64 419 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1) 420 421 /* Max ring size */ 422 #define VMXNET3_TX_RING_MAX_SIZE 4096 423 #define VMXNET3_TC_RING_MAX_SIZE 4096 424 #define VMXNET3_RX_RING_MAX_SIZE 4096 425 #define VMXNET3_RC_RING_MAX_SIZE 8192 426 427 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128 428 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 429 430 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 431 432 /* a list of reasons for queue stop */ 433 434 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */ 435 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */ 436 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */ 437 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */ 438 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */ 439 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */ 440 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */ 441 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */ 442 443 /* completion descriptor types */ 444 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 445 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 446 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */ 447 448 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */ 449 #define VMXNET3_GOS_BITS_32 1 450 #define VMXNET3_GOS_BITS_64 2 451 452 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 453 #define VMXNET3_GOS_TYPE_LINUX 1 454 #define VMXNET3_GOS_TYPE_WIN 2 455 #define VMXNET3_GOS_TYPE_SOLARIS 3 456 #define VMXNET3_GOS_TYPE_FREEBSD 4 457 #define VMXNET3_GOS_TYPE_PXE 5 458 459 /* All structures in DriverShared are padded to multiples of 8 bytes */ 460 461 typedef 462 #include "vmware_pack_begin.h" 463 struct Vmxnet3_GOSInfo { 464 #ifdef __BIG_ENDIAN_BITFIELD 465 uint32 gosMisc: 10; /* other info about gos */ 466 uint32 gosVer: 16; /* gos version */ 467 uint32 gosType: 4; /* which guest */ 468 uint32 gosBits: 2; /* 32-bit or 64-bit? */ 469 #else 470 uint32 gosBits: 2; /* 32-bit or 64-bit? */ 471 uint32 gosType: 4; /* which guest */ 472 uint32 gosVer: 16; /* gos version */ 473 uint32 gosMisc: 10; /* other info about gos */ 474 #endif /* __BIG_ENDIAN_BITFIELD */ 475 } 476 #include "vmware_pack_end.h" 477 Vmxnet3_GOSInfo; 478 479 typedef 480 #include "vmware_pack_begin.h" 481 struct Vmxnet3_DriverInfo { 482 __le32 version; /* driver version */ 483 Vmxnet3_GOSInfo gos; 484 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */ 485 __le32 uptVerSpt; /* upt version supported */ 486 } 487 #include "vmware_pack_end.h" 488 Vmxnet3_DriverInfo; 489 490 #define VMXNET3_REV1_MAGIC 0xbabefee1 491 492 /* 493 * QueueDescPA must be 128 bytes aligned. It points to an array of 494 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 495 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 496 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 497 */ 498 #define VMXNET3_QUEUE_DESC_ALIGN 128 499 500 typedef 501 #include "vmware_pack_begin.h" 502 struct Vmxnet3_MiscConf { 503 Vmxnet3_DriverInfo driverInfo; 504 __le64 uptFeatures; 505 __le64 ddPA; /* driver data PA */ 506 __le64 queueDescPA; /* queue descriptor table PA */ 507 __le32 ddLen; /* driver data len */ 508 __le32 queueDescLen; /* queue descriptor table len, in bytes */ 509 __le32 mtu; 510 __le16 maxNumRxSG; 511 uint8 numTxQueues; 512 uint8 numRxQueues; 513 __le32 reserved[4]; 514 } 515 #include "vmware_pack_end.h" 516 Vmxnet3_MiscConf; 517 518 typedef 519 #include "vmware_pack_begin.h" 520 struct Vmxnet3_TxQueueConf { 521 __le64 txRingBasePA; 522 __le64 dataRingBasePA; 523 __le64 compRingBasePA; 524 __le64 ddPA; /* driver data */ 525 __le64 reserved; 526 __le32 txRingSize; /* # of tx desc */ 527 __le32 dataRingSize; /* # of data desc */ 528 __le32 compRingSize; /* # of comp desc */ 529 __le32 ddLen; /* size of driver data */ 530 uint8 intrIdx; 531 uint8 _pad[1]; 532 __le16 txDataRingDescSize; 533 uint8 _pad2[4]; 534 } 535 #include "vmware_pack_end.h" 536 Vmxnet3_TxQueueConf; 537 538 typedef 539 #include "vmware_pack_begin.h" 540 struct Vmxnet3_RxQueueConf { 541 __le64 rxRingBasePA[2]; 542 __le64 compRingBasePA; 543 __le64 ddPA; /* driver data */ 544 __le64 rxDataRingBasePA; 545 __le32 rxRingSize[2]; /* # of rx desc */ 546 __le32 compRingSize; /* # of rx comp desc */ 547 __le32 ddLen; /* size of driver data */ 548 uint8 intrIdx; 549 uint8 _pad1[1]; 550 __le16 rxDataRingDescSize; /* size of rx data ring buffer */ 551 uint8 _pad2[4]; 552 } 553 #include "vmware_pack_end.h" 554 Vmxnet3_RxQueueConf; 555 556 enum vmxnet3_intr_mask_mode { 557 VMXNET3_IMM_AUTO = 0, 558 VMXNET3_IMM_ACTIVE = 1, 559 VMXNET3_IMM_LAZY = 2 560 }; 561 562 enum vmxnet3_intr_type { 563 VMXNET3_IT_AUTO = 0, 564 VMXNET3_IT_INTX = 1, 565 VMXNET3_IT_MSI = 2, 566 VMXNET3_IT_MSIX = 3 567 }; 568 569 #define VMXNET3_MAX_TX_QUEUES 8 570 #define VMXNET3_MAX_RX_QUEUES 16 571 /* addition 1 for events */ 572 #define VMXNET3_MAX_INTRS 25 573 574 /* value of intrCtrl */ 575 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 576 577 typedef 578 #include "vmware_pack_begin.h" 579 struct Vmxnet3_IntrConf { 580 bool autoMask; 581 uint8 numIntrs; /* # of interrupts */ 582 uint8 eventIntrIdx; 583 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */ 584 __le32 intrCtrl; 585 __le32 reserved[2]; 586 } 587 #include "vmware_pack_end.h" 588 Vmxnet3_IntrConf; 589 590 /* one bit per VLAN ID, the size is in the units of uint32 */ 591 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8)) 592 593 typedef 594 #include "vmware_pack_begin.h" 595 struct Vmxnet3_QueueStatus { 596 bool stopped; 597 uint8 _pad[3]; 598 __le32 error; 599 } 600 #include "vmware_pack_end.h" 601 Vmxnet3_QueueStatus; 602 603 typedef 604 #include "vmware_pack_begin.h" 605 struct Vmxnet3_TxQueueCtrl { 606 __le32 txNumDeferred; 607 __le32 txThreshold; 608 __le64 reserved; 609 } 610 #include "vmware_pack_end.h" 611 Vmxnet3_TxQueueCtrl; 612 613 typedef 614 #include "vmware_pack_begin.h" 615 struct Vmxnet3_RxQueueCtrl { 616 bool updateRxProd; 617 uint8 _pad[7]; 618 __le64 reserved; 619 } 620 #include "vmware_pack_end.h" 621 Vmxnet3_RxQueueCtrl; 622 623 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */ 624 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */ 625 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */ 626 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */ 627 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */ 628 629 typedef 630 #include "vmware_pack_begin.h" 631 struct Vmxnet3_RxFilterConf { 632 __le32 rxMode; /* VMXNET3_RXM_xxx */ 633 __le16 mfTableLen; /* size of the multicast filter table */ 634 __le16 _pad1; 635 __le64 mfTablePA; /* PA of the multicast filters table */ 636 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 637 } 638 #include "vmware_pack_end.h" 639 Vmxnet3_RxFilterConf; 640 641 #define VMXNET3_PM_MAX_FILTERS 6 642 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 643 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 644 645 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */ 646 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */ 647 648 typedef 649 #include "vmware_pack_begin.h" 650 struct Vmxnet3_PM_PktFilter { 651 uint8 maskSize; 652 uint8 patternSize; 653 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 654 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 655 uint8 pad[6]; 656 } 657 #include "vmware_pack_end.h" 658 Vmxnet3_PM_PktFilter; 659 660 typedef 661 #include "vmware_pack_begin.h" 662 struct Vmxnet3_PMConf { 663 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 664 uint8 numFilters; 665 uint8 pad[5]; 666 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 667 } 668 #include "vmware_pack_end.h" 669 Vmxnet3_PMConf; 670 671 typedef 672 #include "vmware_pack_begin.h" 673 struct Vmxnet3_VariableLenConfDesc { 674 __le32 confVer; 675 __le32 confLen; 676 __le64 confPA; 677 } 678 #include "vmware_pack_end.h" 679 Vmxnet3_VariableLenConfDesc; 680 681 typedef 682 #include "vmware_pack_begin.h" 683 struct Vmxnet3_DSDevRead { 684 /* read-only region for device, read by dev in response to a SET cmd */ 685 Vmxnet3_MiscConf misc; 686 Vmxnet3_IntrConf intrConf; 687 Vmxnet3_RxFilterConf rxFilterConf; 688 Vmxnet3_VariableLenConfDesc rssConfDesc; 689 Vmxnet3_VariableLenConfDesc pmConfDesc; 690 Vmxnet3_VariableLenConfDesc pluginConfDesc; 691 } 692 #include "vmware_pack_end.h" 693 Vmxnet3_DSDevRead; 694 695 typedef 696 #include "vmware_pack_begin.h" 697 struct Vmxnet3_TxQueueDesc { 698 Vmxnet3_TxQueueCtrl ctrl; 699 Vmxnet3_TxQueueConf conf; 700 /* Driver read after a GET command */ 701 Vmxnet3_QueueStatus status; 702 UPT1_TxStats stats; 703 uint8 _pad[88]; /* 128 aligned */ 704 } 705 #include "vmware_pack_end.h" 706 Vmxnet3_TxQueueDesc; 707 708 typedef 709 #include "vmware_pack_begin.h" 710 struct Vmxnet3_RxQueueDesc { 711 Vmxnet3_RxQueueCtrl ctrl; 712 Vmxnet3_RxQueueConf conf; 713 /* Driver read after a GET command */ 714 Vmxnet3_QueueStatus status; 715 UPT1_RxStats stats; 716 uint8 _pad[88]; /* 128 aligned */ 717 } 718 #include "vmware_pack_end.h" 719 Vmxnet3_RxQueueDesc; 720 721 typedef 722 #include "vmware_pack_begin.h" 723 struct Vmxnet3_SetPolling { 724 uint8 enablePolling; 725 } 726 #include "vmware_pack_end.h" 727 Vmxnet3_SetPolling; 728 729 typedef 730 #include "vmware_pack_begin.h" 731 struct Vmxnet3_MemoryRegion { 732 __le64 startPA; 733 __le32 length; 734 __le16 txQueueBits; /* bit n corresponding to tx queue n */ 735 __le16 rxQueueBits; /* bit n corresponding to rx queue n */ 736 } 737 #include "vmware_pack_end.h" 738 Vmxnet3_MemoryRegion; 739 740 #define MAX_MEMORY_REGION_PER_QUEUE 16 741 #define MAX_MEMORY_REGION_PER_DEVICE 256 742 743 typedef 744 #include "vmware_pack_begin.h" 745 struct Vmxnet3_MemRegs { 746 __le16 numRegs; 747 __le16 pad[3]; 748 Vmxnet3_MemoryRegion memRegs[1]; 749 } 750 #include "vmware_pack_end.h" 751 Vmxnet3_MemRegs; 752 753 typedef enum Vmxnet3_RSSField { 754 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001, 755 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002, 756 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004, 757 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008, 758 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010, 759 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020, 760 } Vmxnet3_RSSField; 761 762 /* 763 * If the command data <= 16 bytes, use the shared memory direcly. 764 * Otherwise, use the variable length configuration descriptor. 765 */ 766 typedef 767 #include "vmware_pack_begin.h" 768 union Vmxnet3_CmdInfo { 769 Vmxnet3_VariableLenConfDesc varConf; 770 Vmxnet3_SetPolling setPolling; 771 Vmxnet3_RSSField setRSSFields; 772 __le16 reserved[2]; 773 __le64 data[2]; 774 } 775 #include "vmware_pack_end.h" 776 Vmxnet3_CmdInfo; 777 778 typedef 779 #include "vmware_pack_begin.h" 780 struct Vmxnet3_DriverShared { 781 __le32 magic; 782 __le32 pad; /* make devRead start at 64-bit boundaries */ 783 Vmxnet3_DSDevRead devRead; 784 __le32 ecr; 785 __le32 reserved; 786 787 union { 788 __le32 reserved1[4]; 789 Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of executing the 790 * relevant command 791 */ 792 } cu; 793 } 794 #include "vmware_pack_end.h" 795 Vmxnet3_DriverShared; 796 797 #define VMXNET3_ECR_RQERR (1 << 0) 798 #define VMXNET3_ECR_TQERR (1 << 1) 799 #define VMXNET3_ECR_LINK (1 << 2) 800 #define VMXNET3_ECR_DIC (1 << 3) 801 #define VMXNET3_ECR_DEBUG (1 << 4) 802 803 /* flip the gen bit of a ring */ 804 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 805 806 /* only use this if moving the idx won't affect the gen bit */ 807 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 808 do {\ 809 (idx)++;\ 810 if (UNLIKELY((idx) == (ring_size))) {\ 811 (idx) = 0;\ 812 }\ 813 } while (0) 814 815 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 816 vfTable[vid >> 5] |= (1 << (vid & 31)) 817 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 818 vfTable[vid >> 5] &= ~(1 << (vid & 31)) 819 820 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 821 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 822 823 #define VMXNET3_MAX_MTU 9000 824 #define VMXNET3_MIN_MTU 60 825 826 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up 827 #define VMXNET3_LINK_DOWN 0 828 829 #define VMXWIFI_DRIVER_SHARED_LEN 8192 830 831 #define VMXNET3_DID_PASSTHRU 0xFFFF 832 833 #endif /* _VMXNET3_DEFS_H_ */ 834