1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include "txgbe_hw.h" 7 #include "txgbe_eeprom.h" 8 #include "txgbe_mng.h" 9 #include "txgbe_phy.h" 10 11 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr); 12 static void txgbe_i2c_stop(struct txgbe_hw *hw); 13 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw); 14 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, 15 u32 link_partner, struct txgbe_hw *hw); 16 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, 17 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw); 18 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw); 19 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw); 20 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode); 21 static s32 txgbe_check_kr_training(struct txgbe_hw *hw); 22 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, 23 s32 post, s32 mode); 24 static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed); 25 26 /** 27 * txgbe_identify_extphy - Identify a single address for a PHY 28 * @hw: pointer to hardware structure 29 * @phy_addr: PHY address to probe 30 * 31 * Returns true if PHY found 32 */ 33 static bool txgbe_identify_extphy(struct txgbe_hw *hw) 34 { 35 u16 phy_addr = 0; 36 37 if (!txgbe_validate_phy_addr(hw, phy_addr)) { 38 DEBUGOUT("Unable to validate PHY address 0x%04X", 39 phy_addr); 40 return false; 41 } 42 43 if (txgbe_get_phy_id(hw)) 44 return false; 45 46 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id); 47 if (hw->phy.type == txgbe_phy_unknown) { 48 u16 ext_ability = 0; 49 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY, 50 TXGBE_MD_DEV_PMA_PMD, 51 &ext_ability); 52 53 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY | 54 TXGBE_MD_PHY_1000BASET_ABILITY)) 55 hw->phy.type = txgbe_phy_cu_unknown; 56 else 57 hw->phy.type = txgbe_phy_generic; 58 } 59 60 return true; 61 } 62 63 /** 64 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register 65 * @hw: pointer to hardware structure 66 * 67 * Read TXGBE_ETHPHYIF register and save field values, 68 * and check for valid field values. 69 **/ 70 static s32 txgbe_read_phy_if(struct txgbe_hw *hw) 71 { 72 hw->phy.media_type = hw->phy.get_media_type(hw); 73 74 /* Save NW management interface connected on board. This is used 75 * to determine internal PHY mode. 76 */ 77 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF); 78 79 /* If MDIO is connected to external PHY, then set PHY address. */ 80 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT) 81 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel); 82 83 if (!hw->phy.phy_semaphore_mask) { 84 if (hw->bus.lan_id) 85 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; 86 else 87 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY; 88 } 89 90 return 0; 91 } 92 93 /** 94 * txgbe_identify_phy - Get physical layer module 95 * @hw: pointer to hardware structure 96 * 97 * Determines the physical layer module found on the current adapter. 98 **/ 99 s32 txgbe_identify_phy(struct txgbe_hw *hw) 100 { 101 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 102 103 txgbe_read_phy_if(hw); 104 105 if (hw->phy.type != txgbe_phy_unknown) 106 return 0; 107 108 /* Raptor 10GBASE-T requires an external PHY */ 109 if (hw->phy.media_type == txgbe_media_type_copper) { 110 err = txgbe_identify_extphy(hw); 111 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 112 err = txgbe_identify_module(hw); 113 } else { 114 hw->phy.type = txgbe_phy_none; 115 return 0; 116 } 117 118 /* Return error if SFP module has been detected but is not supported */ 119 if (hw->phy.type == txgbe_phy_sfp_unsupported) 120 return TXGBE_ERR_SFP_NOT_SUPPORTED; 121 122 return err; 123 } 124 125 /** 126 * txgbe_check_reset_blocked - check status of MNG FW veto bit 127 * @hw: pointer to the hardware structure 128 * 129 * This function checks the STAT.MNGVETO bit to see if there are 130 * any constraints on link from manageability. For MAC's that don't 131 * have this bit just return faluse since the link can not be blocked 132 * via this method. 133 **/ 134 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw) 135 { 136 u32 mmngc; 137 138 mmngc = rd32(hw, TXGBE_STAT); 139 if (mmngc & TXGBE_STAT_MNGVETO) { 140 DEBUGOUT("MNG_VETO bit detected."); 141 return true; 142 } 143 144 return false; 145 } 146 147 /** 148 * txgbe_validate_phy_addr - Determines phy address is valid 149 * @hw: pointer to hardware structure 150 * @phy_addr: PHY address 151 * 152 **/ 153 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr) 154 { 155 u16 phy_id = 0; 156 bool valid = false; 157 158 hw->phy.addr = phy_addr; 159 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, 160 TXGBE_MD_DEV_PMA_PMD, &phy_id); 161 162 if (phy_id != 0xFFFF && phy_id != 0x0) 163 valid = true; 164 165 DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id); 166 167 return valid; 168 } 169 170 /** 171 * txgbe_get_phy_id - Get the phy type 172 * @hw: pointer to hardware structure 173 * 174 **/ 175 s32 txgbe_get_phy_id(struct txgbe_hw *hw) 176 { 177 u32 err; 178 u16 phy_id_high = 0; 179 u16 phy_id_low = 0; 180 181 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH, 182 TXGBE_MD_DEV_PMA_PMD, 183 &phy_id_high); 184 185 if (err == 0) { 186 hw->phy.id = (u32)(phy_id_high << 16); 187 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW, 188 TXGBE_MD_DEV_PMA_PMD, 189 &phy_id_low); 190 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK); 191 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK); 192 } 193 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X", 194 phy_id_high, phy_id_low); 195 196 return err; 197 } 198 199 /** 200 * txgbe_get_phy_type_from_id - Get the phy type 201 * @phy_id: PHY ID information 202 * 203 **/ 204 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id) 205 { 206 enum txgbe_phy_type phy_type; 207 208 switch (phy_id) { 209 case TXGBE_PHYID_TN1010: 210 phy_type = txgbe_phy_tn; 211 break; 212 case TXGBE_PHYID_QT2022: 213 phy_type = txgbe_phy_qt; 214 break; 215 case TXGBE_PHYID_ATH: 216 phy_type = txgbe_phy_nl; 217 break; 218 case TXGBE_PHYID_MTD3310: 219 phy_type = txgbe_phy_cu_mtd; 220 break; 221 default: 222 phy_type = txgbe_phy_unknown; 223 break; 224 } 225 226 return phy_type; 227 } 228 229 static s32 230 txgbe_reset_extphy(struct txgbe_hw *hw) 231 { 232 u16 ctrl = 0; 233 int err, i; 234 235 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, 236 TXGBE_MD_DEV_GENERAL, &ctrl); 237 if (err != 0) 238 return err; 239 ctrl |= TXGBE_MD_PORT_CTRL_RESET; 240 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL, 241 TXGBE_MD_DEV_GENERAL, ctrl); 242 if (err != 0) 243 return err; 244 245 /* 246 * Poll for reset bit to self-clear indicating reset is complete. 247 * Some PHYs could take up to 3 seconds to complete and need about 248 * 1.7 usec delay after the reset is complete. 249 */ 250 for (i = 0; i < 30; i++) { 251 msec_delay(100); 252 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, 253 TXGBE_MD_DEV_GENERAL, &ctrl); 254 if (err != 0) 255 return err; 256 257 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) { 258 usec_delay(2); 259 break; 260 } 261 } 262 263 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) { 264 err = TXGBE_ERR_RESET_FAILED; 265 DEBUGOUT("PHY reset polling failed to complete."); 266 } 267 268 return err; 269 } 270 271 /** 272 * txgbe_reset_phy - Performs a PHY reset 273 * @hw: pointer to hardware structure 274 **/ 275 s32 txgbe_reset_phy(struct txgbe_hw *hw) 276 { 277 s32 err = 0; 278 279 if (hw->phy.type == txgbe_phy_unknown) 280 err = txgbe_identify_phy(hw); 281 282 if (err != 0 || hw->phy.type == txgbe_phy_none) 283 return err; 284 285 /* Don't reset PHY if it's shut down due to overtemp. */ 286 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP) 287 return err; 288 289 /* Blocked by MNG FW so bail */ 290 if (txgbe_check_reset_blocked(hw)) 291 return err; 292 293 switch (hw->phy.type) { 294 case txgbe_phy_cu_mtd: 295 err = txgbe_reset_extphy(hw); 296 break; 297 default: 298 break; 299 } 300 301 return err; 302 } 303 304 /** 305 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without 306 * the SWFW lock 307 * @hw: pointer to hardware structure 308 * @reg_addr: 32 bit address of PHY register to read 309 * @device_type: 5 bit device type 310 * @phy_data: Pointer to read data from PHY register 311 **/ 312 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, 313 u16 *phy_data) 314 { 315 u32 command, data; 316 317 /* Setup and write the address cycle command */ 318 command = TXGBE_MDIOSCA_REG(reg_addr) | 319 TXGBE_MDIOSCA_DEV(device_type) | 320 TXGBE_MDIOSCA_PORT(hw->phy.addr); 321 wr32(hw, TXGBE_MDIOSCA, command); 322 323 command = TXGBE_MDIOSCD_CMD_READ | 324 TXGBE_MDIOSCD_BUSY; 325 wr32(hw, TXGBE_MDIOSCD, command); 326 327 /* 328 * Check every 10 usec to see if the address cycle completed. 329 * The MDI Command bit will clear when the operation is 330 * complete 331 */ 332 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, 333 0, NULL, 100, 100)) { 334 DEBUGOUT("PHY address command did not complete"); 335 return TXGBE_ERR_PHY; 336 } 337 338 data = rd32(hw, TXGBE_MDIOSCD); 339 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data); 340 341 return 0; 342 } 343 344 /** 345 * txgbe_read_phy_reg - Reads a value from a specified PHY register 346 * using the SWFW lock - this function is needed in most cases 347 * @hw: pointer to hardware structure 348 * @reg_addr: 32 bit address of PHY register to read 349 * @device_type: 5 bit device type 350 * @phy_data: Pointer to read data from PHY register 351 **/ 352 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 353 u32 device_type, u16 *phy_data) 354 { 355 s32 err; 356 u32 gssr = hw->phy.phy_semaphore_mask; 357 358 if (hw->mac.acquire_swfw_sync(hw, gssr)) 359 return TXGBE_ERR_SWFW_SYNC; 360 361 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data); 362 363 hw->mac.release_swfw_sync(hw, gssr); 364 365 return err; 366 } 367 368 /** 369 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register 370 * without SWFW lock 371 * @hw: pointer to hardware structure 372 * @reg_addr: 32 bit PHY register to write 373 * @device_type: 5 bit device type 374 * @phy_data: Data to write to the PHY register 375 **/ 376 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, 377 u32 device_type, u16 phy_data) 378 { 379 u32 command; 380 381 /* write command */ 382 command = TXGBE_MDIOSCA_REG(reg_addr) | 383 TXGBE_MDIOSCA_DEV(device_type) | 384 TXGBE_MDIOSCA_PORT(hw->phy.addr); 385 wr32(hw, TXGBE_MDIOSCA, command); 386 387 command = TXGBE_MDIOSCD_CMD_WRITE | 388 TXGBE_MDIOSCD_DAT(phy_data) | 389 TXGBE_MDIOSCD_BUSY; 390 wr32(hw, TXGBE_MDIOSCD, command); 391 392 /* wait for completion */ 393 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, 394 0, NULL, 100, 100)) { 395 DEBUGOUT("PHY write cmd didn't complete"); 396 return -TERR_PHY; 397 } 398 399 return 0; 400 } 401 402 /** 403 * txgbe_write_phy_reg - Writes a value to specified PHY register 404 * using SWFW lock- this function is needed in most cases 405 * @hw: pointer to hardware structure 406 * @reg_addr: 32 bit PHY register to write 407 * @device_type: 5 bit device type 408 * @phy_data: Data to write to the PHY register 409 **/ 410 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, 411 u32 device_type, u16 phy_data) 412 { 413 s32 err; 414 u32 gssr = hw->phy.phy_semaphore_mask; 415 416 if (hw->mac.acquire_swfw_sync(hw, gssr)) 417 err = TXGBE_ERR_SWFW_SYNC; 418 419 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type, 420 phy_data); 421 hw->mac.release_swfw_sync(hw, gssr); 422 423 return err; 424 } 425 426 /** 427 * txgbe_setup_phy_link - Set and restart auto-neg 428 * @hw: pointer to hardware structure 429 * 430 * Restart auto-negotiation and PHY and waits for completion. 431 **/ 432 s32 txgbe_setup_phy_link(struct txgbe_hw *hw) 433 { 434 s32 err = 0; 435 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG; 436 bool autoneg = false; 437 u32 speed; 438 439 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg); 440 441 /* Set or unset auto-negotiation 10G advertisement */ 442 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 443 TXGBE_MD_DEV_AUTO_NEG, 444 &autoneg_reg); 445 446 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE; 447 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) && 448 (speed & TXGBE_LINK_SPEED_10GB_FULL)) 449 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE; 450 451 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 452 TXGBE_MD_DEV_AUTO_NEG, 453 autoneg_reg); 454 455 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 456 TXGBE_MD_DEV_AUTO_NEG, 457 &autoneg_reg); 458 459 /* Set or unset auto-negotiation 5G advertisement */ 460 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE; 461 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) && 462 (speed & TXGBE_LINK_SPEED_5GB_FULL)) 463 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE; 464 465 /* Set or unset auto-negotiation 2.5G advertisement */ 466 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE; 467 if ((hw->phy.autoneg_advertised & 468 TXGBE_LINK_SPEED_2_5GB_FULL) && 469 (speed & TXGBE_LINK_SPEED_2_5GB_FULL)) 470 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE; 471 /* Set or unset auto-negotiation 1G advertisement */ 472 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE; 473 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) && 474 (speed & TXGBE_LINK_SPEED_1GB_FULL)) 475 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE; 476 477 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 478 TXGBE_MD_DEV_AUTO_NEG, 479 autoneg_reg); 480 481 /* Set or unset auto-negotiation 100M advertisement */ 482 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 483 TXGBE_MD_DEV_AUTO_NEG, 484 &autoneg_reg); 485 486 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE | 487 TXGBE_MII_100BASE_T_ADVERTISE_HALF); 488 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) && 489 (speed & TXGBE_LINK_SPEED_100M_FULL)) 490 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE; 491 492 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 493 TXGBE_MD_DEV_AUTO_NEG, 494 autoneg_reg); 495 496 /* Blocked by MNG FW so don't reset PHY */ 497 if (txgbe_check_reset_blocked(hw)) 498 return err; 499 500 /* Restart PHY auto-negotiation. */ 501 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 502 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg); 503 504 autoneg_reg |= TXGBE_MII_RESTART; 505 506 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 507 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg); 508 509 return err; 510 } 511 512 /** 513 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities 514 * @hw: pointer to hardware structure 515 * @speed: new link speed 516 * @autoneg_wait_to_complete: unused 517 **/ 518 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw, 519 u32 speed, 520 bool autoneg_wait_to_complete) 521 { 522 UNREFERENCED_PARAMETER(autoneg_wait_to_complete); 523 524 /* 525 * Clear autoneg_advertised and set new values based on input link 526 * speed. 527 */ 528 hw->phy.autoneg_advertised = 0; 529 530 if (speed & TXGBE_LINK_SPEED_10GB_FULL) 531 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL; 532 533 if (speed & TXGBE_LINK_SPEED_5GB_FULL) 534 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL; 535 536 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL) 537 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL; 538 539 if (speed & TXGBE_LINK_SPEED_1GB_FULL) 540 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL; 541 542 if (speed & TXGBE_LINK_SPEED_100M_FULL) 543 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL; 544 545 if (speed & TXGBE_LINK_SPEED_10M_FULL) 546 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL; 547 548 /* Setup link based on the new speed settings */ 549 hw->phy.setup_link(hw); 550 551 return 0; 552 } 553 554 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version) 555 { 556 u16 eeprom_verh, eeprom_verl; 557 558 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh); 559 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl); 560 561 *fw_version = (eeprom_verh << 16) | eeprom_verl; 562 563 return 0; 564 } 565 566 /** 567 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy 568 * @hw: pointer to hardware structure 569 * 570 * Determines the supported link capabilities by reading the PHY auto 571 * negotiation register. 572 **/ 573 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw) 574 { 575 s32 err; 576 u16 speed_ability; 577 578 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY, 579 TXGBE_MD_DEV_PMA_PMD, 580 &speed_ability); 581 if (err) 582 return err; 583 584 if (speed_ability & TXGBE_MD_PHY_SPEED_10G) 585 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL; 586 if (speed_ability & TXGBE_MD_PHY_SPEED_1G) 587 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL; 588 if (speed_ability & TXGBE_MD_PHY_SPEED_100M) 589 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL; 590 591 return err; 592 } 593 594 /** 595 * txgbe_get_copper_link_capabilities - Determines link capabilities 596 * @hw: pointer to hardware structure 597 * @speed: pointer to link speed 598 * @autoneg: boolean auto-negotiation value 599 **/ 600 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw, 601 u32 *speed, 602 bool *autoneg) 603 { 604 s32 err = 0; 605 606 *autoneg = true; 607 if (!hw->phy.speeds_supported) 608 err = txgbe_get_copper_speeds_supported(hw); 609 610 *speed = hw->phy.speeds_supported; 611 return err; 612 } 613 614 /** 615 * txgbe_check_phy_link_tnx - Determine link and speed status 616 * @hw: pointer to hardware structure 617 * @speed: current link speed 618 * @link_up: true is link is up, false otherwise 619 * 620 * Reads the VS1 register to determine if link is up and the current speed for 621 * the PHY. 622 **/ 623 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed, 624 bool *link_up) 625 { 626 s32 err = 0; 627 u32 time_out; 628 u32 max_time_out = 10; 629 u16 phy_link = 0; 630 u16 phy_speed = 0; 631 u16 phy_data = 0; 632 633 /* Initialize speed and link to default case */ 634 *link_up = false; 635 *speed = TXGBE_LINK_SPEED_10GB_FULL; 636 637 /* 638 * Check current speed and link status of the PHY register. 639 * This is a vendor specific register and may have to 640 * be changed for other copper PHYs. 641 */ 642 for (time_out = 0; time_out < max_time_out; time_out++) { 643 usec_delay(10); 644 err = hw->phy.read_reg(hw, 645 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS, 646 TXGBE_MD_DEV_VENDOR_1, 647 &phy_data); 648 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS; 649 phy_speed = phy_data & 650 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS; 651 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) { 652 *link_up = true; 653 if (phy_speed == 654 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS) 655 *speed = TXGBE_LINK_SPEED_1GB_FULL; 656 break; 657 } 658 } 659 660 return err; 661 } 662 663 /** 664 * txgbe_setup_phy_link_tnx - Set and restart auto-neg 665 * @hw: pointer to hardware structure 666 * 667 * Restart auto-negotiation and PHY and waits for completion. 668 **/ 669 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw) 670 { 671 s32 err = 0; 672 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG; 673 bool autoneg = false; 674 u32 speed; 675 676 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg); 677 678 if (speed & TXGBE_LINK_SPEED_10GB_FULL) { 679 /* Set or unset auto-negotiation 10G advertisement */ 680 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 681 TXGBE_MD_DEV_AUTO_NEG, 682 &autoneg_reg); 683 684 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE; 685 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) 686 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE; 687 688 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 689 TXGBE_MD_DEV_AUTO_NEG, 690 autoneg_reg); 691 } 692 693 if (speed & TXGBE_LINK_SPEED_1GB_FULL) { 694 /* Set or unset auto-negotiation 1G advertisement */ 695 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG, 696 TXGBE_MD_DEV_AUTO_NEG, 697 &autoneg_reg); 698 699 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 700 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) 701 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 702 703 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG, 704 TXGBE_MD_DEV_AUTO_NEG, 705 autoneg_reg); 706 } 707 708 if (speed & TXGBE_LINK_SPEED_100M_FULL) { 709 /* Set or unset auto-negotiation 100M advertisement */ 710 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 711 TXGBE_MD_DEV_AUTO_NEG, 712 &autoneg_reg); 713 714 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE; 715 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) 716 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE; 717 718 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG, 719 TXGBE_MD_DEV_AUTO_NEG, 720 autoneg_reg); 721 } 722 723 /* Blocked by MNG FW so don't reset PHY */ 724 if (txgbe_check_reset_blocked(hw)) 725 return err; 726 727 /* Restart PHY auto-negotiation. */ 728 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 729 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg); 730 731 autoneg_reg |= TXGBE_MII_RESTART; 732 733 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL, 734 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg); 735 736 return err; 737 } 738 739 /** 740 * txgbe_identify_module - Identifies module type 741 * @hw: pointer to hardware structure 742 * 743 * Determines HW type and calls appropriate function. 744 **/ 745 s32 txgbe_identify_module(struct txgbe_hw *hw) 746 { 747 s32 err = TXGBE_ERR_SFP_NOT_PRESENT; 748 749 switch (hw->phy.media_type) { 750 case txgbe_media_type_fiber: 751 err = txgbe_identify_sfp_module(hw); 752 break; 753 754 case txgbe_media_type_fiber_qsfp: 755 err = txgbe_identify_qsfp_module(hw); 756 break; 757 758 default: 759 hw->phy.sfp_type = txgbe_sfp_type_not_present; 760 err = TXGBE_ERR_SFP_NOT_PRESENT; 761 break; 762 } 763 764 return err; 765 } 766 767 /** 768 * txgbe_identify_sfp_module - Identifies SFP modules 769 * @hw: pointer to hardware structure 770 * 771 * Searches for and identifies the SFP module and assigns appropriate PHY type. 772 **/ 773 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw) 774 { 775 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 776 u32 vendor_oui = 0; 777 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 778 u8 identifier = 0; 779 u8 comp_codes_1g = 0; 780 u8 comp_codes_10g = 0; 781 u8 oui_bytes[3] = {0, 0, 0}; 782 u8 cable_tech = 0; 783 u8 cable_spec = 0; 784 u16 enforce_sfp = 0; 785 786 if (hw->phy.media_type != txgbe_media_type_fiber) { 787 hw->phy.sfp_type = txgbe_sfp_type_not_present; 788 return TXGBE_ERR_SFP_NOT_PRESENT; 789 } 790 791 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER, 792 &identifier); 793 if (err != 0) { 794 ERR_I2C: 795 hw->phy.sfp_type = txgbe_sfp_type_not_present; 796 if (hw->phy.type != txgbe_phy_nl) { 797 hw->phy.id = 0; 798 hw->phy.type = txgbe_phy_unknown; 799 } 800 return TXGBE_ERR_SFP_NOT_PRESENT; 801 } 802 803 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) { 804 hw->phy.type = txgbe_phy_sfp_unsupported; 805 return TXGBE_ERR_SFP_NOT_SUPPORTED; 806 } 807 808 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES, 809 &comp_codes_1g); 810 if (err != 0) 811 goto ERR_I2C; 812 813 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES, 814 &comp_codes_10g); 815 if (err != 0) 816 goto ERR_I2C; 817 818 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY, 819 &cable_tech); 820 if (err != 0) 821 goto ERR_I2C; 822 823 /* ID Module 824 * ========= 825 * 0 SFP_DA_CU 826 * 1 SFP_SR 827 * 2 SFP_LR 828 * 3 SFP_DA_CORE0 - chip-specific 829 * 4 SFP_DA_CORE1 - chip-specific 830 * 5 SFP_SR/LR_CORE0 - chip-specific 831 * 6 SFP_SR/LR_CORE1 - chip-specific 832 * 7 SFP_act_lmt_DA_CORE0 - chip-specific 833 * 8 SFP_act_lmt_DA_CORE1 - chip-specific 834 * 9 SFP_1g_cu_CORE0 - chip-specific 835 * 10 SFP_1g_cu_CORE1 - chip-specific 836 * 11 SFP_1g_sx_CORE0 - chip-specific 837 * 12 SFP_1g_sx_CORE1 - chip-specific 838 */ 839 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) { 840 if (hw->bus.lan_id == 0) 841 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; 842 else 843 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; 844 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) { 845 err = hw->phy.read_i2c_eeprom(hw, 846 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec); 847 if (err != 0) 848 goto ERR_I2C; 849 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 850 hw->phy.sfp_type = (hw->bus.lan_id == 0 851 ? txgbe_sfp_type_da_act_lmt_core0 852 : txgbe_sfp_type_da_act_lmt_core1); 853 } else { 854 hw->phy.sfp_type = txgbe_sfp_type_unknown; 855 } 856 } else if (comp_codes_10g & 857 (TXGBE_SFF_10GBASESR_CAPABLE | 858 TXGBE_SFF_10GBASELR_CAPABLE)) { 859 hw->phy.sfp_type = (hw->bus.lan_id == 0 860 ? txgbe_sfp_type_srlr_core0 861 : txgbe_sfp_type_srlr_core1); 862 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) { 863 hw->phy.sfp_type = (hw->bus.lan_id == 0 864 ? txgbe_sfp_type_1g_cu_core0 865 : txgbe_sfp_type_1g_cu_core1); 866 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) { 867 hw->phy.sfp_type = (hw->bus.lan_id == 0 868 ? txgbe_sfp_type_1g_sx_core0 869 : txgbe_sfp_type_1g_sx_core1); 870 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) { 871 hw->phy.sfp_type = (hw->bus.lan_id == 0 872 ? txgbe_sfp_type_1g_lx_core0 873 : txgbe_sfp_type_1g_lx_core1); 874 } else { 875 hw->phy.sfp_type = txgbe_sfp_type_unknown; 876 } 877 878 if (hw->phy.sfp_type != stored_sfp_type) 879 hw->phy.sfp_setup_needed = true; 880 881 /* Determine if the SFP+ PHY is dual speed or not. */ 882 hw->phy.multispeed_fiber = false; 883 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && 884 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || 885 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && 886 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) 887 hw->phy.multispeed_fiber = true; 888 889 /* Determine PHY vendor */ 890 if (hw->phy.type != txgbe_phy_nl) { 891 hw->phy.id = identifier; 892 err = hw->phy.read_i2c_eeprom(hw, 893 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]); 894 if (err != 0) 895 goto ERR_I2C; 896 897 err = hw->phy.read_i2c_eeprom(hw, 898 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]); 899 if (err != 0) 900 goto ERR_I2C; 901 902 err = hw->phy.read_i2c_eeprom(hw, 903 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]); 904 if (err != 0) 905 goto ERR_I2C; 906 907 vendor_oui = ((u32)oui_bytes[0] << 24) | 908 ((u32)oui_bytes[1] << 16) | 909 ((u32)oui_bytes[2] << 8); 910 switch (vendor_oui) { 911 case TXGBE_SFF_VENDOR_OUI_TYCO: 912 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) 913 hw->phy.type = txgbe_phy_sfp_tyco_passive; 914 break; 915 case TXGBE_SFF_VENDOR_OUI_FTL: 916 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) 917 hw->phy.type = txgbe_phy_sfp_ftl_active; 918 else 919 hw->phy.type = txgbe_phy_sfp_ftl; 920 break; 921 case TXGBE_SFF_VENDOR_OUI_AVAGO: 922 hw->phy.type = txgbe_phy_sfp_avago; 923 break; 924 case TXGBE_SFF_VENDOR_OUI_INTEL: 925 hw->phy.type = txgbe_phy_sfp_intel; 926 break; 927 default: 928 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) 929 hw->phy.type = txgbe_phy_sfp_unknown_passive; 930 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) 931 hw->phy.type = txgbe_phy_sfp_unknown_active; 932 else 933 hw->phy.type = txgbe_phy_sfp_unknown; 934 break; 935 } 936 } 937 938 /* Allow any DA cable vendor */ 939 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE | 940 TXGBE_SFF_CABLE_DA_ACTIVE)) { 941 return 0; 942 } 943 944 /* Verify supported 1G SFP modules */ 945 if (comp_codes_10g == 0 && 946 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 || 947 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 || 948 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 || 949 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 || 950 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 || 951 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) { 952 hw->phy.type = txgbe_phy_sfp_unsupported; 953 return TXGBE_ERR_SFP_NOT_SUPPORTED; 954 } 955 956 hw->mac.get_device_caps(hw, &enforce_sfp); 957 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 958 !hw->allow_unsupported_sfp && 959 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 || 960 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 || 961 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 || 962 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 || 963 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 || 964 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) { 965 DEBUGOUT("SFP+ module not supported"); 966 hw->phy.type = txgbe_phy_sfp_unsupported; 967 return TXGBE_ERR_SFP_NOT_SUPPORTED; 968 } 969 970 return err; 971 } 972 973 /** 974 * txgbe_identify_qsfp_module - Identifies QSFP modules 975 * @hw: pointer to hardware structure 976 * 977 * Searches for and identifies the QSFP module and assigns appropriate PHY type 978 **/ 979 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw) 980 { 981 s32 err = TXGBE_ERR_PHY_ADDR_INVALID; 982 u32 vendor_oui = 0; 983 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 984 u8 identifier = 0; 985 u8 comp_codes_1g = 0; 986 u8 comp_codes_10g = 0; 987 u8 oui_bytes[3] = {0, 0, 0}; 988 u16 enforce_sfp = 0; 989 u8 connector = 0; 990 u8 cable_length = 0; 991 u8 device_tech = 0; 992 bool active_cable = false; 993 994 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) { 995 hw->phy.sfp_type = txgbe_sfp_type_not_present; 996 err = TXGBE_ERR_SFP_NOT_PRESENT; 997 goto out; 998 } 999 1000 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER, 1001 &identifier); 1002 ERR_I2C: 1003 if (err != 0) { 1004 hw->phy.sfp_type = txgbe_sfp_type_not_present; 1005 hw->phy.id = 0; 1006 hw->phy.type = txgbe_phy_unknown; 1007 return TXGBE_ERR_SFP_NOT_PRESENT; 1008 } 1009 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1010 hw->phy.type = txgbe_phy_sfp_unsupported; 1011 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1012 goto out; 1013 } 1014 1015 hw->phy.id = identifier; 1016 1017 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP, 1018 &comp_codes_10g); 1019 1020 if (err != 0) 1021 goto ERR_I2C; 1022 1023 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP, 1024 &comp_codes_1g); 1025 1026 if (err != 0) 1027 goto ERR_I2C; 1028 1029 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1030 hw->phy.type = txgbe_phy_qsfp_unknown_passive; 1031 if (hw->bus.lan_id == 0) 1032 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0; 1033 else 1034 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1; 1035 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | 1036 TXGBE_SFF_10GBASELR_CAPABLE)) { 1037 if (hw->bus.lan_id == 0) 1038 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0; 1039 else 1040 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1; 1041 } else { 1042 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1043 active_cable = true; 1044 1045 if (!active_cable) { 1046 hw->phy.read_i2c_eeprom(hw, 1047 TXGBE_SFF_QSFP_CONNECTOR, 1048 &connector); 1049 1050 hw->phy.read_i2c_eeprom(hw, 1051 TXGBE_SFF_QSFP_CABLE_LENGTH, 1052 &cable_length); 1053 1054 hw->phy.read_i2c_eeprom(hw, 1055 TXGBE_SFF_QSFP_DEVICE_TECH, 1056 &device_tech); 1057 1058 if (connector == 1059 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE && 1060 cable_length > 0 && 1061 ((device_tech >> 4) == 1062 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL)) 1063 active_cable = true; 1064 } 1065 1066 if (active_cable) { 1067 hw->phy.type = txgbe_phy_qsfp_unknown_active; 1068 if (hw->bus.lan_id == 0) 1069 hw->phy.sfp_type = 1070 txgbe_sfp_type_da_act_lmt_core0; 1071 else 1072 hw->phy.sfp_type = 1073 txgbe_sfp_type_da_act_lmt_core1; 1074 } else { 1075 /* unsupported module type */ 1076 hw->phy.type = txgbe_phy_sfp_unsupported; 1077 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1078 goto out; 1079 } 1080 } 1081 1082 if (hw->phy.sfp_type != stored_sfp_type) 1083 hw->phy.sfp_setup_needed = true; 1084 1085 /* Determine if the QSFP+ PHY is dual speed or not. */ 1086 hw->phy.multispeed_fiber = false; 1087 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) && 1088 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) || 1089 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) && 1090 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE))) 1091 hw->phy.multispeed_fiber = true; 1092 1093 /* Determine PHY vendor for optical modules */ 1094 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE | 1095 TXGBE_SFF_10GBASELR_CAPABLE)) { 1096 err = hw->phy.read_i2c_eeprom(hw, 1097 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1098 &oui_bytes[0]); 1099 1100 if (err != 0) 1101 goto ERR_I2C; 1102 1103 err = hw->phy.read_i2c_eeprom(hw, 1104 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1105 &oui_bytes[1]); 1106 1107 if (err != 0) 1108 goto ERR_I2C; 1109 1110 err = hw->phy.read_i2c_eeprom(hw, 1111 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1112 &oui_bytes[2]); 1113 1114 if (err != 0) 1115 goto ERR_I2C; 1116 1117 vendor_oui = 1118 ((oui_bytes[0] << 24) | 1119 (oui_bytes[1] << 16) | 1120 (oui_bytes[2] << 8)); 1121 1122 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL) 1123 hw->phy.type = txgbe_phy_qsfp_intel; 1124 else 1125 hw->phy.type = txgbe_phy_qsfp_unknown; 1126 1127 hw->mac.get_device_caps(hw, &enforce_sfp); 1128 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1129 /* Make sure we're a supported PHY type */ 1130 if (hw->phy.type == txgbe_phy_qsfp_intel) { 1131 err = 0; 1132 } else { 1133 if (hw->allow_unsupported_sfp) { 1134 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. " 1135 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. " 1136 "Wangxun Corporation is not responsible for any harm caused by using untested modules."); 1137 err = 0; 1138 } else { 1139 DEBUGOUT("QSFP module not supported"); 1140 hw->phy.type = 1141 txgbe_phy_sfp_unsupported; 1142 err = TXGBE_ERR_SFP_NOT_SUPPORTED; 1143 } 1144 } 1145 } else { 1146 err = 0; 1147 } 1148 } 1149 1150 out: 1151 return err; 1152 } 1153 1154 /** 1155 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1156 * @hw: pointer to hardware structure 1157 * @byte_offset: EEPROM byte offset to read 1158 * @eeprom_data: value read 1159 * 1160 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1161 **/ 1162 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 1163 u8 *eeprom_data) 1164 { 1165 return hw->phy.read_i2c_byte(hw, byte_offset, 1166 TXGBE_I2C_EEPROM_DEV_ADDR, 1167 eeprom_data); 1168 } 1169 1170 /** 1171 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface 1172 * @hw: pointer to hardware structure 1173 * @byte_offset: byte offset at address 0xA2 1174 * @sff8472_data: value read 1175 * 1176 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1177 **/ 1178 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset, 1179 u8 *sff8472_data) 1180 { 1181 return hw->phy.read_i2c_byte(hw, byte_offset, 1182 TXGBE_I2C_EEPROM_DEV_ADDR2, 1183 sff8472_data); 1184 } 1185 1186 /** 1187 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1188 * @hw: pointer to hardware structure 1189 * @byte_offset: EEPROM byte offset to write 1190 * @eeprom_data: value to write 1191 * 1192 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1193 **/ 1194 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset, 1195 u8 eeprom_data) 1196 { 1197 return hw->phy.write_i2c_byte(hw, byte_offset, 1198 TXGBE_I2C_EEPROM_DEV_ADDR, 1199 eeprom_data); 1200 } 1201 1202 /** 1203 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C 1204 * @hw: pointer to hardware structure 1205 * @byte_offset: byte offset to read 1206 * @dev_addr: address to read from 1207 * @data: value read 1208 * 1209 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1210 * a specified device address. 1211 **/ 1212 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 1213 u8 dev_addr, u8 *data) 1214 { 1215 txgbe_i2c_start(hw, dev_addr); 1216 1217 /* wait tx empty */ 1218 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, 1219 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) { 1220 return -TERR_TIMEOUT; 1221 } 1222 1223 /* read data */ 1224 wr32(hw, TXGBE_I2CDATA, 1225 byte_offset | TXGBE_I2CDATA_STOP); 1226 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ); 1227 1228 /* wait for read complete */ 1229 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL, 1230 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) { 1231 return -TERR_TIMEOUT; 1232 } 1233 1234 txgbe_i2c_stop(hw); 1235 1236 *data = 0xFF & rd32(hw, TXGBE_I2CDATA); 1237 1238 return 0; 1239 } 1240 1241 /** 1242 * txgbe_read_i2c_byte - Reads 8 bit word over I2C 1243 * @hw: pointer to hardware structure 1244 * @byte_offset: byte offset to read 1245 * @dev_addr: address to read from 1246 * @data: value read 1247 * 1248 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1249 * a specified device address. 1250 **/ 1251 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 1252 u8 dev_addr, u8 *data) 1253 { 1254 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1255 int err = 0; 1256 1257 if (hw->mac.acquire_swfw_sync(hw, swfw_mask)) 1258 return TXGBE_ERR_SWFW_SYNC; 1259 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data); 1260 hw->mac.release_swfw_sync(hw, swfw_mask); 1261 return err; 1262 } 1263 1264 /** 1265 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1266 * @hw: pointer to hardware structure 1267 * @byte_offset: byte offset to write 1268 * @dev_addr: address to write to 1269 * @data: value to write 1270 * 1271 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1272 * a specified device address. 1273 **/ 1274 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, 1275 u8 dev_addr, u8 data) 1276 { 1277 txgbe_i2c_start(hw, dev_addr); 1278 1279 /* wait tx empty */ 1280 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY, 1281 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) { 1282 return -TERR_TIMEOUT; 1283 } 1284 1285 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP); 1286 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE); 1287 1288 /* wait for write complete */ 1289 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL, 1290 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) { 1291 return -TERR_TIMEOUT; 1292 } 1293 txgbe_i2c_stop(hw); 1294 1295 return 0; 1296 } 1297 1298 /** 1299 * txgbe_write_i2c_byte - Writes 8 bit word over I2C 1300 * @hw: pointer to hardware structure 1301 * @byte_offset: byte offset to write 1302 * @dev_addr: address to write to 1303 * @data: value to write 1304 * 1305 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1306 * a specified device address. 1307 **/ 1308 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, 1309 u8 dev_addr, u8 data) 1310 { 1311 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1312 int err = 0; 1313 1314 if (hw->mac.acquire_swfw_sync(hw, swfw_mask)) 1315 return TXGBE_ERR_SWFW_SYNC; 1316 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data); 1317 hw->mac.release_swfw_sync(hw, swfw_mask); 1318 1319 return err; 1320 } 1321 1322 /** 1323 * txgbe_i2c_start - Sets I2C start condition 1324 * @hw: pointer to hardware structure 1325 * 1326 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1327 **/ 1328 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr) 1329 { 1330 wr32(hw, TXGBE_I2CENA, 0); 1331 1332 wr32(hw, TXGBE_I2CCON, 1333 (TXGBE_I2CCON_MENA | 1334 TXGBE_I2CCON_SPEED(1) | 1335 TXGBE_I2CCON_RESTART | 1336 TXGBE_I2CCON_SDIA)); 1337 wr32(hw, TXGBE_I2CTAR, dev_addr >> 1); 1338 wr32(hw, TXGBE_I2CSSSCLHCNT, 200); 1339 wr32(hw, TXGBE_I2CSSSCLLCNT, 200); 1340 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */ 1341 wr32(hw, TXGBE_I2CTXTL, 4); 1342 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF); 1343 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF); 1344 1345 wr32(hw, TXGBE_I2CICM, 0); 1346 wr32(hw, TXGBE_I2CENA, 1); 1347 } 1348 1349 /** 1350 * txgbe_i2c_stop - Sets I2C stop condition 1351 * @hw: pointer to hardware structure 1352 * 1353 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1354 **/ 1355 static void txgbe_i2c_stop(struct txgbe_hw *hw) 1356 { 1357 /* wait for completion */ 1358 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST, 1359 0, NULL, 100, 100)) { 1360 DEBUGOUT("i2c stop timeout."); 1361 } 1362 1363 wr32(hw, TXGBE_I2CENA, 0); 1364 } 1365 1366 static void 1367 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) 1368 { 1369 u32 value; 1370 u8 device_type = hw->subsystem_device_id & 0xF0; 1371 1372 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002); 1373 /* for sgmii + external phy, set to 0x0105 (phy sgmii mode) */ 1374 /* for sgmii direct link, set to 0x010c (mac sgmii mode) */ 1375 if (device_type == TXGBE_DEV_ID_MAC_SGMII || 1376 hw->phy.media_type == txgbe_media_type_fiber) 1377 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x010C); 1378 else if (device_type == TXGBE_DEV_ID_SGMII || 1379 device_type == TXGBE_DEV_ID_XAUI) 1380 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105); 1381 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200); 1382 value = rd32_epcs(hw, SR_MII_MMD_CTL); 1383 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9); 1384 wr32_epcs(hw, SR_MII_MMD_CTL, value); 1385 } 1386 1387 static s32 1388 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg) 1389 { 1390 u32 i; 1391 u16 value; 1392 s32 err = 0; 1393 1394 /* 1. Wait xpcs power-up good */ 1395 for (i = 0; i < 100; i++) { 1396 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1397 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1398 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1399 break; 1400 msec_delay(10); 1401 } 1402 if (i == 100) { 1403 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1404 goto out; 1405 } 1406 BP_LOG("It is set to kr.\n"); 1407 1408 wr32_epcs(hw, VR_AN_INTR_MSK, 0x7); 1409 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC); 1410 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC); 1411 1412 if (!autoneg) { 1413 /* 2. Disable xpcs AN-73 */ 1414 wr32_epcs(hw, SR_AN_CTRL, 1415 SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP); 1416 1417 wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET); 1418 1419 if (!(hw->devarg.auto_neg == 1)) { 1420 wr32_epcs(hw, SR_AN_CTRL, 0); 1421 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 1422 } else { 1423 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 1424 value &= ~(1 << 6); 1425 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1426 } 1427 if (hw->devarg.present == 1) { 1428 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 1429 value |= TXGBE_PHY_TX_EQ_CTL1_DEF; 1430 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1431 } 1432 if (hw->devarg.poll == 1) { 1433 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0, 1434 VR_PMA_KRTR_TIMER_MAX_WAIT); 1435 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697); 1436 } 1437 1438 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register 1439 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16) 1440 */ 1441 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1442 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR); 1443 1444 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 1445 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11) 1446 */ 1447 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1448 1449 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 1450 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77 1451 * Bit[7:5](CTLE_POLE_0) = 3'h2 1452 * Bit[4:0](CTLE_BOOST_0) = 4'hA 1453 */ 1454 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A); 1455 1456 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register 1457 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3) 1458 */ 1459 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004); 1460 1461 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital 1462 * Control1 Register Bit[15](VR_RST) 1463 */ 1464 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1465 1466 /* Wait phy initialization done */ 1467 for (i = 0; i < 100; i++) { 1468 if ((rd32_epcs(hw, 1469 VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1470 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1471 break; 1472 msleep(100); 1473 } 1474 if (i == 100) { 1475 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1476 goto out; 1477 } 1478 } else { 1479 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1); 1480 } 1481 1482 if (hw->phy.ffe_set == TXGBE_BP_M_KR) { 1483 value = (0x1804 & ~0x3F3F); 1484 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1485 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1486 1487 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 1488 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1489 } 1490 out: 1491 return err; 1492 } 1493 1494 static s32 1495 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg) 1496 { 1497 u32 i; 1498 s32 err = 0; 1499 u32 value; 1500 1501 /* Check link status, if already set, skip setting it again */ 1502 if (hw->link_status == TXGBE_LINK_STATUS_KX4) 1503 goto out; 1504 1505 BP_LOG("It is set to kx4.\n"); 1506 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0); 1507 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0); 1508 1509 /* 1. Wait xpcs power-up good */ 1510 for (i = 0; i < 100; i++) { 1511 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1512 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1513 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1514 break; 1515 msec_delay(10); 1516 } 1517 if (i == 100) { 1518 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1519 goto out; 1520 } 1521 1522 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1523 ~TXGBE_MACTXCFG_TXE); 1524 1525 /* 2. Disable xpcs AN-73 */ 1526 if (!autoneg) 1527 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1528 else 1529 wr32_epcs(hw, SR_AN_CTRL, 0x3000); 1530 1531 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1532 wr32_ephy(hw, 0x4, 0x250A); 1533 txgbe_flush(hw); 1534 msec_delay(1); 1535 1536 /* Set the eth change_mode bit first in mis_rst register 1537 * for corresponding LAN port 1538 */ 1539 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1540 1541 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01 1542 * PCS_TYPE_SEL: non KR 1543 */ 1544 wr32_epcs(hw, SR_XS_PCS_CTRL2, 1545 SR_PCS_CTRL2_TYPE_SEL_X); 1546 1547 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1 1548 * SS13: 10G speed 1549 */ 1550 wr32_epcs(hw, SR_PMA_CTRL1, 1551 SR_PMA_CTRL1_SS13_KX4); 1552 1553 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0; 1554 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 1555 1556 if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI) 1557 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1558 else 1559 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00); 1560 1561 for (i = 0; i < 4; i++) { 1562 if (i == 0) 1563 value = (0x45 & ~0xFFFF) | (0x7 << 12) | 1564 (0x7 << 8) | 0x6; 1565 else 1566 value = (0xff06 & ~0xFFFF) | (0x7 << 12) | 1567 (0x7 << 8) | 0x6; 1568 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value); 1569 } 1570 1571 value = 0x0 & ~0x7777; 1572 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 1573 1574 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 1575 1576 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1; 1577 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 1578 1579 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA 1580 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER 1581 */ 1582 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 1583 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER); 1584 1585 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA 1586 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH 1587 */ 1588 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1589 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER); 1590 1591 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1592 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0 1593 */ 1594 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 1595 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1596 1597 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1598 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1 1599 */ 1600 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 1601 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1602 1603 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1604 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2 1605 */ 1606 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 1607 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1608 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1609 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3 1610 */ 1611 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 1612 TXGBE_PHY_VCO_CAL_LD0_OTHER); 1613 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1614 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1 1615 */ 1616 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222); 1617 1618 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1619 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3 1620 */ 1621 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222); 1622 1623 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE 1624 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1 1625 */ 1626 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0); 1627 1628 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx 1629 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1 1630 */ 1631 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0); 1632 1633 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate 1634 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0], 1635 * all rates to 3'b010 //TX0/1/2/3_RATE 1636 */ 1637 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222); 1638 1639 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate 1640 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0], 1641 * all rates to 2'b10 //RX0/1/2/3_RATE 1642 */ 1643 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222); 1644 1645 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General 1646 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits 1647 */ 1648 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500); 1649 1650 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General 1651 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits 1652 */ 1653 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500); 1654 1655 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1656 * 2 Register Bit[10:8] = 3'b010 1657 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0 1658 */ 1659 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 1660 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10); 1661 1662 wr32_epcs(hw, 0x1f0000, 0x0); 1663 wr32_epcs(hw, 0x1f8001, 0x0); 1664 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0); 1665 1666 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 1667 * Register Bit[15](VR_RST) 1668 */ 1669 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1670 1671 /* Wait phy initialization done */ 1672 for (i = 0; i < 100; i++) { 1673 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1674 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1675 break; 1676 msleep(100); 1677 } 1678 1679 /* If success, set link status */ 1680 hw->link_status = TXGBE_LINK_STATUS_KX4; 1681 1682 if (i == 100) { 1683 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1684 goto out; 1685 } 1686 1687 if (hw->phy.ffe_set == TXGBE_BP_M_KX4) { 1688 value = (0x1804 & ~0x3F3F); 1689 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1690 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1691 1692 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 1693 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1694 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 1695 value = (0x1804 & ~0x3F3F); 1696 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1697 1698 value = (0x50 & ~0x7F) | 40 | (1 << 6); 1699 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1700 } 1701 out: 1702 return err; 1703 } 1704 1705 static s32 1706 txgbe_set_link_to_kx(struct txgbe_hw *hw, 1707 u32 speed, 1708 bool autoneg) 1709 { 1710 u32 i; 1711 s32 err = 0; 1712 u32 wdata = 0; 1713 u32 value; 1714 1715 /* Check link status, if already set, skip setting it again */ 1716 if (hw->link_status == TXGBE_LINK_STATUS_KX) 1717 goto out; 1718 1719 BP_LOG("It is set to kx. speed =0x%x\n", speed); 1720 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC); 1721 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC); 1722 1723 /* 1. Wait xpcs power-up good */ 1724 for (i = 0; i < 100; i++) { 1725 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1726 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1727 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1728 break; 1729 msec_delay(10); 1730 } 1731 if (i == 100) { 1732 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1733 goto out; 1734 } 1735 1736 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1737 ~TXGBE_MACTXCFG_TXE); 1738 1739 /* 2. Disable xpcs AN-73 */ 1740 if (!autoneg) 1741 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1742 else 1743 wr32_epcs(hw, SR_AN_CTRL, 0x3000); 1744 1745 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1746 wr32_ephy(hw, 0x4, 0x240A); 1747 txgbe_flush(hw); 1748 msec_delay(1); 1749 1750 /* Set the eth change_mode bit first in mis_rst register 1751 * for corresponding LAN port 1752 */ 1753 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1754 1755 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01 1756 * PCS_TYPE_SEL: non KR 1757 */ 1758 wr32_epcs(hw, SR_XS_PCS_CTRL2, 1759 SR_PCS_CTRL2_TYPE_SEL_X); 1760 1761 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0 1762 * SS13: 1G speed 1763 */ 1764 wr32_epcs(hw, SR_PMA_CTRL1, 1765 SR_PMA_CTRL1_SS13_KX); 1766 1767 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6], 1768 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G] 1769 */ 1770 if (speed == TXGBE_LINK_SPEED_100M_FULL) 1771 wdata = 0x2100; 1772 else if (speed == TXGBE_LINK_SPEED_1GB_FULL) 1773 wdata = 0x0140; 1774 else if (speed == TXGBE_LINK_SPEED_10M_FULL) 1775 wdata = 0x0100; 1776 wr32_epcs(hw, SR_MII_MMD_CTL, 1777 wdata); 1778 1779 value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10; 1780 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 1781 1782 if (hw->devarg.sgmii == 1) 1783 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00); 1784 else 1785 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1786 1787 for (i = 0; i < 4; i++) { 1788 if (i) { 1789 value = 0xff06; 1790 } else { 1791 value = (0x45 & ~0xFFFF) | (0x7 << 12) | 1792 (0x7 << 8) | 0x6; 1793 } 1794 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value); 1795 } 1796 1797 value = 0x0 & ~0x7; 1798 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 1799 1800 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 1801 1802 value = (0x6db & ~0x7) | 0x4; 1803 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 1804 1805 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1806 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER 1807 */ 1808 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 1809 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX); 1810 1811 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control 1812 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH 1813 */ 1814 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 1815 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX); 1816 1817 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1818 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0 1819 */ 1820 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 1821 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX); 1822 1823 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549); 1824 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549); 1825 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549); 1826 1827 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO 1828 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0 1829 */ 1830 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 1831 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX); 1832 1833 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929); 1834 1835 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE 1836 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0 1837 */ 1838 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 1839 0x0); 1840 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx 1841 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0 1842 */ 1843 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 1844 0x0010); 1845 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate 1846 * Control Register Bit[2:0] = 3'b011 //TX0_RATE 1847 */ 1848 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 1849 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX); 1850 1851 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate 1852 * Control Register Bit[2:0] = 3'b011 //RX0_RATE 1853 */ 1854 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 1855 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX); 1856 1857 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General 1858 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits 1859 */ 1860 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 1861 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER); 1862 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General 1863 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits 1864 */ 1865 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 1866 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER); 1867 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control 1868 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0, 1869 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0 1870 */ 1871 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 1872 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10); 1873 1874 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL 1875 * Set to 8bit MII (required in 10M/100M SGMII) 1876 */ 1877 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 1878 0x0100); 1879 1880 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 1881 * Register Bit[15](VR_RST) 1882 */ 1883 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 1884 1885 /* Wait phy initialization done */ 1886 for (i = 0; i < 100; i++) { 1887 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 1888 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 1889 break; 1890 msleep(100); 1891 } 1892 1893 /* If success, set link status */ 1894 hw->link_status = TXGBE_LINK_STATUS_KX; 1895 1896 if (i == 100) { 1897 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 1898 goto out; 1899 } 1900 1901 if (hw->phy.ffe_set == TXGBE_BP_M_KX) { 1902 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; 1903 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 1904 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1905 1906 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; 1907 value |= hw->phy.ffe_post | (1 << 6); 1908 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1909 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 1910 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4; 1911 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 1912 1913 value = (0x50 & ~0x7F) | 16 | (1 << 6); 1914 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 1915 } 1916 out: 1917 return err; 1918 } 1919 1920 static s32 1921 txgbe_set_link_to_sfi(struct txgbe_hw *hw, 1922 u32 speed) 1923 { 1924 u32 i; 1925 s32 err = 0; 1926 u32 value = 0; 1927 1928 /* Set the module link speed */ 1929 hw->mac.set_rate_select_speed(hw, speed); 1930 /* 1. Wait xpcs power-up good */ 1931 for (i = 0; i < 100; i++) { 1932 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) & 1933 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) == 1934 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD) 1935 break; 1936 msec_delay(10); 1937 } 1938 if (i == 100) { 1939 err = TXGBE_ERR_XPCS_POWER_UP_FAILED; 1940 goto out; 1941 } 1942 1943 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, 1944 ~TXGBE_MACTXCFG_TXE); 1945 1946 /* 2. Disable xpcs AN-73 */ 1947 wr32_epcs(hw, SR_AN_CTRL, 0x0); 1948 1949 /* Disable PHY MPLLA for eth mode change(after ECO) */ 1950 wr32_ephy(hw, 0x4, 0x243A); 1951 txgbe_flush(hw); 1952 msec_delay(1); 1953 /* Set the eth change_mode bit first in mis_rst register 1954 * for corresponding LAN port 1955 */ 1956 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id)); 1957 1958 if (speed == TXGBE_LINK_SPEED_10GB_FULL) { 1959 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00 1960 * PCS_TYPE_SEL: KR 1961 */ 1962 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0); 1963 value = rd32_epcs(hw, SR_PMA_CTRL1); 1964 value = value | 0x2000; 1965 wr32_epcs(hw, SR_PMA_CTRL1, value); 1966 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33 1967 * MPLLA_MULTIPLIER 1968 */ 1969 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021); 1970 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register 1971 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0 1972 */ 1973 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0); 1974 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1); 1975 value = (value & ~0x700) | 0x500; 1976 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 1977 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 1978 * Bit[12:8](RX_VREF_CTRL) = 5'hF 1979 */ 1980 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 1981 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register 1982 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0 1983 */ 1984 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549); 1985 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register 1986 * Bit[5:0] = 6'd41 //VCO_REF_LD_0 1987 */ 1988 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029); 1989 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register 1990 * Bit[2:0] = 3'b000 //TX0_RATE 1991 */ 1992 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0); 1993 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register 1994 * Bit[2:0] = 3'b000 //RX0_RATE 1995 */ 1996 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0); 1997 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11 1998 * TX0_WIDTH: 20bits 1999 */ 2000 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300); 2001 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11 2002 * RX0_WIDTH: 20bits 2003 */ 2004 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300); 2005 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register 2006 * Bit[10:8] = 3'b110 2007 * MPLLA_DIV16P5_CLK_EN=1 2008 * MPLLA_DIV10_CLK_EN=1 2009 * MPLLA_DIV8_CLK_EN=0 2010 */ 2011 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600); 2012 2013 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2014 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2015 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2016 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77 2017 * Bit[7:5](CTLE_POLE_0) = 3'h2 2018 * Bit[4:0](CTLE_BOOST_0) = 4'hF 2019 */ 2020 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F); 2021 2022 } else { 2023 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2024 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00 2025 * Bit[7:5](CTLE_POLE_0) = 3'h2 2026 * Bit[4:0](CTLE_BOOST_0) = 4'hA 2027 */ 2028 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0); 2029 value = (value & ~0xFFFF) | (2 << 5) | 0x05; 2030 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value); 2031 } 2032 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0); 2033 value = (value & ~0x7) | 0x0; 2034 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 2035 2036 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2037 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2038 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2039 * Bit[7:0](DFE_TAP1_0) = 8'd20 2040 */ 2041 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014); 2042 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE); 2043 value = (value & ~0x11) | 0x11; 2044 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value); 2045 } else { 2046 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2047 * Bit[7:0](DFE_TAP1_0) = 8'd20 2048 */ 2049 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE); 2050 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register 2051 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 2052 */ 2053 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE); 2054 value = (value & ~0x11) | 0x0; 2055 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value); 2056 } 2057 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL); 2058 value = value & ~0x1; 2059 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value); 2060 } else { 2061 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00 2062 * PCS_TYPE_SEL: KR 2063 */ 2064 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1); 2065 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0 2066 * SS13: 1G speed 2067 */ 2068 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000); 2069 /* Set SR MII MMD Control Register to corresponding speed */ 2070 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140); 2071 2072 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1); 2073 value = (value & ~0x710) | 0x500; 2074 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value); 2075 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register 2076 * Bit[12:8](RX_VREF_CTRL) = 5'hF 2077 */ 2078 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00); 2079 2080 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 || 2081 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) { 2082 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F); 2083 } else { 2084 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register 2085 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00 2086 * Bit[7:5](CTLE_POLE_0) = 3'h2 2087 * Bit[4:0](CTLE_BOOST_0) = 4'hA 2088 */ 2089 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0); 2090 value = (value & ~0xFFFF) | 0x7706; 2091 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value); 2092 } 2093 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0); 2094 value = (value & ~0x7) | 0x0; 2095 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value); 2096 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register 2097 * Bit[7:0](DFE_TAP1_0) = 8'd00 2098 */ 2099 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0); 2100 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register 2101 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 2102 */ 2103 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3); 2104 value = (value & ~0x7) | 0x4; 2105 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value); 2106 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020); 2107 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046); 2108 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540); 2109 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A); 2110 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0); 2111 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010); 2112 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003); 2113 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003); 2114 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100); 2115 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100); 2116 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200); 2117 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100); 2118 } 2119 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1 2120 * Register Bit[15](VR_RST) 2121 */ 2122 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000); 2123 2124 /* Wait phy initialization done */ 2125 for (i = 0; i < 100; i++) { 2126 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) & 2127 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0) 2128 break; 2129 msleep(100); 2130 } 2131 if (i == 100) { 2132 err = TXGBE_ERR_PHY_INIT_NOT_DONE; 2133 goto out; 2134 } 2135 2136 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { 2137 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F; 2138 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 2139 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2140 2141 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F; 2142 value |= hw->phy.ffe_post | (1 << 6); 2143 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2144 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { 2145 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2146 value = (value & ~0x3F3F) | (24 << 8) | 4; 2147 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2148 2149 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2150 value = (value & ~0x7F) | 16 | (1 << 6); 2151 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2152 } 2153 out: 2154 return err; 2155 } 2156 2157 /** 2158 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read 2159 * @hw: pointer to hardware structure 2160 */ 2161 u64 txgbe_autoc_read(struct txgbe_hw *hw) 2162 { 2163 u64 autoc; 2164 u32 sr_pcs_ctl; 2165 u32 sr_pma_ctl1; 2166 u32 sr_an_ctl; 2167 u32 sr_an_adv_reg2; 2168 u8 type = hw->subsystem_device_id & 0xFF; 2169 2170 autoc = hw->mac.autoc; 2171 2172 if (hw->phy.multispeed_fiber) { 2173 autoc |= TXGBE_AUTOC_LMS_10G; 2174 } else if (type == TXGBE_DEV_ID_SFP) { 2175 autoc |= TXGBE_AUTOC_LMS_10G; 2176 autoc |= TXGBE_AUTOC_10GS_SFI; 2177 } else if (type == TXGBE_DEV_ID_QSFP) { 2178 autoc = 0; /*TBD*/ 2179 } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) { 2180 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN; 2181 autoc |= TXGBE_AUTOC_10G_XAUI; 2182 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T; 2183 } else if (type == TXGBE_DEV_ID_SGMII) { 2184 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M; 2185 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T | 2186 TXGBE_PHYSICAL_LAYER_100BASE_TX; 2187 } else if (type == TXGBE_DEV_ID_MAC_XAUI) { 2188 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN; 2189 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2190 } else if (type == TXGBE_DEV_ID_MAC_SGMII) { 2191 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN; 2192 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2193 } 2194 2195 if (type != TXGBE_DEV_ID_KR_KX_KX4) 2196 return autoc; 2197 2198 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2); 2199 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1); 2200 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL); 2201 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2); 2202 2203 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X && 2204 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX && 2205 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2206 /* 1G or KX - no backplane auto-negotiation */ 2207 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN | 2208 TXGBE_AUTOC_1G_KX; 2209 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2210 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == 2211 SR_PCS_CTRL2_TYPE_SEL_X && 2212 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 && 2213 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2214 autoc |= TXGBE_AUTOC_LMS_10G | 2215 TXGBE_AUTOC_10G_KX4; 2216 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4; 2217 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == 2218 SR_PCS_CTRL2_TYPE_SEL_R && 2219 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) { 2220 /* 10 GbE serial link (KR -no backplane auto-negotiation) */ 2221 autoc |= TXGBE_AUTOC_LMS_10G | 2222 TXGBE_AUTOC_10GS_KR; 2223 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR; 2224 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) { 2225 /* KX/KX4/KR backplane auto-negotiation enable */ 2226 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR) 2227 autoc |= TXGBE_AUTOC_KR_SUPP; 2228 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4) 2229 autoc |= TXGBE_AUTOC_KX4_SUPP; 2230 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX) 2231 autoc |= TXGBE_AUTOC_KX_SUPP; 2232 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR; 2233 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR | 2234 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2235 TXGBE_PHYSICAL_LAYER_1000BASE_KX; 2236 } 2237 2238 return autoc; 2239 } 2240 2241 /** 2242 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write 2243 * @hw: pointer to hardware structure 2244 * @autoc: value to write to AUTOC 2245 */ 2246 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc) 2247 { 2248 bool autoneg; 2249 u32 speed; 2250 u32 mactxcfg = 0; 2251 u8 device_type = hw->subsystem_device_id & 0xFF; 2252 2253 speed = TXGBD_AUTOC_SPEED(autoc); 2254 autoc &= ~TXGBE_AUTOC_SPEED_MASK; 2255 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false); 2256 autoc &= ~TXGBE_AUTOC_AUTONEG; 2257 2258 if (device_type == TXGBE_DEV_ID_KR_KX_KX4) { 2259 if (!autoneg) { 2260 switch (hw->phy.link_mode) { 2261 case TXGBE_PHYSICAL_LAYER_10GBASE_KR: 2262 txgbe_set_link_to_kr(hw, autoneg); 2263 break; 2264 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4: 2265 txgbe_set_link_to_kx4(hw, autoneg); 2266 break; 2267 case TXGBE_PHYSICAL_LAYER_1000BASE_KX: 2268 txgbe_set_link_to_kx(hw, speed, autoneg); 2269 break; 2270 default: 2271 return; 2272 } 2273 } else { 2274 txgbe_set_link_to_kr(hw, !autoneg); 2275 } 2276 } else if (device_type == TXGBE_DEV_ID_XAUI || 2277 device_type == TXGBE_DEV_ID_SGMII || 2278 device_type == TXGBE_DEV_ID_MAC_XAUI || 2279 device_type == TXGBE_DEV_ID_MAC_SGMII || 2280 (device_type == TXGBE_DEV_ID_SFI_XAUI && 2281 hw->phy.media_type == txgbe_media_type_copper)) { 2282 if (speed == TXGBE_LINK_SPEED_10GB_FULL) { 2283 txgbe_set_link_to_kx4(hw, 0); 2284 } else { 2285 txgbe_set_link_to_kx(hw, speed, 0); 2286 if (hw->devarg.auto_neg == 1) 2287 txgbe_set_sgmii_an37_ability(hw); 2288 } 2289 } else if (hw->phy.media_type == txgbe_media_type_fiber) { 2290 txgbe_set_link_to_sfi(hw, speed); 2291 if (speed == TXGBE_LINK_SPEED_1GB_FULL) 2292 txgbe_set_sgmii_an37_ability(hw); 2293 } 2294 2295 if (speed == TXGBE_LINK_SPEED_10GB_FULL) 2296 mactxcfg = TXGBE_MACTXCFG_SPEED_10G; 2297 else if (speed == TXGBE_LINK_SPEED_1GB_FULL) 2298 mactxcfg = TXGBE_MACTXCFG_SPEED_1G; 2299 2300 /* enable mac transmitter */ 2301 wr32m(hw, TXGBE_MACTXCFG, 2302 TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE, 2303 mactxcfg | TXGBE_MACTXCFG_TXE); 2304 } 2305 2306 void txgbe_bp_down_event(struct txgbe_hw *hw) 2307 { 2308 if (!(hw->devarg.auto_neg == 1)) 2309 return; 2310 2311 BP_LOG("restart phy power.\n"); 2312 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 2313 wr32_epcs(hw, SR_AN_CTRL, 0); 2314 wr32_epcs(hw, VR_AN_INTR_MSK, 0); 2315 2316 msleep(1050); 2317 txgbe_set_link_to_kr(hw, 0); 2318 } 2319 2320 void txgbe_bp_mode_set(struct txgbe_hw *hw) 2321 { 2322 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) 2323 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP; 2324 else if (hw->phy.ffe_set == TXGBE_BP_M_KR) 2325 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4; 2326 else if (hw->phy.ffe_set == TXGBE_BP_M_KX4) 2327 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI; 2328 else if (hw->phy.ffe_set == TXGBE_BP_M_KX) 2329 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII; 2330 } 2331 2332 void txgbe_set_phy_temp(struct txgbe_hw *hw) 2333 { 2334 u32 value; 2335 2336 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) { 2337 BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n", 2338 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2339 2340 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2341 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | 2342 hw->phy.ffe_pre; 2343 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2344 2345 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2346 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); 2347 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2348 } 2349 2350 if (hw->phy.ffe_set == TXGBE_BP_M_KR) { 2351 BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n", 2352 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2353 value = (0x1804 & ~0x3F3F); 2354 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre; 2355 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2356 2357 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post; 2358 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2359 wr32_epcs(hw, 0x18035, 0x00FF); 2360 wr32_epcs(hw, 0x18055, 0x00FF); 2361 } 2362 2363 if (hw->phy.ffe_set == TXGBE_BP_M_KX) { 2364 BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n", 2365 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); 2366 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0); 2367 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) | 2368 hw->phy.ffe_pre; 2369 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); 2370 2371 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2372 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6); 2373 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2374 2375 wr32_epcs(hw, 0x18035, 0x00FF); 2376 wr32_epcs(hw, 0x18055, 0x00FF); 2377 } 2378 } 2379 2380 /** 2381 * txgbe_kr_handle - Handle the interrupt of auto-negotiation 2382 * @hw: pointer to hardware structure 2383 */ 2384 s32 txgbe_kr_handle(struct txgbe_hw *hw) 2385 { 2386 u32 value; 2387 s32 status = 0; 2388 2389 value = rd32_epcs(hw, VR_AN_INTR); 2390 BP_LOG("AN INTERRUPT!! value: 0x%x\n", value); 2391 if (!(value & VR_AN_INTR_PG_RCV)) { 2392 wr32_epcs(hw, VR_AN_INTR, 0); 2393 return status; 2394 } 2395 2396 status = txgbe_handle_bp_flow(0, hw); 2397 2398 return status; 2399 } 2400 2401 /** 2402 * txgbe_handle_bp_flow - Handle backplane AN73 flow 2403 * @hw: pointer to hardware structure 2404 * @link_mode: local AN73 link mode 2405 */ 2406 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw) 2407 { 2408 u32 value, i, lp_reg, ld_reg; 2409 s32 status = 0; 2410 struct txgbe_backplane_ability local_ability, lp_ability; 2411 2412 local_ability.current_link_mode = link_mode; 2413 2414 /* 1. Get the local AN73 Base Page Ability */ 2415 BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n"); 2416 txgbe_get_bp_ability(&local_ability, 0, hw); 2417 2418 /* 2. Check and clear the AN73 Interrupt Status */ 2419 BP_LOG("<2>. Check the AN73 Interrupt Status ...\n"); 2420 txgbe_clear_bp_intr(2, 0, hw); 2421 2422 /* 3.1. Get the link partner AN73 Base Page Ability */ 2423 BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n"); 2424 txgbe_get_bp_ability(&lp_ability, 1, hw); 2425 2426 /* 3.2. Check the AN73 Link Ability with Link Partner */ 2427 BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n"); 2428 BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability); 2429 BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability); 2430 2431 status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw); 2432 2433 wr32_epcs(hw, SR_AN_CTRL, 0); 2434 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0); 2435 2436 /* 3.3. Check the FEC and KR Training for KR mode */ 2437 BP_LOG("<3.3>. Check the FEC for KR mode ...\n"); 2438 if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) { 2439 BP_LOG("Enable the Backplane KR FEC ...\n"); 2440 wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN); 2441 } else { 2442 BP_LOG("Backplane KR FEC is disabled.\n"); 2443 } 2444 2445 printf("Enter training.\n"); 2446 /* CL72 KR training on */ 2447 for (i = 0; i < 2; i++) { 2448 /* 3.4. Check the CL72 KR Training for KR mode */ 2449 BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n"); 2450 BP_LOG("==================%d==================\n", i); 2451 status = txgbe_enable_kr_training(hw); 2452 BP_LOG("Check the Clause 72 KR Training status ...\n"); 2453 status |= txgbe_check_kr_training(hw); 2454 2455 lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2456 lp_reg &= SR_PMA_KR_LP_CESTS_RR; 2457 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", 2458 lp_reg); 2459 ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); 2460 ld_reg &= SR_PMA_KR_LD_CESTS_RR; 2461 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n", 2462 ld_reg); 2463 if (hw->devarg.poll == 0 && status != 0) 2464 lp_reg = SR_PMA_KR_LP_CESTS_RR; 2465 2466 if (lp_reg & ld_reg) { 2467 BP_LOG("==================out==================\n"); 2468 status = txgbe_disable_kr_training(hw, 0, 0); 2469 wr32_epcs(hw, SR_AN_CTRL, 0); 2470 txgbe_clear_bp_intr(2, 0, hw); 2471 txgbe_clear_bp_intr(1, 0, hw); 2472 txgbe_clear_bp_intr(0, 0, hw); 2473 for (i = 0; i < 10; i++) { 2474 value = rd32_epcs(hw, SR_XS_PCS_KR_STS1); 2475 if (value & SR_XS_PCS_KR_STS1_PLU) { 2476 BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n"); 2477 wr32_epcs(hw, SR_AN_CTRL, 0); 2478 return 0; 2479 } 2480 msec_delay(10); 2481 } 2482 msec_delay(1000); 2483 txgbe_set_link_to_kr(hw, 0); 2484 2485 return 0; 2486 } 2487 2488 status |= txgbe_disable_kr_training(hw, 0, 0); 2489 } 2490 2491 txgbe_clear_bp_intr(2, 0, hw); 2492 txgbe_clear_bp_intr(1, 0, hw); 2493 txgbe_clear_bp_intr(0, 0, hw); 2494 2495 return status; 2496 } 2497 2498 /** 2499 * txgbe_get_bp_ability 2500 * @hw: pointer to hardware structure 2501 * @ability: pointer to blackplane ability structure 2502 * @link_partner: 2503 * 1: Get Link Partner Base Page 2504 * 2: Get Link Partner Next Page 2505 * (only get NXP Ability Register 1 at the moment) 2506 * 0: Get Local Device Base Page 2507 */ 2508 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability, 2509 u32 link_partner, struct txgbe_hw *hw) 2510 { 2511 u32 value = 0; 2512 2513 /* Link Partner Base Page */ 2514 if (link_partner == 1) { 2515 /* Read the link partner AN73 Base Page Ability Registers */ 2516 BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n"); 2517 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1); 2518 BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n", 2519 value); 2520 ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value); 2521 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2522 2523 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2); 2524 BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n", 2525 value); 2526 ability->link_ability = 2527 value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX; 2528 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", 2529 ability->link_ability); 2530 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); 2531 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); 2532 2533 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3); 2534 BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n", 2535 value); 2536 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); 2537 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); 2538 ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value); 2539 } else if (link_partner == 2) { 2540 /* Read the link partner AN73 Next Page Ability Registers */ 2541 BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n"); 2542 value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1); 2543 BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value); 2544 ability->next_page = SR_AN_LP_XNP_ABL1_NP(value); 2545 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2546 } else { 2547 /* Read the local AN73 Base Page Ability Registers */ 2548 BP_LOG("Read the local AN73 Base Page Ability Registers...\n"); 2549 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1); 2550 BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value); 2551 ability->next_page = SR_AN_MMD_ADV_REG1_NP(value); 2552 BP_LOG(" Next Page (bit15): %d\n", ability->next_page); 2553 2554 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2); 2555 BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value); 2556 ability->link_ability = 2557 value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX; 2558 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n", 2559 ability->link_ability); 2560 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n"); 2561 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n"); 2562 2563 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3); 2564 BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value); 2565 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01)); 2566 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01)); 2567 ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value); 2568 } 2569 2570 BP_LOG("done.\n"); 2571 } 2572 2573 /** 2574 * txgbe_check_bp_ability 2575 * @hw: pointer to hardware structure 2576 * @ability: pointer to blackplane ability structure 2577 */ 2578 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability, 2579 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw) 2580 { 2581 u32 com_link_abi; 2582 s32 ret = 0; 2583 2584 com_link_abi = local_ability->link_ability & lp_ability->link_ability; 2585 BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n", 2586 com_link_abi, local_ability->link_ability, 2587 lp_ability->link_ability); 2588 2589 if (!com_link_abi) { 2590 BP_LOG("The Link Partner does not support any compatible speed mode.\n"); 2591 ret = -1; 2592 } else if (com_link_abi & BP_TYPE_KR) { 2593 if (local_ability->current_link_mode) { 2594 BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n"); 2595 BP_LOG("Set the local link mode to [LINK_KR] ...\n"); 2596 txgbe_set_link_to_kr(hw, 0); 2597 ret = 1; 2598 } else { 2599 BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n"); 2600 ret = 0; 2601 } 2602 } else if (com_link_abi & BP_TYPE_KX4) { 2603 if (local_ability->current_link_mode == 0x10) { 2604 BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n"); 2605 ret = 0; 2606 } else { 2607 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n"); 2608 BP_LOG("Set the local link mode to [LINK_KX4] ...\n"); 2609 txgbe_set_link_to_kx4(hw, 1); 2610 ret = 1; 2611 } 2612 } else if (com_link_abi & BP_TYPE_KX) { 2613 if (local_ability->current_link_mode == 0x1) { 2614 BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n"); 2615 ret = 0; 2616 } else { 2617 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n"); 2618 BP_LOG("Set the local link mode to [LINK_KX] ...\n"); 2619 txgbe_set_link_to_kx(hw, 1, 1); 2620 ret = 1; 2621 } 2622 } 2623 2624 return ret; 2625 } 2626 2627 /** 2628 * txgbe_clear_bp_intr 2629 * @hw: pointer to hardware structure 2630 * @index: the bit will be cleared 2631 * @index_high: 2632 * index_high = 0: Only the index bit will be cleared 2633 * index_high != 0: the [index_high, index] range will be cleared 2634 */ 2635 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw) 2636 { 2637 u32 rdata = 0, wdata, i; 2638 2639 rdata = rd32_epcs(hw, VR_AN_INTR); 2640 BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n", 2641 rdata); 2642 BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n"); 2643 2644 wdata = rdata; 2645 if (bit_high) { 2646 for (i = bit; i <= bit_high; i++) 2647 wdata &= ~(1 << i); 2648 } else { 2649 wdata &= ~(1 << bit); 2650 } 2651 2652 wr32_epcs(hw, VR_AN_INTR, wdata); 2653 2654 rdata = rd32_epcs(hw, VR_AN_INTR); 2655 BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata); 2656 } 2657 2658 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw) 2659 { 2660 s32 status = 0; 2661 u32 value = 0; 2662 2663 BP_LOG("Enable Clause 72 KR Training ...\n"); 2664 2665 if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) { 2666 /* Set PRBS Timer Duration Control to maximum 6.7ms in 2667 * VR_PMA_KRTR_PRBS_CTRL2 Register 2668 */ 2669 value = CL72_KRTR_PRBS_MODE_EN; 2670 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value); 2671 /* Set PRBS Timer Duration Control to maximum 6.7ms in 2672 * VR_PMA_KRTR_PRBS_CTRL1 Register 2673 */ 2674 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1, 2675 VR_PMA_KRTR_PRBS_TIME_LMT); 2676 /* Enable PRBS Mode to determine KR Training Status by setting 2677 * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register 2678 */ 2679 value = VR_PMA_KRTR_PRBS_MODE_EN; 2680 } 2681 #ifdef CL72_KRTR_PRBS31_EN 2682 /* Enable PRBS Mode to determine KR Training Status by setting 2683 * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register 2684 */ 2685 value = VR_PMA_KRTR_PRBS31_EN; 2686 #endif 2687 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value); 2688 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ 2689 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2690 2691 /* Enable the Clause 72 start-up protocol 2692 * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register. 2693 * Restart the Clause 72 start-up protocol 2694 * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register. 2695 */ 2696 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, 2697 SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR); 2698 2699 return status; 2700 } 2701 2702 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode) 2703 { 2704 s32 status = 0; 2705 2706 BP_LOG("Disable Clause 72 KR Training ...\n"); 2707 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */ 2708 txgbe_read_phy_lane_tx_eq(0, hw, post, mode); 2709 2710 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR); 2711 2712 return status; 2713 } 2714 2715 static s32 txgbe_check_kr_training(struct txgbe_hw *hw) 2716 { 2717 s32 status = 0; 2718 u32 value, test; 2719 int i; 2720 int times = hw->devarg.poll ? 35 : 20; 2721 2722 for (i = 0; i < times; i++) { 2723 value = rd32_epcs(hw, SR_PMA_KR_LP_CEU); 2724 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n", 2725 value); 2726 value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2727 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n", 2728 value); 2729 value = rd32_epcs(hw, SR_PMA_KR_LD_CEU); 2730 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n", 2731 value); 2732 value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS); 2733 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n", 2734 value); 2735 value = rd32_epcs(hw, SR_PMA_KR_PMD_STS); 2736 BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value); 2737 BP_LOG(" Training Failure (bit3): %d\n", 2738 ((value >> 3) & 0x01)); 2739 BP_LOG(" Start-Up Protocol Status (bit2): %d\n", 2740 ((value >> 2) & 0x01)); 2741 BP_LOG(" Frame Lock (bit1): %d\n", 2742 ((value >> 1) & 0x01)); 2743 BP_LOG(" Receiver Status (bit0): %d\n", 2744 ((value >> 0) & 0x01)); 2745 2746 test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS); 2747 if (test & SR_PMA_KR_LP_CESTS_RR) { 2748 BP_LOG("TEST Coefficient Status Register: 0x%x\n", 2749 test); 2750 status = 1; 2751 } 2752 2753 if (value & SR_PMA_KR_PMD_STS_TR_FAIL) { 2754 BP_LOG("Training is completed with failure.\n"); 2755 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2756 return 0; 2757 } 2758 2759 if (value & SR_PMA_KR_PMD_STS_RCV) { 2760 BP_LOG("Receiver trained and ready to receive data.\n"); 2761 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0); 2762 return 0; 2763 } 2764 2765 msec_delay(20); 2766 } 2767 2768 BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n"); 2769 return status; 2770 } 2771 2772 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw, 2773 s32 post, s32 mode) 2774 { 2775 u32 value = 0; 2776 u32 addr; 2777 u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain; 2778 2779 addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8); 2780 value = rd32_ephy(hw, addr); 2781 BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane); 2782 tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value); 2783 BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor); 2784 UNREFERENCED_PARAMETER(tx_main_cursor); 2785 2786 addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8); 2787 value = rd32_ephy(hw, addr); 2788 tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE; 2789 tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value); 2790 BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor); 2791 BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor); 2792 2793 if (mode == 1) { 2794 lmain = 160 - tx_pre_cursor - tx_post_cursor; 2795 if (lmain < 88) 2796 lmain = 88; 2797 2798 if (post) 2799 tx_post_cursor = post; 2800 2801 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor); 2802 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0, 2803 tx_pre_cursor | (lmain << 8)); 2804 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1); 2805 value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF; 2806 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); 2807 } 2808 } 2809