1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_dev.h> 11 #include <ethdev_driver.h> 12 #include <ethdev_pci.h> 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_errno.h> 16 #include <rte_string_fns.h> 17 #include <rte_ether.h> 18 19 #include "efx.h" 20 21 #include "sfc.h" 22 #include "sfc_debug.h" 23 #include "sfc_log.h" 24 #include "sfc_kvargs.h" 25 #include "sfc_ev.h" 26 #include "sfc_rx.h" 27 #include "sfc_tx.h" 28 #include "sfc_flow.h" 29 #include "sfc_flow_tunnel.h" 30 #include "sfc_dp.h" 31 #include "sfc_dp_rx.h" 32 #include "sfc_repr.h" 33 #include "sfc_sw_stats.h" 34 #include "sfc_switch.h" 35 #include "sfc_nic_dma.h" 36 37 #define SFC_XSTAT_ID_INVALID_VAL UINT64_MAX 38 #define SFC_XSTAT_ID_INVALID_NAME '\0' 39 40 uint32_t sfc_logtype_driver; 41 42 static struct sfc_dp_list sfc_dp_head = 43 TAILQ_HEAD_INITIALIZER(sfc_dp_head); 44 45 46 static void sfc_eth_dev_clear_ops(struct rte_eth_dev *dev); 47 48 49 static int 50 sfc_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 51 { 52 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 53 efx_nic_fw_info_t enfi; 54 int ret; 55 int rc; 56 57 rc = efx_nic_get_fw_version(sa->nic, &enfi); 58 if (rc != 0) 59 return -rc; 60 61 ret = snprintf(fw_version, fw_size, 62 "%" PRIu16 ".%" PRIu16 ".%" PRIu16 ".%" PRIu16, 63 enfi.enfi_mc_fw_version[0], enfi.enfi_mc_fw_version[1], 64 enfi.enfi_mc_fw_version[2], enfi.enfi_mc_fw_version[3]); 65 if (ret < 0) 66 return ret; 67 68 if (enfi.enfi_dpcpu_fw_ids_valid) { 69 size_t dpcpu_fw_ids_offset = MIN(fw_size - 1, (size_t)ret); 70 int ret_extra; 71 72 ret_extra = snprintf(fw_version + dpcpu_fw_ids_offset, 73 fw_size - dpcpu_fw_ids_offset, 74 " rx%" PRIx16 " tx%" PRIx16, 75 enfi.enfi_rx_dpcpu_fw_id, 76 enfi.enfi_tx_dpcpu_fw_id); 77 if (ret_extra < 0) 78 return ret_extra; 79 80 ret += ret_extra; 81 } 82 83 if (fw_size < (size_t)(++ret)) 84 return ret; 85 else 86 return 0; 87 } 88 89 static int 90 sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 91 { 92 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 93 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 94 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 95 struct sfc_rss *rss = &sas->rss; 96 struct sfc_mae *mae = &sa->mae; 97 98 sfc_log_init(sa, "entry"); 99 100 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 101 dev_info->max_mtu = EFX_MAC_SDU_MAX; 102 103 dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX; 104 105 dev_info->max_vfs = sa->sriov.num_vfs; 106 107 /* Autonegotiation may be disabled */ 108 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 109 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX)) 110 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_1G; 111 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX)) 112 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10G; 113 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX)) 114 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G; 115 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX)) 116 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 117 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX)) 118 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G; 119 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX)) 120 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G; 121 122 dev_info->max_rx_queues = sa->rxq_max; 123 dev_info->max_tx_queues = sa->txq_max; 124 125 /* By default packets are dropped if no descriptors are available */ 126 dev_info->default_rxconf.rx_drop_en = 1; 127 128 dev_info->rx_queue_offload_capa = sfc_rx_get_queue_offload_caps(sa); 129 130 /* 131 * rx_offload_capa includes both device and queue offloads since 132 * the latter may be requested on a per device basis which makes 133 * sense when some offloads are needed to be set on all queues. 134 */ 135 dev_info->rx_offload_capa = sfc_rx_get_dev_offload_caps(sa) | 136 dev_info->rx_queue_offload_capa; 137 138 dev_info->tx_queue_offload_capa = sfc_tx_get_queue_offload_caps(sa); 139 140 /* 141 * tx_offload_capa includes both device and queue offloads since 142 * the latter may be requested on a per device basis which makes 143 * sense when some offloads are needed to be set on all queues. 144 */ 145 dev_info->tx_offload_capa = sfc_tx_get_dev_offload_caps(sa) | 146 dev_info->tx_queue_offload_capa; 147 148 if (rss->context_type != EFX_RX_SCALE_UNAVAILABLE) { 149 uint64_t rte_hf = 0; 150 unsigned int i; 151 152 for (i = 0; i < rss->hf_map_nb_entries; ++i) 153 rte_hf |= rss->hf_map[i].rte; 154 155 dev_info->reta_size = EFX_RSS_TBL_SIZE; 156 dev_info->hash_key_size = EFX_RSS_KEY_SIZE; 157 dev_info->flow_type_rss_offloads = rte_hf; 158 } 159 160 /* Initialize to hardware limits */ 161 dev_info->rx_desc_lim.nb_max = sa->rxq_max_entries; 162 dev_info->rx_desc_lim.nb_min = sa->rxq_min_entries; 163 /* The RXQ hardware requires that the descriptor count is a power 164 * of 2, but rx_desc_lim cannot properly describe that constraint. 165 */ 166 dev_info->rx_desc_lim.nb_align = sa->rxq_min_entries; 167 168 /* Initialize to hardware limits */ 169 dev_info->tx_desc_lim.nb_max = sa->txq_max_entries; 170 dev_info->tx_desc_lim.nb_min = sa->txq_min_entries; 171 /* 172 * The TXQ hardware requires that the descriptor count is a power 173 * of 2, but tx_desc_lim cannot properly describe that constraint 174 */ 175 dev_info->tx_desc_lim.nb_align = sa->txq_min_entries; 176 177 if (sap->dp_rx->get_dev_info != NULL) 178 sap->dp_rx->get_dev_info(dev_info); 179 if (sap->dp_tx->get_dev_info != NULL) 180 sap->dp_tx->get_dev_info(dev_info); 181 182 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 183 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 184 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 185 186 if (mae->status == SFC_MAE_STATUS_SUPPORTED || 187 mae->status == SFC_MAE_STATUS_ADMIN) { 188 dev_info->switch_info.name = dev->device->driver->name; 189 dev_info->switch_info.domain_id = mae->switch_domain_id; 190 dev_info->switch_info.port_id = mae->switch_port_id; 191 } 192 193 return 0; 194 } 195 196 static const uint32_t * 197 sfc_dev_supported_ptypes_get(struct rte_eth_dev *dev) 198 { 199 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 200 201 return sap->dp_rx->supported_ptypes_get(sap->shared->tunnel_encaps); 202 } 203 204 static int 205 sfc_dev_configure(struct rte_eth_dev *dev) 206 { 207 struct rte_eth_dev_data *dev_data = dev->data; 208 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 209 int rc; 210 211 sfc_log_init(sa, "entry n_rxq=%u n_txq=%u", 212 dev_data->nb_rx_queues, dev_data->nb_tx_queues); 213 214 sfc_adapter_lock(sa); 215 switch (sa->state) { 216 case SFC_ETHDEV_CONFIGURED: 217 /* FALLTHROUGH */ 218 case SFC_ETHDEV_INITIALIZED: 219 rc = sfc_configure(sa); 220 break; 221 default: 222 sfc_err(sa, "unexpected adapter state %u to configure", 223 sa->state); 224 rc = EINVAL; 225 break; 226 } 227 sfc_adapter_unlock(sa); 228 229 sfc_log_init(sa, "done %d", rc); 230 SFC_ASSERT(rc >= 0); 231 return -rc; 232 } 233 234 static int 235 sfc_dev_start(struct rte_eth_dev *dev) 236 { 237 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 238 int rc; 239 240 sfc_log_init(sa, "entry"); 241 242 sfc_adapter_lock(sa); 243 rc = sfc_start(sa); 244 sfc_adapter_unlock(sa); 245 246 sfc_log_init(sa, "done %d", rc); 247 SFC_ASSERT(rc >= 0); 248 return -rc; 249 } 250 251 static int 252 sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 253 { 254 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 255 struct rte_eth_link current_link; 256 int ret; 257 258 sfc_log_init(sa, "entry"); 259 260 if (sa->state != SFC_ETHDEV_STARTED) { 261 sfc_port_link_mode_to_info(EFX_LINK_UNKNOWN, ¤t_link); 262 } else if (wait_to_complete) { 263 efx_link_mode_t link_mode; 264 265 if (efx_port_poll(sa->nic, &link_mode) != 0) 266 link_mode = EFX_LINK_UNKNOWN; 267 sfc_port_link_mode_to_info(link_mode, ¤t_link); 268 269 } else { 270 sfc_ev_mgmt_qpoll(sa); 271 rte_eth_linkstatus_get(dev, ¤t_link); 272 } 273 274 ret = rte_eth_linkstatus_set(dev, ¤t_link); 275 if (ret == 0) 276 sfc_notice(sa, "Link status is %s", 277 current_link.link_status ? "UP" : "DOWN"); 278 279 return ret; 280 } 281 282 static int 283 sfc_dev_stop(struct rte_eth_dev *dev) 284 { 285 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 286 287 sfc_log_init(sa, "entry"); 288 289 sfc_adapter_lock(sa); 290 sfc_stop(sa); 291 sfc_adapter_unlock(sa); 292 293 sfc_log_init(sa, "done"); 294 295 return 0; 296 } 297 298 static int 299 sfc_dev_set_link_up(struct rte_eth_dev *dev) 300 { 301 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 302 int rc; 303 304 sfc_log_init(sa, "entry"); 305 306 sfc_adapter_lock(sa); 307 rc = sfc_start(sa); 308 sfc_adapter_unlock(sa); 309 310 SFC_ASSERT(rc >= 0); 311 return -rc; 312 } 313 314 static int 315 sfc_dev_set_link_down(struct rte_eth_dev *dev) 316 { 317 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 318 319 sfc_log_init(sa, "entry"); 320 321 sfc_adapter_lock(sa); 322 sfc_stop(sa); 323 sfc_adapter_unlock(sa); 324 325 return 0; 326 } 327 328 static void 329 sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev) 330 { 331 free(dev->process_private); 332 rte_eth_dev_release_port(dev); 333 } 334 335 static int 336 sfc_dev_close(struct rte_eth_dev *dev) 337 { 338 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 339 340 sfc_log_init(sa, "entry"); 341 342 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 343 sfc_eth_dev_secondary_clear_ops(dev); 344 return 0; 345 } 346 347 sfc_pre_detach(sa); 348 349 sfc_adapter_lock(sa); 350 switch (sa->state) { 351 case SFC_ETHDEV_STARTED: 352 sfc_stop(sa); 353 SFC_ASSERT(sa->state == SFC_ETHDEV_CONFIGURED); 354 /* FALLTHROUGH */ 355 case SFC_ETHDEV_CONFIGURED: 356 sfc_close(sa); 357 SFC_ASSERT(sa->state == SFC_ETHDEV_INITIALIZED); 358 /* FALLTHROUGH */ 359 case SFC_ETHDEV_INITIALIZED: 360 break; 361 default: 362 sfc_err(sa, "unexpected adapter state %u on close", sa->state); 363 break; 364 } 365 366 /* 367 * Cleanup all resources. 368 * Rollback primary process sfc_eth_dev_init() below. 369 */ 370 371 sfc_eth_dev_clear_ops(dev); 372 373 sfc_nic_dma_detach(sa); 374 sfc_detach(sa); 375 sfc_unprobe(sa); 376 377 sfc_kvargs_cleanup(sa); 378 379 sfc_adapter_unlock(sa); 380 sfc_adapter_lock_fini(sa); 381 382 sfc_log_init(sa, "done"); 383 384 /* Required for logging, so cleanup last */ 385 sa->eth_dev = NULL; 386 387 free(sa); 388 389 return 0; 390 } 391 392 static int 393 sfc_dev_filter_set(struct rte_eth_dev *dev, enum sfc_dev_filter_mode mode, 394 boolean_t enabled) 395 { 396 struct sfc_port *port; 397 boolean_t *toggle; 398 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 399 boolean_t allmulti = (mode == SFC_DEV_FILTER_MODE_ALLMULTI); 400 const char *desc = (allmulti) ? "all-multi" : "promiscuous"; 401 int rc = 0; 402 403 sfc_adapter_lock(sa); 404 405 port = &sa->port; 406 toggle = (allmulti) ? (&port->allmulti) : (&port->promisc); 407 408 if (*toggle != enabled) { 409 *toggle = enabled; 410 411 if (sfc_sa2shared(sa)->isolated) { 412 sfc_warn(sa, "isolated mode is active on the port"); 413 sfc_warn(sa, "the change is to be applied on the next " 414 "start provided that isolated mode is " 415 "disabled prior the next start"); 416 } else if ((sa->state == SFC_ETHDEV_STARTED) && 417 ((rc = sfc_set_rx_mode(sa)) != 0)) { 418 *toggle = !(enabled); 419 sfc_warn(sa, "Failed to %s %s mode, rc = %d", 420 ((enabled) ? "enable" : "disable"), desc, rc); 421 422 /* 423 * For promiscuous and all-multicast filters a 424 * permission failure should be reported as an 425 * unsupported filter. 426 */ 427 if (rc == EPERM) 428 rc = ENOTSUP; 429 } 430 } 431 432 sfc_adapter_unlock(sa); 433 return rc; 434 } 435 436 static int 437 sfc_dev_promisc_enable(struct rte_eth_dev *dev) 438 { 439 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_TRUE); 440 441 SFC_ASSERT(rc >= 0); 442 return -rc; 443 } 444 445 static int 446 sfc_dev_promisc_disable(struct rte_eth_dev *dev) 447 { 448 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_FALSE); 449 450 SFC_ASSERT(rc >= 0); 451 return -rc; 452 } 453 454 static int 455 sfc_dev_allmulti_enable(struct rte_eth_dev *dev) 456 { 457 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_TRUE); 458 459 SFC_ASSERT(rc >= 0); 460 return -rc; 461 } 462 463 static int 464 sfc_dev_allmulti_disable(struct rte_eth_dev *dev) 465 { 466 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_FALSE); 467 468 SFC_ASSERT(rc >= 0); 469 return -rc; 470 } 471 472 static int 473 sfc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 474 uint16_t nb_rx_desc, unsigned int socket_id, 475 const struct rte_eth_rxconf *rx_conf, 476 struct rte_mempool *mb_pool) 477 { 478 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 479 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 480 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 481 struct sfc_rxq_info *rxq_info; 482 sfc_sw_index_t sw_index; 483 int rc; 484 485 sfc_log_init(sa, "RxQ=%u nb_rx_desc=%u socket_id=%u", 486 ethdev_qid, nb_rx_desc, socket_id); 487 488 sfc_adapter_lock(sa); 489 490 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 491 rc = sfc_rx_qinit(sa, sw_index, nb_rx_desc, socket_id, 492 rx_conf, mb_pool); 493 if (rc != 0) 494 goto fail_rx_qinit; 495 496 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 497 dev->data->rx_queues[ethdev_qid] = rxq_info->dp; 498 499 sfc_adapter_unlock(sa); 500 501 return 0; 502 503 fail_rx_qinit: 504 sfc_adapter_unlock(sa); 505 SFC_ASSERT(rc > 0); 506 return -rc; 507 } 508 509 static void 510 sfc_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 511 { 512 struct sfc_dp_rxq *dp_rxq = dev->data->rx_queues[qid]; 513 struct sfc_rxq *rxq; 514 struct sfc_adapter *sa; 515 sfc_sw_index_t sw_index; 516 517 if (dp_rxq == NULL) 518 return; 519 520 rxq = sfc_rxq_by_dp_rxq(dp_rxq); 521 sa = rxq->evq->sa; 522 sfc_adapter_lock(sa); 523 524 sw_index = dp_rxq->dpq.queue_id; 525 526 sfc_log_init(sa, "RxQ=%u", sw_index); 527 528 sfc_rx_qfini(sa, sw_index); 529 530 sfc_adapter_unlock(sa); 531 } 532 533 static int 534 sfc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 535 uint16_t nb_tx_desc, unsigned int socket_id, 536 const struct rte_eth_txconf *tx_conf) 537 { 538 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 539 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 540 struct sfc_txq_info *txq_info; 541 sfc_sw_index_t sw_index; 542 int rc; 543 544 sfc_log_init(sa, "TxQ = %u, nb_tx_desc = %u, socket_id = %u", 545 ethdev_qid, nb_tx_desc, socket_id); 546 547 sfc_adapter_lock(sa); 548 549 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 550 rc = sfc_tx_qinit(sa, sw_index, nb_tx_desc, socket_id, tx_conf); 551 if (rc != 0) 552 goto fail_tx_qinit; 553 554 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 555 dev->data->tx_queues[ethdev_qid] = txq_info->dp; 556 557 sfc_adapter_unlock(sa); 558 return 0; 559 560 fail_tx_qinit: 561 sfc_adapter_unlock(sa); 562 SFC_ASSERT(rc > 0); 563 return -rc; 564 } 565 566 static void 567 sfc_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 568 { 569 struct sfc_dp_txq *dp_txq = dev->data->tx_queues[qid]; 570 struct sfc_txq *txq; 571 sfc_sw_index_t sw_index; 572 struct sfc_adapter *sa; 573 574 if (dp_txq == NULL) 575 return; 576 577 txq = sfc_txq_by_dp_txq(dp_txq); 578 sw_index = dp_txq->dpq.queue_id; 579 580 SFC_ASSERT(txq->evq != NULL); 581 sa = txq->evq->sa; 582 583 sfc_log_init(sa, "TxQ = %u", sw_index); 584 585 sfc_adapter_lock(sa); 586 587 sfc_tx_qfini(sa, sw_index); 588 589 sfc_adapter_unlock(sa); 590 } 591 592 static void 593 sfc_stats_get_dp_rx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 594 { 595 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 596 uint64_t pkts_sum = 0; 597 uint64_t bytes_sum = 0; 598 unsigned int i; 599 600 for (i = 0; i < sas->ethdev_rxq_count; ++i) { 601 struct sfc_rxq_info *rxq_info; 602 603 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, i); 604 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 605 union sfc_pkts_bytes qstats; 606 607 sfc_pkts_bytes_get(&rxq_info->dp->dpq.stats, &qstats); 608 pkts_sum += qstats.pkts - 609 sa->sw_stats.reset_rx_pkts[i]; 610 bytes_sum += qstats.bytes - 611 sa->sw_stats.reset_rx_bytes[i]; 612 } 613 } 614 615 *pkts = pkts_sum; 616 *bytes = bytes_sum; 617 } 618 619 static void 620 sfc_stats_get_dp_tx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 621 { 622 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 623 uint64_t pkts_sum = 0; 624 uint64_t bytes_sum = 0; 625 unsigned int i; 626 627 for (i = 0; i < sas->ethdev_txq_count; ++i) { 628 struct sfc_txq_info *txq_info; 629 630 txq_info = sfc_txq_info_by_ethdev_qid(sas, i); 631 if (txq_info->state & SFC_TXQ_INITIALIZED) { 632 union sfc_pkts_bytes qstats; 633 634 sfc_pkts_bytes_get(&txq_info->dp->dpq.stats, &qstats); 635 pkts_sum += qstats.pkts - 636 sa->sw_stats.reset_tx_pkts[i]; 637 bytes_sum += qstats.bytes - 638 sa->sw_stats.reset_tx_bytes[i]; 639 } 640 } 641 642 *pkts = pkts_sum; 643 *bytes = bytes_sum; 644 } 645 646 /* 647 * Some statistics are computed as A - B where A and B each increase 648 * monotonically with some hardware counter(s) and the counters are read 649 * asynchronously. 650 * 651 * If packet X is counted in A, but not counted in B yet, computed value is 652 * greater than real. 653 * 654 * If packet X is not counted in A at the moment of reading the counter, 655 * but counted in B at the moment of reading the counter, computed value 656 * is less than real. 657 * 658 * However, counter which grows backward is worse evil than slightly wrong 659 * value. So, let's try to guarantee that it never happens except may be 660 * the case when the MAC stats are zeroed as a result of a NIC reset. 661 */ 662 static void 663 sfc_update_diff_stat(uint64_t *stat, uint64_t newval) 664 { 665 if ((int64_t)(newval - *stat) > 0 || newval == 0) 666 *stat = newval; 667 } 668 669 static int 670 sfc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 671 { 672 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 673 bool have_dp_rx_stats = sap->dp_rx->features & SFC_DP_RX_FEAT_STATS; 674 bool have_dp_tx_stats = sap->dp_tx->features & SFC_DP_TX_FEAT_STATS; 675 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 676 struct sfc_port *port = &sa->port; 677 uint64_t *mac_stats; 678 int ret; 679 680 sfc_adapter_lock(sa); 681 682 if (have_dp_rx_stats) 683 sfc_stats_get_dp_rx(sa, &stats->ipackets, &stats->ibytes); 684 if (have_dp_tx_stats) 685 sfc_stats_get_dp_tx(sa, &stats->opackets, &stats->obytes); 686 687 ret = sfc_port_update_mac_stats(sa, B_FALSE); 688 if (ret != 0) 689 goto unlock; 690 691 mac_stats = port->mac_stats_buf; 692 693 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, 694 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS)) { 695 if (!have_dp_rx_stats) { 696 stats->ipackets = 697 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS] + 698 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS] + 699 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]; 700 stats->ibytes = 701 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_BYTES] + 702 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES] + 703 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]; 704 705 /* CRC is included in these stats, but shouldn't be */ 706 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 707 } 708 if (!have_dp_tx_stats) { 709 stats->opackets = 710 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS] + 711 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS] + 712 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]; 713 stats->obytes = 714 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_BYTES] + 715 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES] + 716 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]; 717 718 /* CRC is included in these stats, but shouldn't be */ 719 stats->obytes -= stats->opackets * RTE_ETHER_CRC_LEN; 720 } 721 stats->imissed = mac_stats[EFX_MAC_VADAPTER_RX_BAD_PACKETS]; 722 stats->oerrors = mac_stats[EFX_MAC_VADAPTER_TX_BAD_PACKETS]; 723 } else { 724 if (!have_dp_tx_stats) { 725 stats->opackets = mac_stats[EFX_MAC_TX_PKTS]; 726 stats->obytes = mac_stats[EFX_MAC_TX_OCTETS] - 727 mac_stats[EFX_MAC_TX_PKTS] * RTE_ETHER_CRC_LEN; 728 } 729 730 /* 731 * Take into account stats which are whenever supported 732 * on EF10. If some stat is not supported by current 733 * firmware variant or HW revision, it is guaranteed 734 * to be zero in mac_stats. 735 */ 736 stats->imissed = 737 mac_stats[EFX_MAC_RX_NODESC_DROP_CNT] + 738 mac_stats[EFX_MAC_PM_TRUNC_BB_OVERFLOW] + 739 mac_stats[EFX_MAC_PM_DISCARD_BB_OVERFLOW] + 740 mac_stats[EFX_MAC_PM_TRUNC_VFIFO_FULL] + 741 mac_stats[EFX_MAC_PM_DISCARD_VFIFO_FULL] + 742 mac_stats[EFX_MAC_PM_TRUNC_QBB] + 743 mac_stats[EFX_MAC_PM_DISCARD_QBB] + 744 mac_stats[EFX_MAC_PM_DISCARD_MAPPING] + 745 mac_stats[EFX_MAC_RXDP_Q_DISABLED_PKTS] + 746 mac_stats[EFX_MAC_RXDP_DI_DROPPED_PKTS]; 747 stats->ierrors = 748 mac_stats[EFX_MAC_RX_FCS_ERRORS] + 749 mac_stats[EFX_MAC_RX_ALIGN_ERRORS] + 750 mac_stats[EFX_MAC_RX_JABBER_PKTS]; 751 /* no oerrors counters supported on EF10 */ 752 753 if (!have_dp_rx_stats) { 754 /* Exclude missed, errors and pauses from Rx packets */ 755 sfc_update_diff_stat(&port->ipackets, 756 mac_stats[EFX_MAC_RX_PKTS] - 757 mac_stats[EFX_MAC_RX_PAUSE_PKTS] - 758 stats->imissed - stats->ierrors); 759 stats->ipackets = port->ipackets; 760 stats->ibytes = mac_stats[EFX_MAC_RX_OCTETS] - 761 mac_stats[EFX_MAC_RX_PKTS] * RTE_ETHER_CRC_LEN; 762 } 763 } 764 765 unlock: 766 sfc_adapter_unlock(sa); 767 SFC_ASSERT(ret >= 0); 768 return -ret; 769 } 770 771 static int 772 sfc_stats_reset(struct rte_eth_dev *dev) 773 { 774 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 775 struct sfc_port *port = &sa->port; 776 int rc; 777 778 sfc_adapter_lock(sa); 779 780 if (sa->state != SFC_ETHDEV_STARTED) { 781 /* 782 * The operation cannot be done if port is not started; it 783 * will be scheduled to be done during the next port start 784 */ 785 port->mac_stats_reset_pending = B_TRUE; 786 sfc_adapter_unlock(sa); 787 return 0; 788 } 789 790 rc = sfc_port_reset_mac_stats(sa); 791 if (rc != 0) 792 sfc_err(sa, "failed to reset statistics (rc = %d)", rc); 793 794 sfc_sw_xstats_reset(sa); 795 796 sfc_adapter_unlock(sa); 797 798 SFC_ASSERT(rc >= 0); 799 return -rc; 800 } 801 802 static unsigned int 803 sfc_xstats_get_nb_supported(struct sfc_adapter *sa) 804 { 805 struct sfc_port *port = &sa->port; 806 unsigned int nb_supported; 807 808 sfc_adapter_lock(sa); 809 nb_supported = port->mac_stats_nb_supported + 810 sfc_sw_xstats_get_nb_supported(sa); 811 sfc_adapter_unlock(sa); 812 813 return nb_supported; 814 } 815 816 static int 817 sfc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 818 unsigned int xstats_count) 819 { 820 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 821 unsigned int nb_written = 0; 822 unsigned int nb_supported = 0; 823 int rc; 824 825 if (unlikely(xstats == NULL)) 826 return sfc_xstats_get_nb_supported(sa); 827 828 rc = sfc_port_get_mac_stats(sa, xstats, xstats_count, &nb_written); 829 if (rc < 0) 830 return rc; 831 832 nb_supported = rc; 833 sfc_sw_xstats_get_vals(sa, xstats, xstats_count, &nb_written, 834 &nb_supported); 835 836 return nb_supported; 837 } 838 839 static int 840 sfc_xstats_get_names(struct rte_eth_dev *dev, 841 struct rte_eth_xstat_name *xstats_names, 842 unsigned int xstats_count) 843 { 844 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 845 struct sfc_port *port = &sa->port; 846 unsigned int i; 847 unsigned int nstats = 0; 848 unsigned int nb_written = 0; 849 int ret; 850 851 if (unlikely(xstats_names == NULL)) 852 return sfc_xstats_get_nb_supported(sa); 853 854 for (i = 0; i < EFX_MAC_NSTATS; ++i) { 855 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, i)) { 856 if (nstats < xstats_count) { 857 strlcpy(xstats_names[nstats].name, 858 efx_mac_stat_name(sa->nic, i), 859 sizeof(xstats_names[0].name)); 860 nb_written++; 861 } 862 nstats++; 863 } 864 } 865 866 ret = sfc_sw_xstats_get_names(sa, xstats_names, xstats_count, 867 &nb_written, &nstats); 868 if (ret != 0) { 869 SFC_ASSERT(ret < 0); 870 return ret; 871 } 872 873 return nstats; 874 } 875 876 static int 877 sfc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 878 uint64_t *values, unsigned int n) 879 { 880 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 881 struct sfc_port *port = &sa->port; 882 unsigned int nb_supported; 883 unsigned int i; 884 int rc; 885 886 if (unlikely(ids == NULL || values == NULL)) 887 return -EINVAL; 888 889 /* 890 * Values array could be filled in nonsequential order. Fill values with 891 * constant indicating invalid ID first. 892 */ 893 for (i = 0; i < n; i++) 894 values[i] = SFC_XSTAT_ID_INVALID_VAL; 895 896 rc = sfc_port_get_mac_stats_by_id(sa, ids, values, n); 897 if (rc != 0) 898 return rc; 899 900 nb_supported = port->mac_stats_nb_supported; 901 sfc_sw_xstats_get_vals_by_id(sa, ids, values, n, &nb_supported); 902 903 /* Return number of written stats before invalid ID is encountered. */ 904 for (i = 0; i < n; i++) { 905 if (values[i] == SFC_XSTAT_ID_INVALID_VAL) 906 return i; 907 } 908 909 return n; 910 } 911 912 static int 913 sfc_xstats_get_names_by_id(struct rte_eth_dev *dev, 914 const uint64_t *ids, 915 struct rte_eth_xstat_name *xstats_names, 916 unsigned int size) 917 { 918 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 919 struct sfc_port *port = &sa->port; 920 unsigned int nb_supported; 921 unsigned int i; 922 int ret; 923 924 if (unlikely(xstats_names == NULL && ids != NULL) || 925 unlikely(xstats_names != NULL && ids == NULL)) 926 return -EINVAL; 927 928 if (unlikely(xstats_names == NULL && ids == NULL)) 929 return sfc_xstats_get_nb_supported(sa); 930 931 /* 932 * Names array could be filled in nonsequential order. Fill names with 933 * string indicating invalid ID first. 934 */ 935 for (i = 0; i < size; i++) 936 xstats_names[i].name[0] = SFC_XSTAT_ID_INVALID_NAME; 937 938 sfc_adapter_lock(sa); 939 940 SFC_ASSERT(port->mac_stats_nb_supported <= 941 RTE_DIM(port->mac_stats_by_id)); 942 943 for (i = 0; i < size; i++) { 944 if (ids[i] < port->mac_stats_nb_supported) { 945 strlcpy(xstats_names[i].name, 946 efx_mac_stat_name(sa->nic, 947 port->mac_stats_by_id[ids[i]]), 948 sizeof(xstats_names[0].name)); 949 } 950 } 951 952 nb_supported = port->mac_stats_nb_supported; 953 954 sfc_adapter_unlock(sa); 955 956 ret = sfc_sw_xstats_get_names_by_id(sa, ids, xstats_names, size, 957 &nb_supported); 958 if (ret != 0) { 959 SFC_ASSERT(ret < 0); 960 return ret; 961 } 962 963 /* Return number of written names before invalid ID is encountered. */ 964 for (i = 0; i < size; i++) { 965 if (xstats_names[i].name[0] == SFC_XSTAT_ID_INVALID_NAME) 966 return i; 967 } 968 969 return size; 970 } 971 972 static int 973 sfc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 974 { 975 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 976 unsigned int wanted_fc, link_fc; 977 978 memset(fc_conf, 0, sizeof(*fc_conf)); 979 980 sfc_adapter_lock(sa); 981 982 if (sa->state == SFC_ETHDEV_STARTED) 983 efx_mac_fcntl_get(sa->nic, &wanted_fc, &link_fc); 984 else 985 link_fc = sa->port.flow_ctrl; 986 987 switch (link_fc) { 988 case 0: 989 fc_conf->mode = RTE_ETH_FC_NONE; 990 break; 991 case EFX_FCNTL_RESPOND: 992 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 993 break; 994 case EFX_FCNTL_GENERATE: 995 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 996 break; 997 case (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE): 998 fc_conf->mode = RTE_ETH_FC_FULL; 999 break; 1000 default: 1001 sfc_err(sa, "%s: unexpected flow control value %#x", 1002 __func__, link_fc); 1003 } 1004 1005 fc_conf->autoneg = sa->port.flow_ctrl_autoneg; 1006 1007 sfc_adapter_unlock(sa); 1008 1009 return 0; 1010 } 1011 1012 static int 1013 sfc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1014 { 1015 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1016 struct sfc_port *port = &sa->port; 1017 unsigned int fcntl; 1018 int rc; 1019 1020 if (fc_conf->high_water != 0 || fc_conf->low_water != 0 || 1021 fc_conf->pause_time != 0 || fc_conf->send_xon != 0 || 1022 fc_conf->mac_ctrl_frame_fwd != 0) { 1023 sfc_err(sa, "unsupported flow control settings specified"); 1024 rc = EINVAL; 1025 goto fail_inval; 1026 } 1027 1028 switch (fc_conf->mode) { 1029 case RTE_ETH_FC_NONE: 1030 fcntl = 0; 1031 break; 1032 case RTE_ETH_FC_RX_PAUSE: 1033 fcntl = EFX_FCNTL_RESPOND; 1034 break; 1035 case RTE_ETH_FC_TX_PAUSE: 1036 fcntl = EFX_FCNTL_GENERATE; 1037 break; 1038 case RTE_ETH_FC_FULL: 1039 fcntl = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 1040 break; 1041 default: 1042 rc = EINVAL; 1043 goto fail_inval; 1044 } 1045 1046 sfc_adapter_lock(sa); 1047 1048 if (sa->state == SFC_ETHDEV_STARTED) { 1049 rc = efx_mac_fcntl_set(sa->nic, fcntl, fc_conf->autoneg); 1050 if (rc != 0) 1051 goto fail_mac_fcntl_set; 1052 } 1053 1054 port->flow_ctrl = fcntl; 1055 port->flow_ctrl_autoneg = fc_conf->autoneg; 1056 1057 sfc_adapter_unlock(sa); 1058 1059 return 0; 1060 1061 fail_mac_fcntl_set: 1062 sfc_adapter_unlock(sa); 1063 fail_inval: 1064 SFC_ASSERT(rc > 0); 1065 return -rc; 1066 } 1067 1068 static int 1069 sfc_check_scatter_on_all_rx_queues(struct sfc_adapter *sa, size_t pdu) 1070 { 1071 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1072 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1073 boolean_t scatter_enabled; 1074 const char *error; 1075 unsigned int i; 1076 1077 for (i = 0; i < sas->rxq_count; i++) { 1078 if ((sas->rxq_info[i].state & SFC_RXQ_INITIALIZED) == 0) 1079 continue; 1080 1081 scatter_enabled = (sas->rxq_info[i].type_flags & 1082 EFX_RXQ_FLAG_SCATTER); 1083 1084 if (!sfc_rx_check_scatter(pdu, sa->rxq_ctrl[i].buf_size, 1085 encp->enc_rx_prefix_size, 1086 scatter_enabled, 1087 encp->enc_rx_scatter_max, &error)) { 1088 sfc_err(sa, "MTU check for RxQ %u failed: %s", i, 1089 error); 1090 return EINVAL; 1091 } 1092 } 1093 1094 return 0; 1095 } 1096 1097 static int 1098 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1099 { 1100 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1101 size_t pdu = EFX_MAC_PDU(mtu); 1102 size_t old_pdu; 1103 int rc; 1104 1105 sfc_log_init(sa, "mtu=%u", mtu); 1106 1107 rc = EINVAL; 1108 if (pdu < EFX_MAC_PDU_MIN) { 1109 sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)", 1110 (unsigned int)mtu, (unsigned int)pdu, 1111 EFX_MAC_PDU_MIN); 1112 goto fail_inval; 1113 } 1114 if (pdu > EFX_MAC_PDU_MAX) { 1115 sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)", 1116 (unsigned int)mtu, (unsigned int)pdu, 1117 (unsigned int)EFX_MAC_PDU_MAX); 1118 goto fail_inval; 1119 } 1120 1121 sfc_adapter_lock(sa); 1122 1123 rc = sfc_check_scatter_on_all_rx_queues(sa, pdu); 1124 if (rc != 0) 1125 goto fail_check_scatter; 1126 1127 if (pdu != sa->port.pdu) { 1128 if (sa->state == SFC_ETHDEV_STARTED) { 1129 sfc_stop(sa); 1130 1131 old_pdu = sa->port.pdu; 1132 sa->port.pdu = pdu; 1133 rc = sfc_start(sa); 1134 if (rc != 0) 1135 goto fail_start; 1136 } else { 1137 sa->port.pdu = pdu; 1138 } 1139 } 1140 1141 sfc_adapter_unlock(sa); 1142 1143 sfc_log_init(sa, "done"); 1144 return 0; 1145 1146 fail_start: 1147 sa->port.pdu = old_pdu; 1148 if (sfc_start(sa) != 0) 1149 sfc_err(sa, "cannot start with neither new (%u) nor old (%u) " 1150 "PDU max size - port is stopped", 1151 (unsigned int)pdu, (unsigned int)old_pdu); 1152 1153 fail_check_scatter: 1154 sfc_adapter_unlock(sa); 1155 1156 fail_inval: 1157 sfc_log_init(sa, "failed %d", rc); 1158 SFC_ASSERT(rc > 0); 1159 return -rc; 1160 } 1161 static int 1162 sfc_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1163 { 1164 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1165 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1166 struct sfc_port *port = &sa->port; 1167 struct rte_ether_addr *old_addr = &dev->data->mac_addrs[0]; 1168 int rc = 0; 1169 1170 sfc_adapter_lock(sa); 1171 1172 if (rte_is_same_ether_addr(mac_addr, &port->default_mac_addr)) 1173 goto unlock; 1174 1175 /* 1176 * Copy the address to the device private data so that 1177 * it could be recalled in the case of adapter restart. 1178 */ 1179 rte_ether_addr_copy(mac_addr, &port->default_mac_addr); 1180 1181 /* 1182 * Neither of the two following checks can return 1183 * an error. The new MAC address is preserved in 1184 * the device private data and can be activated 1185 * on the next port start if the user prevents 1186 * isolated mode from being enabled. 1187 */ 1188 if (sfc_sa2shared(sa)->isolated) { 1189 sfc_warn(sa, "isolated mode is active on the port"); 1190 sfc_warn(sa, "will not set MAC address"); 1191 goto unlock; 1192 } 1193 1194 if (sa->state != SFC_ETHDEV_STARTED) { 1195 sfc_notice(sa, "the port is not started"); 1196 sfc_notice(sa, "the new MAC address will be set on port start"); 1197 1198 goto unlock; 1199 } 1200 1201 if (encp->enc_allow_set_mac_with_installed_filters) { 1202 rc = efx_mac_addr_set(sa->nic, mac_addr->addr_bytes); 1203 if (rc != 0) { 1204 sfc_err(sa, "cannot set MAC address (rc = %u)", rc); 1205 goto unlock; 1206 } 1207 1208 /* 1209 * Changing the MAC address by means of MCDI request 1210 * has no effect on received traffic, therefore 1211 * we also need to update unicast filters 1212 */ 1213 rc = sfc_set_rx_mode_unchecked(sa); 1214 if (rc != 0) { 1215 sfc_err(sa, "cannot set filter (rc = %u)", rc); 1216 /* Rollback the old address */ 1217 (void)efx_mac_addr_set(sa->nic, old_addr->addr_bytes); 1218 (void)sfc_set_rx_mode_unchecked(sa); 1219 } 1220 } else { 1221 sfc_warn(sa, "cannot set MAC address with filters installed"); 1222 sfc_warn(sa, "adapter will be restarted to pick the new MAC"); 1223 sfc_warn(sa, "(some traffic may be dropped)"); 1224 1225 /* 1226 * Since setting MAC address with filters installed is not 1227 * allowed on the adapter, the new MAC address will be set 1228 * by means of adapter restart. sfc_start() shall retrieve 1229 * the new address from the device private data and set it. 1230 */ 1231 sfc_stop(sa); 1232 rc = sfc_start(sa); 1233 if (rc != 0) 1234 sfc_err(sa, "cannot restart adapter (rc = %u)", rc); 1235 } 1236 1237 unlock: 1238 if (rc != 0) 1239 rte_ether_addr_copy(old_addr, &port->default_mac_addr); 1240 1241 sfc_adapter_unlock(sa); 1242 1243 SFC_ASSERT(rc >= 0); 1244 return -rc; 1245 } 1246 1247 1248 static int 1249 sfc_set_mc_addr_list(struct rte_eth_dev *dev, 1250 struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr) 1251 { 1252 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1253 struct sfc_port *port = &sa->port; 1254 uint8_t *mc_addrs = port->mcast_addrs; 1255 int rc; 1256 unsigned int i; 1257 1258 if (sfc_sa2shared(sa)->isolated) { 1259 sfc_err(sa, "isolated mode is active on the port"); 1260 sfc_err(sa, "will not set multicast address list"); 1261 return -ENOTSUP; 1262 } 1263 1264 if (mc_addrs == NULL) 1265 return -ENOBUFS; 1266 1267 if (nb_mc_addr > port->max_mcast_addrs) { 1268 sfc_err(sa, "too many multicast addresses: %u > %u", 1269 nb_mc_addr, port->max_mcast_addrs); 1270 return -EINVAL; 1271 } 1272 1273 for (i = 0; i < nb_mc_addr; ++i) { 1274 rte_memcpy(mc_addrs, mc_addr_set[i].addr_bytes, 1275 EFX_MAC_ADDR_LEN); 1276 mc_addrs += EFX_MAC_ADDR_LEN; 1277 } 1278 1279 port->nb_mcast_addrs = nb_mc_addr; 1280 1281 if (sa->state != SFC_ETHDEV_STARTED) 1282 return 0; 1283 1284 rc = efx_mac_multicast_list_set(sa->nic, port->mcast_addrs, 1285 port->nb_mcast_addrs); 1286 if (rc != 0) 1287 sfc_err(sa, "cannot set multicast address list (rc = %u)", rc); 1288 1289 SFC_ASSERT(rc >= 0); 1290 return -rc; 1291 } 1292 1293 /* 1294 * The function is used by the secondary process as well. It must not 1295 * use any process-local pointers from the adapter data. 1296 */ 1297 static void 1298 sfc_rx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1299 struct rte_eth_rxq_info *qinfo) 1300 { 1301 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1302 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1303 struct sfc_rxq_info *rxq_info; 1304 1305 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1306 1307 qinfo->mp = rxq_info->refill_mb_pool; 1308 qinfo->conf.rx_free_thresh = rxq_info->refill_threshold; 1309 qinfo->conf.rx_drop_en = 1; 1310 qinfo->conf.rx_deferred_start = rxq_info->deferred_start; 1311 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 1312 if (rxq_info->type_flags & EFX_RXQ_FLAG_SCATTER) { 1313 qinfo->conf.offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; 1314 qinfo->scattered_rx = 1; 1315 } 1316 qinfo->nb_desc = rxq_info->entries; 1317 } 1318 1319 /* 1320 * The function is used by the secondary process as well. It must not 1321 * use any process-local pointers from the adapter data. 1322 */ 1323 static void 1324 sfc_tx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1325 struct rte_eth_txq_info *qinfo) 1326 { 1327 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1328 struct sfc_txq_info *txq_info; 1329 1330 SFC_ASSERT(ethdev_qid < sas->ethdev_txq_count); 1331 1332 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1333 1334 memset(qinfo, 0, sizeof(*qinfo)); 1335 1336 qinfo->conf.offloads = txq_info->offloads; 1337 qinfo->conf.tx_free_thresh = txq_info->free_thresh; 1338 qinfo->conf.tx_deferred_start = txq_info->deferred_start; 1339 qinfo->nb_desc = txq_info->entries; 1340 } 1341 1342 /* 1343 * The function is used by the secondary process as well. It must not 1344 * use any process-local pointers from the adapter data. 1345 */ 1346 static uint32_t 1347 sfc_rx_queue_count(void *rx_queue) 1348 { 1349 struct sfc_dp_rxq *dp_rxq = rx_queue; 1350 const struct sfc_dp_rx *dp_rx; 1351 struct sfc_rxq_info *rxq_info; 1352 1353 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1354 rxq_info = sfc_rxq_info_by_dp_rxq(dp_rxq); 1355 1356 if ((rxq_info->state & SFC_RXQ_STARTED) == 0) 1357 return 0; 1358 1359 return dp_rx->qdesc_npending(dp_rxq); 1360 } 1361 1362 /* 1363 * The function is used by the secondary process as well. It must not 1364 * use any process-local pointers from the adapter data. 1365 */ 1366 static int 1367 sfc_rx_descriptor_status(void *queue, uint16_t offset) 1368 { 1369 struct sfc_dp_rxq *dp_rxq = queue; 1370 const struct sfc_dp_rx *dp_rx; 1371 1372 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1373 1374 return dp_rx->qdesc_status(dp_rxq, offset); 1375 } 1376 1377 /* 1378 * The function is used by the secondary process as well. It must not 1379 * use any process-local pointers from the adapter data. 1380 */ 1381 static int 1382 sfc_tx_descriptor_status(void *queue, uint16_t offset) 1383 { 1384 struct sfc_dp_txq *dp_txq = queue; 1385 const struct sfc_dp_tx *dp_tx; 1386 1387 dp_tx = sfc_dp_tx_by_dp_txq(dp_txq); 1388 1389 return dp_tx->qdesc_status(dp_txq, offset); 1390 } 1391 1392 static int 1393 sfc_rx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1394 { 1395 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1396 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1397 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1398 struct sfc_rxq_info *rxq_info; 1399 sfc_sw_index_t sw_index; 1400 int rc; 1401 1402 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1403 1404 sfc_adapter_lock(sa); 1405 1406 rc = EINVAL; 1407 if (sa->state != SFC_ETHDEV_STARTED) 1408 goto fail_not_started; 1409 1410 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1411 if (rxq_info->state != SFC_RXQ_INITIALIZED) 1412 goto fail_not_setup; 1413 1414 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1415 rc = sfc_rx_qstart(sa, sw_index); 1416 if (rc != 0) 1417 goto fail_rx_qstart; 1418 1419 rxq_info->deferred_started = B_TRUE; 1420 1421 sfc_adapter_unlock(sa); 1422 1423 return 0; 1424 1425 fail_rx_qstart: 1426 fail_not_setup: 1427 fail_not_started: 1428 sfc_adapter_unlock(sa); 1429 SFC_ASSERT(rc > 0); 1430 return -rc; 1431 } 1432 1433 static int 1434 sfc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1435 { 1436 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1437 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1438 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1439 struct sfc_rxq_info *rxq_info; 1440 sfc_sw_index_t sw_index; 1441 1442 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1443 1444 sfc_adapter_lock(sa); 1445 1446 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1447 sfc_rx_qstop(sa, sw_index); 1448 1449 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1450 rxq_info->deferred_started = B_FALSE; 1451 1452 sfc_adapter_unlock(sa); 1453 1454 return 0; 1455 } 1456 1457 static int 1458 sfc_tx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1459 { 1460 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1461 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1462 struct sfc_txq_info *txq_info; 1463 sfc_sw_index_t sw_index; 1464 int rc; 1465 1466 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1467 1468 sfc_adapter_lock(sa); 1469 1470 rc = EINVAL; 1471 if (sa->state != SFC_ETHDEV_STARTED) 1472 goto fail_not_started; 1473 1474 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1475 if (txq_info->state != SFC_TXQ_INITIALIZED) 1476 goto fail_not_setup; 1477 1478 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1479 rc = sfc_tx_qstart(sa, sw_index); 1480 if (rc != 0) 1481 goto fail_tx_qstart; 1482 1483 txq_info->deferred_started = B_TRUE; 1484 1485 sfc_adapter_unlock(sa); 1486 return 0; 1487 1488 fail_tx_qstart: 1489 1490 fail_not_setup: 1491 fail_not_started: 1492 sfc_adapter_unlock(sa); 1493 SFC_ASSERT(rc > 0); 1494 return -rc; 1495 } 1496 1497 static int 1498 sfc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1499 { 1500 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1501 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1502 struct sfc_txq_info *txq_info; 1503 sfc_sw_index_t sw_index; 1504 1505 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1506 1507 sfc_adapter_lock(sa); 1508 1509 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1510 sfc_tx_qstop(sa, sw_index); 1511 1512 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1513 txq_info->deferred_started = B_FALSE; 1514 1515 sfc_adapter_unlock(sa); 1516 return 0; 1517 } 1518 1519 static efx_tunnel_protocol_t 1520 sfc_tunnel_rte_type_to_efx_udp_proto(enum rte_eth_tunnel_type rte_type) 1521 { 1522 switch (rte_type) { 1523 case RTE_ETH_TUNNEL_TYPE_VXLAN: 1524 return EFX_TUNNEL_PROTOCOL_VXLAN; 1525 case RTE_ETH_TUNNEL_TYPE_GENEVE: 1526 return EFX_TUNNEL_PROTOCOL_GENEVE; 1527 default: 1528 return EFX_TUNNEL_NPROTOS; 1529 } 1530 } 1531 1532 enum sfc_udp_tunnel_op_e { 1533 SFC_UDP_TUNNEL_ADD_PORT, 1534 SFC_UDP_TUNNEL_DEL_PORT, 1535 }; 1536 1537 static int 1538 sfc_dev_udp_tunnel_op(struct rte_eth_dev *dev, 1539 struct rte_eth_udp_tunnel *tunnel_udp, 1540 enum sfc_udp_tunnel_op_e op) 1541 { 1542 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1543 efx_tunnel_protocol_t tunnel_proto; 1544 int rc; 1545 1546 sfc_log_init(sa, "%s udp_port=%u prot_type=%u", 1547 (op == SFC_UDP_TUNNEL_ADD_PORT) ? "add" : 1548 (op == SFC_UDP_TUNNEL_DEL_PORT) ? "delete" : "unknown", 1549 tunnel_udp->udp_port, tunnel_udp->prot_type); 1550 1551 tunnel_proto = 1552 sfc_tunnel_rte_type_to_efx_udp_proto(tunnel_udp->prot_type); 1553 if (tunnel_proto >= EFX_TUNNEL_NPROTOS) { 1554 rc = ENOTSUP; 1555 goto fail_bad_proto; 1556 } 1557 1558 sfc_adapter_lock(sa); 1559 1560 switch (op) { 1561 case SFC_UDP_TUNNEL_ADD_PORT: 1562 rc = efx_tunnel_config_udp_add(sa->nic, 1563 tunnel_udp->udp_port, 1564 tunnel_proto); 1565 break; 1566 case SFC_UDP_TUNNEL_DEL_PORT: 1567 rc = efx_tunnel_config_udp_remove(sa->nic, 1568 tunnel_udp->udp_port, 1569 tunnel_proto); 1570 break; 1571 default: 1572 rc = EINVAL; 1573 goto fail_bad_op; 1574 } 1575 1576 if (rc != 0) 1577 goto fail_op; 1578 1579 if (sa->state == SFC_ETHDEV_STARTED) { 1580 rc = efx_tunnel_reconfigure(sa->nic); 1581 if (rc == EAGAIN) { 1582 /* 1583 * Configuration is accepted by FW and MC reboot 1584 * is initiated to apply the changes. MC reboot 1585 * will be handled in a usual way (MC reboot 1586 * event on management event queue and adapter 1587 * restart). 1588 */ 1589 rc = 0; 1590 } else if (rc != 0) { 1591 goto fail_reconfigure; 1592 } 1593 } 1594 1595 sfc_adapter_unlock(sa); 1596 return 0; 1597 1598 fail_reconfigure: 1599 /* Remove/restore entry since the change makes the trouble */ 1600 switch (op) { 1601 case SFC_UDP_TUNNEL_ADD_PORT: 1602 (void)efx_tunnel_config_udp_remove(sa->nic, 1603 tunnel_udp->udp_port, 1604 tunnel_proto); 1605 break; 1606 case SFC_UDP_TUNNEL_DEL_PORT: 1607 (void)efx_tunnel_config_udp_add(sa->nic, 1608 tunnel_udp->udp_port, 1609 tunnel_proto); 1610 break; 1611 } 1612 1613 fail_op: 1614 fail_bad_op: 1615 sfc_adapter_unlock(sa); 1616 1617 fail_bad_proto: 1618 SFC_ASSERT(rc > 0); 1619 return -rc; 1620 } 1621 1622 static int 1623 sfc_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 1624 struct rte_eth_udp_tunnel *tunnel_udp) 1625 { 1626 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_ADD_PORT); 1627 } 1628 1629 static int 1630 sfc_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 1631 struct rte_eth_udp_tunnel *tunnel_udp) 1632 { 1633 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_DEL_PORT); 1634 } 1635 1636 /* 1637 * The function is used by the secondary process as well. It must not 1638 * use any process-local pointers from the adapter data. 1639 */ 1640 static int 1641 sfc_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1642 struct rte_eth_rss_conf *rss_conf) 1643 { 1644 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1645 struct sfc_rss *rss = &sas->rss; 1646 1647 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) 1648 return -ENOTSUP; 1649 1650 /* 1651 * Mapping of hash configuration between RTE and EFX is not one-to-one, 1652 * hence, conversion is done here to derive a correct set of RTE_ETH_RSS 1653 * flags which corresponds to the active EFX configuration stored 1654 * locally in 'sfc_adapter' and kept up-to-date 1655 */ 1656 rss_conf->rss_hf = sfc_rx_hf_efx_to_rte(rss, rss->hash_types); 1657 rss_conf->rss_key_len = EFX_RSS_KEY_SIZE; 1658 if (rss_conf->rss_key != NULL) 1659 rte_memcpy(rss_conf->rss_key, rss->key, EFX_RSS_KEY_SIZE); 1660 1661 return 0; 1662 } 1663 1664 static int 1665 sfc_dev_rss_hash_update(struct rte_eth_dev *dev, 1666 struct rte_eth_rss_conf *rss_conf) 1667 { 1668 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1669 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1670 unsigned int efx_hash_types; 1671 unsigned int n_contexts; 1672 unsigned int mode_i = 0; 1673 unsigned int key_i = 0; 1674 uint32_t contexts[2]; 1675 unsigned int i = 0; 1676 int rc = 0; 1677 1678 if (sfc_sa2shared(sa)->isolated) 1679 return -ENOTSUP; 1680 1681 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1682 sfc_err(sa, "RSS is not available"); 1683 return -ENOTSUP; 1684 } 1685 1686 if (rss->channels == 0) { 1687 sfc_err(sa, "RSS is not configured"); 1688 return -EINVAL; 1689 } 1690 1691 if ((rss_conf->rss_key != NULL) && 1692 (rss_conf->rss_key_len != sizeof(rss->key))) { 1693 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1694 sizeof(rss->key)); 1695 return -EINVAL; 1696 } 1697 1698 sfc_adapter_lock(sa); 1699 1700 rc = sfc_rx_hf_rte_to_efx(sa, rss_conf->rss_hf, &efx_hash_types); 1701 if (rc != 0) 1702 goto fail_rx_hf_rte_to_efx; 1703 1704 contexts[0] = EFX_RSS_CONTEXT_DEFAULT; 1705 contexts[1] = rss->dummy_ctx.nic_handle; 1706 n_contexts = (rss->dummy_ctx.nic_handle_refcnt == 0) ? 1 : 2; 1707 1708 for (mode_i = 0; mode_i < n_contexts; mode_i++) { 1709 rc = efx_rx_scale_mode_set(sa->nic, contexts[mode_i], 1710 rss->hash_alg, efx_hash_types, 1711 B_TRUE); 1712 if (rc != 0) 1713 goto fail_scale_mode_set; 1714 } 1715 1716 if (rss_conf->rss_key != NULL) { 1717 if (sa->state == SFC_ETHDEV_STARTED) { 1718 for (key_i = 0; key_i < n_contexts; key_i++) { 1719 rc = efx_rx_scale_key_set(sa->nic, 1720 contexts[key_i], 1721 rss_conf->rss_key, 1722 sizeof(rss->key)); 1723 if (rc != 0) 1724 goto fail_scale_key_set; 1725 } 1726 } 1727 1728 rte_memcpy(rss->key, rss_conf->rss_key, sizeof(rss->key)); 1729 } 1730 1731 rss->hash_types = efx_hash_types; 1732 1733 sfc_adapter_unlock(sa); 1734 1735 return 0; 1736 1737 fail_scale_key_set: 1738 for (i = 0; i < key_i; i++) { 1739 if (efx_rx_scale_key_set(sa->nic, contexts[i], rss->key, 1740 sizeof(rss->key)) != 0) 1741 sfc_err(sa, "failed to restore RSS key"); 1742 } 1743 1744 fail_scale_mode_set: 1745 for (i = 0; i < mode_i; i++) { 1746 if (efx_rx_scale_mode_set(sa->nic, contexts[i], 1747 EFX_RX_HASHALG_TOEPLITZ, 1748 rss->hash_types, B_TRUE) != 0) 1749 sfc_err(sa, "failed to restore RSS mode"); 1750 } 1751 1752 fail_rx_hf_rte_to_efx: 1753 sfc_adapter_unlock(sa); 1754 return -rc; 1755 } 1756 1757 /* 1758 * The function is used by the secondary process as well. It must not 1759 * use any process-local pointers from the adapter data. 1760 */ 1761 static int 1762 sfc_dev_rss_reta_query(struct rte_eth_dev *dev, 1763 struct rte_eth_rss_reta_entry64 *reta_conf, 1764 uint16_t reta_size) 1765 { 1766 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1767 struct sfc_rss *rss = &sas->rss; 1768 int entry; 1769 1770 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE || sas->isolated) 1771 return -ENOTSUP; 1772 1773 if (rss->channels == 0) 1774 return -EINVAL; 1775 1776 if (reta_size != EFX_RSS_TBL_SIZE) 1777 return -EINVAL; 1778 1779 for (entry = 0; entry < reta_size; entry++) { 1780 int grp = entry / RTE_ETH_RETA_GROUP_SIZE; 1781 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1782 1783 if ((reta_conf[grp].mask >> grp_idx) & 1) 1784 reta_conf[grp].reta[grp_idx] = rss->tbl[entry]; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static int 1791 sfc_dev_rss_reta_update(struct rte_eth_dev *dev, 1792 struct rte_eth_rss_reta_entry64 *reta_conf, 1793 uint16_t reta_size) 1794 { 1795 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1796 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1797 unsigned int *rss_tbl_new; 1798 uint16_t entry; 1799 int rc = 0; 1800 1801 1802 if (sfc_sa2shared(sa)->isolated) 1803 return -ENOTSUP; 1804 1805 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1806 sfc_err(sa, "RSS is not available"); 1807 return -ENOTSUP; 1808 } 1809 1810 if (rss->channels == 0) { 1811 sfc_err(sa, "RSS is not configured"); 1812 return -EINVAL; 1813 } 1814 1815 if (reta_size != EFX_RSS_TBL_SIZE) { 1816 sfc_err(sa, "RETA size is wrong (should be %u)", 1817 EFX_RSS_TBL_SIZE); 1818 return -EINVAL; 1819 } 1820 1821 rss_tbl_new = rte_zmalloc("rss_tbl_new", sizeof(rss->tbl), 0); 1822 if (rss_tbl_new == NULL) 1823 return -ENOMEM; 1824 1825 sfc_adapter_lock(sa); 1826 1827 rte_memcpy(rss_tbl_new, rss->tbl, sizeof(rss->tbl)); 1828 1829 for (entry = 0; entry < reta_size; entry++) { 1830 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1831 struct rte_eth_rss_reta_entry64 *grp; 1832 1833 grp = &reta_conf[entry / RTE_ETH_RETA_GROUP_SIZE]; 1834 1835 if (grp->mask & (1ull << grp_idx)) { 1836 if (grp->reta[grp_idx] >= rss->channels) { 1837 rc = EINVAL; 1838 goto bad_reta_entry; 1839 } 1840 rss_tbl_new[entry] = grp->reta[grp_idx]; 1841 } 1842 } 1843 1844 if (sa->state == SFC_ETHDEV_STARTED) { 1845 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1846 rss_tbl_new, EFX_RSS_TBL_SIZE); 1847 if (rc != 0) 1848 goto fail_scale_tbl_set; 1849 } 1850 1851 rte_memcpy(rss->tbl, rss_tbl_new, sizeof(rss->tbl)); 1852 1853 fail_scale_tbl_set: 1854 bad_reta_entry: 1855 sfc_adapter_unlock(sa); 1856 1857 rte_free(rss_tbl_new); 1858 1859 SFC_ASSERT(rc >= 0); 1860 return -rc; 1861 } 1862 1863 static int 1864 sfc_dev_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 1865 const struct rte_flow_ops **ops) 1866 { 1867 *ops = &sfc_flow_ops; 1868 return 0; 1869 } 1870 1871 static int 1872 sfc_pool_ops_supported(struct rte_eth_dev *dev, const char *pool) 1873 { 1874 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1875 1876 /* 1877 * If Rx datapath does not provide callback to check mempool, 1878 * all pools are supported. 1879 */ 1880 if (sap->dp_rx->pool_ops_supported == NULL) 1881 return 1; 1882 1883 return sap->dp_rx->pool_ops_supported(pool); 1884 } 1885 1886 static int 1887 sfc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1888 { 1889 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1890 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1891 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1892 struct sfc_rxq_info *rxq_info; 1893 1894 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1895 1896 return sap->dp_rx->intr_enable(rxq_info->dp); 1897 } 1898 1899 static int 1900 sfc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1901 { 1902 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1903 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1904 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1905 struct sfc_rxq_info *rxq_info; 1906 1907 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1908 1909 return sap->dp_rx->intr_disable(rxq_info->dp); 1910 } 1911 1912 struct sfc_mport_journal_ctx { 1913 struct sfc_adapter *sa; 1914 uint16_t switch_domain_id; 1915 uint32_t mcdi_handle; 1916 bool controllers_assigned; 1917 efx_pcie_interface_t *controllers; 1918 size_t nb_controllers; 1919 }; 1920 1921 static int 1922 sfc_journal_ctx_add_controller(struct sfc_mport_journal_ctx *ctx, 1923 efx_pcie_interface_t intf) 1924 { 1925 efx_pcie_interface_t *new_controllers; 1926 size_t i, target; 1927 size_t new_size; 1928 1929 if (ctx->controllers == NULL) { 1930 ctx->controllers = rte_malloc("sfc_controller_mapping", 1931 sizeof(ctx->controllers[0]), 0); 1932 if (ctx->controllers == NULL) 1933 return ENOMEM; 1934 1935 ctx->controllers[0] = intf; 1936 ctx->nb_controllers = 1; 1937 1938 return 0; 1939 } 1940 1941 for (i = 0; i < ctx->nb_controllers; i++) { 1942 if (ctx->controllers[i] == intf) 1943 return 0; 1944 if (ctx->controllers[i] > intf) 1945 break; 1946 } 1947 target = i; 1948 1949 ctx->nb_controllers += 1; 1950 new_size = ctx->nb_controllers * sizeof(ctx->controllers[0]); 1951 1952 new_controllers = rte_realloc(ctx->controllers, new_size, 0); 1953 if (new_controllers == NULL) { 1954 rte_free(ctx->controllers); 1955 return ENOMEM; 1956 } 1957 ctx->controllers = new_controllers; 1958 1959 for (i = target + 1; i < ctx->nb_controllers; i++) 1960 ctx->controllers[i] = ctx->controllers[i - 1]; 1961 1962 ctx->controllers[target] = intf; 1963 1964 return 0; 1965 } 1966 1967 static efx_rc_t 1968 sfc_process_mport_journal_entry(struct sfc_mport_journal_ctx *ctx, 1969 efx_mport_desc_t *mport) 1970 { 1971 struct sfc_mae_switch_port_request req; 1972 efx_mport_sel_t entity_selector; 1973 efx_mport_sel_t ethdev_mport; 1974 uint16_t switch_port_id; 1975 efx_rc_t efx_rc; 1976 int rc; 1977 1978 sfc_dbg(ctx->sa, 1979 "processing mport id %u (controller %u pf %u vf %u)", 1980 mport->emd_id.id, mport->emd_vnic.ev_intf, 1981 mport->emd_vnic.ev_pf, mport->emd_vnic.ev_vf); 1982 efx_mae_mport_invalid(ðdev_mport); 1983 1984 if (!ctx->controllers_assigned) { 1985 rc = sfc_journal_ctx_add_controller(ctx, 1986 mport->emd_vnic.ev_intf); 1987 if (rc != 0) 1988 return rc; 1989 } 1990 1991 /* Build Mport selector */ 1992 efx_rc = efx_mae_mport_by_pcie_mh_function(mport->emd_vnic.ev_intf, 1993 mport->emd_vnic.ev_pf, 1994 mport->emd_vnic.ev_vf, 1995 &entity_selector); 1996 if (efx_rc != 0) { 1997 sfc_err(ctx->sa, "failed to build entity mport selector for c%upf%uvf%u", 1998 mport->emd_vnic.ev_intf, 1999 mport->emd_vnic.ev_pf, 2000 mport->emd_vnic.ev_vf); 2001 return efx_rc; 2002 } 2003 2004 rc = sfc_mae_switch_port_id_by_entity(ctx->switch_domain_id, 2005 &entity_selector, 2006 SFC_MAE_SWITCH_PORT_REPRESENTOR, 2007 &switch_port_id); 2008 switch (rc) { 2009 case 0: 2010 /* Already registered */ 2011 break; 2012 case ENOENT: 2013 /* 2014 * No representor has been created for this entity. 2015 * Create a dummy switch registry entry with an invalid ethdev 2016 * mport selector. When a corresponding representor is created, 2017 * this entry will be updated. 2018 */ 2019 req.type = SFC_MAE_SWITCH_PORT_REPRESENTOR; 2020 req.entity_mportp = &entity_selector; 2021 req.ethdev_mportp = ðdev_mport; 2022 req.ethdev_port_id = RTE_MAX_ETHPORTS; 2023 req.port_data.repr.intf = mport->emd_vnic.ev_intf; 2024 req.port_data.repr.pf = mport->emd_vnic.ev_pf; 2025 req.port_data.repr.vf = mport->emd_vnic.ev_vf; 2026 2027 rc = sfc_mae_assign_switch_port(ctx->switch_domain_id, 2028 &req, &switch_port_id); 2029 if (rc != 0) { 2030 sfc_err(ctx->sa, 2031 "failed to assign MAE switch port for c%upf%uvf%u: %s", 2032 mport->emd_vnic.ev_intf, 2033 mport->emd_vnic.ev_pf, 2034 mport->emd_vnic.ev_vf, 2035 rte_strerror(rc)); 2036 return rc; 2037 } 2038 break; 2039 default: 2040 sfc_err(ctx->sa, "failed to find MAE switch port for c%upf%uvf%u: %s", 2041 mport->emd_vnic.ev_intf, 2042 mport->emd_vnic.ev_pf, 2043 mport->emd_vnic.ev_vf, 2044 rte_strerror(rc)); 2045 return rc; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static efx_rc_t 2052 sfc_process_mport_journal_cb(void *data, efx_mport_desc_t *mport, 2053 size_t mport_len) 2054 { 2055 struct sfc_mport_journal_ctx *ctx = data; 2056 2057 if (ctx == NULL || ctx->sa == NULL) { 2058 sfc_err(ctx->sa, "received NULL context or SFC adapter"); 2059 return EINVAL; 2060 } 2061 2062 if (mport_len != sizeof(*mport)) { 2063 sfc_err(ctx->sa, "actual and expected mport buffer sizes differ"); 2064 return EINVAL; 2065 } 2066 2067 SFC_ASSERT(sfc_adapter_is_locked(ctx->sa)); 2068 2069 /* 2070 * If a zombie flag is set, it means the mport has been marked for 2071 * deletion and cannot be used for any new operations. The mport will 2072 * be destroyed completely once all references to it are released. 2073 */ 2074 if (mport->emd_zombie) { 2075 sfc_dbg(ctx->sa, "mport is a zombie, skipping"); 2076 return 0; 2077 } 2078 if (mport->emd_type != EFX_MPORT_TYPE_VNIC) { 2079 sfc_dbg(ctx->sa, "mport is not a VNIC, skipping"); 2080 return 0; 2081 } 2082 if (mport->emd_vnic.ev_client_type != EFX_MPORT_VNIC_CLIENT_FUNCTION) { 2083 sfc_dbg(ctx->sa, "mport is not a function, skipping"); 2084 return 0; 2085 } 2086 if (mport->emd_vnic.ev_handle == ctx->mcdi_handle) { 2087 sfc_dbg(ctx->sa, "mport is this driver instance, skipping"); 2088 return 0; 2089 } 2090 2091 return sfc_process_mport_journal_entry(ctx, mport); 2092 } 2093 2094 static int 2095 sfc_process_mport_journal(struct sfc_adapter *sa) 2096 { 2097 struct sfc_mport_journal_ctx ctx; 2098 const efx_pcie_interface_t *controllers; 2099 size_t nb_controllers; 2100 efx_rc_t efx_rc; 2101 int rc; 2102 2103 memset(&ctx, 0, sizeof(ctx)); 2104 ctx.sa = sa; 2105 ctx.switch_domain_id = sa->mae.switch_domain_id; 2106 2107 efx_rc = efx_mcdi_get_own_client_handle(sa->nic, &ctx.mcdi_handle); 2108 if (efx_rc != 0) { 2109 sfc_err(sa, "failed to get own MCDI handle"); 2110 SFC_ASSERT(efx_rc > 0); 2111 return efx_rc; 2112 } 2113 2114 rc = sfc_mae_switch_domain_controllers(ctx.switch_domain_id, 2115 &controllers, &nb_controllers); 2116 if (rc != 0) { 2117 sfc_err(sa, "failed to get controller mapping"); 2118 return rc; 2119 } 2120 2121 ctx.controllers_assigned = controllers != NULL; 2122 ctx.controllers = NULL; 2123 ctx.nb_controllers = 0; 2124 2125 efx_rc = efx_mae_read_mport_journal(sa->nic, 2126 sfc_process_mport_journal_cb, &ctx); 2127 if (efx_rc != 0) { 2128 sfc_err(sa, "failed to process MAE mport journal"); 2129 SFC_ASSERT(efx_rc > 0); 2130 return efx_rc; 2131 } 2132 2133 if (controllers == NULL) { 2134 rc = sfc_mae_switch_domain_map_controllers(ctx.switch_domain_id, 2135 ctx.controllers, 2136 ctx.nb_controllers); 2137 if (rc != 0) 2138 return rc; 2139 } 2140 2141 return 0; 2142 } 2143 2144 static void 2145 sfc_count_representors_cb(enum sfc_mae_switch_port_type type, 2146 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2147 uint16_t ethdev_port_id __rte_unused, 2148 const efx_mport_sel_t *entity_mportp __rte_unused, 2149 uint16_t switch_port_id __rte_unused, 2150 union sfc_mae_switch_port_data *port_datap 2151 __rte_unused, 2152 void *user_datap) 2153 { 2154 int *counter = user_datap; 2155 2156 SFC_ASSERT(counter != NULL); 2157 2158 if (type == SFC_MAE_SWITCH_PORT_REPRESENTOR) 2159 (*counter)++; 2160 } 2161 2162 struct sfc_get_representors_ctx { 2163 struct rte_eth_representor_info *info; 2164 struct sfc_adapter *sa; 2165 uint16_t switch_domain_id; 2166 const efx_pcie_interface_t *controllers; 2167 size_t nb_controllers; 2168 }; 2169 2170 static void 2171 sfc_get_representors_cb(enum sfc_mae_switch_port_type type, 2172 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2173 uint16_t ethdev_port_id __rte_unused, 2174 const efx_mport_sel_t *entity_mportp __rte_unused, 2175 uint16_t switch_port_id, 2176 union sfc_mae_switch_port_data *port_datap, 2177 void *user_datap) 2178 { 2179 struct sfc_get_representors_ctx *ctx = user_datap; 2180 struct rte_eth_representor_range *range; 2181 int ret; 2182 int rc; 2183 2184 SFC_ASSERT(ctx != NULL); 2185 SFC_ASSERT(ctx->info != NULL); 2186 SFC_ASSERT(ctx->sa != NULL); 2187 2188 if (type != SFC_MAE_SWITCH_PORT_REPRESENTOR) { 2189 sfc_dbg(ctx->sa, "not a representor, skipping"); 2190 return; 2191 } 2192 if (ctx->info->nb_ranges >= ctx->info->nb_ranges_alloc) { 2193 sfc_dbg(ctx->sa, "info structure is full already"); 2194 return; 2195 } 2196 2197 range = &ctx->info->ranges[ctx->info->nb_ranges]; 2198 rc = sfc_mae_switch_controller_from_mapping(ctx->controllers, 2199 ctx->nb_controllers, 2200 port_datap->repr.intf, 2201 &range->controller); 2202 if (rc != 0) { 2203 sfc_err(ctx->sa, "invalid representor controller: %d", 2204 port_datap->repr.intf); 2205 range->controller = -1; 2206 } 2207 range->pf = port_datap->repr.pf; 2208 range->id_base = switch_port_id; 2209 range->id_end = switch_port_id; 2210 2211 if (port_datap->repr.vf != EFX_PCI_VF_INVALID) { 2212 range->type = RTE_ETH_REPRESENTOR_VF; 2213 range->vf = port_datap->repr.vf; 2214 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2215 "c%dpf%dvf%d", range->controller, range->pf, 2216 range->vf); 2217 } else { 2218 range->type = RTE_ETH_REPRESENTOR_PF; 2219 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2220 "c%dpf%d", range->controller, range->pf); 2221 } 2222 if (ret >= RTE_DEV_NAME_MAX_LEN) { 2223 sfc_err(ctx->sa, "representor name has been truncated: %s", 2224 range->name); 2225 } 2226 2227 ctx->info->nb_ranges++; 2228 } 2229 2230 static int 2231 sfc_representor_info_get(struct rte_eth_dev *dev, 2232 struct rte_eth_representor_info *info) 2233 { 2234 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2235 struct sfc_get_representors_ctx get_repr_ctx; 2236 const efx_nic_cfg_t *nic_cfg; 2237 uint16_t switch_domain_id; 2238 uint32_t nb_repr; 2239 int controller; 2240 int rc; 2241 2242 sfc_adapter_lock(sa); 2243 2244 if (sa->mae.status != SFC_MAE_STATUS_ADMIN) { 2245 sfc_adapter_unlock(sa); 2246 return -ENOTSUP; 2247 } 2248 2249 rc = sfc_process_mport_journal(sa); 2250 if (rc != 0) { 2251 sfc_adapter_unlock(sa); 2252 SFC_ASSERT(rc > 0); 2253 return -rc; 2254 } 2255 2256 switch_domain_id = sa->mae.switch_domain_id; 2257 2258 nb_repr = 0; 2259 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2260 sfc_count_representors_cb, 2261 &nb_repr); 2262 if (rc != 0) { 2263 sfc_adapter_unlock(sa); 2264 SFC_ASSERT(rc > 0); 2265 return -rc; 2266 } 2267 2268 if (info == NULL) { 2269 sfc_adapter_unlock(sa); 2270 return nb_repr; 2271 } 2272 2273 rc = sfc_mae_switch_domain_controllers(switch_domain_id, 2274 &get_repr_ctx.controllers, 2275 &get_repr_ctx.nb_controllers); 2276 if (rc != 0) { 2277 sfc_adapter_unlock(sa); 2278 SFC_ASSERT(rc > 0); 2279 return -rc; 2280 } 2281 2282 nic_cfg = efx_nic_cfg_get(sa->nic); 2283 2284 rc = sfc_mae_switch_domain_get_controller(switch_domain_id, 2285 nic_cfg->enc_intf, 2286 &controller); 2287 if (rc != 0) { 2288 sfc_err(sa, "invalid controller: %d", nic_cfg->enc_intf); 2289 controller = -1; 2290 } 2291 2292 info->controller = controller; 2293 info->pf = nic_cfg->enc_pf; 2294 2295 get_repr_ctx.info = info; 2296 get_repr_ctx.sa = sa; 2297 get_repr_ctx.switch_domain_id = switch_domain_id; 2298 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2299 sfc_get_representors_cb, 2300 &get_repr_ctx); 2301 if (rc != 0) { 2302 sfc_adapter_unlock(sa); 2303 SFC_ASSERT(rc > 0); 2304 return -rc; 2305 } 2306 2307 sfc_adapter_unlock(sa); 2308 return nb_repr; 2309 } 2310 2311 static int 2312 sfc_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 2313 { 2314 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2315 uint64_t supported = 0; 2316 2317 sfc_adapter_lock(sa); 2318 2319 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_FLAG) != 0) 2320 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 2321 2322 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_MARK) != 0) 2323 supported |= RTE_ETH_RX_METADATA_USER_MARK; 2324 2325 if (sfc_flow_tunnel_is_supported(sa)) 2326 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 2327 2328 sa->negotiated_rx_metadata = supported & *features; 2329 *features = sa->negotiated_rx_metadata; 2330 2331 sfc_adapter_unlock(sa); 2332 2333 return 0; 2334 } 2335 2336 static const struct eth_dev_ops sfc_eth_dev_ops = { 2337 .dev_configure = sfc_dev_configure, 2338 .dev_start = sfc_dev_start, 2339 .dev_stop = sfc_dev_stop, 2340 .dev_set_link_up = sfc_dev_set_link_up, 2341 .dev_set_link_down = sfc_dev_set_link_down, 2342 .dev_close = sfc_dev_close, 2343 .promiscuous_enable = sfc_dev_promisc_enable, 2344 .promiscuous_disable = sfc_dev_promisc_disable, 2345 .allmulticast_enable = sfc_dev_allmulti_enable, 2346 .allmulticast_disable = sfc_dev_allmulti_disable, 2347 .link_update = sfc_dev_link_update, 2348 .stats_get = sfc_stats_get, 2349 .stats_reset = sfc_stats_reset, 2350 .xstats_get = sfc_xstats_get, 2351 .xstats_reset = sfc_stats_reset, 2352 .xstats_get_names = sfc_xstats_get_names, 2353 .dev_infos_get = sfc_dev_infos_get, 2354 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2355 .mtu_set = sfc_dev_set_mtu, 2356 .rx_queue_start = sfc_rx_queue_start, 2357 .rx_queue_stop = sfc_rx_queue_stop, 2358 .tx_queue_start = sfc_tx_queue_start, 2359 .tx_queue_stop = sfc_tx_queue_stop, 2360 .rx_queue_setup = sfc_rx_queue_setup, 2361 .rx_queue_release = sfc_rx_queue_release, 2362 .rx_queue_intr_enable = sfc_rx_queue_intr_enable, 2363 .rx_queue_intr_disable = sfc_rx_queue_intr_disable, 2364 .tx_queue_setup = sfc_tx_queue_setup, 2365 .tx_queue_release = sfc_tx_queue_release, 2366 .flow_ctrl_get = sfc_flow_ctrl_get, 2367 .flow_ctrl_set = sfc_flow_ctrl_set, 2368 .mac_addr_set = sfc_mac_addr_set, 2369 .udp_tunnel_port_add = sfc_dev_udp_tunnel_port_add, 2370 .udp_tunnel_port_del = sfc_dev_udp_tunnel_port_del, 2371 .reta_update = sfc_dev_rss_reta_update, 2372 .reta_query = sfc_dev_rss_reta_query, 2373 .rss_hash_update = sfc_dev_rss_hash_update, 2374 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2375 .flow_ops_get = sfc_dev_flow_ops_get, 2376 .set_mc_addr_list = sfc_set_mc_addr_list, 2377 .rxq_info_get = sfc_rx_queue_info_get, 2378 .txq_info_get = sfc_tx_queue_info_get, 2379 .fw_version_get = sfc_fw_version_get, 2380 .xstats_get_by_id = sfc_xstats_get_by_id, 2381 .xstats_get_names_by_id = sfc_xstats_get_names_by_id, 2382 .pool_ops_supported = sfc_pool_ops_supported, 2383 .representor_info_get = sfc_representor_info_get, 2384 .rx_metadata_negotiate = sfc_rx_metadata_negotiate, 2385 }; 2386 2387 struct sfc_ethdev_init_data { 2388 uint16_t nb_representors; 2389 }; 2390 2391 /** 2392 * Duplicate a string in potentially shared memory required for 2393 * multi-process support. 2394 * 2395 * strdup() allocates from process-local heap/memory. 2396 */ 2397 static char * 2398 sfc_strdup(const char *str) 2399 { 2400 size_t size; 2401 char *copy; 2402 2403 if (str == NULL) 2404 return NULL; 2405 2406 size = strlen(str) + 1; 2407 copy = rte_malloc(__func__, size, 0); 2408 if (copy != NULL) 2409 rte_memcpy(copy, str, size); 2410 2411 return copy; 2412 } 2413 2414 static int 2415 sfc_eth_dev_set_ops(struct rte_eth_dev *dev) 2416 { 2417 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2418 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2419 const struct sfc_dp_rx *dp_rx; 2420 const struct sfc_dp_tx *dp_tx; 2421 const efx_nic_cfg_t *encp; 2422 unsigned int avail_caps = 0; 2423 const char *rx_name = NULL; 2424 const char *tx_name = NULL; 2425 int rc; 2426 2427 switch (sa->family) { 2428 case EFX_FAMILY_HUNTINGTON: 2429 case EFX_FAMILY_MEDFORD: 2430 case EFX_FAMILY_MEDFORD2: 2431 avail_caps |= SFC_DP_HW_FW_CAP_EF10; 2432 avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX; 2433 avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX; 2434 break; 2435 case EFX_FAMILY_RIVERHEAD: 2436 avail_caps |= SFC_DP_HW_FW_CAP_EF100; 2437 break; 2438 default: 2439 break; 2440 } 2441 2442 encp = efx_nic_cfg_get(sa->nic); 2443 if (encp->enc_rx_es_super_buffer_supported) 2444 avail_caps |= SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER; 2445 2446 rc = sfc_kvargs_process(sa, SFC_KVARG_RX_DATAPATH, 2447 sfc_kvarg_string_handler, &rx_name); 2448 if (rc != 0) 2449 goto fail_kvarg_rx_datapath; 2450 2451 if (rx_name != NULL) { 2452 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, rx_name); 2453 if (dp_rx == NULL) { 2454 sfc_err(sa, "Rx datapath %s not found", rx_name); 2455 rc = ENOENT; 2456 goto fail_dp_rx; 2457 } 2458 if (!sfc_dp_match_hw_fw_caps(&dp_rx->dp, avail_caps)) { 2459 sfc_err(sa, 2460 "Insufficient Hw/FW capabilities to use Rx datapath %s", 2461 rx_name); 2462 rc = EINVAL; 2463 goto fail_dp_rx_caps; 2464 } 2465 } else { 2466 dp_rx = sfc_dp_find_rx_by_caps(&sfc_dp_head, avail_caps); 2467 if (dp_rx == NULL) { 2468 sfc_err(sa, "Rx datapath by caps %#x not found", 2469 avail_caps); 2470 rc = ENOENT; 2471 goto fail_dp_rx; 2472 } 2473 } 2474 2475 sas->dp_rx_name = sfc_strdup(dp_rx->dp.name); 2476 if (sas->dp_rx_name == NULL) { 2477 rc = ENOMEM; 2478 goto fail_dp_rx_name; 2479 } 2480 2481 if (strcmp(dp_rx->dp.name, SFC_KVARG_DATAPATH_EF10_ESSB) == 0) { 2482 /* FLAG and MARK are always available from Rx prefix. */ 2483 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_FLAG; 2484 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_MARK; 2485 } 2486 2487 sfc_notice(sa, "use %s Rx datapath", sas->dp_rx_name); 2488 2489 rc = sfc_kvargs_process(sa, SFC_KVARG_TX_DATAPATH, 2490 sfc_kvarg_string_handler, &tx_name); 2491 if (rc != 0) 2492 goto fail_kvarg_tx_datapath; 2493 2494 if (tx_name != NULL) { 2495 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, tx_name); 2496 if (dp_tx == NULL) { 2497 sfc_err(sa, "Tx datapath %s not found", tx_name); 2498 rc = ENOENT; 2499 goto fail_dp_tx; 2500 } 2501 if (!sfc_dp_match_hw_fw_caps(&dp_tx->dp, avail_caps)) { 2502 sfc_err(sa, 2503 "Insufficient Hw/FW capabilities to use Tx datapath %s", 2504 tx_name); 2505 rc = EINVAL; 2506 goto fail_dp_tx_caps; 2507 } 2508 } else { 2509 dp_tx = sfc_dp_find_tx_by_caps(&sfc_dp_head, avail_caps); 2510 if (dp_tx == NULL) { 2511 sfc_err(sa, "Tx datapath by caps %#x not found", 2512 avail_caps); 2513 rc = ENOENT; 2514 goto fail_dp_tx; 2515 } 2516 } 2517 2518 sas->dp_tx_name = sfc_strdup(dp_tx->dp.name); 2519 if (sas->dp_tx_name == NULL) { 2520 rc = ENOMEM; 2521 goto fail_dp_tx_name; 2522 } 2523 2524 sfc_notice(sa, "use %s Tx datapath", sas->dp_tx_name); 2525 2526 sa->priv.dp_rx = dp_rx; 2527 sa->priv.dp_tx = dp_tx; 2528 2529 dev->rx_pkt_burst = dp_rx->pkt_burst; 2530 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2531 dev->tx_pkt_burst = dp_tx->pkt_burst; 2532 2533 dev->rx_queue_count = sfc_rx_queue_count; 2534 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2535 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2536 dev->dev_ops = &sfc_eth_dev_ops; 2537 2538 return 0; 2539 2540 fail_dp_tx_name: 2541 fail_dp_tx_caps: 2542 fail_dp_tx: 2543 fail_kvarg_tx_datapath: 2544 rte_free(sas->dp_rx_name); 2545 sas->dp_rx_name = NULL; 2546 2547 fail_dp_rx_name: 2548 fail_dp_rx_caps: 2549 fail_dp_rx: 2550 fail_kvarg_rx_datapath: 2551 return rc; 2552 } 2553 2554 static void 2555 sfc_eth_dev_clear_ops(struct rte_eth_dev *dev) 2556 { 2557 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2558 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2559 2560 dev->dev_ops = NULL; 2561 dev->tx_pkt_prepare = NULL; 2562 dev->rx_pkt_burst = NULL; 2563 dev->tx_pkt_burst = NULL; 2564 2565 rte_free(sas->dp_tx_name); 2566 sas->dp_tx_name = NULL; 2567 sa->priv.dp_tx = NULL; 2568 2569 rte_free(sas->dp_rx_name); 2570 sas->dp_rx_name = NULL; 2571 sa->priv.dp_rx = NULL; 2572 } 2573 2574 static const struct eth_dev_ops sfc_eth_dev_secondary_ops = { 2575 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2576 .reta_query = sfc_dev_rss_reta_query, 2577 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2578 .rxq_info_get = sfc_rx_queue_info_get, 2579 .txq_info_get = sfc_tx_queue_info_get, 2580 }; 2581 2582 static int 2583 sfc_eth_dev_secondary_init(struct rte_eth_dev *dev, uint32_t logtype_main) 2584 { 2585 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2586 struct sfc_adapter_priv *sap; 2587 const struct sfc_dp_rx *dp_rx; 2588 const struct sfc_dp_tx *dp_tx; 2589 int rc; 2590 2591 /* 2592 * Allocate process private data from heap, since it should not 2593 * be located in shared memory allocated using rte_malloc() API. 2594 */ 2595 sap = calloc(1, sizeof(*sap)); 2596 if (sap == NULL) { 2597 rc = ENOMEM; 2598 goto fail_alloc_priv; 2599 } 2600 2601 sap->logtype_main = logtype_main; 2602 2603 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, sas->dp_rx_name); 2604 if (dp_rx == NULL) { 2605 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2606 "cannot find %s Rx datapath", sas->dp_rx_name); 2607 rc = ENOENT; 2608 goto fail_dp_rx; 2609 } 2610 if (~dp_rx->features & SFC_DP_RX_FEAT_MULTI_PROCESS) { 2611 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2612 "%s Rx datapath does not support multi-process", 2613 sas->dp_rx_name); 2614 rc = EINVAL; 2615 goto fail_dp_rx_multi_process; 2616 } 2617 2618 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, sas->dp_tx_name); 2619 if (dp_tx == NULL) { 2620 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2621 "cannot find %s Tx datapath", sas->dp_tx_name); 2622 rc = ENOENT; 2623 goto fail_dp_tx; 2624 } 2625 if (~dp_tx->features & SFC_DP_TX_FEAT_MULTI_PROCESS) { 2626 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2627 "%s Tx datapath does not support multi-process", 2628 sas->dp_tx_name); 2629 rc = EINVAL; 2630 goto fail_dp_tx_multi_process; 2631 } 2632 2633 sap->dp_rx = dp_rx; 2634 sap->dp_tx = dp_tx; 2635 2636 dev->process_private = sap; 2637 dev->rx_pkt_burst = dp_rx->pkt_burst; 2638 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2639 dev->tx_pkt_burst = dp_tx->pkt_burst; 2640 dev->rx_queue_count = sfc_rx_queue_count; 2641 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2642 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2643 dev->dev_ops = &sfc_eth_dev_secondary_ops; 2644 2645 return 0; 2646 2647 fail_dp_tx_multi_process: 2648 fail_dp_tx: 2649 fail_dp_rx_multi_process: 2650 fail_dp_rx: 2651 free(sap); 2652 2653 fail_alloc_priv: 2654 return rc; 2655 } 2656 2657 static void 2658 sfc_register_dp(void) 2659 { 2660 /* Register once */ 2661 if (TAILQ_EMPTY(&sfc_dp_head)) { 2662 /* Prefer EF10 datapath */ 2663 sfc_dp_register(&sfc_dp_head, &sfc_ef100_rx.dp); 2664 sfc_dp_register(&sfc_dp_head, &sfc_ef10_essb_rx.dp); 2665 sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp); 2666 sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp); 2667 2668 sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp); 2669 sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp); 2670 sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp); 2671 sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp); 2672 } 2673 } 2674 2675 static int 2676 sfc_parse_switch_mode(struct sfc_adapter *sa, bool has_representors) 2677 { 2678 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 2679 const char *switch_mode = NULL; 2680 int rc; 2681 2682 sfc_log_init(sa, "entry"); 2683 2684 rc = sfc_kvargs_process(sa, SFC_KVARG_SWITCH_MODE, 2685 sfc_kvarg_string_handler, &switch_mode); 2686 if (rc != 0) 2687 goto fail_kvargs; 2688 2689 if (switch_mode == NULL) { 2690 sa->switchdev = encp->enc_mae_admin && 2691 (!encp->enc_datapath_cap_evb || 2692 has_representors); 2693 } else if (strcasecmp(switch_mode, SFC_KVARG_SWITCH_MODE_LEGACY) == 0) { 2694 sa->switchdev = false; 2695 } else if (strcasecmp(switch_mode, 2696 SFC_KVARG_SWITCH_MODE_SWITCHDEV) == 0) { 2697 sa->switchdev = true; 2698 } else { 2699 sfc_err(sa, "invalid switch mode device argument '%s'", 2700 switch_mode); 2701 rc = EINVAL; 2702 goto fail_mode; 2703 } 2704 2705 sfc_log_init(sa, "done"); 2706 2707 return 0; 2708 2709 fail_mode: 2710 fail_kvargs: 2711 sfc_log_init(sa, "failed: %s", rte_strerror(rc)); 2712 2713 return rc; 2714 } 2715 2716 static int 2717 sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params) 2718 { 2719 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2720 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2721 struct sfc_ethdev_init_data *init_data = init_params; 2722 uint32_t logtype_main; 2723 struct sfc_adapter *sa; 2724 int rc; 2725 const efx_nic_cfg_t *encp; 2726 const struct rte_ether_addr *from; 2727 int ret; 2728 2729 if (sfc_efx_dev_class_get(pci_dev->device.devargs) != 2730 SFC_EFX_DEV_CLASS_NET) { 2731 SFC_GENERIC_LOG(DEBUG, 2732 "Incompatible device class: skip probing, should be probed by other sfc driver."); 2733 return 1; 2734 } 2735 2736 rc = sfc_dp_mport_register(); 2737 if (rc != 0) 2738 return rc; 2739 2740 sfc_register_dp(); 2741 2742 logtype_main = sfc_register_logtype(&pci_dev->addr, 2743 SFC_LOGTYPE_MAIN_STR, 2744 RTE_LOG_NOTICE); 2745 2746 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2747 return -sfc_eth_dev_secondary_init(dev, logtype_main); 2748 2749 /* Required for logging */ 2750 ret = snprintf(sas->log_prefix, sizeof(sas->log_prefix), 2751 "PMD: sfc_efx " PCI_PRI_FMT " #%" PRIu16 ": ", 2752 pci_dev->addr.domain, pci_dev->addr.bus, 2753 pci_dev->addr.devid, pci_dev->addr.function, 2754 dev->data->port_id); 2755 if (ret < 0 || ret >= (int)sizeof(sas->log_prefix)) { 2756 SFC_GENERIC_LOG(ERR, 2757 "reserved log prefix is too short for " PCI_PRI_FMT, 2758 pci_dev->addr.domain, pci_dev->addr.bus, 2759 pci_dev->addr.devid, pci_dev->addr.function); 2760 return -EINVAL; 2761 } 2762 sas->pci_addr = pci_dev->addr; 2763 sas->port_id = dev->data->port_id; 2764 2765 /* 2766 * Allocate process private data from heap, since it should not 2767 * be located in shared memory allocated using rte_malloc() API. 2768 */ 2769 sa = calloc(1, sizeof(*sa)); 2770 if (sa == NULL) { 2771 rc = ENOMEM; 2772 goto fail_alloc_sa; 2773 } 2774 2775 dev->process_private = sa; 2776 2777 /* Required for logging */ 2778 sa->priv.shared = sas; 2779 sa->priv.logtype_main = logtype_main; 2780 2781 sa->eth_dev = dev; 2782 2783 /* Copy PCI device info to the dev->data */ 2784 rte_eth_copy_pci_info(dev, pci_dev); 2785 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 2786 2787 rc = sfc_kvargs_parse(sa); 2788 if (rc != 0) 2789 goto fail_kvargs_parse; 2790 2791 sfc_log_init(sa, "entry"); 2792 2793 dev->data->mac_addrs = rte_zmalloc("sfc", RTE_ETHER_ADDR_LEN, 0); 2794 if (dev->data->mac_addrs == NULL) { 2795 rc = ENOMEM; 2796 goto fail_mac_addrs; 2797 } 2798 2799 sfc_adapter_lock_init(sa); 2800 sfc_adapter_lock(sa); 2801 2802 sfc_log_init(sa, "probing"); 2803 rc = sfc_probe(sa); 2804 if (rc != 0) 2805 goto fail_probe; 2806 2807 /* 2808 * Selecting a default switch mode requires the NIC to be probed and 2809 * to have its capabilities filled in. 2810 */ 2811 rc = sfc_parse_switch_mode(sa, init_data->nb_representors > 0); 2812 if (rc != 0) 2813 goto fail_switch_mode; 2814 2815 sfc_log_init(sa, "set device ops"); 2816 rc = sfc_eth_dev_set_ops(dev); 2817 if (rc != 0) 2818 goto fail_set_ops; 2819 2820 sfc_log_init(sa, "attaching"); 2821 rc = sfc_attach(sa); 2822 if (rc != 0) 2823 goto fail_attach; 2824 2825 if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_ADMIN) { 2826 sfc_err(sa, 2827 "failed to enable switchdev mode without admin MAE privilege"); 2828 rc = ENOTSUP; 2829 goto fail_switchdev_no_mae; 2830 } 2831 2832 encp = efx_nic_cfg_get(sa->nic); 2833 2834 /* 2835 * The arguments are really reverse order in comparison to 2836 * Linux kernel. Copy from NIC config to Ethernet device data. 2837 */ 2838 from = (const struct rte_ether_addr *)(encp->enc_mac_addr); 2839 rte_ether_addr_copy(from, &dev->data->mac_addrs[0]); 2840 2841 /* 2842 * Setup the NIC DMA mapping handler. All internal mempools 2843 * MUST be created on attach before this point, and the 2844 * adapter MUST NOT create mempools with the adapter lock 2845 * held after this point. 2846 */ 2847 rc = sfc_nic_dma_attach(sa); 2848 if (rc != 0) 2849 goto fail_nic_dma_attach; 2850 2851 sfc_adapter_unlock(sa); 2852 2853 sfc_log_init(sa, "done"); 2854 return 0; 2855 2856 fail_nic_dma_attach: 2857 fail_switchdev_no_mae: 2858 sfc_detach(sa); 2859 2860 fail_attach: 2861 sfc_eth_dev_clear_ops(dev); 2862 2863 fail_set_ops: 2864 fail_switch_mode: 2865 sfc_unprobe(sa); 2866 2867 fail_probe: 2868 sfc_adapter_unlock(sa); 2869 sfc_adapter_lock_fini(sa); 2870 rte_free(dev->data->mac_addrs); 2871 dev->data->mac_addrs = NULL; 2872 2873 fail_mac_addrs: 2874 sfc_kvargs_cleanup(sa); 2875 2876 fail_kvargs_parse: 2877 sfc_log_init(sa, "failed %d", rc); 2878 dev->process_private = NULL; 2879 free(sa); 2880 2881 fail_alloc_sa: 2882 SFC_ASSERT(rc > 0); 2883 return -rc; 2884 } 2885 2886 static int 2887 sfc_eth_dev_uninit(struct rte_eth_dev *dev) 2888 { 2889 sfc_dev_close(dev); 2890 2891 return 0; 2892 } 2893 2894 static const struct rte_pci_id pci_id_sfc_efx_map[] = { 2895 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE) }, 2896 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE_VF) }, 2897 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT) }, 2898 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT_VF) }, 2899 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD) }, 2900 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) }, 2901 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) }, 2902 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) }, 2903 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) }, 2904 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) }, 2905 { .vendor_id = 0 /* sentinel */ } 2906 }; 2907 2908 static int 2909 sfc_parse_rte_devargs(const char *args, struct rte_eth_devargs *devargs) 2910 { 2911 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 2912 int rc; 2913 2914 if (args != NULL) { 2915 rc = rte_eth_devargs_parse(args, ð_da); 2916 if (rc != 0) { 2917 SFC_GENERIC_LOG(ERR, 2918 "Failed to parse generic devargs '%s'", 2919 args); 2920 return rc; 2921 } 2922 } 2923 2924 *devargs = eth_da; 2925 2926 return 0; 2927 } 2928 2929 static int 2930 sfc_eth_dev_find_or_create(struct rte_pci_device *pci_dev, 2931 struct sfc_ethdev_init_data *init_data, 2932 struct rte_eth_dev **devp, 2933 bool *dev_created) 2934 { 2935 struct rte_eth_dev *dev; 2936 bool created = false; 2937 int rc; 2938 2939 dev = rte_eth_dev_allocated(pci_dev->device.name); 2940 if (dev == NULL) { 2941 rc = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 2942 sizeof(struct sfc_adapter_shared), 2943 eth_dev_pci_specific_init, pci_dev, 2944 sfc_eth_dev_init, init_data); 2945 if (rc != 0) { 2946 SFC_GENERIC_LOG(ERR, "Failed to create sfc ethdev '%s'", 2947 pci_dev->device.name); 2948 return rc; 2949 } 2950 2951 created = true; 2952 2953 dev = rte_eth_dev_allocated(pci_dev->device.name); 2954 if (dev == NULL) { 2955 SFC_GENERIC_LOG(ERR, 2956 "Failed to find allocated sfc ethdev '%s'", 2957 pci_dev->device.name); 2958 return -ENODEV; 2959 } 2960 } 2961 2962 *devp = dev; 2963 *dev_created = created; 2964 2965 return 0; 2966 } 2967 2968 static int 2969 sfc_eth_dev_create_repr(struct sfc_adapter *sa, 2970 efx_pcie_interface_t controller, 2971 uint16_t port, 2972 uint16_t repr_port, 2973 enum rte_eth_representor_type type) 2974 { 2975 struct sfc_repr_entity_info entity; 2976 efx_mport_sel_t mport_sel; 2977 int rc; 2978 2979 switch (type) { 2980 case RTE_ETH_REPRESENTOR_NONE: 2981 return 0; 2982 case RTE_ETH_REPRESENTOR_VF: 2983 case RTE_ETH_REPRESENTOR_PF: 2984 break; 2985 case RTE_ETH_REPRESENTOR_SF: 2986 sfc_err(sa, "SF representors are not supported"); 2987 return ENOTSUP; 2988 default: 2989 sfc_err(sa, "unknown representor type: %d", type); 2990 return ENOTSUP; 2991 } 2992 2993 rc = efx_mae_mport_by_pcie_mh_function(controller, 2994 port, 2995 repr_port, 2996 &mport_sel); 2997 if (rc != 0) { 2998 sfc_err(sa, 2999 "failed to get m-port selector for controller %u port %u repr_port %u: %s", 3000 controller, port, repr_port, rte_strerror(-rc)); 3001 return rc; 3002 } 3003 3004 memset(&entity, 0, sizeof(entity)); 3005 entity.type = type; 3006 entity.intf = controller; 3007 entity.pf = port; 3008 entity.vf = repr_port; 3009 3010 rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id, 3011 &mport_sel); 3012 if (rc != 0) { 3013 sfc_err(sa, 3014 "failed to create representor for controller %u port %u repr_port %u: %s", 3015 controller, port, repr_port, rte_strerror(-rc)); 3016 return rc; 3017 } 3018 3019 return 0; 3020 } 3021 3022 static int 3023 sfc_eth_dev_create_repr_port(struct sfc_adapter *sa, 3024 const struct rte_eth_devargs *eth_da, 3025 efx_pcie_interface_t controller, 3026 uint16_t port) 3027 { 3028 int first_error = 0; 3029 uint16_t i; 3030 int rc; 3031 3032 if (eth_da->type == RTE_ETH_REPRESENTOR_PF) { 3033 return sfc_eth_dev_create_repr(sa, controller, port, 3034 EFX_PCI_VF_INVALID, 3035 eth_da->type); 3036 } 3037 3038 for (i = 0; i < eth_da->nb_representor_ports; i++) { 3039 rc = sfc_eth_dev_create_repr(sa, controller, port, 3040 eth_da->representor_ports[i], 3041 eth_da->type); 3042 if (rc != 0 && first_error == 0) 3043 first_error = rc; 3044 } 3045 3046 return first_error; 3047 } 3048 3049 static int 3050 sfc_eth_dev_create_repr_controller(struct sfc_adapter *sa, 3051 const struct rte_eth_devargs *eth_da, 3052 efx_pcie_interface_t controller) 3053 { 3054 const efx_nic_cfg_t *encp; 3055 int first_error = 0; 3056 uint16_t default_port; 3057 uint16_t i; 3058 int rc; 3059 3060 if (eth_da->nb_ports == 0) { 3061 encp = efx_nic_cfg_get(sa->nic); 3062 default_port = encp->enc_intf == controller ? encp->enc_pf : 0; 3063 return sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3064 default_port); 3065 } 3066 3067 for (i = 0; i < eth_da->nb_ports; i++) { 3068 rc = sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3069 eth_da->ports[i]); 3070 if (rc != 0 && first_error == 0) 3071 first_error = rc; 3072 } 3073 3074 return first_error; 3075 } 3076 3077 static int 3078 sfc_eth_dev_create_representors(struct rte_eth_dev *dev, 3079 const struct rte_eth_devargs *eth_da) 3080 { 3081 efx_pcie_interface_t intf; 3082 const efx_nic_cfg_t *encp; 3083 struct sfc_adapter *sa; 3084 uint16_t switch_domain_id; 3085 uint16_t i; 3086 int rc; 3087 3088 sa = sfc_adapter_by_eth_dev(dev); 3089 switch_domain_id = sa->mae.switch_domain_id; 3090 3091 switch (eth_da->type) { 3092 case RTE_ETH_REPRESENTOR_NONE: 3093 return 0; 3094 case RTE_ETH_REPRESENTOR_PF: 3095 case RTE_ETH_REPRESENTOR_VF: 3096 break; 3097 case RTE_ETH_REPRESENTOR_SF: 3098 sfc_err(sa, "SF representors are not supported"); 3099 return -ENOTSUP; 3100 default: 3101 sfc_err(sa, "unknown representor type: %d", 3102 eth_da->type); 3103 return -ENOTSUP; 3104 } 3105 3106 if (!sa->switchdev) { 3107 sfc_err(sa, "cannot create representors in non-switchdev mode"); 3108 return -EINVAL; 3109 } 3110 3111 if (!sfc_repr_available(sfc_sa2shared(sa))) { 3112 sfc_err(sa, "cannot create representors: unsupported"); 3113 3114 return -ENOTSUP; 3115 } 3116 3117 /* 3118 * This is needed to construct the DPDK controller -> EFX interface 3119 * mapping. 3120 */ 3121 sfc_adapter_lock(sa); 3122 rc = sfc_process_mport_journal(sa); 3123 sfc_adapter_unlock(sa); 3124 if (rc != 0) { 3125 SFC_ASSERT(rc > 0); 3126 return -rc; 3127 } 3128 3129 if (eth_da->nb_mh_controllers > 0) { 3130 for (i = 0; i < eth_da->nb_mh_controllers; i++) { 3131 rc = sfc_mae_switch_domain_get_intf(switch_domain_id, 3132 eth_da->mh_controllers[i], 3133 &intf); 3134 if (rc != 0) { 3135 sfc_err(sa, "failed to get representor"); 3136 continue; 3137 } 3138 sfc_eth_dev_create_repr_controller(sa, eth_da, intf); 3139 } 3140 } else { 3141 encp = efx_nic_cfg_get(sa->nic); 3142 sfc_eth_dev_create_repr_controller(sa, eth_da, encp->enc_intf); 3143 } 3144 3145 return 0; 3146 } 3147 3148 static int sfc_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3149 struct rte_pci_device *pci_dev) 3150 { 3151 struct sfc_ethdev_init_data init_data; 3152 struct rte_eth_devargs eth_da; 3153 struct rte_eth_dev *dev; 3154 bool dev_created; 3155 int rc; 3156 3157 if (pci_dev->device.devargs != NULL) { 3158 rc = sfc_parse_rte_devargs(pci_dev->device.devargs->args, 3159 ð_da); 3160 if (rc != 0) 3161 return rc; 3162 } else { 3163 memset(ð_da, 0, sizeof(eth_da)); 3164 } 3165 3166 /* If no VF representors specified, check for PF ones */ 3167 if (eth_da.nb_representor_ports > 0) 3168 init_data.nb_representors = eth_da.nb_representor_ports; 3169 else 3170 init_data.nb_representors = eth_da.nb_ports; 3171 3172 if (init_data.nb_representors > 0 && 3173 rte_eal_process_type() != RTE_PROC_PRIMARY) { 3174 SFC_GENERIC_LOG(ERR, 3175 "Create representors from secondary process not supported, dev '%s'", 3176 pci_dev->device.name); 3177 return -ENOTSUP; 3178 } 3179 3180 /* 3181 * Driver supports RTE_PCI_DRV_PROBE_AGAIN. Hence create device only 3182 * if it does not already exist. Re-probing an existing device is 3183 * expected to allow additional representors to be configured. 3184 */ 3185 rc = sfc_eth_dev_find_or_create(pci_dev, &init_data, &dev, 3186 &dev_created); 3187 if (rc != 0) 3188 return rc; 3189 3190 rc = sfc_eth_dev_create_representors(dev, ð_da); 3191 if (rc != 0) { 3192 if (dev_created) 3193 (void)rte_eth_dev_destroy(dev, sfc_eth_dev_uninit); 3194 3195 return rc; 3196 } 3197 3198 return 0; 3199 } 3200 3201 static int sfc_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3202 { 3203 return rte_eth_dev_pci_generic_remove(pci_dev, sfc_eth_dev_uninit); 3204 } 3205 3206 static struct rte_pci_driver sfc_efx_pmd = { 3207 .id_table = pci_id_sfc_efx_map, 3208 .drv_flags = 3209 RTE_PCI_DRV_INTR_LSC | 3210 RTE_PCI_DRV_NEED_MAPPING | 3211 RTE_PCI_DRV_PROBE_AGAIN, 3212 .probe = sfc_eth_dev_pci_probe, 3213 .remove = sfc_eth_dev_pci_remove, 3214 }; 3215 3216 RTE_PMD_REGISTER_PCI(net_sfc_efx, sfc_efx_pmd); 3217 RTE_PMD_REGISTER_PCI_TABLE(net_sfc_efx, pci_id_sfc_efx_map); 3218 RTE_PMD_REGISTER_KMOD_DEP(net_sfc_efx, "* igb_uio | uio_pci_generic | vfio-pci"); 3219 RTE_PMD_REGISTER_PARAM_STRING(net_sfc_efx, 3220 SFC_KVARG_SWITCH_MODE "=" SFC_KVARG_VALUES_SWITCH_MODE " " 3221 SFC_KVARG_RX_DATAPATH "=" SFC_KVARG_VALUES_RX_DATAPATH " " 3222 SFC_KVARG_TX_DATAPATH "=" SFC_KVARG_VALUES_TX_DATAPATH " " 3223 SFC_KVARG_PERF_PROFILE "=" SFC_KVARG_VALUES_PERF_PROFILE " " 3224 SFC_KVARG_FW_VARIANT "=" SFC_KVARG_VALUES_FW_VARIANT " " 3225 SFC_KVARG_RXD_WAIT_TIMEOUT_NS "=<long> " 3226 SFC_KVARG_STATS_UPDATE_PERIOD_MS "=<long>"); 3227 3228 RTE_INIT(sfc_driver_register_logtype) 3229 { 3230 int ret; 3231 3232 ret = rte_log_register_type_and_pick_level(SFC_LOGTYPE_PREFIX "driver", 3233 RTE_LOG_NOTICE); 3234 sfc_logtype_driver = (ret < 0) ? RTE_LOGTYPE_PMD : ret; 3235 } 3236