1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <dev_driver.h> 11 #include <ethdev_driver.h> 12 #include <ethdev_pci.h> 13 #include <rte_pci.h> 14 #include <bus_pci_driver.h> 15 #include <rte_errno.h> 16 #include <rte_string_fns.h> 17 #include <rte_ether.h> 18 19 #include "efx.h" 20 21 #include "sfc.h" 22 #include "sfc_debug.h" 23 #include "sfc_log.h" 24 #include "sfc_kvargs.h" 25 #include "sfc_ev.h" 26 #include "sfc_rx.h" 27 #include "sfc_tx.h" 28 #include "sfc_flow.h" 29 #include "sfc_flow_tunnel.h" 30 #include "sfc_dp.h" 31 #include "sfc_dp_rx.h" 32 #include "sfc_repr.h" 33 #include "sfc_sw_stats.h" 34 #include "sfc_switch.h" 35 #include "sfc_nic_dma.h" 36 37 #define SFC_XSTAT_ID_INVALID_VAL UINT64_MAX 38 #define SFC_XSTAT_ID_INVALID_NAME '\0' 39 40 uint32_t sfc_logtype_driver; 41 42 static struct sfc_dp_list sfc_dp_head = 43 TAILQ_HEAD_INITIALIZER(sfc_dp_head); 44 45 46 static void sfc_eth_dev_clear_ops(struct rte_eth_dev *dev); 47 48 49 static int 50 sfc_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 51 { 52 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 53 efx_nic_fw_info_t enfi; 54 int ret; 55 int rc; 56 57 rc = efx_nic_get_fw_version(sa->nic, &enfi); 58 if (rc != 0) 59 return -rc; 60 61 ret = snprintf(fw_version, fw_size, 62 "%" PRIu16 ".%" PRIu16 ".%" PRIu16 ".%" PRIu16, 63 enfi.enfi_mc_fw_version[0], enfi.enfi_mc_fw_version[1], 64 enfi.enfi_mc_fw_version[2], enfi.enfi_mc_fw_version[3]); 65 if (ret < 0) 66 return ret; 67 68 if (enfi.enfi_dpcpu_fw_ids_valid) { 69 size_t dpcpu_fw_ids_offset = MIN(fw_size - 1, (size_t)ret); 70 int ret_extra; 71 72 ret_extra = snprintf(fw_version + dpcpu_fw_ids_offset, 73 fw_size - dpcpu_fw_ids_offset, 74 " rx%" PRIx16 " tx%" PRIx16, 75 enfi.enfi_rx_dpcpu_fw_id, 76 enfi.enfi_tx_dpcpu_fw_id); 77 if (ret_extra < 0) 78 return ret_extra; 79 80 ret += ret_extra; 81 } 82 83 if (fw_size < (size_t)(++ret)) 84 return ret; 85 else 86 return 0; 87 } 88 89 static int 90 sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 91 { 92 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 93 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 94 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 95 struct sfc_rss *rss = &sas->rss; 96 struct sfc_mae *mae = &sa->mae; 97 98 sfc_log_init(sa, "entry"); 99 100 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 101 dev_info->max_mtu = EFX_MAC_SDU_MAX; 102 103 dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX; 104 105 dev_info->max_vfs = sa->sriov.num_vfs; 106 107 /* Autonegotiation may be disabled */ 108 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 109 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX)) 110 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_1G; 111 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX)) 112 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10G; 113 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX)) 114 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G; 115 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX)) 116 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 117 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX)) 118 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G; 119 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX)) 120 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G; 121 122 dev_info->max_rx_queues = sa->rxq_max; 123 dev_info->max_tx_queues = sa->txq_max; 124 125 /* By default packets are dropped if no descriptors are available */ 126 dev_info->default_rxconf.rx_drop_en = 1; 127 128 dev_info->rx_queue_offload_capa = sfc_rx_get_queue_offload_caps(sa); 129 130 /* 131 * rx_offload_capa includes both device and queue offloads since 132 * the latter may be requested on a per device basis which makes 133 * sense when some offloads are needed to be set on all queues. 134 */ 135 dev_info->rx_offload_capa = sfc_rx_get_dev_offload_caps(sa) | 136 dev_info->rx_queue_offload_capa; 137 138 dev_info->tx_queue_offload_capa = sfc_tx_get_queue_offload_caps(sa); 139 140 /* 141 * tx_offload_capa includes both device and queue offloads since 142 * the latter may be requested on a per device basis which makes 143 * sense when some offloads are needed to be set on all queues. 144 */ 145 dev_info->tx_offload_capa = sfc_tx_get_dev_offload_caps(sa) | 146 dev_info->tx_queue_offload_capa; 147 148 if (rss->context_type != EFX_RX_SCALE_UNAVAILABLE) { 149 uint64_t rte_hf = 0; 150 unsigned int i; 151 152 for (i = 0; i < rss->hf_map_nb_entries; ++i) 153 rte_hf |= rss->hf_map[i].rte; 154 155 dev_info->reta_size = EFX_RSS_TBL_SIZE; 156 dev_info->hash_key_size = EFX_RSS_KEY_SIZE; 157 dev_info->flow_type_rss_offloads = rte_hf; 158 } 159 160 /* Initialize to hardware limits */ 161 dev_info->rx_desc_lim.nb_max = sa->rxq_max_entries; 162 dev_info->rx_desc_lim.nb_min = sa->rxq_min_entries; 163 /* The RXQ hardware requires that the descriptor count is a power 164 * of 2, but rx_desc_lim cannot properly describe that constraint. 165 */ 166 dev_info->rx_desc_lim.nb_align = sa->rxq_min_entries; 167 168 /* Initialize to hardware limits */ 169 dev_info->tx_desc_lim.nb_max = sa->txq_max_entries; 170 dev_info->tx_desc_lim.nb_min = sa->txq_min_entries; 171 /* 172 * The TXQ hardware requires that the descriptor count is a power 173 * of 2, but tx_desc_lim cannot properly describe that constraint 174 */ 175 dev_info->tx_desc_lim.nb_align = sa->txq_min_entries; 176 177 if (sap->dp_rx->get_dev_info != NULL) 178 sap->dp_rx->get_dev_info(dev_info); 179 if (sap->dp_tx->get_dev_info != NULL) 180 sap->dp_tx->get_dev_info(dev_info); 181 182 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 183 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 184 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 185 186 if (mae->status == SFC_MAE_STATUS_SUPPORTED || 187 mae->status == SFC_MAE_STATUS_ADMIN) { 188 dev_info->switch_info.name = dev->device->driver->name; 189 dev_info->switch_info.domain_id = mae->switch_domain_id; 190 dev_info->switch_info.port_id = mae->switch_port_id; 191 } 192 193 return 0; 194 } 195 196 static const uint32_t * 197 sfc_dev_supported_ptypes_get(struct rte_eth_dev *dev) 198 { 199 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 200 201 return sap->dp_rx->supported_ptypes_get(sap->shared->tunnel_encaps); 202 } 203 204 static int 205 sfc_dev_configure(struct rte_eth_dev *dev) 206 { 207 struct rte_eth_dev_data *dev_data = dev->data; 208 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 209 int rc; 210 211 sfc_log_init(sa, "entry n_rxq=%u n_txq=%u", 212 dev_data->nb_rx_queues, dev_data->nb_tx_queues); 213 214 sfc_adapter_lock(sa); 215 switch (sa->state) { 216 case SFC_ETHDEV_CONFIGURED: 217 /* FALLTHROUGH */ 218 case SFC_ETHDEV_INITIALIZED: 219 rc = sfc_configure(sa); 220 break; 221 default: 222 sfc_err(sa, "unexpected adapter state %u to configure", 223 sa->state); 224 rc = EINVAL; 225 break; 226 } 227 sfc_adapter_unlock(sa); 228 229 sfc_log_init(sa, "done %d", rc); 230 SFC_ASSERT(rc >= 0); 231 return -rc; 232 } 233 234 static int 235 sfc_dev_start(struct rte_eth_dev *dev) 236 { 237 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 238 int rc; 239 240 sfc_log_init(sa, "entry"); 241 242 sfc_adapter_lock(sa); 243 rc = sfc_start(sa); 244 sfc_adapter_unlock(sa); 245 246 sfc_log_init(sa, "done %d", rc); 247 SFC_ASSERT(rc >= 0); 248 return -rc; 249 } 250 251 static void 252 sfc_dev_get_rte_link(struct rte_eth_dev *dev, int wait_to_complete, 253 struct rte_eth_link *link) 254 { 255 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 256 257 SFC_ASSERT(link != NULL); 258 259 if (sa->state != SFC_ETHDEV_STARTED) { 260 sfc_port_link_mode_to_info(EFX_LINK_UNKNOWN, link); 261 } else if (wait_to_complete) { 262 efx_link_mode_t link_mode; 263 264 if (efx_port_poll(sa->nic, &link_mode) != 0) 265 link_mode = EFX_LINK_UNKNOWN; 266 sfc_port_link_mode_to_info(link_mode, link); 267 } else { 268 sfc_ev_mgmt_qpoll(sa); 269 rte_eth_linkstatus_get(dev, link); 270 } 271 } 272 273 static int 274 sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 275 { 276 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 277 struct rte_eth_link current_link; 278 int ret; 279 280 sfc_log_init(sa, "entry"); 281 282 sfc_dev_get_rte_link(dev, wait_to_complete, ¤t_link); 283 284 ret = rte_eth_linkstatus_set(dev, ¤t_link); 285 if (ret == 0) 286 sfc_notice(sa, "Link status is %s", 287 current_link.link_status ? "UP" : "DOWN"); 288 289 return ret; 290 } 291 292 static int 293 sfc_dev_stop(struct rte_eth_dev *dev) 294 { 295 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 296 297 sfc_log_init(sa, "entry"); 298 299 sfc_adapter_lock(sa); 300 sfc_stop(sa); 301 sfc_adapter_unlock(sa); 302 303 sfc_log_init(sa, "done"); 304 305 return 0; 306 } 307 308 static int 309 sfc_dev_set_link_up(struct rte_eth_dev *dev) 310 { 311 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 312 int rc; 313 314 sfc_log_init(sa, "entry"); 315 316 sfc_adapter_lock(sa); 317 rc = sfc_start(sa); 318 sfc_adapter_unlock(sa); 319 320 SFC_ASSERT(rc >= 0); 321 return -rc; 322 } 323 324 static int 325 sfc_dev_set_link_down(struct rte_eth_dev *dev) 326 { 327 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 328 329 sfc_log_init(sa, "entry"); 330 331 sfc_adapter_lock(sa); 332 sfc_stop(sa); 333 sfc_adapter_unlock(sa); 334 335 return 0; 336 } 337 338 static void 339 sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev) 340 { 341 free(dev->process_private); 342 rte_eth_dev_release_port(dev); 343 } 344 345 static int 346 sfc_dev_close(struct rte_eth_dev *dev) 347 { 348 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 349 350 sfc_log_init(sa, "entry"); 351 352 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 353 sfc_eth_dev_secondary_clear_ops(dev); 354 return 0; 355 } 356 357 sfc_pre_detach(sa); 358 359 sfc_adapter_lock(sa); 360 switch (sa->state) { 361 case SFC_ETHDEV_STARTED: 362 sfc_stop(sa); 363 SFC_ASSERT(sa->state == SFC_ETHDEV_CONFIGURED); 364 /* FALLTHROUGH */ 365 case SFC_ETHDEV_CONFIGURED: 366 sfc_close(sa); 367 SFC_ASSERT(sa->state == SFC_ETHDEV_INITIALIZED); 368 /* FALLTHROUGH */ 369 case SFC_ETHDEV_INITIALIZED: 370 break; 371 default: 372 sfc_err(sa, "unexpected adapter state %u on close", sa->state); 373 break; 374 } 375 376 /* 377 * Cleanup all resources. 378 * Rollback primary process sfc_eth_dev_init() below. 379 */ 380 381 sfc_eth_dev_clear_ops(dev); 382 383 sfc_nic_dma_detach(sa); 384 sfc_detach(sa); 385 sfc_unprobe(sa); 386 387 sfc_kvargs_cleanup(sa); 388 389 sfc_adapter_unlock(sa); 390 sfc_adapter_lock_fini(sa); 391 392 sfc_log_init(sa, "done"); 393 394 /* Required for logging, so cleanup last */ 395 sa->eth_dev = NULL; 396 397 free(sa); 398 399 return 0; 400 } 401 402 static int 403 sfc_dev_filter_set(struct rte_eth_dev *dev, enum sfc_dev_filter_mode mode, 404 boolean_t enabled) 405 { 406 struct sfc_port *port; 407 boolean_t *toggle; 408 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 409 boolean_t allmulti = (mode == SFC_DEV_FILTER_MODE_ALLMULTI); 410 const char *desc = (allmulti) ? "all-multi" : "promiscuous"; 411 int rc = 0; 412 413 sfc_adapter_lock(sa); 414 415 port = &sa->port; 416 toggle = (allmulti) ? (&port->allmulti) : (&port->promisc); 417 418 if (*toggle != enabled) { 419 *toggle = enabled; 420 421 if (sfc_sa2shared(sa)->isolated) { 422 sfc_warn(sa, "isolated mode is active on the port"); 423 sfc_warn(sa, "the change is to be applied on the next " 424 "start provided that isolated mode is " 425 "disabled prior the next start"); 426 } else if ((sa->state == SFC_ETHDEV_STARTED) && 427 ((rc = sfc_set_rx_mode(sa)) != 0)) { 428 *toggle = !(enabled); 429 sfc_warn(sa, "Failed to %s %s mode, rc = %d", 430 ((enabled) ? "enable" : "disable"), desc, rc); 431 432 /* 433 * For promiscuous and all-multicast filters a 434 * permission failure should be reported as an 435 * unsupported filter. 436 */ 437 if (rc == EPERM) 438 rc = ENOTSUP; 439 } 440 } 441 442 sfc_adapter_unlock(sa); 443 return rc; 444 } 445 446 static int 447 sfc_dev_promisc_enable(struct rte_eth_dev *dev) 448 { 449 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_TRUE); 450 451 SFC_ASSERT(rc >= 0); 452 return -rc; 453 } 454 455 static int 456 sfc_dev_promisc_disable(struct rte_eth_dev *dev) 457 { 458 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_FALSE); 459 460 SFC_ASSERT(rc >= 0); 461 return -rc; 462 } 463 464 static int 465 sfc_dev_allmulti_enable(struct rte_eth_dev *dev) 466 { 467 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_TRUE); 468 469 SFC_ASSERT(rc >= 0); 470 return -rc; 471 } 472 473 static int 474 sfc_dev_allmulti_disable(struct rte_eth_dev *dev) 475 { 476 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_FALSE); 477 478 SFC_ASSERT(rc >= 0); 479 return -rc; 480 } 481 482 static int 483 sfc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 484 uint16_t nb_rx_desc, unsigned int socket_id, 485 const struct rte_eth_rxconf *rx_conf, 486 struct rte_mempool *mb_pool) 487 { 488 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 489 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 490 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 491 struct sfc_rxq_info *rxq_info; 492 sfc_sw_index_t sw_index; 493 int rc; 494 495 sfc_log_init(sa, "RxQ=%u nb_rx_desc=%u socket_id=%u", 496 ethdev_qid, nb_rx_desc, socket_id); 497 498 sfc_adapter_lock(sa); 499 500 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 501 rc = sfc_rx_qinit(sa, sw_index, nb_rx_desc, socket_id, 502 rx_conf, mb_pool); 503 if (rc != 0) 504 goto fail_rx_qinit; 505 506 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 507 dev->data->rx_queues[ethdev_qid] = rxq_info->dp; 508 509 sfc_adapter_unlock(sa); 510 511 return 0; 512 513 fail_rx_qinit: 514 sfc_adapter_unlock(sa); 515 SFC_ASSERT(rc > 0); 516 return -rc; 517 } 518 519 static void 520 sfc_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 521 { 522 struct sfc_dp_rxq *dp_rxq = dev->data->rx_queues[qid]; 523 struct sfc_rxq *rxq; 524 struct sfc_adapter *sa; 525 sfc_sw_index_t sw_index; 526 527 if (dp_rxq == NULL) 528 return; 529 530 rxq = sfc_rxq_by_dp_rxq(dp_rxq); 531 sa = rxq->evq->sa; 532 sfc_adapter_lock(sa); 533 534 sw_index = dp_rxq->dpq.queue_id; 535 536 sfc_log_init(sa, "RxQ=%u", sw_index); 537 538 sfc_rx_qfini(sa, sw_index); 539 540 sfc_adapter_unlock(sa); 541 } 542 543 static int 544 sfc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 545 uint16_t nb_tx_desc, unsigned int socket_id, 546 const struct rte_eth_txconf *tx_conf) 547 { 548 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 549 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 550 struct sfc_txq_info *txq_info; 551 sfc_sw_index_t sw_index; 552 int rc; 553 554 sfc_log_init(sa, "TxQ = %u, nb_tx_desc = %u, socket_id = %u", 555 ethdev_qid, nb_tx_desc, socket_id); 556 557 sfc_adapter_lock(sa); 558 559 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 560 rc = sfc_tx_qinit(sa, sw_index, nb_tx_desc, socket_id, tx_conf); 561 if (rc != 0) 562 goto fail_tx_qinit; 563 564 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 565 dev->data->tx_queues[ethdev_qid] = txq_info->dp; 566 567 sfc_adapter_unlock(sa); 568 return 0; 569 570 fail_tx_qinit: 571 sfc_adapter_unlock(sa); 572 SFC_ASSERT(rc > 0); 573 return -rc; 574 } 575 576 static void 577 sfc_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 578 { 579 struct sfc_dp_txq *dp_txq = dev->data->tx_queues[qid]; 580 struct sfc_txq *txq; 581 sfc_sw_index_t sw_index; 582 struct sfc_adapter *sa; 583 584 if (dp_txq == NULL) 585 return; 586 587 txq = sfc_txq_by_dp_txq(dp_txq); 588 sw_index = dp_txq->dpq.queue_id; 589 590 SFC_ASSERT(txq->evq != NULL); 591 sa = txq->evq->sa; 592 593 sfc_log_init(sa, "TxQ = %u", sw_index); 594 595 sfc_adapter_lock(sa); 596 597 sfc_tx_qfini(sa, sw_index); 598 599 sfc_adapter_unlock(sa); 600 } 601 602 static void 603 sfc_stats_get_dp_rx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 604 { 605 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 606 uint64_t pkts_sum = 0; 607 uint64_t bytes_sum = 0; 608 unsigned int i; 609 610 for (i = 0; i < sas->ethdev_rxq_count; ++i) { 611 struct sfc_rxq_info *rxq_info; 612 613 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, i); 614 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 615 union sfc_pkts_bytes qstats; 616 617 sfc_pkts_bytes_get(&rxq_info->dp->dpq.stats, &qstats); 618 pkts_sum += qstats.pkts - 619 sa->sw_stats.reset_rx_pkts[i]; 620 bytes_sum += qstats.bytes - 621 sa->sw_stats.reset_rx_bytes[i]; 622 } 623 } 624 625 *pkts = pkts_sum; 626 *bytes = bytes_sum; 627 } 628 629 static void 630 sfc_stats_get_dp_tx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 631 { 632 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 633 uint64_t pkts_sum = 0; 634 uint64_t bytes_sum = 0; 635 unsigned int i; 636 637 for (i = 0; i < sas->ethdev_txq_count; ++i) { 638 struct sfc_txq_info *txq_info; 639 640 txq_info = sfc_txq_info_by_ethdev_qid(sas, i); 641 if (txq_info->state & SFC_TXQ_INITIALIZED) { 642 union sfc_pkts_bytes qstats; 643 644 sfc_pkts_bytes_get(&txq_info->dp->dpq.stats, &qstats); 645 pkts_sum += qstats.pkts - 646 sa->sw_stats.reset_tx_pkts[i]; 647 bytes_sum += qstats.bytes - 648 sa->sw_stats.reset_tx_bytes[i]; 649 } 650 } 651 652 *pkts = pkts_sum; 653 *bytes = bytes_sum; 654 } 655 656 /* 657 * Some statistics are computed as A - B where A and B each increase 658 * monotonically with some hardware counter(s) and the counters are read 659 * asynchronously. 660 * 661 * If packet X is counted in A, but not counted in B yet, computed value is 662 * greater than real. 663 * 664 * If packet X is not counted in A at the moment of reading the counter, 665 * but counted in B at the moment of reading the counter, computed value 666 * is less than real. 667 * 668 * However, counter which grows backward is worse evil than slightly wrong 669 * value. So, let's try to guarantee that it never happens except may be 670 * the case when the MAC stats are zeroed as a result of a NIC reset. 671 */ 672 static void 673 sfc_update_diff_stat(uint64_t *stat, uint64_t newval) 674 { 675 if ((int64_t)(newval - *stat) > 0 || newval == 0) 676 *stat = newval; 677 } 678 679 static int 680 sfc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 681 { 682 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 683 bool have_dp_rx_stats = sap->dp_rx->features & SFC_DP_RX_FEAT_STATS; 684 bool have_dp_tx_stats = sap->dp_tx->features & SFC_DP_TX_FEAT_STATS; 685 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 686 struct sfc_port *port = &sa->port; 687 uint64_t *mac_stats; 688 int ret; 689 690 sfc_adapter_lock(sa); 691 692 if (have_dp_rx_stats) { 693 sfc_stats_get_dp_rx(sa, &stats->ipackets, &stats->ibytes); 694 if (dev->data->dev_conf.rxmode.offloads & 695 RTE_ETH_RX_OFFLOAD_KEEP_CRC) { 696 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 697 } 698 } 699 if (have_dp_tx_stats) 700 sfc_stats_get_dp_tx(sa, &stats->opackets, &stats->obytes); 701 702 ret = sfc_port_update_mac_stats(sa, B_FALSE); 703 if (ret != 0) 704 goto unlock; 705 706 mac_stats = port->mac_stats_buf; 707 708 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, 709 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS)) { 710 if (!have_dp_rx_stats) { 711 stats->ipackets = 712 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS] + 713 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS] + 714 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]; 715 stats->ibytes = 716 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_BYTES] + 717 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES] + 718 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]; 719 720 /* CRC is included in these stats, but shouldn't be */ 721 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 722 } 723 if (!have_dp_tx_stats) { 724 stats->opackets = 725 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS] + 726 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS] + 727 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]; 728 stats->obytes = 729 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_BYTES] + 730 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES] + 731 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]; 732 733 /* CRC is included in these stats, but shouldn't be */ 734 stats->obytes -= stats->opackets * RTE_ETHER_CRC_LEN; 735 } 736 stats->imissed = mac_stats[EFX_MAC_VADAPTER_RX_BAD_PACKETS]; 737 stats->oerrors = mac_stats[EFX_MAC_VADAPTER_TX_BAD_PACKETS]; 738 } else { 739 if (!have_dp_tx_stats) { 740 stats->opackets = mac_stats[EFX_MAC_TX_PKTS]; 741 stats->obytes = mac_stats[EFX_MAC_TX_OCTETS] - 742 mac_stats[EFX_MAC_TX_PKTS] * RTE_ETHER_CRC_LEN; 743 } 744 745 /* 746 * Take into account stats which are whenever supported 747 * on EF10. If some stat is not supported by current 748 * firmware variant or HW revision, it is guaranteed 749 * to be zero in mac_stats. 750 */ 751 stats->imissed = 752 mac_stats[EFX_MAC_RX_NODESC_DROP_CNT] + 753 mac_stats[EFX_MAC_PM_TRUNC_BB_OVERFLOW] + 754 mac_stats[EFX_MAC_PM_DISCARD_BB_OVERFLOW] + 755 mac_stats[EFX_MAC_PM_TRUNC_VFIFO_FULL] + 756 mac_stats[EFX_MAC_PM_DISCARD_VFIFO_FULL] + 757 mac_stats[EFX_MAC_PM_TRUNC_QBB] + 758 mac_stats[EFX_MAC_PM_DISCARD_QBB] + 759 mac_stats[EFX_MAC_PM_DISCARD_MAPPING] + 760 mac_stats[EFX_MAC_RXDP_Q_DISABLED_PKTS] + 761 mac_stats[EFX_MAC_RXDP_DI_DROPPED_PKTS]; 762 stats->ierrors = 763 mac_stats[EFX_MAC_RX_FCS_ERRORS] + 764 mac_stats[EFX_MAC_RX_ALIGN_ERRORS] + 765 mac_stats[EFX_MAC_RX_JABBER_PKTS]; 766 /* no oerrors counters supported on EF10 */ 767 768 if (!have_dp_rx_stats) { 769 /* Exclude missed, errors and pauses from Rx packets */ 770 sfc_update_diff_stat(&port->ipackets, 771 mac_stats[EFX_MAC_RX_PKTS] - 772 mac_stats[EFX_MAC_RX_PAUSE_PKTS] - 773 stats->imissed - stats->ierrors); 774 stats->ipackets = port->ipackets; 775 stats->ibytes = mac_stats[EFX_MAC_RX_OCTETS] - 776 mac_stats[EFX_MAC_RX_PKTS] * RTE_ETHER_CRC_LEN; 777 } 778 } 779 780 unlock: 781 sfc_adapter_unlock(sa); 782 SFC_ASSERT(ret >= 0); 783 return -ret; 784 } 785 786 static int 787 sfc_stats_reset(struct rte_eth_dev *dev) 788 { 789 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 790 struct sfc_port *port = &sa->port; 791 int rc; 792 793 sfc_adapter_lock(sa); 794 795 if (sa->state != SFC_ETHDEV_STARTED) { 796 /* 797 * The operation cannot be done if port is not started; it 798 * will be scheduled to be done during the next port start 799 */ 800 port->mac_stats_reset_pending = B_TRUE; 801 sfc_adapter_unlock(sa); 802 return 0; 803 } 804 805 rc = sfc_port_reset_mac_stats(sa); 806 if (rc != 0) 807 sfc_err(sa, "failed to reset statistics (rc = %d)", rc); 808 809 sfc_sw_xstats_reset(sa); 810 811 sfc_adapter_unlock(sa); 812 813 SFC_ASSERT(rc >= 0); 814 return -rc; 815 } 816 817 static unsigned int 818 sfc_xstats_get_nb_supported(struct sfc_adapter *sa) 819 { 820 struct sfc_port *port = &sa->port; 821 unsigned int nb_supported; 822 823 sfc_adapter_lock(sa); 824 nb_supported = port->mac_stats_nb_supported + 825 sfc_sw_xstats_get_nb_supported(sa); 826 sfc_adapter_unlock(sa); 827 828 return nb_supported; 829 } 830 831 static int 832 sfc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 833 unsigned int xstats_count) 834 { 835 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 836 unsigned int nb_written = 0; 837 unsigned int nb_supported = 0; 838 int rc; 839 840 if (unlikely(xstats == NULL)) 841 return sfc_xstats_get_nb_supported(sa); 842 843 rc = sfc_port_get_mac_stats(sa, xstats, xstats_count, &nb_written); 844 if (rc < 0) 845 return rc; 846 847 nb_supported = rc; 848 sfc_sw_xstats_get_vals(sa, xstats, xstats_count, &nb_written, 849 &nb_supported); 850 851 return nb_supported; 852 } 853 854 static int 855 sfc_xstats_get_names(struct rte_eth_dev *dev, 856 struct rte_eth_xstat_name *xstats_names, 857 unsigned int xstats_count) 858 { 859 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 860 struct sfc_port *port = &sa->port; 861 unsigned int i; 862 unsigned int nstats = 0; 863 unsigned int nb_written = 0; 864 int ret; 865 866 if (unlikely(xstats_names == NULL)) 867 return sfc_xstats_get_nb_supported(sa); 868 869 for (i = 0; i < EFX_MAC_NSTATS; ++i) { 870 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, i)) { 871 if (nstats < xstats_count) { 872 strlcpy(xstats_names[nstats].name, 873 efx_mac_stat_name(sa->nic, i), 874 sizeof(xstats_names[0].name)); 875 nb_written++; 876 } 877 nstats++; 878 } 879 } 880 881 ret = sfc_sw_xstats_get_names(sa, xstats_names, xstats_count, 882 &nb_written, &nstats); 883 if (ret != 0) { 884 SFC_ASSERT(ret < 0); 885 return ret; 886 } 887 888 return nstats; 889 } 890 891 static int 892 sfc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 893 uint64_t *values, unsigned int n) 894 { 895 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 896 struct sfc_port *port = &sa->port; 897 unsigned int nb_supported; 898 unsigned int i; 899 int rc; 900 901 if (unlikely(ids == NULL || values == NULL)) 902 return -EINVAL; 903 904 /* 905 * Values array could be filled in nonsequential order. Fill values with 906 * constant indicating invalid ID first. 907 */ 908 for (i = 0; i < n; i++) 909 values[i] = SFC_XSTAT_ID_INVALID_VAL; 910 911 rc = sfc_port_get_mac_stats_by_id(sa, ids, values, n); 912 if (rc != 0) 913 return rc; 914 915 nb_supported = port->mac_stats_nb_supported; 916 sfc_sw_xstats_get_vals_by_id(sa, ids, values, n, &nb_supported); 917 918 /* Return number of written stats before invalid ID is encountered. */ 919 for (i = 0; i < n; i++) { 920 if (values[i] == SFC_XSTAT_ID_INVALID_VAL) 921 return i; 922 } 923 924 return n; 925 } 926 927 static int 928 sfc_xstats_get_names_by_id(struct rte_eth_dev *dev, 929 const uint64_t *ids, 930 struct rte_eth_xstat_name *xstats_names, 931 unsigned int size) 932 { 933 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 934 struct sfc_port *port = &sa->port; 935 unsigned int nb_supported; 936 unsigned int i; 937 int ret; 938 939 if (unlikely(xstats_names == NULL && ids != NULL) || 940 unlikely(xstats_names != NULL && ids == NULL)) 941 return -EINVAL; 942 943 if (unlikely(xstats_names == NULL && ids == NULL)) 944 return sfc_xstats_get_nb_supported(sa); 945 946 /* 947 * Names array could be filled in nonsequential order. Fill names with 948 * string indicating invalid ID first. 949 */ 950 for (i = 0; i < size; i++) 951 xstats_names[i].name[0] = SFC_XSTAT_ID_INVALID_NAME; 952 953 sfc_adapter_lock(sa); 954 955 SFC_ASSERT(port->mac_stats_nb_supported <= 956 RTE_DIM(port->mac_stats_by_id)); 957 958 for (i = 0; i < size; i++) { 959 if (ids[i] < port->mac_stats_nb_supported) { 960 strlcpy(xstats_names[i].name, 961 efx_mac_stat_name(sa->nic, 962 port->mac_stats_by_id[ids[i]]), 963 sizeof(xstats_names[0].name)); 964 } 965 } 966 967 nb_supported = port->mac_stats_nb_supported; 968 969 sfc_adapter_unlock(sa); 970 971 ret = sfc_sw_xstats_get_names_by_id(sa, ids, xstats_names, size, 972 &nb_supported); 973 if (ret != 0) { 974 SFC_ASSERT(ret < 0); 975 return ret; 976 } 977 978 /* Return number of written names before invalid ID is encountered. */ 979 for (i = 0; i < size; i++) { 980 if (xstats_names[i].name[0] == SFC_XSTAT_ID_INVALID_NAME) 981 return i; 982 } 983 984 return size; 985 } 986 987 static int 988 sfc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 989 { 990 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 991 unsigned int wanted_fc, link_fc; 992 993 memset(fc_conf, 0, sizeof(*fc_conf)); 994 995 sfc_adapter_lock(sa); 996 997 if (sa->state == SFC_ETHDEV_STARTED) 998 efx_mac_fcntl_get(sa->nic, &wanted_fc, &link_fc); 999 else 1000 link_fc = sa->port.flow_ctrl; 1001 1002 switch (link_fc) { 1003 case 0: 1004 fc_conf->mode = RTE_ETH_FC_NONE; 1005 break; 1006 case EFX_FCNTL_RESPOND: 1007 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1008 break; 1009 case EFX_FCNTL_GENERATE: 1010 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1011 break; 1012 case (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE): 1013 fc_conf->mode = RTE_ETH_FC_FULL; 1014 break; 1015 default: 1016 sfc_err(sa, "%s: unexpected flow control value %#x", 1017 __func__, link_fc); 1018 } 1019 1020 fc_conf->autoneg = sa->port.flow_ctrl_autoneg; 1021 1022 sfc_adapter_unlock(sa); 1023 1024 return 0; 1025 } 1026 1027 static int 1028 sfc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1029 { 1030 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1031 struct sfc_port *port = &sa->port; 1032 unsigned int fcntl; 1033 int rc; 1034 1035 if (fc_conf->high_water != 0 || fc_conf->low_water != 0 || 1036 fc_conf->pause_time != 0 || fc_conf->send_xon != 0 || 1037 fc_conf->mac_ctrl_frame_fwd != 0) { 1038 sfc_err(sa, "unsupported flow control settings specified"); 1039 rc = EINVAL; 1040 goto fail_inval; 1041 } 1042 1043 switch (fc_conf->mode) { 1044 case RTE_ETH_FC_NONE: 1045 fcntl = 0; 1046 break; 1047 case RTE_ETH_FC_RX_PAUSE: 1048 fcntl = EFX_FCNTL_RESPOND; 1049 break; 1050 case RTE_ETH_FC_TX_PAUSE: 1051 fcntl = EFX_FCNTL_GENERATE; 1052 break; 1053 case RTE_ETH_FC_FULL: 1054 fcntl = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 1055 break; 1056 default: 1057 rc = EINVAL; 1058 goto fail_inval; 1059 } 1060 1061 sfc_adapter_lock(sa); 1062 1063 if (sa->state == SFC_ETHDEV_STARTED) { 1064 rc = efx_mac_fcntl_set(sa->nic, fcntl, fc_conf->autoneg); 1065 if (rc != 0) 1066 goto fail_mac_fcntl_set; 1067 } 1068 1069 port->flow_ctrl = fcntl; 1070 port->flow_ctrl_autoneg = fc_conf->autoneg; 1071 1072 sfc_adapter_unlock(sa); 1073 1074 return 0; 1075 1076 fail_mac_fcntl_set: 1077 sfc_adapter_unlock(sa); 1078 fail_inval: 1079 SFC_ASSERT(rc > 0); 1080 return -rc; 1081 } 1082 1083 static int 1084 sfc_check_scatter_on_all_rx_queues(struct sfc_adapter *sa, size_t pdu) 1085 { 1086 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1087 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1088 boolean_t scatter_enabled; 1089 const char *error; 1090 unsigned int i; 1091 1092 for (i = 0; i < sas->rxq_count; i++) { 1093 if ((sas->rxq_info[i].state & SFC_RXQ_INITIALIZED) == 0) 1094 continue; 1095 1096 scatter_enabled = (sas->rxq_info[i].type_flags & 1097 EFX_RXQ_FLAG_SCATTER); 1098 1099 if (!sfc_rx_check_scatter(pdu, sa->rxq_ctrl[i].buf_size, 1100 encp->enc_rx_prefix_size, 1101 scatter_enabled, 1102 encp->enc_rx_scatter_max, &error)) { 1103 sfc_err(sa, "MTU check for RxQ %u failed: %s", i, 1104 error); 1105 return EINVAL; 1106 } 1107 } 1108 1109 return 0; 1110 } 1111 1112 static int 1113 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1114 { 1115 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1116 size_t pdu = EFX_MAC_PDU(mtu); 1117 size_t old_pdu; 1118 int rc; 1119 1120 sfc_log_init(sa, "mtu=%u", mtu); 1121 1122 rc = EINVAL; 1123 if (pdu < EFX_MAC_PDU_MIN) { 1124 sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)", 1125 (unsigned int)mtu, (unsigned int)pdu, 1126 EFX_MAC_PDU_MIN); 1127 goto fail_inval; 1128 } 1129 if (pdu > EFX_MAC_PDU_MAX) { 1130 sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)", 1131 (unsigned int)mtu, (unsigned int)pdu, 1132 (unsigned int)EFX_MAC_PDU_MAX); 1133 goto fail_inval; 1134 } 1135 1136 sfc_adapter_lock(sa); 1137 1138 rc = sfc_check_scatter_on_all_rx_queues(sa, pdu); 1139 if (rc != 0) 1140 goto fail_check_scatter; 1141 1142 if (pdu != sa->port.pdu) { 1143 if (sa->state == SFC_ETHDEV_STARTED) { 1144 sfc_stop(sa); 1145 1146 old_pdu = sa->port.pdu; 1147 sa->port.pdu = pdu; 1148 rc = sfc_start(sa); 1149 if (rc != 0) 1150 goto fail_start; 1151 } else { 1152 sa->port.pdu = pdu; 1153 } 1154 } 1155 1156 sfc_adapter_unlock(sa); 1157 1158 sfc_log_init(sa, "done"); 1159 return 0; 1160 1161 fail_start: 1162 sa->port.pdu = old_pdu; 1163 if (sfc_start(sa) != 0) 1164 sfc_err(sa, "cannot start with neither new (%u) nor old (%u) " 1165 "PDU max size - port is stopped", 1166 (unsigned int)pdu, (unsigned int)old_pdu); 1167 1168 fail_check_scatter: 1169 sfc_adapter_unlock(sa); 1170 1171 fail_inval: 1172 sfc_log_init(sa, "failed %d", rc); 1173 SFC_ASSERT(rc > 0); 1174 return -rc; 1175 } 1176 static int 1177 sfc_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1178 { 1179 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1180 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1181 struct sfc_port *port = &sa->port; 1182 struct rte_ether_addr *old_addr = &dev->data->mac_addrs[0]; 1183 int rc = 0; 1184 1185 sfc_adapter_lock(sa); 1186 1187 if (rte_is_same_ether_addr(mac_addr, &port->default_mac_addr)) 1188 goto unlock; 1189 1190 /* 1191 * Copy the address to the device private data so that 1192 * it could be recalled in the case of adapter restart. 1193 */ 1194 rte_ether_addr_copy(mac_addr, &port->default_mac_addr); 1195 1196 /* 1197 * Neither of the two following checks can return 1198 * an error. The new MAC address is preserved in 1199 * the device private data and can be activated 1200 * on the next port start if the user prevents 1201 * isolated mode from being enabled. 1202 */ 1203 if (sfc_sa2shared(sa)->isolated) { 1204 sfc_warn(sa, "isolated mode is active on the port"); 1205 sfc_warn(sa, "will not set MAC address"); 1206 goto unlock; 1207 } 1208 1209 if (sa->state != SFC_ETHDEV_STARTED) { 1210 sfc_notice(sa, "the port is not started"); 1211 sfc_notice(sa, "the new MAC address will be set on port start"); 1212 1213 goto unlock; 1214 } 1215 1216 if (encp->enc_allow_set_mac_with_installed_filters) { 1217 rc = efx_mac_addr_set(sa->nic, mac_addr->addr_bytes); 1218 if (rc != 0) { 1219 sfc_err(sa, "cannot set MAC address (rc = %u)", rc); 1220 goto unlock; 1221 } 1222 1223 /* 1224 * Changing the MAC address by means of MCDI request 1225 * has no effect on received traffic, therefore 1226 * we also need to update unicast filters 1227 */ 1228 rc = sfc_set_rx_mode_unchecked(sa); 1229 if (rc != 0) { 1230 sfc_err(sa, "cannot set filter (rc = %u)", rc); 1231 /* Rollback the old address */ 1232 (void)efx_mac_addr_set(sa->nic, old_addr->addr_bytes); 1233 (void)sfc_set_rx_mode_unchecked(sa); 1234 } 1235 } else { 1236 sfc_warn(sa, "cannot set MAC address with filters installed"); 1237 sfc_warn(sa, "adapter will be restarted to pick the new MAC"); 1238 sfc_warn(sa, "(some traffic may be dropped)"); 1239 1240 /* 1241 * Since setting MAC address with filters installed is not 1242 * allowed on the adapter, the new MAC address will be set 1243 * by means of adapter restart. sfc_start() shall retrieve 1244 * the new address from the device private data and set it. 1245 */ 1246 sfc_stop(sa); 1247 rc = sfc_start(sa); 1248 if (rc != 0) 1249 sfc_err(sa, "cannot restart adapter (rc = %u)", rc); 1250 } 1251 1252 unlock: 1253 if (rc != 0) 1254 rte_ether_addr_copy(old_addr, &port->default_mac_addr); 1255 1256 sfc_adapter_unlock(sa); 1257 1258 SFC_ASSERT(rc >= 0); 1259 return -rc; 1260 } 1261 1262 1263 static int 1264 sfc_set_mc_addr_list(struct rte_eth_dev *dev, 1265 struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr) 1266 { 1267 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1268 struct sfc_port *port = &sa->port; 1269 uint8_t *mc_addrs = port->mcast_addrs; 1270 int rc; 1271 unsigned int i; 1272 1273 if (sfc_sa2shared(sa)->isolated) { 1274 sfc_err(sa, "isolated mode is active on the port"); 1275 sfc_err(sa, "will not set multicast address list"); 1276 return -ENOTSUP; 1277 } 1278 1279 if (mc_addrs == NULL) 1280 return -ENOBUFS; 1281 1282 if (nb_mc_addr > port->max_mcast_addrs) { 1283 sfc_err(sa, "too many multicast addresses: %u > %u", 1284 nb_mc_addr, port->max_mcast_addrs); 1285 return -EINVAL; 1286 } 1287 1288 for (i = 0; i < nb_mc_addr; ++i) { 1289 rte_memcpy(mc_addrs, mc_addr_set[i].addr_bytes, 1290 EFX_MAC_ADDR_LEN); 1291 mc_addrs += EFX_MAC_ADDR_LEN; 1292 } 1293 1294 port->nb_mcast_addrs = nb_mc_addr; 1295 1296 if (sa->state != SFC_ETHDEV_STARTED) 1297 return 0; 1298 1299 rc = efx_mac_multicast_list_set(sa->nic, port->mcast_addrs, 1300 port->nb_mcast_addrs); 1301 if (rc != 0) 1302 sfc_err(sa, "cannot set multicast address list (rc = %u)", rc); 1303 1304 SFC_ASSERT(rc >= 0); 1305 return -rc; 1306 } 1307 1308 /* 1309 * The function is used by the secondary process as well. It must not 1310 * use any process-local pointers from the adapter data. 1311 */ 1312 static void 1313 sfc_rx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1314 struct rte_eth_rxq_info *qinfo) 1315 { 1316 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1317 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1318 struct sfc_rxq_info *rxq_info; 1319 1320 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1321 1322 qinfo->mp = rxq_info->refill_mb_pool; 1323 qinfo->conf.rx_free_thresh = rxq_info->refill_threshold; 1324 qinfo->conf.rx_drop_en = 1; 1325 qinfo->conf.rx_deferred_start = rxq_info->deferred_start; 1326 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 1327 if (rxq_info->type_flags & EFX_RXQ_FLAG_SCATTER) { 1328 qinfo->conf.offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; 1329 qinfo->scattered_rx = 1; 1330 } 1331 qinfo->nb_desc = rxq_info->entries; 1332 } 1333 1334 /* 1335 * The function is used by the secondary process as well. It must not 1336 * use any process-local pointers from the adapter data. 1337 */ 1338 static void 1339 sfc_tx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1340 struct rte_eth_txq_info *qinfo) 1341 { 1342 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1343 struct sfc_txq_info *txq_info; 1344 1345 SFC_ASSERT(ethdev_qid < sas->ethdev_txq_count); 1346 1347 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1348 1349 memset(qinfo, 0, sizeof(*qinfo)); 1350 1351 qinfo->conf.offloads = txq_info->offloads; 1352 qinfo->conf.tx_free_thresh = txq_info->free_thresh; 1353 qinfo->conf.tx_deferred_start = txq_info->deferred_start; 1354 qinfo->nb_desc = txq_info->entries; 1355 } 1356 1357 /* 1358 * The function is used by the secondary process as well. It must not 1359 * use any process-local pointers from the adapter data. 1360 */ 1361 static uint32_t 1362 sfc_rx_queue_count(void *rx_queue) 1363 { 1364 struct sfc_dp_rxq *dp_rxq = rx_queue; 1365 const struct sfc_dp_rx *dp_rx; 1366 struct sfc_rxq_info *rxq_info; 1367 1368 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1369 rxq_info = sfc_rxq_info_by_dp_rxq(dp_rxq); 1370 1371 if ((rxq_info->state & SFC_RXQ_STARTED) == 0) 1372 return 0; 1373 1374 return dp_rx->qdesc_npending(dp_rxq); 1375 } 1376 1377 /* 1378 * The function is used by the secondary process as well. It must not 1379 * use any process-local pointers from the adapter data. 1380 */ 1381 static int 1382 sfc_rx_descriptor_status(void *queue, uint16_t offset) 1383 { 1384 struct sfc_dp_rxq *dp_rxq = queue; 1385 const struct sfc_dp_rx *dp_rx; 1386 1387 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1388 1389 return dp_rx->qdesc_status(dp_rxq, offset); 1390 } 1391 1392 /* 1393 * The function is used by the secondary process as well. It must not 1394 * use any process-local pointers from the adapter data. 1395 */ 1396 static int 1397 sfc_tx_descriptor_status(void *queue, uint16_t offset) 1398 { 1399 struct sfc_dp_txq *dp_txq = queue; 1400 const struct sfc_dp_tx *dp_tx; 1401 1402 dp_tx = sfc_dp_tx_by_dp_txq(dp_txq); 1403 1404 return dp_tx->qdesc_status(dp_txq, offset); 1405 } 1406 1407 static int 1408 sfc_rx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1409 { 1410 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1411 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1412 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1413 struct sfc_rxq_info *rxq_info; 1414 sfc_sw_index_t sw_index; 1415 int rc; 1416 1417 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1418 1419 sfc_adapter_lock(sa); 1420 1421 rc = EINVAL; 1422 if (sa->state != SFC_ETHDEV_STARTED) 1423 goto fail_not_started; 1424 1425 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1426 if (rxq_info->state != SFC_RXQ_INITIALIZED) 1427 goto fail_not_setup; 1428 1429 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1430 rc = sfc_rx_qstart(sa, sw_index); 1431 if (rc != 0) 1432 goto fail_rx_qstart; 1433 1434 rxq_info->deferred_started = B_TRUE; 1435 1436 sfc_adapter_unlock(sa); 1437 1438 return 0; 1439 1440 fail_rx_qstart: 1441 fail_not_setup: 1442 fail_not_started: 1443 sfc_adapter_unlock(sa); 1444 SFC_ASSERT(rc > 0); 1445 return -rc; 1446 } 1447 1448 static int 1449 sfc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1450 { 1451 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1452 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1453 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1454 struct sfc_rxq_info *rxq_info; 1455 sfc_sw_index_t sw_index; 1456 1457 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1458 1459 sfc_adapter_lock(sa); 1460 1461 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1462 sfc_rx_qstop(sa, sw_index); 1463 1464 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1465 rxq_info->deferred_started = B_FALSE; 1466 1467 sfc_adapter_unlock(sa); 1468 1469 return 0; 1470 } 1471 1472 static int 1473 sfc_tx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1474 { 1475 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1476 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1477 struct sfc_txq_info *txq_info; 1478 sfc_sw_index_t sw_index; 1479 int rc; 1480 1481 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1482 1483 sfc_adapter_lock(sa); 1484 1485 rc = EINVAL; 1486 if (sa->state != SFC_ETHDEV_STARTED) 1487 goto fail_not_started; 1488 1489 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1490 if (txq_info->state != SFC_TXQ_INITIALIZED) 1491 goto fail_not_setup; 1492 1493 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1494 rc = sfc_tx_qstart(sa, sw_index); 1495 if (rc != 0) 1496 goto fail_tx_qstart; 1497 1498 txq_info->deferred_started = B_TRUE; 1499 1500 sfc_adapter_unlock(sa); 1501 return 0; 1502 1503 fail_tx_qstart: 1504 1505 fail_not_setup: 1506 fail_not_started: 1507 sfc_adapter_unlock(sa); 1508 SFC_ASSERT(rc > 0); 1509 return -rc; 1510 } 1511 1512 static int 1513 sfc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1514 { 1515 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1516 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1517 struct sfc_txq_info *txq_info; 1518 sfc_sw_index_t sw_index; 1519 1520 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1521 1522 sfc_adapter_lock(sa); 1523 1524 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1525 sfc_tx_qstop(sa, sw_index); 1526 1527 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1528 txq_info->deferred_started = B_FALSE; 1529 1530 sfc_adapter_unlock(sa); 1531 return 0; 1532 } 1533 1534 static efx_tunnel_protocol_t 1535 sfc_tunnel_rte_type_to_efx_udp_proto(enum rte_eth_tunnel_type rte_type) 1536 { 1537 switch (rte_type) { 1538 case RTE_ETH_TUNNEL_TYPE_VXLAN: 1539 return EFX_TUNNEL_PROTOCOL_VXLAN; 1540 case RTE_ETH_TUNNEL_TYPE_GENEVE: 1541 return EFX_TUNNEL_PROTOCOL_GENEVE; 1542 default: 1543 return EFX_TUNNEL_NPROTOS; 1544 } 1545 } 1546 1547 enum sfc_udp_tunnel_op_e { 1548 SFC_UDP_TUNNEL_ADD_PORT, 1549 SFC_UDP_TUNNEL_DEL_PORT, 1550 }; 1551 1552 static int 1553 sfc_dev_udp_tunnel_op(struct rte_eth_dev *dev, 1554 struct rte_eth_udp_tunnel *tunnel_udp, 1555 enum sfc_udp_tunnel_op_e op) 1556 { 1557 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1558 efx_tunnel_protocol_t tunnel_proto; 1559 int rc; 1560 1561 sfc_log_init(sa, "%s udp_port=%u prot_type=%u", 1562 (op == SFC_UDP_TUNNEL_ADD_PORT) ? "add" : 1563 (op == SFC_UDP_TUNNEL_DEL_PORT) ? "delete" : "unknown", 1564 tunnel_udp->udp_port, tunnel_udp->prot_type); 1565 1566 tunnel_proto = 1567 sfc_tunnel_rte_type_to_efx_udp_proto(tunnel_udp->prot_type); 1568 if (tunnel_proto >= EFX_TUNNEL_NPROTOS) { 1569 rc = ENOTSUP; 1570 goto fail_bad_proto; 1571 } 1572 1573 sfc_adapter_lock(sa); 1574 1575 switch (op) { 1576 case SFC_UDP_TUNNEL_ADD_PORT: 1577 rc = efx_tunnel_config_udp_add(sa->nic, 1578 tunnel_udp->udp_port, 1579 tunnel_proto); 1580 break; 1581 case SFC_UDP_TUNNEL_DEL_PORT: 1582 rc = efx_tunnel_config_udp_remove(sa->nic, 1583 tunnel_udp->udp_port, 1584 tunnel_proto); 1585 break; 1586 default: 1587 rc = EINVAL; 1588 goto fail_bad_op; 1589 } 1590 1591 if (rc != 0) 1592 goto fail_op; 1593 1594 if (sa->state == SFC_ETHDEV_STARTED) { 1595 rc = efx_tunnel_reconfigure(sa->nic); 1596 if (rc == EAGAIN) { 1597 /* 1598 * Configuration is accepted by FW and MC reboot 1599 * is initiated to apply the changes. MC reboot 1600 * will be handled in a usual way (MC reboot 1601 * event on management event queue and adapter 1602 * restart). 1603 */ 1604 rc = 0; 1605 } else if (rc != 0) { 1606 goto fail_reconfigure; 1607 } 1608 } 1609 1610 sfc_adapter_unlock(sa); 1611 return 0; 1612 1613 fail_reconfigure: 1614 /* Remove/restore entry since the change makes the trouble */ 1615 switch (op) { 1616 case SFC_UDP_TUNNEL_ADD_PORT: 1617 (void)efx_tunnel_config_udp_remove(sa->nic, 1618 tunnel_udp->udp_port, 1619 tunnel_proto); 1620 break; 1621 case SFC_UDP_TUNNEL_DEL_PORT: 1622 (void)efx_tunnel_config_udp_add(sa->nic, 1623 tunnel_udp->udp_port, 1624 tunnel_proto); 1625 break; 1626 } 1627 1628 fail_op: 1629 fail_bad_op: 1630 sfc_adapter_unlock(sa); 1631 1632 fail_bad_proto: 1633 SFC_ASSERT(rc > 0); 1634 return -rc; 1635 } 1636 1637 static int 1638 sfc_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 1639 struct rte_eth_udp_tunnel *tunnel_udp) 1640 { 1641 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_ADD_PORT); 1642 } 1643 1644 static int 1645 sfc_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 1646 struct rte_eth_udp_tunnel *tunnel_udp) 1647 { 1648 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_DEL_PORT); 1649 } 1650 1651 /* 1652 * The function is used by the secondary process as well. It must not 1653 * use any process-local pointers from the adapter data. 1654 */ 1655 static int 1656 sfc_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1657 struct rte_eth_rss_conf *rss_conf) 1658 { 1659 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1660 struct sfc_rss *rss = &sas->rss; 1661 1662 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) 1663 return -ENOTSUP; 1664 1665 /* 1666 * Mapping of hash configuration between RTE and EFX is not one-to-one, 1667 * hence, conversion is done here to derive a correct set of RTE_ETH_RSS 1668 * flags which corresponds to the active EFX configuration stored 1669 * locally in 'sfc_adapter' and kept up-to-date 1670 */ 1671 rss_conf->rss_hf = sfc_rx_hf_efx_to_rte(rss, rss->hash_types); 1672 rss_conf->rss_key_len = EFX_RSS_KEY_SIZE; 1673 if (rss_conf->rss_key != NULL) 1674 rte_memcpy(rss_conf->rss_key, rss->key, EFX_RSS_KEY_SIZE); 1675 1676 return 0; 1677 } 1678 1679 static int 1680 sfc_dev_rss_hash_update(struct rte_eth_dev *dev, 1681 struct rte_eth_rss_conf *rss_conf) 1682 { 1683 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1684 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1685 unsigned int efx_hash_types; 1686 unsigned int n_contexts; 1687 unsigned int mode_i = 0; 1688 unsigned int key_i = 0; 1689 uint32_t contexts[2]; 1690 unsigned int i = 0; 1691 int rc = 0; 1692 1693 if (sfc_sa2shared(sa)->isolated) 1694 return -ENOTSUP; 1695 1696 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1697 sfc_err(sa, "RSS is not available"); 1698 return -ENOTSUP; 1699 } 1700 1701 if (rss->channels == 0) { 1702 sfc_err(sa, "RSS is not configured"); 1703 return -EINVAL; 1704 } 1705 1706 if ((rss_conf->rss_key != NULL) && 1707 (rss_conf->rss_key_len != sizeof(rss->key))) { 1708 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1709 sizeof(rss->key)); 1710 return -EINVAL; 1711 } 1712 1713 sfc_adapter_lock(sa); 1714 1715 rc = sfc_rx_hf_rte_to_efx(sa, rss_conf->rss_hf, &efx_hash_types); 1716 if (rc != 0) 1717 goto fail_rx_hf_rte_to_efx; 1718 1719 contexts[0] = EFX_RSS_CONTEXT_DEFAULT; 1720 contexts[1] = rss->dummy_ctx.nic_handle; 1721 n_contexts = (rss->dummy_ctx.nic_handle_refcnt == 0) ? 1 : 2; 1722 1723 for (mode_i = 0; mode_i < n_contexts; mode_i++) { 1724 rc = efx_rx_scale_mode_set(sa->nic, contexts[mode_i], 1725 rss->hash_alg, efx_hash_types, 1726 B_TRUE); 1727 if (rc != 0) 1728 goto fail_scale_mode_set; 1729 } 1730 1731 if (rss_conf->rss_key != NULL) { 1732 if (sa->state == SFC_ETHDEV_STARTED) { 1733 for (key_i = 0; key_i < n_contexts; key_i++) { 1734 rc = efx_rx_scale_key_set(sa->nic, 1735 contexts[key_i], 1736 rss_conf->rss_key, 1737 sizeof(rss->key)); 1738 if (rc != 0) 1739 goto fail_scale_key_set; 1740 } 1741 } 1742 1743 rte_memcpy(rss->key, rss_conf->rss_key, sizeof(rss->key)); 1744 } 1745 1746 rss->hash_types = efx_hash_types; 1747 1748 sfc_adapter_unlock(sa); 1749 1750 return 0; 1751 1752 fail_scale_key_set: 1753 for (i = 0; i < key_i; i++) { 1754 if (efx_rx_scale_key_set(sa->nic, contexts[i], rss->key, 1755 sizeof(rss->key)) != 0) 1756 sfc_err(sa, "failed to restore RSS key"); 1757 } 1758 1759 fail_scale_mode_set: 1760 for (i = 0; i < mode_i; i++) { 1761 if (efx_rx_scale_mode_set(sa->nic, contexts[i], 1762 EFX_RX_HASHALG_TOEPLITZ, 1763 rss->hash_types, B_TRUE) != 0) 1764 sfc_err(sa, "failed to restore RSS mode"); 1765 } 1766 1767 fail_rx_hf_rte_to_efx: 1768 sfc_adapter_unlock(sa); 1769 return -rc; 1770 } 1771 1772 /* 1773 * The function is used by the secondary process as well. It must not 1774 * use any process-local pointers from the adapter data. 1775 */ 1776 static int 1777 sfc_dev_rss_reta_query(struct rte_eth_dev *dev, 1778 struct rte_eth_rss_reta_entry64 *reta_conf, 1779 uint16_t reta_size) 1780 { 1781 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1782 struct sfc_rss *rss = &sas->rss; 1783 int entry; 1784 1785 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE || sas->isolated) 1786 return -ENOTSUP; 1787 1788 if (rss->channels == 0) 1789 return -EINVAL; 1790 1791 if (reta_size != EFX_RSS_TBL_SIZE) 1792 return -EINVAL; 1793 1794 for (entry = 0; entry < reta_size; entry++) { 1795 int grp = entry / RTE_ETH_RETA_GROUP_SIZE; 1796 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1797 1798 if ((reta_conf[grp].mask >> grp_idx) & 1) 1799 reta_conf[grp].reta[grp_idx] = rss->tbl[entry]; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int 1806 sfc_dev_rss_reta_update(struct rte_eth_dev *dev, 1807 struct rte_eth_rss_reta_entry64 *reta_conf, 1808 uint16_t reta_size) 1809 { 1810 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1811 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1812 unsigned int *rss_tbl_new; 1813 uint16_t entry; 1814 int rc = 0; 1815 1816 1817 if (sfc_sa2shared(sa)->isolated) 1818 return -ENOTSUP; 1819 1820 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1821 sfc_err(sa, "RSS is not available"); 1822 return -ENOTSUP; 1823 } 1824 1825 if (rss->channels == 0) { 1826 sfc_err(sa, "RSS is not configured"); 1827 return -EINVAL; 1828 } 1829 1830 if (reta_size != EFX_RSS_TBL_SIZE) { 1831 sfc_err(sa, "RETA size is wrong (should be %u)", 1832 EFX_RSS_TBL_SIZE); 1833 return -EINVAL; 1834 } 1835 1836 rss_tbl_new = rte_zmalloc("rss_tbl_new", sizeof(rss->tbl), 0); 1837 if (rss_tbl_new == NULL) 1838 return -ENOMEM; 1839 1840 sfc_adapter_lock(sa); 1841 1842 rte_memcpy(rss_tbl_new, rss->tbl, sizeof(rss->tbl)); 1843 1844 for (entry = 0; entry < reta_size; entry++) { 1845 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1846 struct rte_eth_rss_reta_entry64 *grp; 1847 1848 grp = &reta_conf[entry / RTE_ETH_RETA_GROUP_SIZE]; 1849 1850 if (grp->mask & (1ull << grp_idx)) { 1851 if (grp->reta[grp_idx] >= rss->channels) { 1852 rc = EINVAL; 1853 goto bad_reta_entry; 1854 } 1855 rss_tbl_new[entry] = grp->reta[grp_idx]; 1856 } 1857 } 1858 1859 if (sa->state == SFC_ETHDEV_STARTED) { 1860 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1861 rss_tbl_new, EFX_RSS_TBL_SIZE); 1862 if (rc != 0) 1863 goto fail_scale_tbl_set; 1864 } 1865 1866 rte_memcpy(rss->tbl, rss_tbl_new, sizeof(rss->tbl)); 1867 1868 fail_scale_tbl_set: 1869 bad_reta_entry: 1870 sfc_adapter_unlock(sa); 1871 1872 rte_free(rss_tbl_new); 1873 1874 SFC_ASSERT(rc >= 0); 1875 return -rc; 1876 } 1877 1878 static int 1879 sfc_dev_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 1880 const struct rte_flow_ops **ops) 1881 { 1882 *ops = &sfc_flow_ops; 1883 return 0; 1884 } 1885 1886 static int 1887 sfc_pool_ops_supported(struct rte_eth_dev *dev, const char *pool) 1888 { 1889 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1890 1891 /* 1892 * If Rx datapath does not provide callback to check mempool, 1893 * all pools are supported. 1894 */ 1895 if (sap->dp_rx->pool_ops_supported == NULL) 1896 return 1; 1897 1898 return sap->dp_rx->pool_ops_supported(pool); 1899 } 1900 1901 static int 1902 sfc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1903 { 1904 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1905 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1906 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1907 struct sfc_rxq_info *rxq_info; 1908 1909 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1910 1911 return sap->dp_rx->intr_enable(rxq_info->dp); 1912 } 1913 1914 static int 1915 sfc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1916 { 1917 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1918 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1919 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1920 struct sfc_rxq_info *rxq_info; 1921 1922 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1923 1924 return sap->dp_rx->intr_disable(rxq_info->dp); 1925 } 1926 1927 struct sfc_mport_journal_ctx { 1928 struct sfc_adapter *sa; 1929 uint16_t switch_domain_id; 1930 uint32_t mcdi_handle; 1931 bool controllers_assigned; 1932 efx_pcie_interface_t *controllers; 1933 size_t nb_controllers; 1934 }; 1935 1936 static int 1937 sfc_journal_ctx_add_controller(struct sfc_mport_journal_ctx *ctx, 1938 efx_pcie_interface_t intf) 1939 { 1940 efx_pcie_interface_t *new_controllers; 1941 size_t i, target; 1942 size_t new_size; 1943 1944 if (ctx->controllers == NULL) { 1945 ctx->controllers = rte_malloc("sfc_controller_mapping", 1946 sizeof(ctx->controllers[0]), 0); 1947 if (ctx->controllers == NULL) 1948 return ENOMEM; 1949 1950 ctx->controllers[0] = intf; 1951 ctx->nb_controllers = 1; 1952 1953 return 0; 1954 } 1955 1956 for (i = 0; i < ctx->nb_controllers; i++) { 1957 if (ctx->controllers[i] == intf) 1958 return 0; 1959 if (ctx->controllers[i] > intf) 1960 break; 1961 } 1962 target = i; 1963 1964 ctx->nb_controllers += 1; 1965 new_size = ctx->nb_controllers * sizeof(ctx->controllers[0]); 1966 1967 new_controllers = rte_realloc(ctx->controllers, new_size, 0); 1968 if (new_controllers == NULL) { 1969 rte_free(ctx->controllers); 1970 return ENOMEM; 1971 } 1972 ctx->controllers = new_controllers; 1973 1974 for (i = target + 1; i < ctx->nb_controllers; i++) 1975 ctx->controllers[i] = ctx->controllers[i - 1]; 1976 1977 ctx->controllers[target] = intf; 1978 1979 return 0; 1980 } 1981 1982 static efx_rc_t 1983 sfc_process_mport_journal_entry(struct sfc_mport_journal_ctx *ctx, 1984 efx_mport_desc_t *mport) 1985 { 1986 struct sfc_mae_switch_port_request req; 1987 efx_mport_sel_t entity_selector; 1988 efx_mport_sel_t ethdev_mport; 1989 uint16_t switch_port_id; 1990 efx_rc_t efx_rc; 1991 int rc; 1992 1993 sfc_dbg(ctx->sa, 1994 "processing mport id %u (controller %u pf %u vf %u)", 1995 mport->emd_id.id, mport->emd_vnic.ev_intf, 1996 mport->emd_vnic.ev_pf, mport->emd_vnic.ev_vf); 1997 efx_mae_mport_invalid(ðdev_mport); 1998 1999 if (!ctx->controllers_assigned) { 2000 rc = sfc_journal_ctx_add_controller(ctx, 2001 mport->emd_vnic.ev_intf); 2002 if (rc != 0) 2003 return rc; 2004 } 2005 2006 /* Build Mport selector */ 2007 efx_rc = efx_mae_mport_by_pcie_mh_function(mport->emd_vnic.ev_intf, 2008 mport->emd_vnic.ev_pf, 2009 mport->emd_vnic.ev_vf, 2010 &entity_selector); 2011 if (efx_rc != 0) { 2012 sfc_err(ctx->sa, "failed to build entity mport selector for c%upf%uvf%u", 2013 mport->emd_vnic.ev_intf, 2014 mport->emd_vnic.ev_pf, 2015 mport->emd_vnic.ev_vf); 2016 return efx_rc; 2017 } 2018 2019 rc = sfc_mae_switch_port_id_by_entity(ctx->switch_domain_id, 2020 &entity_selector, 2021 SFC_MAE_SWITCH_PORT_REPRESENTOR, 2022 &switch_port_id); 2023 switch (rc) { 2024 case 0: 2025 /* Already registered */ 2026 break; 2027 case ENOENT: 2028 /* 2029 * No representor has been created for this entity. 2030 * Create a dummy switch registry entry with an invalid ethdev 2031 * mport selector. When a corresponding representor is created, 2032 * this entry will be updated. 2033 */ 2034 req.type = SFC_MAE_SWITCH_PORT_REPRESENTOR; 2035 req.entity_mportp = &entity_selector; 2036 req.ethdev_mportp = ðdev_mport; 2037 req.ethdev_port_id = RTE_MAX_ETHPORTS; 2038 req.port_data.repr.intf = mport->emd_vnic.ev_intf; 2039 req.port_data.repr.pf = mport->emd_vnic.ev_pf; 2040 req.port_data.repr.vf = mport->emd_vnic.ev_vf; 2041 2042 rc = sfc_mae_assign_switch_port(ctx->switch_domain_id, 2043 &req, &switch_port_id); 2044 if (rc != 0) { 2045 sfc_err(ctx->sa, 2046 "failed to assign MAE switch port for c%upf%uvf%u: %s", 2047 mport->emd_vnic.ev_intf, 2048 mport->emd_vnic.ev_pf, 2049 mport->emd_vnic.ev_vf, 2050 rte_strerror(rc)); 2051 return rc; 2052 } 2053 break; 2054 default: 2055 sfc_err(ctx->sa, "failed to find MAE switch port for c%upf%uvf%u: %s", 2056 mport->emd_vnic.ev_intf, 2057 mport->emd_vnic.ev_pf, 2058 mport->emd_vnic.ev_vf, 2059 rte_strerror(rc)); 2060 return rc; 2061 } 2062 2063 return 0; 2064 } 2065 2066 static efx_rc_t 2067 sfc_process_mport_journal_cb(void *data, efx_mport_desc_t *mport, 2068 size_t mport_len) 2069 { 2070 struct sfc_mport_journal_ctx *ctx = data; 2071 2072 if (ctx == NULL || ctx->sa == NULL) { 2073 SFC_GENERIC_LOG(ERR, "received NULL context or SFC adapter"); 2074 return EINVAL; 2075 } 2076 2077 if (mport_len != sizeof(*mport)) { 2078 sfc_err(ctx->sa, "actual and expected mport buffer sizes differ"); 2079 return EINVAL; 2080 } 2081 2082 SFC_ASSERT(sfc_adapter_is_locked(ctx->sa)); 2083 2084 /* 2085 * If a zombie flag is set, it means the mport has been marked for 2086 * deletion and cannot be used for any new operations. The mport will 2087 * be destroyed completely once all references to it are released. 2088 */ 2089 if (mport->emd_zombie) { 2090 sfc_dbg(ctx->sa, "mport is a zombie, skipping"); 2091 return 0; 2092 } 2093 if (mport->emd_type != EFX_MPORT_TYPE_VNIC) { 2094 sfc_dbg(ctx->sa, "mport is not a VNIC, skipping"); 2095 return 0; 2096 } 2097 if (mport->emd_vnic.ev_client_type != EFX_MPORT_VNIC_CLIENT_FUNCTION) { 2098 sfc_dbg(ctx->sa, "mport is not a function, skipping"); 2099 return 0; 2100 } 2101 if (mport->emd_vnic.ev_handle == ctx->mcdi_handle) { 2102 sfc_dbg(ctx->sa, "mport is this driver instance, skipping"); 2103 return 0; 2104 } 2105 2106 return sfc_process_mport_journal_entry(ctx, mport); 2107 } 2108 2109 static int 2110 sfc_process_mport_journal(struct sfc_adapter *sa) 2111 { 2112 struct sfc_mport_journal_ctx ctx; 2113 const efx_pcie_interface_t *controllers; 2114 size_t nb_controllers; 2115 efx_rc_t efx_rc; 2116 int rc; 2117 2118 memset(&ctx, 0, sizeof(ctx)); 2119 ctx.sa = sa; 2120 ctx.switch_domain_id = sa->mae.switch_domain_id; 2121 2122 efx_rc = efx_mcdi_get_own_client_handle(sa->nic, &ctx.mcdi_handle); 2123 if (efx_rc != 0) { 2124 sfc_err(sa, "failed to get own MCDI handle"); 2125 SFC_ASSERT(efx_rc > 0); 2126 return efx_rc; 2127 } 2128 2129 rc = sfc_mae_switch_domain_controllers(ctx.switch_domain_id, 2130 &controllers, &nb_controllers); 2131 if (rc != 0) { 2132 sfc_err(sa, "failed to get controller mapping"); 2133 return rc; 2134 } 2135 2136 ctx.controllers_assigned = controllers != NULL; 2137 ctx.controllers = NULL; 2138 ctx.nb_controllers = 0; 2139 2140 efx_rc = efx_mae_read_mport_journal(sa->nic, 2141 sfc_process_mport_journal_cb, &ctx); 2142 if (efx_rc != 0) { 2143 sfc_err(sa, "failed to process MAE mport journal"); 2144 SFC_ASSERT(efx_rc > 0); 2145 return efx_rc; 2146 } 2147 2148 if (controllers == NULL) { 2149 rc = sfc_mae_switch_domain_map_controllers(ctx.switch_domain_id, 2150 ctx.controllers, 2151 ctx.nb_controllers); 2152 if (rc != 0) 2153 return rc; 2154 } 2155 2156 return 0; 2157 } 2158 2159 static void 2160 sfc_count_representors_cb(enum sfc_mae_switch_port_type type, 2161 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2162 uint16_t ethdev_port_id __rte_unused, 2163 const efx_mport_sel_t *entity_mportp __rte_unused, 2164 uint16_t switch_port_id __rte_unused, 2165 union sfc_mae_switch_port_data *port_datap 2166 __rte_unused, 2167 void *user_datap) 2168 { 2169 int *counter = user_datap; 2170 2171 SFC_ASSERT(counter != NULL); 2172 2173 if (type == SFC_MAE_SWITCH_PORT_REPRESENTOR) 2174 (*counter)++; 2175 } 2176 2177 struct sfc_get_representors_ctx { 2178 struct rte_eth_representor_info *info; 2179 struct sfc_adapter *sa; 2180 uint16_t switch_domain_id; 2181 const efx_pcie_interface_t *controllers; 2182 size_t nb_controllers; 2183 }; 2184 2185 static void 2186 sfc_get_representors_cb(enum sfc_mae_switch_port_type type, 2187 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2188 uint16_t ethdev_port_id __rte_unused, 2189 const efx_mport_sel_t *entity_mportp __rte_unused, 2190 uint16_t switch_port_id, 2191 union sfc_mae_switch_port_data *port_datap, 2192 void *user_datap) 2193 { 2194 struct sfc_get_representors_ctx *ctx = user_datap; 2195 struct rte_eth_representor_range *range; 2196 int ret; 2197 int rc; 2198 2199 SFC_ASSERT(ctx != NULL); 2200 SFC_ASSERT(ctx->info != NULL); 2201 SFC_ASSERT(ctx->sa != NULL); 2202 2203 if (type != SFC_MAE_SWITCH_PORT_REPRESENTOR) { 2204 sfc_dbg(ctx->sa, "not a representor, skipping"); 2205 return; 2206 } 2207 if (ctx->info->nb_ranges >= ctx->info->nb_ranges_alloc) { 2208 sfc_dbg(ctx->sa, "info structure is full already"); 2209 return; 2210 } 2211 2212 range = &ctx->info->ranges[ctx->info->nb_ranges]; 2213 rc = sfc_mae_switch_controller_from_mapping(ctx->controllers, 2214 ctx->nb_controllers, 2215 port_datap->repr.intf, 2216 &range->controller); 2217 if (rc != 0) { 2218 sfc_err(ctx->sa, "invalid representor controller: %d", 2219 port_datap->repr.intf); 2220 range->controller = -1; 2221 } 2222 range->pf = port_datap->repr.pf; 2223 range->id_base = switch_port_id; 2224 range->id_end = switch_port_id; 2225 2226 if (port_datap->repr.vf != EFX_PCI_VF_INVALID) { 2227 range->type = RTE_ETH_REPRESENTOR_VF; 2228 range->vf = port_datap->repr.vf; 2229 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2230 "c%dpf%dvf%d", range->controller, range->pf, 2231 range->vf); 2232 } else { 2233 range->type = RTE_ETH_REPRESENTOR_PF; 2234 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2235 "c%dpf%d", range->controller, range->pf); 2236 } 2237 if (ret >= RTE_DEV_NAME_MAX_LEN) { 2238 sfc_err(ctx->sa, "representor name has been truncated: %s", 2239 range->name); 2240 } 2241 2242 ctx->info->nb_ranges++; 2243 } 2244 2245 static int 2246 sfc_representor_info_get(struct rte_eth_dev *dev, 2247 struct rte_eth_representor_info *info) 2248 { 2249 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2250 struct sfc_get_representors_ctx get_repr_ctx; 2251 const efx_nic_cfg_t *nic_cfg; 2252 uint16_t switch_domain_id; 2253 uint32_t nb_repr; 2254 int controller; 2255 int rc; 2256 2257 sfc_adapter_lock(sa); 2258 2259 if (sa->mae.status != SFC_MAE_STATUS_ADMIN) { 2260 sfc_adapter_unlock(sa); 2261 return -ENOTSUP; 2262 } 2263 2264 rc = sfc_process_mport_journal(sa); 2265 if (rc != 0) { 2266 sfc_adapter_unlock(sa); 2267 SFC_ASSERT(rc > 0); 2268 return -rc; 2269 } 2270 2271 switch_domain_id = sa->mae.switch_domain_id; 2272 2273 nb_repr = 0; 2274 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2275 sfc_count_representors_cb, 2276 &nb_repr); 2277 if (rc != 0) { 2278 sfc_adapter_unlock(sa); 2279 SFC_ASSERT(rc > 0); 2280 return -rc; 2281 } 2282 2283 if (info == NULL) { 2284 sfc_adapter_unlock(sa); 2285 return nb_repr; 2286 } 2287 2288 rc = sfc_mae_switch_domain_controllers(switch_domain_id, 2289 &get_repr_ctx.controllers, 2290 &get_repr_ctx.nb_controllers); 2291 if (rc != 0) { 2292 sfc_adapter_unlock(sa); 2293 SFC_ASSERT(rc > 0); 2294 return -rc; 2295 } 2296 2297 nic_cfg = efx_nic_cfg_get(sa->nic); 2298 2299 rc = sfc_mae_switch_domain_get_controller(switch_domain_id, 2300 nic_cfg->enc_intf, 2301 &controller); 2302 if (rc != 0) { 2303 sfc_err(sa, "invalid controller: %d", nic_cfg->enc_intf); 2304 controller = -1; 2305 } 2306 2307 info->controller = controller; 2308 info->pf = nic_cfg->enc_pf; 2309 2310 get_repr_ctx.info = info; 2311 get_repr_ctx.sa = sa; 2312 get_repr_ctx.switch_domain_id = switch_domain_id; 2313 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2314 sfc_get_representors_cb, 2315 &get_repr_ctx); 2316 if (rc != 0) { 2317 sfc_adapter_unlock(sa); 2318 SFC_ASSERT(rc > 0); 2319 return -rc; 2320 } 2321 2322 sfc_adapter_unlock(sa); 2323 return nb_repr; 2324 } 2325 2326 static int 2327 sfc_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 2328 { 2329 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2330 uint64_t supported = 0; 2331 2332 sfc_adapter_lock(sa); 2333 2334 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_FLAG) != 0) 2335 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 2336 2337 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_MARK) != 0) 2338 supported |= RTE_ETH_RX_METADATA_USER_MARK; 2339 2340 if (sfc_ft_is_supported(sa)) 2341 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 2342 2343 sa->negotiated_rx_metadata = supported & *features; 2344 *features = sa->negotiated_rx_metadata; 2345 2346 sfc_adapter_unlock(sa); 2347 2348 return 0; 2349 } 2350 2351 static unsigned int 2352 sfc_fec_get_capa_speed_to_fec(uint32_t supported_caps, 2353 struct rte_eth_fec_capa *speed_fec_capa) 2354 { 2355 unsigned int num = 0; 2356 bool baser = false; 2357 bool rs = false; 2358 2359 if (supported_caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC)) 2360 baser = true; 2361 if (supported_caps & EFX_PHY_CAP_FEC_BIT(RS_FEC)) 2362 rs = true; 2363 2364 /* 2365 * NOFEC and AUTO FEC modes are always supported. 2366 * FW does not provide information about the supported 2367 * FEC modes per the link speed. 2368 * Supported FEC depends on supported link speeds and 2369 * supported FEC modes by a device. 2370 */ 2371 if (supported_caps & (1u << EFX_PHY_CAP_10000FDX)) { 2372 if (speed_fec_capa != NULL) { 2373 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_10G; 2374 speed_fec_capa[num].capa = 2375 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2376 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2377 if (baser) { 2378 speed_fec_capa[num].capa |= 2379 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2380 } 2381 } 2382 num++; 2383 } 2384 if (supported_caps & (1u << EFX_PHY_CAP_25000FDX)) { 2385 if (speed_fec_capa != NULL) { 2386 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_25G; 2387 speed_fec_capa[num].capa = 2388 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2389 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2390 if (baser) { 2391 speed_fec_capa[num].capa |= 2392 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2393 } 2394 if (rs) { 2395 speed_fec_capa[num].capa |= 2396 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2397 } 2398 } 2399 num++; 2400 } 2401 if (supported_caps & (1u << EFX_PHY_CAP_40000FDX)) { 2402 if (speed_fec_capa != NULL) { 2403 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_40G; 2404 speed_fec_capa[num].capa = 2405 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2406 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2407 if (baser) { 2408 speed_fec_capa[num].capa |= 2409 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2410 } 2411 } 2412 num++; 2413 } 2414 if (supported_caps & (1u << EFX_PHY_CAP_50000FDX)) { 2415 if (speed_fec_capa != NULL) { 2416 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_50G; 2417 speed_fec_capa[num].capa = 2418 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2419 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2420 if (baser) { 2421 speed_fec_capa[num].capa |= 2422 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2423 } 2424 if (rs) { 2425 speed_fec_capa[num].capa |= 2426 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2427 } 2428 } 2429 num++; 2430 } 2431 if (supported_caps & (1u << EFX_PHY_CAP_100000FDX)) { 2432 if (speed_fec_capa != NULL) { 2433 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_100G; 2434 speed_fec_capa[num].capa = 2435 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2436 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2437 if (rs) { 2438 speed_fec_capa[num].capa |= 2439 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2440 } 2441 } 2442 num++; 2443 } 2444 2445 return num; 2446 } 2447 2448 static int 2449 sfc_fec_get_capability(struct rte_eth_dev *dev, 2450 struct rte_eth_fec_capa *speed_fec_capa, 2451 unsigned int num) 2452 { 2453 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2454 unsigned int num_entries; 2455 uint32_t supported_caps; 2456 2457 sfc_adapter_lock(sa); 2458 2459 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &supported_caps); 2460 2461 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, NULL); 2462 if (speed_fec_capa == NULL || num < num_entries) 2463 goto adapter_unlock; 2464 2465 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, 2466 speed_fec_capa); 2467 2468 adapter_unlock: 2469 sfc_adapter_unlock(sa); 2470 2471 return num_entries; 2472 } 2473 2474 static uint32_t 2475 sfc_efx_caps_to_fec(uint32_t caps, bool is_25g) 2476 { 2477 bool rs_req = caps & EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED); 2478 bool rs = caps & EFX_PHY_CAP_FEC_BIT(RS_FEC); 2479 bool baser_req; 2480 bool baser; 2481 2482 if (is_25g) { 2483 baser = caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC); 2484 baser_req = caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED); 2485 } else { 2486 baser = caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC); 2487 baser_req = caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED); 2488 } 2489 2490 if (!baser && !rs) 2491 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC); 2492 2493 if (rs_req) 2494 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS); 2495 2496 if (baser_req) 2497 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER); 2498 2499 return 0; 2500 } 2501 2502 static int 2503 sfc_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 2504 { 2505 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2506 struct sfc_port *port = &sa->port; 2507 struct rte_eth_link current_link; 2508 efx_phy_fec_type_t active_fec; 2509 bool is_25g = false; 2510 int rc = 0; 2511 2512 sfc_adapter_lock(sa); 2513 2514 sfc_dev_get_rte_link(dev, 1, ¤t_link); 2515 2516 if (current_link.link_status == RTE_ETH_LINK_DOWN) { 2517 uint32_t speed = current_link.link_speed; 2518 2519 if (port->fec_auto) { 2520 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO); 2521 goto adapter_unlock; 2522 } 2523 2524 is_25g = (speed == RTE_ETH_SPEED_NUM_25G || 2525 speed == RTE_ETH_SPEED_NUM_50G); 2526 2527 *fec_capa = sfc_efx_caps_to_fec(port->fec_cfg, is_25g); 2528 if (*fec_capa == 0) 2529 rc = ENOTSUP; 2530 2531 goto adapter_unlock; 2532 } 2533 2534 rc = efx_phy_fec_type_get(sa->nic, &active_fec); 2535 if (rc != 0) 2536 goto adapter_unlock; 2537 2538 switch (active_fec) { 2539 case EFX_PHY_FEC_NONE: 2540 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC); 2541 break; 2542 case EFX_PHY_FEC_BASER: 2543 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER); 2544 break; 2545 case EFX_PHY_FEC_RS: 2546 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS); 2547 break; 2548 default: 2549 rc = ENOTSUP; 2550 break; 2551 } 2552 2553 adapter_unlock: 2554 sfc_adapter_unlock(sa); 2555 2556 if (rc != 0) 2557 sfc_err(sa, "failed to get FEC mode"); 2558 2559 SFC_ASSERT(rc >= 0); 2560 return -rc; 2561 } 2562 2563 static int 2564 sfc_fec_capa_check(struct rte_eth_dev *dev, uint32_t fec_capa, 2565 uint32_t supported_caps) 2566 { 2567 struct rte_eth_fec_capa *speed_fec_capa; 2568 struct rte_eth_link current_link; 2569 bool is_supported = false; 2570 unsigned int num_entries; 2571 bool auto_fec = false; 2572 unsigned int i; 2573 2574 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2575 2576 if (sa->state != SFC_ETHDEV_STARTED) 2577 return 0; 2578 2579 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) { 2580 auto_fec = true; 2581 fec_capa &= ~RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO); 2582 } 2583 2584 /* 2585 * If only the AUTO bit is set, the decision on which FEC 2586 * mode to use will be made by HW/FW or driver. 2587 */ 2588 if (auto_fec && fec_capa == 0) 2589 return 0; 2590 2591 sfc_dev_get_rte_link(dev, 1, ¤t_link); 2592 2593 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, NULL); 2594 if (num_entries == 0) 2595 return ENOTSUP; 2596 2597 speed_fec_capa = rte_calloc("fec_capa", num_entries, 2598 sizeof(*speed_fec_capa), 0); 2599 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, 2600 speed_fec_capa); 2601 2602 for (i = 0; i < num_entries; i++) { 2603 if (speed_fec_capa[i].speed == current_link.link_speed) { 2604 if ((fec_capa & speed_fec_capa[i].capa) != 0) 2605 is_supported = true; 2606 2607 break; 2608 } 2609 } 2610 2611 rte_free(speed_fec_capa); 2612 2613 if (is_supported) 2614 return 0; 2615 2616 return ENOTSUP; 2617 } 2618 2619 static int 2620 sfc_fec_capa_to_efx(uint32_t supported_caps, uint32_t fec_capa, 2621 uint32_t *efx_fec_caps) 2622 { 2623 bool fec_is_set = false; 2624 bool auto_fec = false; 2625 bool nofec = false; 2626 uint32_t ret = 0; 2627 2628 if (efx_fec_caps == NULL) 2629 return EINVAL; 2630 2631 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) 2632 auto_fec = true; 2633 2634 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC)) 2635 nofec = true; 2636 2637 if (fec_capa == RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) { 2638 ret |= (EFX_PHY_CAP_FEC_BIT(BASER_FEC) | 2639 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | 2640 EFX_PHY_CAP_FEC_BIT(RS_FEC)) & supported_caps; 2641 goto done; 2642 } 2643 2644 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS)) { 2645 fec_is_set = true; 2646 2647 if (supported_caps & EFX_PHY_CAP_FEC_BIT(RS_FEC)) { 2648 ret |= EFX_PHY_CAP_FEC_BIT(RS_FEC) | 2649 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED); 2650 } 2651 } 2652 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER)) { 2653 if (!auto_fec && fec_is_set) 2654 return EINVAL; 2655 2656 if (supported_caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC)) { 2657 ret |= EFX_PHY_CAP_FEC_BIT(BASER_FEC) | 2658 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED); 2659 } 2660 if (supported_caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC)) { 2661 ret |= EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | 2662 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED); 2663 } 2664 } 2665 2666 if (ret == 0 && !nofec) 2667 return ENOTSUP; 2668 2669 done: 2670 *efx_fec_caps = ret; 2671 return 0; 2672 } 2673 2674 static int 2675 sfc_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 2676 { 2677 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2678 struct sfc_port *port = &sa->port; 2679 uint32_t supported_caps; 2680 uint32_t efx_fec_caps; 2681 uint32_t updated_caps; 2682 int rc = 0; 2683 2684 sfc_adapter_lock(sa); 2685 2686 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &supported_caps); 2687 2688 rc = sfc_fec_capa_check(dev, fec_capa, supported_caps); 2689 if (rc != 0) 2690 goto adapter_unlock; 2691 2692 rc = sfc_fec_capa_to_efx(supported_caps, fec_capa, &efx_fec_caps); 2693 if (rc != 0) 2694 goto adapter_unlock; 2695 2696 if (sa->state == SFC_ETHDEV_STARTED) { 2697 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_CURRENT, 2698 &updated_caps); 2699 updated_caps = updated_caps & ~EFX_PHY_CAP_FEC_MASK; 2700 updated_caps |= efx_fec_caps; 2701 2702 rc = efx_phy_adv_cap_set(sa->nic, updated_caps); 2703 if (rc != 0) 2704 goto adapter_unlock; 2705 } 2706 2707 port->fec_cfg = efx_fec_caps; 2708 /* 2709 * There is no chance to recognize AUTO mode from the 2710 * saved FEC capabilities as AUTO mode can have the same 2711 * set of bits as any other mode from the EFX point of view. 2712 * Save it in the proper variable. 2713 */ 2714 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) 2715 port->fec_auto = true; 2716 else 2717 port->fec_auto = false; 2718 2719 adapter_unlock: 2720 sfc_adapter_unlock(sa); 2721 2722 SFC_ASSERT(rc >= 0); 2723 return -rc; 2724 } 2725 2726 static const struct eth_dev_ops sfc_eth_dev_ops = { 2727 .dev_configure = sfc_dev_configure, 2728 .dev_start = sfc_dev_start, 2729 .dev_stop = sfc_dev_stop, 2730 .dev_set_link_up = sfc_dev_set_link_up, 2731 .dev_set_link_down = sfc_dev_set_link_down, 2732 .dev_close = sfc_dev_close, 2733 .promiscuous_enable = sfc_dev_promisc_enable, 2734 .promiscuous_disable = sfc_dev_promisc_disable, 2735 .allmulticast_enable = sfc_dev_allmulti_enable, 2736 .allmulticast_disable = sfc_dev_allmulti_disable, 2737 .link_update = sfc_dev_link_update, 2738 .stats_get = sfc_stats_get, 2739 .stats_reset = sfc_stats_reset, 2740 .xstats_get = sfc_xstats_get, 2741 .xstats_reset = sfc_stats_reset, 2742 .xstats_get_names = sfc_xstats_get_names, 2743 .dev_infos_get = sfc_dev_infos_get, 2744 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2745 .mtu_set = sfc_dev_set_mtu, 2746 .rx_queue_start = sfc_rx_queue_start, 2747 .rx_queue_stop = sfc_rx_queue_stop, 2748 .tx_queue_start = sfc_tx_queue_start, 2749 .tx_queue_stop = sfc_tx_queue_stop, 2750 .rx_queue_setup = sfc_rx_queue_setup, 2751 .rx_queue_release = sfc_rx_queue_release, 2752 .rx_queue_intr_enable = sfc_rx_queue_intr_enable, 2753 .rx_queue_intr_disable = sfc_rx_queue_intr_disable, 2754 .tx_queue_setup = sfc_tx_queue_setup, 2755 .tx_queue_release = sfc_tx_queue_release, 2756 .flow_ctrl_get = sfc_flow_ctrl_get, 2757 .flow_ctrl_set = sfc_flow_ctrl_set, 2758 .mac_addr_set = sfc_mac_addr_set, 2759 .udp_tunnel_port_add = sfc_dev_udp_tunnel_port_add, 2760 .udp_tunnel_port_del = sfc_dev_udp_tunnel_port_del, 2761 .reta_update = sfc_dev_rss_reta_update, 2762 .reta_query = sfc_dev_rss_reta_query, 2763 .rss_hash_update = sfc_dev_rss_hash_update, 2764 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2765 .flow_ops_get = sfc_dev_flow_ops_get, 2766 .set_mc_addr_list = sfc_set_mc_addr_list, 2767 .rxq_info_get = sfc_rx_queue_info_get, 2768 .txq_info_get = sfc_tx_queue_info_get, 2769 .fw_version_get = sfc_fw_version_get, 2770 .xstats_get_by_id = sfc_xstats_get_by_id, 2771 .xstats_get_names_by_id = sfc_xstats_get_names_by_id, 2772 .pool_ops_supported = sfc_pool_ops_supported, 2773 .representor_info_get = sfc_representor_info_get, 2774 .rx_metadata_negotiate = sfc_rx_metadata_negotiate, 2775 .fec_get_capability = sfc_fec_get_capability, 2776 .fec_get = sfc_fec_get, 2777 .fec_set = sfc_fec_set, 2778 }; 2779 2780 struct sfc_ethdev_init_data { 2781 uint16_t nb_representors; 2782 }; 2783 2784 /** 2785 * Duplicate a string in potentially shared memory required for 2786 * multi-process support. 2787 * 2788 * strdup() allocates from process-local heap/memory. 2789 */ 2790 static char * 2791 sfc_strdup(const char *str) 2792 { 2793 size_t size; 2794 char *copy; 2795 2796 if (str == NULL) 2797 return NULL; 2798 2799 size = strlen(str) + 1; 2800 copy = rte_malloc(__func__, size, 0); 2801 if (copy != NULL) 2802 rte_memcpy(copy, str, size); 2803 2804 return copy; 2805 } 2806 2807 static int 2808 sfc_eth_dev_set_ops(struct rte_eth_dev *dev) 2809 { 2810 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2811 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2812 const struct sfc_dp_rx *dp_rx; 2813 const struct sfc_dp_tx *dp_tx; 2814 const efx_nic_cfg_t *encp; 2815 unsigned int avail_caps = 0; 2816 const char *rx_name = NULL; 2817 const char *tx_name = NULL; 2818 int rc; 2819 2820 switch (sa->family) { 2821 case EFX_FAMILY_HUNTINGTON: 2822 case EFX_FAMILY_MEDFORD: 2823 case EFX_FAMILY_MEDFORD2: 2824 avail_caps |= SFC_DP_HW_FW_CAP_EF10; 2825 avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX; 2826 avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX; 2827 break; 2828 case EFX_FAMILY_RIVERHEAD: 2829 avail_caps |= SFC_DP_HW_FW_CAP_EF100; 2830 break; 2831 default: 2832 break; 2833 } 2834 2835 encp = efx_nic_cfg_get(sa->nic); 2836 if (encp->enc_rx_es_super_buffer_supported) 2837 avail_caps |= SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER; 2838 2839 rc = sfc_kvargs_process(sa, SFC_KVARG_RX_DATAPATH, 2840 sfc_kvarg_string_handler, &rx_name); 2841 if (rc != 0) 2842 goto fail_kvarg_rx_datapath; 2843 2844 if (rx_name != NULL) { 2845 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, rx_name); 2846 if (dp_rx == NULL) { 2847 sfc_err(sa, "Rx datapath %s not found", rx_name); 2848 rc = ENOENT; 2849 goto fail_dp_rx; 2850 } 2851 if (!sfc_dp_match_hw_fw_caps(&dp_rx->dp, avail_caps)) { 2852 sfc_err(sa, 2853 "Insufficient Hw/FW capabilities to use Rx datapath %s", 2854 rx_name); 2855 rc = EINVAL; 2856 goto fail_dp_rx_caps; 2857 } 2858 } else { 2859 dp_rx = sfc_dp_find_rx_by_caps(&sfc_dp_head, avail_caps); 2860 if (dp_rx == NULL) { 2861 sfc_err(sa, "Rx datapath by caps %#x not found", 2862 avail_caps); 2863 rc = ENOENT; 2864 goto fail_dp_rx; 2865 } 2866 } 2867 2868 sas->dp_rx_name = sfc_strdup(dp_rx->dp.name); 2869 if (sas->dp_rx_name == NULL) { 2870 rc = ENOMEM; 2871 goto fail_dp_rx_name; 2872 } 2873 2874 if (strcmp(dp_rx->dp.name, SFC_KVARG_DATAPATH_EF10_ESSB) == 0) { 2875 /* FLAG and MARK are always available from Rx prefix. */ 2876 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_FLAG; 2877 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_MARK; 2878 } 2879 2880 sfc_notice(sa, "use %s Rx datapath", sas->dp_rx_name); 2881 2882 rc = sfc_kvargs_process(sa, SFC_KVARG_TX_DATAPATH, 2883 sfc_kvarg_string_handler, &tx_name); 2884 if (rc != 0) 2885 goto fail_kvarg_tx_datapath; 2886 2887 if (tx_name != NULL) { 2888 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, tx_name); 2889 if (dp_tx == NULL) { 2890 sfc_err(sa, "Tx datapath %s not found", tx_name); 2891 rc = ENOENT; 2892 goto fail_dp_tx; 2893 } 2894 if (!sfc_dp_match_hw_fw_caps(&dp_tx->dp, avail_caps)) { 2895 sfc_err(sa, 2896 "Insufficient Hw/FW capabilities to use Tx datapath %s", 2897 tx_name); 2898 rc = EINVAL; 2899 goto fail_dp_tx_caps; 2900 } 2901 } else { 2902 dp_tx = sfc_dp_find_tx_by_caps(&sfc_dp_head, avail_caps); 2903 if (dp_tx == NULL) { 2904 sfc_err(sa, "Tx datapath by caps %#x not found", 2905 avail_caps); 2906 rc = ENOENT; 2907 goto fail_dp_tx; 2908 } 2909 } 2910 2911 sas->dp_tx_name = sfc_strdup(dp_tx->dp.name); 2912 if (sas->dp_tx_name == NULL) { 2913 rc = ENOMEM; 2914 goto fail_dp_tx_name; 2915 } 2916 2917 sfc_notice(sa, "use %s Tx datapath", sas->dp_tx_name); 2918 2919 sa->priv.dp_rx = dp_rx; 2920 sa->priv.dp_tx = dp_tx; 2921 2922 dev->rx_pkt_burst = dp_rx->pkt_burst; 2923 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2924 dev->tx_pkt_burst = dp_tx->pkt_burst; 2925 2926 dev->rx_queue_count = sfc_rx_queue_count; 2927 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2928 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2929 dev->dev_ops = &sfc_eth_dev_ops; 2930 2931 return 0; 2932 2933 fail_dp_tx_name: 2934 fail_dp_tx_caps: 2935 fail_dp_tx: 2936 fail_kvarg_tx_datapath: 2937 rte_free(sas->dp_rx_name); 2938 sas->dp_rx_name = NULL; 2939 2940 fail_dp_rx_name: 2941 fail_dp_rx_caps: 2942 fail_dp_rx: 2943 fail_kvarg_rx_datapath: 2944 return rc; 2945 } 2946 2947 static void 2948 sfc_eth_dev_clear_ops(struct rte_eth_dev *dev) 2949 { 2950 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2951 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2952 2953 dev->dev_ops = NULL; 2954 dev->tx_pkt_prepare = NULL; 2955 dev->rx_pkt_burst = NULL; 2956 dev->tx_pkt_burst = NULL; 2957 2958 rte_free(sas->dp_tx_name); 2959 sas->dp_tx_name = NULL; 2960 sa->priv.dp_tx = NULL; 2961 2962 rte_free(sas->dp_rx_name); 2963 sas->dp_rx_name = NULL; 2964 sa->priv.dp_rx = NULL; 2965 } 2966 2967 static const struct eth_dev_ops sfc_eth_dev_secondary_ops = { 2968 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2969 .reta_query = sfc_dev_rss_reta_query, 2970 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2971 .rxq_info_get = sfc_rx_queue_info_get, 2972 .txq_info_get = sfc_tx_queue_info_get, 2973 }; 2974 2975 static int 2976 sfc_eth_dev_secondary_init(struct rte_eth_dev *dev, uint32_t logtype_main) 2977 { 2978 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2979 struct sfc_adapter_priv *sap; 2980 const struct sfc_dp_rx *dp_rx; 2981 const struct sfc_dp_tx *dp_tx; 2982 int rc; 2983 2984 /* 2985 * Allocate process private data from heap, since it should not 2986 * be located in shared memory allocated using rte_malloc() API. 2987 */ 2988 sap = calloc(1, sizeof(*sap)); 2989 if (sap == NULL) { 2990 rc = ENOMEM; 2991 goto fail_alloc_priv; 2992 } 2993 2994 sap->logtype_main = logtype_main; 2995 2996 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, sas->dp_rx_name); 2997 if (dp_rx == NULL) { 2998 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2999 "cannot find %s Rx datapath", sas->dp_rx_name); 3000 rc = ENOENT; 3001 goto fail_dp_rx; 3002 } 3003 if (~dp_rx->features & SFC_DP_RX_FEAT_MULTI_PROCESS) { 3004 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3005 "%s Rx datapath does not support multi-process", 3006 sas->dp_rx_name); 3007 rc = EINVAL; 3008 goto fail_dp_rx_multi_process; 3009 } 3010 3011 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, sas->dp_tx_name); 3012 if (dp_tx == NULL) { 3013 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3014 "cannot find %s Tx datapath", sas->dp_tx_name); 3015 rc = ENOENT; 3016 goto fail_dp_tx; 3017 } 3018 if (~dp_tx->features & SFC_DP_TX_FEAT_MULTI_PROCESS) { 3019 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3020 "%s Tx datapath does not support multi-process", 3021 sas->dp_tx_name); 3022 rc = EINVAL; 3023 goto fail_dp_tx_multi_process; 3024 } 3025 3026 sap->dp_rx = dp_rx; 3027 sap->dp_tx = dp_tx; 3028 3029 dev->process_private = sap; 3030 dev->rx_pkt_burst = dp_rx->pkt_burst; 3031 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 3032 dev->tx_pkt_burst = dp_tx->pkt_burst; 3033 dev->rx_queue_count = sfc_rx_queue_count; 3034 dev->rx_descriptor_status = sfc_rx_descriptor_status; 3035 dev->tx_descriptor_status = sfc_tx_descriptor_status; 3036 dev->dev_ops = &sfc_eth_dev_secondary_ops; 3037 3038 return 0; 3039 3040 fail_dp_tx_multi_process: 3041 fail_dp_tx: 3042 fail_dp_rx_multi_process: 3043 fail_dp_rx: 3044 free(sap); 3045 3046 fail_alloc_priv: 3047 return rc; 3048 } 3049 3050 static void 3051 sfc_register_dp(void) 3052 { 3053 /* Register once */ 3054 if (TAILQ_EMPTY(&sfc_dp_head)) { 3055 /* Prefer EF10 datapath */ 3056 sfc_dp_register(&sfc_dp_head, &sfc_ef100_rx.dp); 3057 sfc_dp_register(&sfc_dp_head, &sfc_ef10_essb_rx.dp); 3058 sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp); 3059 sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp); 3060 3061 sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp); 3062 sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp); 3063 sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp); 3064 sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp); 3065 } 3066 } 3067 3068 static int 3069 sfc_parse_switch_mode(struct sfc_adapter *sa, bool has_representors) 3070 { 3071 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 3072 const char *switch_mode = NULL; 3073 int rc; 3074 3075 sfc_log_init(sa, "entry"); 3076 3077 rc = sfc_kvargs_process(sa, SFC_KVARG_SWITCH_MODE, 3078 sfc_kvarg_string_handler, &switch_mode); 3079 if (rc != 0) 3080 goto fail_kvargs; 3081 3082 if (switch_mode == NULL) { 3083 sa->switchdev = encp->enc_mae_admin && 3084 (!encp->enc_datapath_cap_evb || 3085 has_representors); 3086 } else if (strcasecmp(switch_mode, SFC_KVARG_SWITCH_MODE_LEGACY) == 0) { 3087 sa->switchdev = false; 3088 } else if (strcasecmp(switch_mode, 3089 SFC_KVARG_SWITCH_MODE_SWITCHDEV) == 0) { 3090 sa->switchdev = true; 3091 } else { 3092 sfc_err(sa, "invalid switch mode device argument '%s'", 3093 switch_mode); 3094 rc = EINVAL; 3095 goto fail_mode; 3096 } 3097 3098 sfc_log_init(sa, "done"); 3099 3100 return 0; 3101 3102 fail_mode: 3103 fail_kvargs: 3104 sfc_log_init(sa, "failed: %s", rte_strerror(rc)); 3105 3106 return rc; 3107 } 3108 3109 static int 3110 sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params) 3111 { 3112 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 3113 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3114 struct sfc_ethdev_init_data *init_data = init_params; 3115 uint32_t logtype_main; 3116 struct sfc_adapter *sa; 3117 int rc; 3118 const efx_nic_cfg_t *encp; 3119 const struct rte_ether_addr *from; 3120 int ret; 3121 3122 if (sfc_efx_dev_class_get(pci_dev->device.devargs) != 3123 SFC_EFX_DEV_CLASS_NET) { 3124 SFC_GENERIC_LOG(DEBUG, 3125 "Incompatible device class: skip probing, should be probed by other sfc driver."); 3126 return 1; 3127 } 3128 3129 rc = sfc_dp_mport_register(); 3130 if (rc != 0) 3131 return rc; 3132 3133 sfc_register_dp(); 3134 3135 logtype_main = sfc_register_logtype(&pci_dev->addr, 3136 SFC_LOGTYPE_MAIN_STR, 3137 RTE_LOG_NOTICE); 3138 3139 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3140 return -sfc_eth_dev_secondary_init(dev, logtype_main); 3141 3142 /* Required for logging */ 3143 ret = snprintf(sas->log_prefix, sizeof(sas->log_prefix), 3144 "PMD: sfc_efx " PCI_PRI_FMT " #%" PRIu16 ": ", 3145 pci_dev->addr.domain, pci_dev->addr.bus, 3146 pci_dev->addr.devid, pci_dev->addr.function, 3147 dev->data->port_id); 3148 if (ret < 0 || ret >= (int)sizeof(sas->log_prefix)) { 3149 SFC_GENERIC_LOG(ERR, 3150 "reserved log prefix is too short for " PCI_PRI_FMT, 3151 pci_dev->addr.domain, pci_dev->addr.bus, 3152 pci_dev->addr.devid, pci_dev->addr.function); 3153 return -EINVAL; 3154 } 3155 sas->pci_addr = pci_dev->addr; 3156 sas->port_id = dev->data->port_id; 3157 3158 /* 3159 * Allocate process private data from heap, since it should not 3160 * be located in shared memory allocated using rte_malloc() API. 3161 */ 3162 sa = calloc(1, sizeof(*sa)); 3163 if (sa == NULL) { 3164 rc = ENOMEM; 3165 goto fail_alloc_sa; 3166 } 3167 3168 dev->process_private = sa; 3169 3170 /* Required for logging */ 3171 sa->priv.shared = sas; 3172 sa->priv.logtype_main = logtype_main; 3173 3174 sa->eth_dev = dev; 3175 3176 /* Copy PCI device info to the dev->data */ 3177 rte_eth_copy_pci_info(dev, pci_dev); 3178 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3179 3180 rc = sfc_kvargs_parse(sa); 3181 if (rc != 0) 3182 goto fail_kvargs_parse; 3183 3184 sfc_log_init(sa, "entry"); 3185 3186 dev->data->mac_addrs = rte_zmalloc("sfc", RTE_ETHER_ADDR_LEN, 0); 3187 if (dev->data->mac_addrs == NULL) { 3188 rc = ENOMEM; 3189 goto fail_mac_addrs; 3190 } 3191 3192 sfc_adapter_lock_init(sa); 3193 sfc_adapter_lock(sa); 3194 3195 sfc_log_init(sa, "probing"); 3196 rc = sfc_probe(sa); 3197 if (rc != 0) 3198 goto fail_probe; 3199 3200 /* 3201 * Selecting a default switch mode requires the NIC to be probed and 3202 * to have its capabilities filled in. 3203 */ 3204 rc = sfc_parse_switch_mode(sa, init_data->nb_representors > 0); 3205 if (rc != 0) 3206 goto fail_switch_mode; 3207 3208 sfc_log_init(sa, "set device ops"); 3209 rc = sfc_eth_dev_set_ops(dev); 3210 if (rc != 0) 3211 goto fail_set_ops; 3212 3213 sfc_log_init(sa, "attaching"); 3214 rc = sfc_attach(sa); 3215 if (rc != 0) 3216 goto fail_attach; 3217 3218 if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_ADMIN) { 3219 sfc_err(sa, 3220 "failed to enable switchdev mode without admin MAE privilege"); 3221 rc = ENOTSUP; 3222 goto fail_switchdev_no_mae; 3223 } 3224 3225 encp = efx_nic_cfg_get(sa->nic); 3226 3227 /* 3228 * The arguments are really reverse order in comparison to 3229 * Linux kernel. Copy from NIC config to Ethernet device data. 3230 */ 3231 from = (const struct rte_ether_addr *)(encp->enc_mac_addr); 3232 rte_ether_addr_copy(from, &dev->data->mac_addrs[0]); 3233 3234 /* 3235 * Setup the NIC DMA mapping handler. All internal mempools 3236 * MUST be created on attach before this point, and the 3237 * adapter MUST NOT create mempools with the adapter lock 3238 * held after this point. 3239 */ 3240 rc = sfc_nic_dma_attach(sa); 3241 if (rc != 0) 3242 goto fail_nic_dma_attach; 3243 3244 sfc_adapter_unlock(sa); 3245 3246 sfc_log_init(sa, "done"); 3247 return 0; 3248 3249 fail_nic_dma_attach: 3250 fail_switchdev_no_mae: 3251 sfc_detach(sa); 3252 3253 fail_attach: 3254 sfc_eth_dev_clear_ops(dev); 3255 3256 fail_set_ops: 3257 fail_switch_mode: 3258 sfc_unprobe(sa); 3259 3260 fail_probe: 3261 sfc_adapter_unlock(sa); 3262 sfc_adapter_lock_fini(sa); 3263 rte_free(dev->data->mac_addrs); 3264 dev->data->mac_addrs = NULL; 3265 3266 fail_mac_addrs: 3267 sfc_kvargs_cleanup(sa); 3268 3269 fail_kvargs_parse: 3270 sfc_log_init(sa, "failed %d", rc); 3271 dev->process_private = NULL; 3272 free(sa); 3273 3274 fail_alloc_sa: 3275 SFC_ASSERT(rc > 0); 3276 return -rc; 3277 } 3278 3279 static int 3280 sfc_eth_dev_uninit(struct rte_eth_dev *dev) 3281 { 3282 sfc_dev_close(dev); 3283 3284 return 0; 3285 } 3286 3287 static const struct rte_pci_id pci_id_sfc_efx_map[] = { 3288 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE) }, 3289 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE_VF) }, 3290 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT) }, 3291 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT_VF) }, 3292 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD) }, 3293 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) }, 3294 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) }, 3295 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) }, 3296 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) }, 3297 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) }, 3298 { .vendor_id = 0 /* sentinel */ } 3299 }; 3300 3301 static int 3302 sfc_parse_rte_devargs(const char *args, struct rte_eth_devargs *devargs) 3303 { 3304 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 3305 int rc; 3306 3307 if (args != NULL) { 3308 rc = rte_eth_devargs_parse(args, ð_da); 3309 if (rc != 0) { 3310 SFC_GENERIC_LOG(ERR, 3311 "Failed to parse generic devargs '%s'", 3312 args); 3313 return rc; 3314 } 3315 } 3316 3317 *devargs = eth_da; 3318 3319 return 0; 3320 } 3321 3322 static int 3323 sfc_eth_dev_find_or_create(struct rte_pci_device *pci_dev, 3324 struct sfc_ethdev_init_data *init_data, 3325 struct rte_eth_dev **devp, 3326 bool *dev_created) 3327 { 3328 struct rte_eth_dev *dev; 3329 bool created = false; 3330 int rc; 3331 3332 dev = rte_eth_dev_allocated(pci_dev->device.name); 3333 if (dev == NULL) { 3334 rc = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 3335 sizeof(struct sfc_adapter_shared), 3336 eth_dev_pci_specific_init, pci_dev, 3337 sfc_eth_dev_init, init_data); 3338 if (rc != 0) { 3339 SFC_GENERIC_LOG(ERR, "Failed to create sfc ethdev '%s'", 3340 pci_dev->device.name); 3341 return rc; 3342 } 3343 3344 created = true; 3345 3346 dev = rte_eth_dev_allocated(pci_dev->device.name); 3347 if (dev == NULL) { 3348 SFC_GENERIC_LOG(ERR, 3349 "Failed to find allocated sfc ethdev '%s'", 3350 pci_dev->device.name); 3351 return -ENODEV; 3352 } 3353 } 3354 3355 *devp = dev; 3356 *dev_created = created; 3357 3358 return 0; 3359 } 3360 3361 static int 3362 sfc_eth_dev_create_repr(struct sfc_adapter *sa, 3363 efx_pcie_interface_t controller, 3364 uint16_t port, 3365 uint16_t repr_port, 3366 enum rte_eth_representor_type type) 3367 { 3368 struct sfc_repr_entity_info entity; 3369 efx_mport_sel_t mport_sel; 3370 int rc; 3371 3372 switch (type) { 3373 case RTE_ETH_REPRESENTOR_NONE: 3374 return 0; 3375 case RTE_ETH_REPRESENTOR_VF: 3376 case RTE_ETH_REPRESENTOR_PF: 3377 break; 3378 case RTE_ETH_REPRESENTOR_SF: 3379 sfc_err(sa, "SF representors are not supported"); 3380 return ENOTSUP; 3381 default: 3382 sfc_err(sa, "unknown representor type: %d", type); 3383 return ENOTSUP; 3384 } 3385 3386 rc = efx_mae_mport_by_pcie_mh_function(controller, 3387 port, 3388 repr_port, 3389 &mport_sel); 3390 if (rc != 0) { 3391 sfc_err(sa, 3392 "failed to get m-port selector for controller %u port %u repr_port %u: %s", 3393 controller, port, repr_port, rte_strerror(-rc)); 3394 return rc; 3395 } 3396 3397 memset(&entity, 0, sizeof(entity)); 3398 entity.type = type; 3399 entity.intf = controller; 3400 entity.pf = port; 3401 entity.vf = repr_port; 3402 3403 rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id, 3404 &mport_sel); 3405 if (rc != 0) { 3406 sfc_err(sa, 3407 "failed to create representor for controller %u port %u repr_port %u: %s", 3408 controller, port, repr_port, rte_strerror(-rc)); 3409 return rc; 3410 } 3411 3412 return 0; 3413 } 3414 3415 static int 3416 sfc_eth_dev_create_repr_port(struct sfc_adapter *sa, 3417 const struct rte_eth_devargs *eth_da, 3418 efx_pcie_interface_t controller, 3419 uint16_t port) 3420 { 3421 int first_error = 0; 3422 uint16_t i; 3423 int rc; 3424 3425 if (eth_da->type == RTE_ETH_REPRESENTOR_PF) { 3426 return sfc_eth_dev_create_repr(sa, controller, port, 3427 EFX_PCI_VF_INVALID, 3428 eth_da->type); 3429 } 3430 3431 for (i = 0; i < eth_da->nb_representor_ports; i++) { 3432 rc = sfc_eth_dev_create_repr(sa, controller, port, 3433 eth_da->representor_ports[i], 3434 eth_da->type); 3435 if (rc != 0 && first_error == 0) 3436 first_error = rc; 3437 } 3438 3439 return first_error; 3440 } 3441 3442 static int 3443 sfc_eth_dev_create_repr_controller(struct sfc_adapter *sa, 3444 const struct rte_eth_devargs *eth_da, 3445 efx_pcie_interface_t controller) 3446 { 3447 const efx_nic_cfg_t *encp; 3448 int first_error = 0; 3449 uint16_t default_port; 3450 uint16_t i; 3451 int rc; 3452 3453 if (eth_da->nb_ports == 0) { 3454 encp = efx_nic_cfg_get(sa->nic); 3455 default_port = encp->enc_intf == controller ? encp->enc_pf : 0; 3456 return sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3457 default_port); 3458 } 3459 3460 for (i = 0; i < eth_da->nb_ports; i++) { 3461 rc = sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3462 eth_da->ports[i]); 3463 if (rc != 0 && first_error == 0) 3464 first_error = rc; 3465 } 3466 3467 return first_error; 3468 } 3469 3470 static int 3471 sfc_eth_dev_create_representors(struct rte_eth_dev *dev, 3472 const struct rte_eth_devargs *eth_da) 3473 { 3474 efx_pcie_interface_t intf; 3475 const efx_nic_cfg_t *encp; 3476 struct sfc_adapter *sa; 3477 uint16_t switch_domain_id; 3478 uint16_t i; 3479 int rc; 3480 3481 sa = sfc_adapter_by_eth_dev(dev); 3482 switch_domain_id = sa->mae.switch_domain_id; 3483 3484 switch (eth_da->type) { 3485 case RTE_ETH_REPRESENTOR_NONE: 3486 return 0; 3487 case RTE_ETH_REPRESENTOR_PF: 3488 case RTE_ETH_REPRESENTOR_VF: 3489 break; 3490 case RTE_ETH_REPRESENTOR_SF: 3491 sfc_err(sa, "SF representors are not supported"); 3492 return -ENOTSUP; 3493 default: 3494 sfc_err(sa, "unknown representor type: %d", 3495 eth_da->type); 3496 return -ENOTSUP; 3497 } 3498 3499 if (!sa->switchdev) { 3500 sfc_err(sa, "cannot create representors in non-switchdev mode"); 3501 return -EINVAL; 3502 } 3503 3504 if (!sfc_repr_available(sfc_sa2shared(sa))) { 3505 sfc_err(sa, "cannot create representors: unsupported"); 3506 3507 return -ENOTSUP; 3508 } 3509 3510 /* 3511 * This is needed to construct the DPDK controller -> EFX interface 3512 * mapping. 3513 */ 3514 sfc_adapter_lock(sa); 3515 rc = sfc_process_mport_journal(sa); 3516 sfc_adapter_unlock(sa); 3517 if (rc != 0) { 3518 SFC_ASSERT(rc > 0); 3519 return -rc; 3520 } 3521 3522 if (eth_da->nb_mh_controllers > 0) { 3523 for (i = 0; i < eth_da->nb_mh_controllers; i++) { 3524 rc = sfc_mae_switch_domain_get_intf(switch_domain_id, 3525 eth_da->mh_controllers[i], 3526 &intf); 3527 if (rc != 0) { 3528 sfc_err(sa, "failed to get representor"); 3529 continue; 3530 } 3531 sfc_eth_dev_create_repr_controller(sa, eth_da, intf); 3532 } 3533 } else { 3534 encp = efx_nic_cfg_get(sa->nic); 3535 sfc_eth_dev_create_repr_controller(sa, eth_da, encp->enc_intf); 3536 } 3537 3538 return 0; 3539 } 3540 3541 static int sfc_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3542 struct rte_pci_device *pci_dev) 3543 { 3544 struct sfc_ethdev_init_data init_data; 3545 struct rte_eth_devargs eth_da; 3546 struct rte_eth_dev *dev; 3547 bool dev_created; 3548 int rc; 3549 3550 if (pci_dev->device.devargs != NULL) { 3551 rc = sfc_parse_rte_devargs(pci_dev->device.devargs->args, 3552 ð_da); 3553 if (rc != 0) 3554 return rc; 3555 } else { 3556 memset(ð_da, 0, sizeof(eth_da)); 3557 } 3558 3559 /* If no VF representors specified, check for PF ones */ 3560 if (eth_da.nb_representor_ports > 0) 3561 init_data.nb_representors = eth_da.nb_representor_ports; 3562 else 3563 init_data.nb_representors = eth_da.nb_ports; 3564 3565 if (init_data.nb_representors > 0 && 3566 rte_eal_process_type() != RTE_PROC_PRIMARY) { 3567 SFC_GENERIC_LOG(ERR, 3568 "Create representors from secondary process not supported, dev '%s'", 3569 pci_dev->device.name); 3570 return -ENOTSUP; 3571 } 3572 3573 /* 3574 * Driver supports RTE_PCI_DRV_PROBE_AGAIN. Hence create device only 3575 * if it does not already exist. Re-probing an existing device is 3576 * expected to allow additional representors to be configured. 3577 */ 3578 rc = sfc_eth_dev_find_or_create(pci_dev, &init_data, &dev, 3579 &dev_created); 3580 if (rc != 0) 3581 return rc; 3582 3583 rc = sfc_eth_dev_create_representors(dev, ð_da); 3584 if (rc != 0) { 3585 if (dev_created) 3586 (void)rte_eth_dev_destroy(dev, sfc_eth_dev_uninit); 3587 3588 return rc; 3589 } 3590 3591 return 0; 3592 } 3593 3594 static int sfc_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3595 { 3596 return rte_eth_dev_pci_generic_remove(pci_dev, sfc_eth_dev_uninit); 3597 } 3598 3599 static struct rte_pci_driver sfc_efx_pmd = { 3600 .id_table = pci_id_sfc_efx_map, 3601 .drv_flags = 3602 RTE_PCI_DRV_INTR_LSC | 3603 RTE_PCI_DRV_NEED_MAPPING | 3604 RTE_PCI_DRV_PROBE_AGAIN, 3605 .probe = sfc_eth_dev_pci_probe, 3606 .remove = sfc_eth_dev_pci_remove, 3607 }; 3608 3609 RTE_PMD_REGISTER_PCI(net_sfc_efx, sfc_efx_pmd); 3610 RTE_PMD_REGISTER_PCI_TABLE(net_sfc_efx, pci_id_sfc_efx_map); 3611 RTE_PMD_REGISTER_KMOD_DEP(net_sfc_efx, "* igb_uio | uio_pci_generic | vfio-pci"); 3612 RTE_PMD_REGISTER_PARAM_STRING(net_sfc_efx, 3613 SFC_KVARG_SWITCH_MODE "=" SFC_KVARG_VALUES_SWITCH_MODE " " 3614 SFC_KVARG_RX_DATAPATH "=" SFC_KVARG_VALUES_RX_DATAPATH " " 3615 SFC_KVARG_TX_DATAPATH "=" SFC_KVARG_VALUES_TX_DATAPATH " " 3616 SFC_KVARG_PERF_PROFILE "=" SFC_KVARG_VALUES_PERF_PROFILE " " 3617 SFC_KVARG_FW_VARIANT "=" SFC_KVARG_VALUES_FW_VARIANT " " 3618 SFC_KVARG_RXD_WAIT_TIMEOUT_NS "=<long> " 3619 SFC_KVARG_STATS_UPDATE_PERIOD_MS "=<long>"); 3620 3621 RTE_INIT(sfc_driver_register_logtype) 3622 { 3623 int ret; 3624 3625 ret = rte_log_register_type_and_pick_level(SFC_LOGTYPE_PREFIX "driver", 3626 RTE_LOG_NOTICE); 3627 sfc_logtype_driver = (ret < 0) ? RTE_LOGTYPE_EAL : ret; 3628 } 3629