1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_dev.h> 11 #include <ethdev_driver.h> 12 #include <ethdev_pci.h> 13 #include <rte_pci.h> 14 #include <rte_bus_pci.h> 15 #include <rte_errno.h> 16 #include <rte_string_fns.h> 17 #include <rte_ether.h> 18 19 #include "efx.h" 20 21 #include "sfc.h" 22 #include "sfc_debug.h" 23 #include "sfc_log.h" 24 #include "sfc_kvargs.h" 25 #include "sfc_ev.h" 26 #include "sfc_rx.h" 27 #include "sfc_tx.h" 28 #include "sfc_flow.h" 29 #include "sfc_flow_tunnel.h" 30 #include "sfc_dp.h" 31 #include "sfc_dp_rx.h" 32 #include "sfc_repr.h" 33 #include "sfc_sw_stats.h" 34 #include "sfc_switch.h" 35 36 #define SFC_XSTAT_ID_INVALID_VAL UINT64_MAX 37 #define SFC_XSTAT_ID_INVALID_NAME '\0' 38 39 uint32_t sfc_logtype_driver; 40 41 static struct sfc_dp_list sfc_dp_head = 42 TAILQ_HEAD_INITIALIZER(sfc_dp_head); 43 44 45 static void sfc_eth_dev_clear_ops(struct rte_eth_dev *dev); 46 47 48 static int 49 sfc_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 50 { 51 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 52 efx_nic_fw_info_t enfi; 53 int ret; 54 int rc; 55 56 rc = efx_nic_get_fw_version(sa->nic, &enfi); 57 if (rc != 0) 58 return -rc; 59 60 ret = snprintf(fw_version, fw_size, 61 "%" PRIu16 ".%" PRIu16 ".%" PRIu16 ".%" PRIu16, 62 enfi.enfi_mc_fw_version[0], enfi.enfi_mc_fw_version[1], 63 enfi.enfi_mc_fw_version[2], enfi.enfi_mc_fw_version[3]); 64 if (ret < 0) 65 return ret; 66 67 if (enfi.enfi_dpcpu_fw_ids_valid) { 68 size_t dpcpu_fw_ids_offset = MIN(fw_size - 1, (size_t)ret); 69 int ret_extra; 70 71 ret_extra = snprintf(fw_version + dpcpu_fw_ids_offset, 72 fw_size - dpcpu_fw_ids_offset, 73 " rx%" PRIx16 " tx%" PRIx16, 74 enfi.enfi_rx_dpcpu_fw_id, 75 enfi.enfi_tx_dpcpu_fw_id); 76 if (ret_extra < 0) 77 return ret_extra; 78 79 ret += ret_extra; 80 } 81 82 if (fw_size < (size_t)(++ret)) 83 return ret; 84 else 85 return 0; 86 } 87 88 static int 89 sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 90 { 91 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 92 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 93 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 94 struct sfc_rss *rss = &sas->rss; 95 struct sfc_mae *mae = &sa->mae; 96 uint64_t txq_offloads_def = 0; 97 98 sfc_log_init(sa, "entry"); 99 100 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 101 dev_info->max_mtu = EFX_MAC_SDU_MAX; 102 103 dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX; 104 105 dev_info->max_vfs = sa->sriov.num_vfs; 106 107 /* Autonegotiation may be disabled */ 108 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 109 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX)) 110 dev_info->speed_capa |= ETH_LINK_SPEED_1G; 111 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX)) 112 dev_info->speed_capa |= ETH_LINK_SPEED_10G; 113 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX)) 114 dev_info->speed_capa |= ETH_LINK_SPEED_25G; 115 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX)) 116 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 117 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX)) 118 dev_info->speed_capa |= ETH_LINK_SPEED_50G; 119 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX)) 120 dev_info->speed_capa |= ETH_LINK_SPEED_100G; 121 122 dev_info->max_rx_queues = sa->rxq_max; 123 dev_info->max_tx_queues = sa->txq_max; 124 125 /* By default packets are dropped if no descriptors are available */ 126 dev_info->default_rxconf.rx_drop_en = 1; 127 128 dev_info->rx_queue_offload_capa = sfc_rx_get_queue_offload_caps(sa); 129 130 /* 131 * rx_offload_capa includes both device and queue offloads since 132 * the latter may be requested on a per device basis which makes 133 * sense when some offloads are needed to be set on all queues. 134 */ 135 dev_info->rx_offload_capa = sfc_rx_get_dev_offload_caps(sa) | 136 dev_info->rx_queue_offload_capa; 137 138 dev_info->tx_queue_offload_capa = sfc_tx_get_queue_offload_caps(sa); 139 140 /* 141 * tx_offload_capa includes both device and queue offloads since 142 * the latter may be requested on a per device basis which makes 143 * sense when some offloads are needed to be set on all queues. 144 */ 145 dev_info->tx_offload_capa = sfc_tx_get_dev_offload_caps(sa) | 146 dev_info->tx_queue_offload_capa; 147 148 if (dev_info->tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 149 txq_offloads_def |= DEV_TX_OFFLOAD_MBUF_FAST_FREE; 150 151 dev_info->default_txconf.offloads |= txq_offloads_def; 152 153 if (rss->context_type != EFX_RX_SCALE_UNAVAILABLE) { 154 uint64_t rte_hf = 0; 155 unsigned int i; 156 157 for (i = 0; i < rss->hf_map_nb_entries; ++i) 158 rte_hf |= rss->hf_map[i].rte; 159 160 dev_info->reta_size = EFX_RSS_TBL_SIZE; 161 dev_info->hash_key_size = EFX_RSS_KEY_SIZE; 162 dev_info->flow_type_rss_offloads = rte_hf; 163 } 164 165 /* Initialize to hardware limits */ 166 dev_info->rx_desc_lim.nb_max = sa->rxq_max_entries; 167 dev_info->rx_desc_lim.nb_min = sa->rxq_min_entries; 168 /* The RXQ hardware requires that the descriptor count is a power 169 * of 2, but rx_desc_lim cannot properly describe that constraint. 170 */ 171 dev_info->rx_desc_lim.nb_align = sa->rxq_min_entries; 172 173 /* Initialize to hardware limits */ 174 dev_info->tx_desc_lim.nb_max = sa->txq_max_entries; 175 dev_info->tx_desc_lim.nb_min = sa->txq_min_entries; 176 /* 177 * The TXQ hardware requires that the descriptor count is a power 178 * of 2, but tx_desc_lim cannot properly describe that constraint 179 */ 180 dev_info->tx_desc_lim.nb_align = sa->txq_min_entries; 181 182 if (sap->dp_rx->get_dev_info != NULL) 183 sap->dp_rx->get_dev_info(dev_info); 184 if (sap->dp_tx->get_dev_info != NULL) 185 sap->dp_tx->get_dev_info(dev_info); 186 187 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 188 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 189 190 if (mae->status == SFC_MAE_STATUS_SUPPORTED) { 191 dev_info->switch_info.name = dev->device->driver->name; 192 dev_info->switch_info.domain_id = mae->switch_domain_id; 193 dev_info->switch_info.port_id = mae->switch_port_id; 194 } 195 196 return 0; 197 } 198 199 static const uint32_t * 200 sfc_dev_supported_ptypes_get(struct rte_eth_dev *dev) 201 { 202 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 203 204 return sap->dp_rx->supported_ptypes_get(sap->shared->tunnel_encaps); 205 } 206 207 static int 208 sfc_dev_configure(struct rte_eth_dev *dev) 209 { 210 struct rte_eth_dev_data *dev_data = dev->data; 211 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 212 int rc; 213 214 sfc_log_init(sa, "entry n_rxq=%u n_txq=%u", 215 dev_data->nb_rx_queues, dev_data->nb_tx_queues); 216 217 sfc_adapter_lock(sa); 218 switch (sa->state) { 219 case SFC_ETHDEV_CONFIGURED: 220 /* FALLTHROUGH */ 221 case SFC_ETHDEV_INITIALIZED: 222 rc = sfc_configure(sa); 223 break; 224 default: 225 sfc_err(sa, "unexpected adapter state %u to configure", 226 sa->state); 227 rc = EINVAL; 228 break; 229 } 230 sfc_adapter_unlock(sa); 231 232 sfc_log_init(sa, "done %d", rc); 233 SFC_ASSERT(rc >= 0); 234 return -rc; 235 } 236 237 static int 238 sfc_dev_start(struct rte_eth_dev *dev) 239 { 240 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 241 int rc; 242 243 sfc_log_init(sa, "entry"); 244 245 sfc_adapter_lock(sa); 246 rc = sfc_start(sa); 247 sfc_adapter_unlock(sa); 248 249 sfc_log_init(sa, "done %d", rc); 250 SFC_ASSERT(rc >= 0); 251 return -rc; 252 } 253 254 static int 255 sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 256 { 257 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 258 struct rte_eth_link current_link; 259 int ret; 260 261 sfc_log_init(sa, "entry"); 262 263 if (sa->state != SFC_ETHDEV_STARTED) { 264 sfc_port_link_mode_to_info(EFX_LINK_UNKNOWN, ¤t_link); 265 } else if (wait_to_complete) { 266 efx_link_mode_t link_mode; 267 268 if (efx_port_poll(sa->nic, &link_mode) != 0) 269 link_mode = EFX_LINK_UNKNOWN; 270 sfc_port_link_mode_to_info(link_mode, ¤t_link); 271 272 } else { 273 sfc_ev_mgmt_qpoll(sa); 274 rte_eth_linkstatus_get(dev, ¤t_link); 275 } 276 277 ret = rte_eth_linkstatus_set(dev, ¤t_link); 278 if (ret == 0) 279 sfc_notice(sa, "Link status is %s", 280 current_link.link_status ? "UP" : "DOWN"); 281 282 return ret; 283 } 284 285 static int 286 sfc_dev_stop(struct rte_eth_dev *dev) 287 { 288 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 289 290 sfc_log_init(sa, "entry"); 291 292 sfc_adapter_lock(sa); 293 sfc_stop(sa); 294 sfc_adapter_unlock(sa); 295 296 sfc_log_init(sa, "done"); 297 298 return 0; 299 } 300 301 static int 302 sfc_dev_set_link_up(struct rte_eth_dev *dev) 303 { 304 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 305 int rc; 306 307 sfc_log_init(sa, "entry"); 308 309 sfc_adapter_lock(sa); 310 rc = sfc_start(sa); 311 sfc_adapter_unlock(sa); 312 313 SFC_ASSERT(rc >= 0); 314 return -rc; 315 } 316 317 static int 318 sfc_dev_set_link_down(struct rte_eth_dev *dev) 319 { 320 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 321 322 sfc_log_init(sa, "entry"); 323 324 sfc_adapter_lock(sa); 325 sfc_stop(sa); 326 sfc_adapter_unlock(sa); 327 328 return 0; 329 } 330 331 static void 332 sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev) 333 { 334 free(dev->process_private); 335 rte_eth_dev_release_port(dev); 336 } 337 338 static int 339 sfc_dev_close(struct rte_eth_dev *dev) 340 { 341 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 342 343 sfc_log_init(sa, "entry"); 344 345 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 346 sfc_eth_dev_secondary_clear_ops(dev); 347 return 0; 348 } 349 350 sfc_pre_detach(sa); 351 352 sfc_adapter_lock(sa); 353 switch (sa->state) { 354 case SFC_ETHDEV_STARTED: 355 sfc_stop(sa); 356 SFC_ASSERT(sa->state == SFC_ETHDEV_CONFIGURED); 357 /* FALLTHROUGH */ 358 case SFC_ETHDEV_CONFIGURED: 359 sfc_close(sa); 360 SFC_ASSERT(sa->state == SFC_ETHDEV_INITIALIZED); 361 /* FALLTHROUGH */ 362 case SFC_ETHDEV_INITIALIZED: 363 break; 364 default: 365 sfc_err(sa, "unexpected adapter state %u on close", sa->state); 366 break; 367 } 368 369 /* 370 * Cleanup all resources. 371 * Rollback primary process sfc_eth_dev_init() below. 372 */ 373 374 sfc_eth_dev_clear_ops(dev); 375 376 sfc_detach(sa); 377 sfc_unprobe(sa); 378 379 sfc_kvargs_cleanup(sa); 380 381 sfc_adapter_unlock(sa); 382 sfc_adapter_lock_fini(sa); 383 384 sfc_log_init(sa, "done"); 385 386 /* Required for logging, so cleanup last */ 387 sa->eth_dev = NULL; 388 389 free(sa); 390 391 return 0; 392 } 393 394 static int 395 sfc_dev_filter_set(struct rte_eth_dev *dev, enum sfc_dev_filter_mode mode, 396 boolean_t enabled) 397 { 398 struct sfc_port *port; 399 boolean_t *toggle; 400 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 401 boolean_t allmulti = (mode == SFC_DEV_FILTER_MODE_ALLMULTI); 402 const char *desc = (allmulti) ? "all-multi" : "promiscuous"; 403 int rc = 0; 404 405 sfc_adapter_lock(sa); 406 407 port = &sa->port; 408 toggle = (allmulti) ? (&port->allmulti) : (&port->promisc); 409 410 if (*toggle != enabled) { 411 *toggle = enabled; 412 413 if (sfc_sa2shared(sa)->isolated) { 414 sfc_warn(sa, "isolated mode is active on the port"); 415 sfc_warn(sa, "the change is to be applied on the next " 416 "start provided that isolated mode is " 417 "disabled prior the next start"); 418 } else if ((sa->state == SFC_ETHDEV_STARTED) && 419 ((rc = sfc_set_rx_mode(sa)) != 0)) { 420 *toggle = !(enabled); 421 sfc_warn(sa, "Failed to %s %s mode, rc = %d", 422 ((enabled) ? "enable" : "disable"), desc, rc); 423 424 /* 425 * For promiscuous and all-multicast filters a 426 * permission failure should be reported as an 427 * unsupported filter. 428 */ 429 if (rc == EPERM) 430 rc = ENOTSUP; 431 } 432 } 433 434 sfc_adapter_unlock(sa); 435 return rc; 436 } 437 438 static int 439 sfc_dev_promisc_enable(struct rte_eth_dev *dev) 440 { 441 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_TRUE); 442 443 SFC_ASSERT(rc >= 0); 444 return -rc; 445 } 446 447 static int 448 sfc_dev_promisc_disable(struct rte_eth_dev *dev) 449 { 450 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_FALSE); 451 452 SFC_ASSERT(rc >= 0); 453 return -rc; 454 } 455 456 static int 457 sfc_dev_allmulti_enable(struct rte_eth_dev *dev) 458 { 459 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_TRUE); 460 461 SFC_ASSERT(rc >= 0); 462 return -rc; 463 } 464 465 static int 466 sfc_dev_allmulti_disable(struct rte_eth_dev *dev) 467 { 468 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_FALSE); 469 470 SFC_ASSERT(rc >= 0); 471 return -rc; 472 } 473 474 static int 475 sfc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 476 uint16_t nb_rx_desc, unsigned int socket_id, 477 const struct rte_eth_rxconf *rx_conf, 478 struct rte_mempool *mb_pool) 479 { 480 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 481 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 482 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 483 struct sfc_rxq_info *rxq_info; 484 sfc_sw_index_t sw_index; 485 int rc; 486 487 sfc_log_init(sa, "RxQ=%u nb_rx_desc=%u socket_id=%u", 488 ethdev_qid, nb_rx_desc, socket_id); 489 490 sfc_adapter_lock(sa); 491 492 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 493 rc = sfc_rx_qinit(sa, sw_index, nb_rx_desc, socket_id, 494 rx_conf, mb_pool); 495 if (rc != 0) 496 goto fail_rx_qinit; 497 498 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 499 dev->data->rx_queues[ethdev_qid] = rxq_info->dp; 500 501 sfc_adapter_unlock(sa); 502 503 return 0; 504 505 fail_rx_qinit: 506 sfc_adapter_unlock(sa); 507 SFC_ASSERT(rc > 0); 508 return -rc; 509 } 510 511 static void 512 sfc_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 513 { 514 struct sfc_dp_rxq *dp_rxq = dev->data->rx_queues[qid]; 515 struct sfc_rxq *rxq; 516 struct sfc_adapter *sa; 517 sfc_sw_index_t sw_index; 518 519 if (dp_rxq == NULL) 520 return; 521 522 rxq = sfc_rxq_by_dp_rxq(dp_rxq); 523 sa = rxq->evq->sa; 524 sfc_adapter_lock(sa); 525 526 sw_index = dp_rxq->dpq.queue_id; 527 528 sfc_log_init(sa, "RxQ=%u", sw_index); 529 530 sfc_rx_qfini(sa, sw_index); 531 532 sfc_adapter_unlock(sa); 533 } 534 535 static int 536 sfc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 537 uint16_t nb_tx_desc, unsigned int socket_id, 538 const struct rte_eth_txconf *tx_conf) 539 { 540 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 541 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 542 struct sfc_txq_info *txq_info; 543 sfc_sw_index_t sw_index; 544 int rc; 545 546 sfc_log_init(sa, "TxQ = %u, nb_tx_desc = %u, socket_id = %u", 547 ethdev_qid, nb_tx_desc, socket_id); 548 549 sfc_adapter_lock(sa); 550 551 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 552 rc = sfc_tx_qinit(sa, sw_index, nb_tx_desc, socket_id, tx_conf); 553 if (rc != 0) 554 goto fail_tx_qinit; 555 556 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 557 dev->data->tx_queues[ethdev_qid] = txq_info->dp; 558 559 sfc_adapter_unlock(sa); 560 return 0; 561 562 fail_tx_qinit: 563 sfc_adapter_unlock(sa); 564 SFC_ASSERT(rc > 0); 565 return -rc; 566 } 567 568 static void 569 sfc_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 570 { 571 struct sfc_dp_txq *dp_txq = dev->data->tx_queues[qid]; 572 struct sfc_txq *txq; 573 sfc_sw_index_t sw_index; 574 struct sfc_adapter *sa; 575 576 if (dp_txq == NULL) 577 return; 578 579 txq = sfc_txq_by_dp_txq(dp_txq); 580 sw_index = dp_txq->dpq.queue_id; 581 582 SFC_ASSERT(txq->evq != NULL); 583 sa = txq->evq->sa; 584 585 sfc_log_init(sa, "TxQ = %u", sw_index); 586 587 sfc_adapter_lock(sa); 588 589 sfc_tx_qfini(sa, sw_index); 590 591 sfc_adapter_unlock(sa); 592 } 593 594 static void 595 sfc_stats_get_dp_rx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 596 { 597 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 598 uint64_t pkts_sum = 0; 599 uint64_t bytes_sum = 0; 600 unsigned int i; 601 602 for (i = 0; i < sas->ethdev_rxq_count; ++i) { 603 struct sfc_rxq_info *rxq_info; 604 605 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, i); 606 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 607 union sfc_pkts_bytes qstats; 608 609 sfc_pkts_bytes_get(&rxq_info->dp->dpq.stats, &qstats); 610 pkts_sum += qstats.pkts - 611 sa->sw_stats.reset_rx_pkts[i]; 612 bytes_sum += qstats.bytes - 613 sa->sw_stats.reset_rx_bytes[i]; 614 } 615 } 616 617 *pkts = pkts_sum; 618 *bytes = bytes_sum; 619 } 620 621 static void 622 sfc_stats_get_dp_tx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 623 { 624 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 625 uint64_t pkts_sum = 0; 626 uint64_t bytes_sum = 0; 627 unsigned int i; 628 629 for (i = 0; i < sas->ethdev_txq_count; ++i) { 630 struct sfc_txq_info *txq_info; 631 632 txq_info = sfc_txq_info_by_ethdev_qid(sas, i); 633 if (txq_info->state & SFC_TXQ_INITIALIZED) { 634 union sfc_pkts_bytes qstats; 635 636 sfc_pkts_bytes_get(&txq_info->dp->dpq.stats, &qstats); 637 pkts_sum += qstats.pkts - 638 sa->sw_stats.reset_tx_pkts[i]; 639 bytes_sum += qstats.bytes - 640 sa->sw_stats.reset_tx_bytes[i]; 641 } 642 } 643 644 *pkts = pkts_sum; 645 *bytes = bytes_sum; 646 } 647 648 /* 649 * Some statistics are computed as A - B where A and B each increase 650 * monotonically with some hardware counter(s) and the counters are read 651 * asynchronously. 652 * 653 * If packet X is counted in A, but not counted in B yet, computed value is 654 * greater than real. 655 * 656 * If packet X is not counted in A at the moment of reading the counter, 657 * but counted in B at the moment of reading the counter, computed value 658 * is less than real. 659 * 660 * However, counter which grows backward is worse evil than slightly wrong 661 * value. So, let's try to guarantee that it never happens except may be 662 * the case when the MAC stats are zeroed as a result of a NIC reset. 663 */ 664 static void 665 sfc_update_diff_stat(uint64_t *stat, uint64_t newval) 666 { 667 if ((int64_t)(newval - *stat) > 0 || newval == 0) 668 *stat = newval; 669 } 670 671 static int 672 sfc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 673 { 674 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 675 bool have_dp_rx_stats = sap->dp_rx->features & SFC_DP_RX_FEAT_STATS; 676 bool have_dp_tx_stats = sap->dp_tx->features & SFC_DP_TX_FEAT_STATS; 677 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 678 struct sfc_port *port = &sa->port; 679 uint64_t *mac_stats; 680 int ret; 681 682 sfc_adapter_lock(sa); 683 684 if (have_dp_rx_stats) 685 sfc_stats_get_dp_rx(sa, &stats->ipackets, &stats->ibytes); 686 if (have_dp_tx_stats) 687 sfc_stats_get_dp_tx(sa, &stats->opackets, &stats->obytes); 688 689 ret = sfc_port_update_mac_stats(sa, B_FALSE); 690 if (ret != 0) 691 goto unlock; 692 693 mac_stats = port->mac_stats_buf; 694 695 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, 696 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS)) { 697 if (!have_dp_rx_stats) { 698 stats->ipackets = 699 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS] + 700 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS] + 701 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]; 702 stats->ibytes = 703 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_BYTES] + 704 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES] + 705 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]; 706 707 /* CRC is included in these stats, but shouldn't be */ 708 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 709 } 710 if (!have_dp_tx_stats) { 711 stats->opackets = 712 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS] + 713 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS] + 714 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]; 715 stats->obytes = 716 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_BYTES] + 717 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES] + 718 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]; 719 720 /* CRC is included in these stats, but shouldn't be */ 721 stats->obytes -= stats->opackets * RTE_ETHER_CRC_LEN; 722 } 723 stats->imissed = mac_stats[EFX_MAC_VADAPTER_RX_BAD_PACKETS]; 724 stats->oerrors = mac_stats[EFX_MAC_VADAPTER_TX_BAD_PACKETS]; 725 } else { 726 if (!have_dp_tx_stats) { 727 stats->opackets = mac_stats[EFX_MAC_TX_PKTS]; 728 stats->obytes = mac_stats[EFX_MAC_TX_OCTETS] - 729 mac_stats[EFX_MAC_TX_PKTS] * RTE_ETHER_CRC_LEN; 730 } 731 732 /* 733 * Take into account stats which are whenever supported 734 * on EF10. If some stat is not supported by current 735 * firmware variant or HW revision, it is guaranteed 736 * to be zero in mac_stats. 737 */ 738 stats->imissed = 739 mac_stats[EFX_MAC_RX_NODESC_DROP_CNT] + 740 mac_stats[EFX_MAC_PM_TRUNC_BB_OVERFLOW] + 741 mac_stats[EFX_MAC_PM_DISCARD_BB_OVERFLOW] + 742 mac_stats[EFX_MAC_PM_TRUNC_VFIFO_FULL] + 743 mac_stats[EFX_MAC_PM_DISCARD_VFIFO_FULL] + 744 mac_stats[EFX_MAC_PM_TRUNC_QBB] + 745 mac_stats[EFX_MAC_PM_DISCARD_QBB] + 746 mac_stats[EFX_MAC_PM_DISCARD_MAPPING] + 747 mac_stats[EFX_MAC_RXDP_Q_DISABLED_PKTS] + 748 mac_stats[EFX_MAC_RXDP_DI_DROPPED_PKTS]; 749 stats->ierrors = 750 mac_stats[EFX_MAC_RX_FCS_ERRORS] + 751 mac_stats[EFX_MAC_RX_ALIGN_ERRORS] + 752 mac_stats[EFX_MAC_RX_JABBER_PKTS]; 753 /* no oerrors counters supported on EF10 */ 754 755 if (!have_dp_rx_stats) { 756 /* Exclude missed, errors and pauses from Rx packets */ 757 sfc_update_diff_stat(&port->ipackets, 758 mac_stats[EFX_MAC_RX_PKTS] - 759 mac_stats[EFX_MAC_RX_PAUSE_PKTS] - 760 stats->imissed - stats->ierrors); 761 stats->ipackets = port->ipackets; 762 stats->ibytes = mac_stats[EFX_MAC_RX_OCTETS] - 763 mac_stats[EFX_MAC_RX_PKTS] * RTE_ETHER_CRC_LEN; 764 } 765 } 766 767 unlock: 768 sfc_adapter_unlock(sa); 769 SFC_ASSERT(ret >= 0); 770 return -ret; 771 } 772 773 static int 774 sfc_stats_reset(struct rte_eth_dev *dev) 775 { 776 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 777 struct sfc_port *port = &sa->port; 778 int rc; 779 780 sfc_adapter_lock(sa); 781 782 if (sa->state != SFC_ETHDEV_STARTED) { 783 /* 784 * The operation cannot be done if port is not started; it 785 * will be scheduled to be done during the next port start 786 */ 787 port->mac_stats_reset_pending = B_TRUE; 788 sfc_adapter_unlock(sa); 789 return 0; 790 } 791 792 rc = sfc_port_reset_mac_stats(sa); 793 if (rc != 0) 794 sfc_err(sa, "failed to reset statistics (rc = %d)", rc); 795 796 sfc_sw_xstats_reset(sa); 797 798 sfc_adapter_unlock(sa); 799 800 SFC_ASSERT(rc >= 0); 801 return -rc; 802 } 803 804 static unsigned int 805 sfc_xstats_get_nb_supported(struct sfc_adapter *sa) 806 { 807 struct sfc_port *port = &sa->port; 808 unsigned int nb_supported; 809 810 sfc_adapter_lock(sa); 811 nb_supported = port->mac_stats_nb_supported + 812 sfc_sw_xstats_get_nb_supported(sa); 813 sfc_adapter_unlock(sa); 814 815 return nb_supported; 816 } 817 818 static int 819 sfc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 820 unsigned int xstats_count) 821 { 822 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 823 unsigned int nb_written = 0; 824 unsigned int nb_supported = 0; 825 int rc; 826 827 if (unlikely(xstats == NULL)) 828 return sfc_xstats_get_nb_supported(sa); 829 830 rc = sfc_port_get_mac_stats(sa, xstats, xstats_count, &nb_written); 831 if (rc < 0) 832 return rc; 833 834 nb_supported = rc; 835 sfc_sw_xstats_get_vals(sa, xstats, xstats_count, &nb_written, 836 &nb_supported); 837 838 return nb_supported; 839 } 840 841 static int 842 sfc_xstats_get_names(struct rte_eth_dev *dev, 843 struct rte_eth_xstat_name *xstats_names, 844 unsigned int xstats_count) 845 { 846 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 847 struct sfc_port *port = &sa->port; 848 unsigned int i; 849 unsigned int nstats = 0; 850 unsigned int nb_written = 0; 851 int ret; 852 853 if (unlikely(xstats_names == NULL)) 854 return sfc_xstats_get_nb_supported(sa); 855 856 for (i = 0; i < EFX_MAC_NSTATS; ++i) { 857 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, i)) { 858 if (nstats < xstats_count) { 859 strlcpy(xstats_names[nstats].name, 860 efx_mac_stat_name(sa->nic, i), 861 sizeof(xstats_names[0].name)); 862 nb_written++; 863 } 864 nstats++; 865 } 866 } 867 868 ret = sfc_sw_xstats_get_names(sa, xstats_names, xstats_count, 869 &nb_written, &nstats); 870 if (ret != 0) { 871 SFC_ASSERT(ret < 0); 872 return ret; 873 } 874 875 return nstats; 876 } 877 878 static int 879 sfc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 880 uint64_t *values, unsigned int n) 881 { 882 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 883 struct sfc_port *port = &sa->port; 884 unsigned int nb_supported; 885 unsigned int i; 886 int rc; 887 888 if (unlikely(ids == NULL || values == NULL)) 889 return -EINVAL; 890 891 /* 892 * Values array could be filled in nonsequential order. Fill values with 893 * constant indicating invalid ID first. 894 */ 895 for (i = 0; i < n; i++) 896 values[i] = SFC_XSTAT_ID_INVALID_VAL; 897 898 rc = sfc_port_get_mac_stats_by_id(sa, ids, values, n); 899 if (rc != 0) 900 return rc; 901 902 nb_supported = port->mac_stats_nb_supported; 903 sfc_sw_xstats_get_vals_by_id(sa, ids, values, n, &nb_supported); 904 905 /* Return number of written stats before invalid ID is encountered. */ 906 for (i = 0; i < n; i++) { 907 if (values[i] == SFC_XSTAT_ID_INVALID_VAL) 908 return i; 909 } 910 911 return n; 912 } 913 914 static int 915 sfc_xstats_get_names_by_id(struct rte_eth_dev *dev, 916 const uint64_t *ids, 917 struct rte_eth_xstat_name *xstats_names, 918 unsigned int size) 919 { 920 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 921 struct sfc_port *port = &sa->port; 922 unsigned int nb_supported; 923 unsigned int i; 924 int ret; 925 926 if (unlikely(xstats_names == NULL && ids != NULL) || 927 unlikely(xstats_names != NULL && ids == NULL)) 928 return -EINVAL; 929 930 if (unlikely(xstats_names == NULL && ids == NULL)) 931 return sfc_xstats_get_nb_supported(sa); 932 933 /* 934 * Names array could be filled in nonsequential order. Fill names with 935 * string indicating invalid ID first. 936 */ 937 for (i = 0; i < size; i++) 938 xstats_names[i].name[0] = SFC_XSTAT_ID_INVALID_NAME; 939 940 sfc_adapter_lock(sa); 941 942 SFC_ASSERT(port->mac_stats_nb_supported <= 943 RTE_DIM(port->mac_stats_by_id)); 944 945 for (i = 0; i < size; i++) { 946 if (ids[i] < port->mac_stats_nb_supported) { 947 strlcpy(xstats_names[i].name, 948 efx_mac_stat_name(sa->nic, 949 port->mac_stats_by_id[ids[i]]), 950 sizeof(xstats_names[0].name)); 951 } 952 } 953 954 nb_supported = port->mac_stats_nb_supported; 955 956 sfc_adapter_unlock(sa); 957 958 ret = sfc_sw_xstats_get_names_by_id(sa, ids, xstats_names, size, 959 &nb_supported); 960 if (ret != 0) { 961 SFC_ASSERT(ret < 0); 962 return ret; 963 } 964 965 /* Return number of written names before invalid ID is encountered. */ 966 for (i = 0; i < size; i++) { 967 if (xstats_names[i].name[0] == SFC_XSTAT_ID_INVALID_NAME) 968 return i; 969 } 970 971 return size; 972 } 973 974 static int 975 sfc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 976 { 977 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 978 unsigned int wanted_fc, link_fc; 979 980 memset(fc_conf, 0, sizeof(*fc_conf)); 981 982 sfc_adapter_lock(sa); 983 984 if (sa->state == SFC_ETHDEV_STARTED) 985 efx_mac_fcntl_get(sa->nic, &wanted_fc, &link_fc); 986 else 987 link_fc = sa->port.flow_ctrl; 988 989 switch (link_fc) { 990 case 0: 991 fc_conf->mode = RTE_FC_NONE; 992 break; 993 case EFX_FCNTL_RESPOND: 994 fc_conf->mode = RTE_FC_RX_PAUSE; 995 break; 996 case EFX_FCNTL_GENERATE: 997 fc_conf->mode = RTE_FC_TX_PAUSE; 998 break; 999 case (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE): 1000 fc_conf->mode = RTE_FC_FULL; 1001 break; 1002 default: 1003 sfc_err(sa, "%s: unexpected flow control value %#x", 1004 __func__, link_fc); 1005 } 1006 1007 fc_conf->autoneg = sa->port.flow_ctrl_autoneg; 1008 1009 sfc_adapter_unlock(sa); 1010 1011 return 0; 1012 } 1013 1014 static int 1015 sfc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1016 { 1017 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1018 struct sfc_port *port = &sa->port; 1019 unsigned int fcntl; 1020 int rc; 1021 1022 if (fc_conf->high_water != 0 || fc_conf->low_water != 0 || 1023 fc_conf->pause_time != 0 || fc_conf->send_xon != 0 || 1024 fc_conf->mac_ctrl_frame_fwd != 0) { 1025 sfc_err(sa, "unsupported flow control settings specified"); 1026 rc = EINVAL; 1027 goto fail_inval; 1028 } 1029 1030 switch (fc_conf->mode) { 1031 case RTE_FC_NONE: 1032 fcntl = 0; 1033 break; 1034 case RTE_FC_RX_PAUSE: 1035 fcntl = EFX_FCNTL_RESPOND; 1036 break; 1037 case RTE_FC_TX_PAUSE: 1038 fcntl = EFX_FCNTL_GENERATE; 1039 break; 1040 case RTE_FC_FULL: 1041 fcntl = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 1042 break; 1043 default: 1044 rc = EINVAL; 1045 goto fail_inval; 1046 } 1047 1048 sfc_adapter_lock(sa); 1049 1050 if (sa->state == SFC_ETHDEV_STARTED) { 1051 rc = efx_mac_fcntl_set(sa->nic, fcntl, fc_conf->autoneg); 1052 if (rc != 0) 1053 goto fail_mac_fcntl_set; 1054 } 1055 1056 port->flow_ctrl = fcntl; 1057 port->flow_ctrl_autoneg = fc_conf->autoneg; 1058 1059 sfc_adapter_unlock(sa); 1060 1061 return 0; 1062 1063 fail_mac_fcntl_set: 1064 sfc_adapter_unlock(sa); 1065 fail_inval: 1066 SFC_ASSERT(rc > 0); 1067 return -rc; 1068 } 1069 1070 static int 1071 sfc_check_scatter_on_all_rx_queues(struct sfc_adapter *sa, size_t pdu) 1072 { 1073 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1074 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1075 boolean_t scatter_enabled; 1076 const char *error; 1077 unsigned int i; 1078 1079 for (i = 0; i < sas->rxq_count; i++) { 1080 if ((sas->rxq_info[i].state & SFC_RXQ_INITIALIZED) == 0) 1081 continue; 1082 1083 scatter_enabled = (sas->rxq_info[i].type_flags & 1084 EFX_RXQ_FLAG_SCATTER); 1085 1086 if (!sfc_rx_check_scatter(pdu, sa->rxq_ctrl[i].buf_size, 1087 encp->enc_rx_prefix_size, 1088 scatter_enabled, 1089 encp->enc_rx_scatter_max, &error)) { 1090 sfc_err(sa, "MTU check for RxQ %u failed: %s", i, 1091 error); 1092 return EINVAL; 1093 } 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int 1100 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1101 { 1102 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1103 size_t pdu = EFX_MAC_PDU(mtu); 1104 size_t old_pdu; 1105 int rc; 1106 1107 sfc_log_init(sa, "mtu=%u", mtu); 1108 1109 rc = EINVAL; 1110 if (pdu < EFX_MAC_PDU_MIN) { 1111 sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)", 1112 (unsigned int)mtu, (unsigned int)pdu, 1113 EFX_MAC_PDU_MIN); 1114 goto fail_inval; 1115 } 1116 if (pdu > EFX_MAC_PDU_MAX) { 1117 sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)", 1118 (unsigned int)mtu, (unsigned int)pdu, 1119 (unsigned int)EFX_MAC_PDU_MAX); 1120 goto fail_inval; 1121 } 1122 1123 sfc_adapter_lock(sa); 1124 1125 rc = sfc_check_scatter_on_all_rx_queues(sa, pdu); 1126 if (rc != 0) 1127 goto fail_check_scatter; 1128 1129 if (pdu != sa->port.pdu) { 1130 if (sa->state == SFC_ETHDEV_STARTED) { 1131 sfc_stop(sa); 1132 1133 old_pdu = sa->port.pdu; 1134 sa->port.pdu = pdu; 1135 rc = sfc_start(sa); 1136 if (rc != 0) 1137 goto fail_start; 1138 } else { 1139 sa->port.pdu = pdu; 1140 } 1141 } 1142 1143 /* 1144 * The driver does not use it, but other PMDs update jumbo frame 1145 * flag when MTU is set. 1146 */ 1147 if (mtu > RTE_ETHER_MTU) { 1148 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1149 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1150 } 1151 1152 sfc_adapter_unlock(sa); 1153 1154 sfc_log_init(sa, "done"); 1155 return 0; 1156 1157 fail_start: 1158 sa->port.pdu = old_pdu; 1159 if (sfc_start(sa) != 0) 1160 sfc_err(sa, "cannot start with neither new (%u) nor old (%u) " 1161 "PDU max size - port is stopped", 1162 (unsigned int)pdu, (unsigned int)old_pdu); 1163 1164 fail_check_scatter: 1165 sfc_adapter_unlock(sa); 1166 1167 fail_inval: 1168 sfc_log_init(sa, "failed %d", rc); 1169 SFC_ASSERT(rc > 0); 1170 return -rc; 1171 } 1172 static int 1173 sfc_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1174 { 1175 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1176 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1177 struct sfc_port *port = &sa->port; 1178 struct rte_ether_addr *old_addr = &dev->data->mac_addrs[0]; 1179 int rc = 0; 1180 1181 sfc_adapter_lock(sa); 1182 1183 if (rte_is_same_ether_addr(mac_addr, &port->default_mac_addr)) 1184 goto unlock; 1185 1186 /* 1187 * Copy the address to the device private data so that 1188 * it could be recalled in the case of adapter restart. 1189 */ 1190 rte_ether_addr_copy(mac_addr, &port->default_mac_addr); 1191 1192 /* 1193 * Neither of the two following checks can return 1194 * an error. The new MAC address is preserved in 1195 * the device private data and can be activated 1196 * on the next port start if the user prevents 1197 * isolated mode from being enabled. 1198 */ 1199 if (sfc_sa2shared(sa)->isolated) { 1200 sfc_warn(sa, "isolated mode is active on the port"); 1201 sfc_warn(sa, "will not set MAC address"); 1202 goto unlock; 1203 } 1204 1205 if (sa->state != SFC_ETHDEV_STARTED) { 1206 sfc_notice(sa, "the port is not started"); 1207 sfc_notice(sa, "the new MAC address will be set on port start"); 1208 1209 goto unlock; 1210 } 1211 1212 if (encp->enc_allow_set_mac_with_installed_filters) { 1213 rc = efx_mac_addr_set(sa->nic, mac_addr->addr_bytes); 1214 if (rc != 0) { 1215 sfc_err(sa, "cannot set MAC address (rc = %u)", rc); 1216 goto unlock; 1217 } 1218 1219 /* 1220 * Changing the MAC address by means of MCDI request 1221 * has no effect on received traffic, therefore 1222 * we also need to update unicast filters 1223 */ 1224 rc = sfc_set_rx_mode_unchecked(sa); 1225 if (rc != 0) { 1226 sfc_err(sa, "cannot set filter (rc = %u)", rc); 1227 /* Rollback the old address */ 1228 (void)efx_mac_addr_set(sa->nic, old_addr->addr_bytes); 1229 (void)sfc_set_rx_mode_unchecked(sa); 1230 } 1231 } else { 1232 sfc_warn(sa, "cannot set MAC address with filters installed"); 1233 sfc_warn(sa, "adapter will be restarted to pick the new MAC"); 1234 sfc_warn(sa, "(some traffic may be dropped)"); 1235 1236 /* 1237 * Since setting MAC address with filters installed is not 1238 * allowed on the adapter, the new MAC address will be set 1239 * by means of adapter restart. sfc_start() shall retrieve 1240 * the new address from the device private data and set it. 1241 */ 1242 sfc_stop(sa); 1243 rc = sfc_start(sa); 1244 if (rc != 0) 1245 sfc_err(sa, "cannot restart adapter (rc = %u)", rc); 1246 } 1247 1248 unlock: 1249 if (rc != 0) 1250 rte_ether_addr_copy(old_addr, &port->default_mac_addr); 1251 1252 sfc_adapter_unlock(sa); 1253 1254 SFC_ASSERT(rc >= 0); 1255 return -rc; 1256 } 1257 1258 1259 static int 1260 sfc_set_mc_addr_list(struct rte_eth_dev *dev, 1261 struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr) 1262 { 1263 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1264 struct sfc_port *port = &sa->port; 1265 uint8_t *mc_addrs = port->mcast_addrs; 1266 int rc; 1267 unsigned int i; 1268 1269 if (sfc_sa2shared(sa)->isolated) { 1270 sfc_err(sa, "isolated mode is active on the port"); 1271 sfc_err(sa, "will not set multicast address list"); 1272 return -ENOTSUP; 1273 } 1274 1275 if (mc_addrs == NULL) 1276 return -ENOBUFS; 1277 1278 if (nb_mc_addr > port->max_mcast_addrs) { 1279 sfc_err(sa, "too many multicast addresses: %u > %u", 1280 nb_mc_addr, port->max_mcast_addrs); 1281 return -EINVAL; 1282 } 1283 1284 for (i = 0; i < nb_mc_addr; ++i) { 1285 rte_memcpy(mc_addrs, mc_addr_set[i].addr_bytes, 1286 EFX_MAC_ADDR_LEN); 1287 mc_addrs += EFX_MAC_ADDR_LEN; 1288 } 1289 1290 port->nb_mcast_addrs = nb_mc_addr; 1291 1292 if (sa->state != SFC_ETHDEV_STARTED) 1293 return 0; 1294 1295 rc = efx_mac_multicast_list_set(sa->nic, port->mcast_addrs, 1296 port->nb_mcast_addrs); 1297 if (rc != 0) 1298 sfc_err(sa, "cannot set multicast address list (rc = %u)", rc); 1299 1300 SFC_ASSERT(rc >= 0); 1301 return -rc; 1302 } 1303 1304 /* 1305 * The function is used by the secondary process as well. It must not 1306 * use any process-local pointers from the adapter data. 1307 */ 1308 static void 1309 sfc_rx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1310 struct rte_eth_rxq_info *qinfo) 1311 { 1312 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1313 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1314 struct sfc_rxq_info *rxq_info; 1315 1316 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1317 1318 qinfo->mp = rxq_info->refill_mb_pool; 1319 qinfo->conf.rx_free_thresh = rxq_info->refill_threshold; 1320 qinfo->conf.rx_drop_en = 1; 1321 qinfo->conf.rx_deferred_start = rxq_info->deferred_start; 1322 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 1323 if (rxq_info->type_flags & EFX_RXQ_FLAG_SCATTER) { 1324 qinfo->conf.offloads |= DEV_RX_OFFLOAD_SCATTER; 1325 qinfo->scattered_rx = 1; 1326 } 1327 qinfo->nb_desc = rxq_info->entries; 1328 } 1329 1330 /* 1331 * The function is used by the secondary process as well. It must not 1332 * use any process-local pointers from the adapter data. 1333 */ 1334 static void 1335 sfc_tx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1336 struct rte_eth_txq_info *qinfo) 1337 { 1338 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1339 struct sfc_txq_info *txq_info; 1340 1341 SFC_ASSERT(ethdev_qid < sas->ethdev_txq_count); 1342 1343 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1344 1345 memset(qinfo, 0, sizeof(*qinfo)); 1346 1347 qinfo->conf.offloads = txq_info->offloads; 1348 qinfo->conf.tx_free_thresh = txq_info->free_thresh; 1349 qinfo->conf.tx_deferred_start = txq_info->deferred_start; 1350 qinfo->nb_desc = txq_info->entries; 1351 } 1352 1353 /* 1354 * The function is used by the secondary process as well. It must not 1355 * use any process-local pointers from the adapter data. 1356 */ 1357 static uint32_t 1358 sfc_rx_queue_count(void *rx_queue) 1359 { 1360 struct sfc_dp_rxq *dp_rxq = rx_queue; 1361 const struct sfc_dp_rx *dp_rx; 1362 struct sfc_rxq_info *rxq_info; 1363 1364 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1365 rxq_info = sfc_rxq_info_by_dp_rxq(dp_rxq); 1366 1367 if ((rxq_info->state & SFC_RXQ_STARTED) == 0) 1368 return 0; 1369 1370 return dp_rx->qdesc_npending(dp_rxq); 1371 } 1372 1373 /* 1374 * The function is used by the secondary process as well. It must not 1375 * use any process-local pointers from the adapter data. 1376 */ 1377 static int 1378 sfc_rx_descriptor_status(void *queue, uint16_t offset) 1379 { 1380 struct sfc_dp_rxq *dp_rxq = queue; 1381 const struct sfc_dp_rx *dp_rx; 1382 1383 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1384 1385 return dp_rx->qdesc_status(dp_rxq, offset); 1386 } 1387 1388 /* 1389 * The function is used by the secondary process as well. It must not 1390 * use any process-local pointers from the adapter data. 1391 */ 1392 static int 1393 sfc_tx_descriptor_status(void *queue, uint16_t offset) 1394 { 1395 struct sfc_dp_txq *dp_txq = queue; 1396 const struct sfc_dp_tx *dp_tx; 1397 1398 dp_tx = sfc_dp_tx_by_dp_txq(dp_txq); 1399 1400 return dp_tx->qdesc_status(dp_txq, offset); 1401 } 1402 1403 static int 1404 sfc_rx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1405 { 1406 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1407 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1408 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1409 struct sfc_rxq_info *rxq_info; 1410 sfc_sw_index_t sw_index; 1411 int rc; 1412 1413 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1414 1415 sfc_adapter_lock(sa); 1416 1417 rc = EINVAL; 1418 if (sa->state != SFC_ETHDEV_STARTED) 1419 goto fail_not_started; 1420 1421 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1422 if (rxq_info->state != SFC_RXQ_INITIALIZED) 1423 goto fail_not_setup; 1424 1425 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1426 rc = sfc_rx_qstart(sa, sw_index); 1427 if (rc != 0) 1428 goto fail_rx_qstart; 1429 1430 rxq_info->deferred_started = B_TRUE; 1431 1432 sfc_adapter_unlock(sa); 1433 1434 return 0; 1435 1436 fail_rx_qstart: 1437 fail_not_setup: 1438 fail_not_started: 1439 sfc_adapter_unlock(sa); 1440 SFC_ASSERT(rc > 0); 1441 return -rc; 1442 } 1443 1444 static int 1445 sfc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1446 { 1447 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1448 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1449 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1450 struct sfc_rxq_info *rxq_info; 1451 sfc_sw_index_t sw_index; 1452 1453 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1454 1455 sfc_adapter_lock(sa); 1456 1457 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1458 sfc_rx_qstop(sa, sw_index); 1459 1460 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1461 rxq_info->deferred_started = B_FALSE; 1462 1463 sfc_adapter_unlock(sa); 1464 1465 return 0; 1466 } 1467 1468 static int 1469 sfc_tx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1470 { 1471 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1472 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1473 struct sfc_txq_info *txq_info; 1474 sfc_sw_index_t sw_index; 1475 int rc; 1476 1477 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1478 1479 sfc_adapter_lock(sa); 1480 1481 rc = EINVAL; 1482 if (sa->state != SFC_ETHDEV_STARTED) 1483 goto fail_not_started; 1484 1485 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1486 if (txq_info->state != SFC_TXQ_INITIALIZED) 1487 goto fail_not_setup; 1488 1489 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1490 rc = sfc_tx_qstart(sa, sw_index); 1491 if (rc != 0) 1492 goto fail_tx_qstart; 1493 1494 txq_info->deferred_started = B_TRUE; 1495 1496 sfc_adapter_unlock(sa); 1497 return 0; 1498 1499 fail_tx_qstart: 1500 1501 fail_not_setup: 1502 fail_not_started: 1503 sfc_adapter_unlock(sa); 1504 SFC_ASSERT(rc > 0); 1505 return -rc; 1506 } 1507 1508 static int 1509 sfc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1510 { 1511 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1512 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1513 struct sfc_txq_info *txq_info; 1514 sfc_sw_index_t sw_index; 1515 1516 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1517 1518 sfc_adapter_lock(sa); 1519 1520 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1521 sfc_tx_qstop(sa, sw_index); 1522 1523 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1524 txq_info->deferred_started = B_FALSE; 1525 1526 sfc_adapter_unlock(sa); 1527 return 0; 1528 } 1529 1530 static efx_tunnel_protocol_t 1531 sfc_tunnel_rte_type_to_efx_udp_proto(enum rte_eth_tunnel_type rte_type) 1532 { 1533 switch (rte_type) { 1534 case RTE_TUNNEL_TYPE_VXLAN: 1535 return EFX_TUNNEL_PROTOCOL_VXLAN; 1536 case RTE_TUNNEL_TYPE_GENEVE: 1537 return EFX_TUNNEL_PROTOCOL_GENEVE; 1538 default: 1539 return EFX_TUNNEL_NPROTOS; 1540 } 1541 } 1542 1543 enum sfc_udp_tunnel_op_e { 1544 SFC_UDP_TUNNEL_ADD_PORT, 1545 SFC_UDP_TUNNEL_DEL_PORT, 1546 }; 1547 1548 static int 1549 sfc_dev_udp_tunnel_op(struct rte_eth_dev *dev, 1550 struct rte_eth_udp_tunnel *tunnel_udp, 1551 enum sfc_udp_tunnel_op_e op) 1552 { 1553 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1554 efx_tunnel_protocol_t tunnel_proto; 1555 int rc; 1556 1557 sfc_log_init(sa, "%s udp_port=%u prot_type=%u", 1558 (op == SFC_UDP_TUNNEL_ADD_PORT) ? "add" : 1559 (op == SFC_UDP_TUNNEL_DEL_PORT) ? "delete" : "unknown", 1560 tunnel_udp->udp_port, tunnel_udp->prot_type); 1561 1562 tunnel_proto = 1563 sfc_tunnel_rte_type_to_efx_udp_proto(tunnel_udp->prot_type); 1564 if (tunnel_proto >= EFX_TUNNEL_NPROTOS) { 1565 rc = ENOTSUP; 1566 goto fail_bad_proto; 1567 } 1568 1569 sfc_adapter_lock(sa); 1570 1571 switch (op) { 1572 case SFC_UDP_TUNNEL_ADD_PORT: 1573 rc = efx_tunnel_config_udp_add(sa->nic, 1574 tunnel_udp->udp_port, 1575 tunnel_proto); 1576 break; 1577 case SFC_UDP_TUNNEL_DEL_PORT: 1578 rc = efx_tunnel_config_udp_remove(sa->nic, 1579 tunnel_udp->udp_port, 1580 tunnel_proto); 1581 break; 1582 default: 1583 rc = EINVAL; 1584 goto fail_bad_op; 1585 } 1586 1587 if (rc != 0) 1588 goto fail_op; 1589 1590 if (sa->state == SFC_ETHDEV_STARTED) { 1591 rc = efx_tunnel_reconfigure(sa->nic); 1592 if (rc == EAGAIN) { 1593 /* 1594 * Configuration is accepted by FW and MC reboot 1595 * is initiated to apply the changes. MC reboot 1596 * will be handled in a usual way (MC reboot 1597 * event on management event queue and adapter 1598 * restart). 1599 */ 1600 rc = 0; 1601 } else if (rc != 0) { 1602 goto fail_reconfigure; 1603 } 1604 } 1605 1606 sfc_adapter_unlock(sa); 1607 return 0; 1608 1609 fail_reconfigure: 1610 /* Remove/restore entry since the change makes the trouble */ 1611 switch (op) { 1612 case SFC_UDP_TUNNEL_ADD_PORT: 1613 (void)efx_tunnel_config_udp_remove(sa->nic, 1614 tunnel_udp->udp_port, 1615 tunnel_proto); 1616 break; 1617 case SFC_UDP_TUNNEL_DEL_PORT: 1618 (void)efx_tunnel_config_udp_add(sa->nic, 1619 tunnel_udp->udp_port, 1620 tunnel_proto); 1621 break; 1622 } 1623 1624 fail_op: 1625 fail_bad_op: 1626 sfc_adapter_unlock(sa); 1627 1628 fail_bad_proto: 1629 SFC_ASSERT(rc > 0); 1630 return -rc; 1631 } 1632 1633 static int 1634 sfc_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 1635 struct rte_eth_udp_tunnel *tunnel_udp) 1636 { 1637 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_ADD_PORT); 1638 } 1639 1640 static int 1641 sfc_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 1642 struct rte_eth_udp_tunnel *tunnel_udp) 1643 { 1644 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_DEL_PORT); 1645 } 1646 1647 /* 1648 * The function is used by the secondary process as well. It must not 1649 * use any process-local pointers from the adapter data. 1650 */ 1651 static int 1652 sfc_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1653 struct rte_eth_rss_conf *rss_conf) 1654 { 1655 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1656 struct sfc_rss *rss = &sas->rss; 1657 1658 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) 1659 return -ENOTSUP; 1660 1661 /* 1662 * Mapping of hash configuration between RTE and EFX is not one-to-one, 1663 * hence, conversion is done here to derive a correct set of ETH_RSS 1664 * flags which corresponds to the active EFX configuration stored 1665 * locally in 'sfc_adapter' and kept up-to-date 1666 */ 1667 rss_conf->rss_hf = sfc_rx_hf_efx_to_rte(rss, rss->hash_types); 1668 rss_conf->rss_key_len = EFX_RSS_KEY_SIZE; 1669 if (rss_conf->rss_key != NULL) 1670 rte_memcpy(rss_conf->rss_key, rss->key, EFX_RSS_KEY_SIZE); 1671 1672 return 0; 1673 } 1674 1675 static int 1676 sfc_dev_rss_hash_update(struct rte_eth_dev *dev, 1677 struct rte_eth_rss_conf *rss_conf) 1678 { 1679 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1680 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1681 unsigned int efx_hash_types; 1682 uint32_t contexts[] = {EFX_RSS_CONTEXT_DEFAULT, rss->dummy_rss_context}; 1683 unsigned int n_contexts; 1684 unsigned int mode_i = 0; 1685 unsigned int key_i = 0; 1686 unsigned int i = 0; 1687 int rc = 0; 1688 1689 n_contexts = rss->dummy_rss_context == EFX_RSS_CONTEXT_DEFAULT ? 1 : 2; 1690 1691 if (sfc_sa2shared(sa)->isolated) 1692 return -ENOTSUP; 1693 1694 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1695 sfc_err(sa, "RSS is not available"); 1696 return -ENOTSUP; 1697 } 1698 1699 if (rss->channels == 0) { 1700 sfc_err(sa, "RSS is not configured"); 1701 return -EINVAL; 1702 } 1703 1704 if ((rss_conf->rss_key != NULL) && 1705 (rss_conf->rss_key_len != sizeof(rss->key))) { 1706 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1707 sizeof(rss->key)); 1708 return -EINVAL; 1709 } 1710 1711 sfc_adapter_lock(sa); 1712 1713 rc = sfc_rx_hf_rte_to_efx(sa, rss_conf->rss_hf, &efx_hash_types); 1714 if (rc != 0) 1715 goto fail_rx_hf_rte_to_efx; 1716 1717 for (mode_i = 0; mode_i < n_contexts; mode_i++) { 1718 rc = efx_rx_scale_mode_set(sa->nic, contexts[mode_i], 1719 rss->hash_alg, efx_hash_types, 1720 B_TRUE); 1721 if (rc != 0) 1722 goto fail_scale_mode_set; 1723 } 1724 1725 if (rss_conf->rss_key != NULL) { 1726 if (sa->state == SFC_ETHDEV_STARTED) { 1727 for (key_i = 0; key_i < n_contexts; key_i++) { 1728 rc = efx_rx_scale_key_set(sa->nic, 1729 contexts[key_i], 1730 rss_conf->rss_key, 1731 sizeof(rss->key)); 1732 if (rc != 0) 1733 goto fail_scale_key_set; 1734 } 1735 } 1736 1737 rte_memcpy(rss->key, rss_conf->rss_key, sizeof(rss->key)); 1738 } 1739 1740 rss->hash_types = efx_hash_types; 1741 1742 sfc_adapter_unlock(sa); 1743 1744 return 0; 1745 1746 fail_scale_key_set: 1747 for (i = 0; i < key_i; i++) { 1748 if (efx_rx_scale_key_set(sa->nic, contexts[i], rss->key, 1749 sizeof(rss->key)) != 0) 1750 sfc_err(sa, "failed to restore RSS key"); 1751 } 1752 1753 fail_scale_mode_set: 1754 for (i = 0; i < mode_i; i++) { 1755 if (efx_rx_scale_mode_set(sa->nic, contexts[i], 1756 EFX_RX_HASHALG_TOEPLITZ, 1757 rss->hash_types, B_TRUE) != 0) 1758 sfc_err(sa, "failed to restore RSS mode"); 1759 } 1760 1761 fail_rx_hf_rte_to_efx: 1762 sfc_adapter_unlock(sa); 1763 return -rc; 1764 } 1765 1766 /* 1767 * The function is used by the secondary process as well. It must not 1768 * use any process-local pointers from the adapter data. 1769 */ 1770 static int 1771 sfc_dev_rss_reta_query(struct rte_eth_dev *dev, 1772 struct rte_eth_rss_reta_entry64 *reta_conf, 1773 uint16_t reta_size) 1774 { 1775 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1776 struct sfc_rss *rss = &sas->rss; 1777 int entry; 1778 1779 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE || sas->isolated) 1780 return -ENOTSUP; 1781 1782 if (rss->channels == 0) 1783 return -EINVAL; 1784 1785 if (reta_size != EFX_RSS_TBL_SIZE) 1786 return -EINVAL; 1787 1788 for (entry = 0; entry < reta_size; entry++) { 1789 int grp = entry / RTE_RETA_GROUP_SIZE; 1790 int grp_idx = entry % RTE_RETA_GROUP_SIZE; 1791 1792 if ((reta_conf[grp].mask >> grp_idx) & 1) 1793 reta_conf[grp].reta[grp_idx] = rss->tbl[entry]; 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int 1800 sfc_dev_rss_reta_update(struct rte_eth_dev *dev, 1801 struct rte_eth_rss_reta_entry64 *reta_conf, 1802 uint16_t reta_size) 1803 { 1804 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1805 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1806 unsigned int *rss_tbl_new; 1807 uint16_t entry; 1808 int rc = 0; 1809 1810 1811 if (sfc_sa2shared(sa)->isolated) 1812 return -ENOTSUP; 1813 1814 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1815 sfc_err(sa, "RSS is not available"); 1816 return -ENOTSUP; 1817 } 1818 1819 if (rss->channels == 0) { 1820 sfc_err(sa, "RSS is not configured"); 1821 return -EINVAL; 1822 } 1823 1824 if (reta_size != EFX_RSS_TBL_SIZE) { 1825 sfc_err(sa, "RETA size is wrong (should be %u)", 1826 EFX_RSS_TBL_SIZE); 1827 return -EINVAL; 1828 } 1829 1830 rss_tbl_new = rte_zmalloc("rss_tbl_new", sizeof(rss->tbl), 0); 1831 if (rss_tbl_new == NULL) 1832 return -ENOMEM; 1833 1834 sfc_adapter_lock(sa); 1835 1836 rte_memcpy(rss_tbl_new, rss->tbl, sizeof(rss->tbl)); 1837 1838 for (entry = 0; entry < reta_size; entry++) { 1839 int grp_idx = entry % RTE_RETA_GROUP_SIZE; 1840 struct rte_eth_rss_reta_entry64 *grp; 1841 1842 grp = &reta_conf[entry / RTE_RETA_GROUP_SIZE]; 1843 1844 if (grp->mask & (1ull << grp_idx)) { 1845 if (grp->reta[grp_idx] >= rss->channels) { 1846 rc = EINVAL; 1847 goto bad_reta_entry; 1848 } 1849 rss_tbl_new[entry] = grp->reta[grp_idx]; 1850 } 1851 } 1852 1853 if (sa->state == SFC_ETHDEV_STARTED) { 1854 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1855 rss_tbl_new, EFX_RSS_TBL_SIZE); 1856 if (rc != 0) 1857 goto fail_scale_tbl_set; 1858 } 1859 1860 rte_memcpy(rss->tbl, rss_tbl_new, sizeof(rss->tbl)); 1861 1862 fail_scale_tbl_set: 1863 bad_reta_entry: 1864 sfc_adapter_unlock(sa); 1865 1866 rte_free(rss_tbl_new); 1867 1868 SFC_ASSERT(rc >= 0); 1869 return -rc; 1870 } 1871 1872 static int 1873 sfc_dev_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 1874 const struct rte_flow_ops **ops) 1875 { 1876 *ops = &sfc_flow_ops; 1877 return 0; 1878 } 1879 1880 static int 1881 sfc_pool_ops_supported(struct rte_eth_dev *dev, const char *pool) 1882 { 1883 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1884 1885 /* 1886 * If Rx datapath does not provide callback to check mempool, 1887 * all pools are supported. 1888 */ 1889 if (sap->dp_rx->pool_ops_supported == NULL) 1890 return 1; 1891 1892 return sap->dp_rx->pool_ops_supported(pool); 1893 } 1894 1895 static int 1896 sfc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1897 { 1898 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1899 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1900 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1901 struct sfc_rxq_info *rxq_info; 1902 1903 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1904 1905 return sap->dp_rx->intr_enable(rxq_info->dp); 1906 } 1907 1908 static int 1909 sfc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1910 { 1911 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1912 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1913 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1914 struct sfc_rxq_info *rxq_info; 1915 1916 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1917 1918 return sap->dp_rx->intr_disable(rxq_info->dp); 1919 } 1920 1921 struct sfc_mport_journal_ctx { 1922 struct sfc_adapter *sa; 1923 uint16_t switch_domain_id; 1924 uint32_t mcdi_handle; 1925 bool controllers_assigned; 1926 efx_pcie_interface_t *controllers; 1927 size_t nb_controllers; 1928 }; 1929 1930 static int 1931 sfc_journal_ctx_add_controller(struct sfc_mport_journal_ctx *ctx, 1932 efx_pcie_interface_t intf) 1933 { 1934 efx_pcie_interface_t *new_controllers; 1935 size_t i, target; 1936 size_t new_size; 1937 1938 if (ctx->controllers == NULL) { 1939 ctx->controllers = rte_malloc("sfc_controller_mapping", 1940 sizeof(ctx->controllers[0]), 0); 1941 if (ctx->controllers == NULL) 1942 return ENOMEM; 1943 1944 ctx->controllers[0] = intf; 1945 ctx->nb_controllers = 1; 1946 1947 return 0; 1948 } 1949 1950 for (i = 0; i < ctx->nb_controllers; i++) { 1951 if (ctx->controllers[i] == intf) 1952 return 0; 1953 if (ctx->controllers[i] > intf) 1954 break; 1955 } 1956 target = i; 1957 1958 ctx->nb_controllers += 1; 1959 new_size = ctx->nb_controllers * sizeof(ctx->controllers[0]); 1960 1961 new_controllers = rte_realloc(ctx->controllers, new_size, 0); 1962 if (new_controllers == NULL) { 1963 rte_free(ctx->controllers); 1964 return ENOMEM; 1965 } 1966 ctx->controllers = new_controllers; 1967 1968 for (i = target + 1; i < ctx->nb_controllers; i++) 1969 ctx->controllers[i] = ctx->controllers[i - 1]; 1970 1971 ctx->controllers[target] = intf; 1972 1973 return 0; 1974 } 1975 1976 static efx_rc_t 1977 sfc_process_mport_journal_entry(struct sfc_mport_journal_ctx *ctx, 1978 efx_mport_desc_t *mport) 1979 { 1980 struct sfc_mae_switch_port_request req; 1981 efx_mport_sel_t entity_selector; 1982 efx_mport_sel_t ethdev_mport; 1983 uint16_t switch_port_id; 1984 efx_rc_t efx_rc; 1985 int rc; 1986 1987 sfc_dbg(ctx->sa, 1988 "processing mport id %u (controller %u pf %u vf %u)", 1989 mport->emd_id.id, mport->emd_vnic.ev_intf, 1990 mport->emd_vnic.ev_pf, mport->emd_vnic.ev_vf); 1991 efx_mae_mport_invalid(ðdev_mport); 1992 1993 if (!ctx->controllers_assigned) { 1994 rc = sfc_journal_ctx_add_controller(ctx, 1995 mport->emd_vnic.ev_intf); 1996 if (rc != 0) 1997 return rc; 1998 } 1999 2000 /* Build Mport selector */ 2001 efx_rc = efx_mae_mport_by_pcie_mh_function(mport->emd_vnic.ev_intf, 2002 mport->emd_vnic.ev_pf, 2003 mport->emd_vnic.ev_vf, 2004 &entity_selector); 2005 if (efx_rc != 0) { 2006 sfc_err(ctx->sa, "failed to build entity mport selector for c%upf%uvf%u", 2007 mport->emd_vnic.ev_intf, 2008 mport->emd_vnic.ev_pf, 2009 mport->emd_vnic.ev_vf); 2010 return efx_rc; 2011 } 2012 2013 rc = sfc_mae_switch_port_id_by_entity(ctx->switch_domain_id, 2014 &entity_selector, 2015 SFC_MAE_SWITCH_PORT_REPRESENTOR, 2016 &switch_port_id); 2017 switch (rc) { 2018 case 0: 2019 /* Already registered */ 2020 break; 2021 case ENOENT: 2022 /* 2023 * No representor has been created for this entity. 2024 * Create a dummy switch registry entry with an invalid ethdev 2025 * mport selector. When a corresponding representor is created, 2026 * this entry will be updated. 2027 */ 2028 req.type = SFC_MAE_SWITCH_PORT_REPRESENTOR; 2029 req.entity_mportp = &entity_selector; 2030 req.ethdev_mportp = ðdev_mport; 2031 req.ethdev_port_id = RTE_MAX_ETHPORTS; 2032 req.port_data.repr.intf = mport->emd_vnic.ev_intf; 2033 req.port_data.repr.pf = mport->emd_vnic.ev_pf; 2034 req.port_data.repr.vf = mport->emd_vnic.ev_vf; 2035 2036 rc = sfc_mae_assign_switch_port(ctx->switch_domain_id, 2037 &req, &switch_port_id); 2038 if (rc != 0) { 2039 sfc_err(ctx->sa, 2040 "failed to assign MAE switch port for c%upf%uvf%u: %s", 2041 mport->emd_vnic.ev_intf, 2042 mport->emd_vnic.ev_pf, 2043 mport->emd_vnic.ev_vf, 2044 rte_strerror(rc)); 2045 return rc; 2046 } 2047 break; 2048 default: 2049 sfc_err(ctx->sa, "failed to find MAE switch port for c%upf%uvf%u: %s", 2050 mport->emd_vnic.ev_intf, 2051 mport->emd_vnic.ev_pf, 2052 mport->emd_vnic.ev_vf, 2053 rte_strerror(rc)); 2054 return rc; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static efx_rc_t 2061 sfc_process_mport_journal_cb(void *data, efx_mport_desc_t *mport, 2062 size_t mport_len) 2063 { 2064 struct sfc_mport_journal_ctx *ctx = data; 2065 2066 if (ctx == NULL || ctx->sa == NULL) { 2067 sfc_err(ctx->sa, "received NULL context or SFC adapter"); 2068 return EINVAL; 2069 } 2070 2071 if (mport_len != sizeof(*mport)) { 2072 sfc_err(ctx->sa, "actual and expected mport buffer sizes differ"); 2073 return EINVAL; 2074 } 2075 2076 SFC_ASSERT(sfc_adapter_is_locked(ctx->sa)); 2077 2078 /* 2079 * If a zombie flag is set, it means the mport has been marked for 2080 * deletion and cannot be used for any new operations. The mport will 2081 * be destroyed completely once all references to it are released. 2082 */ 2083 if (mport->emd_zombie) { 2084 sfc_dbg(ctx->sa, "mport is a zombie, skipping"); 2085 return 0; 2086 } 2087 if (mport->emd_type != EFX_MPORT_TYPE_VNIC) { 2088 sfc_dbg(ctx->sa, "mport is not a VNIC, skipping"); 2089 return 0; 2090 } 2091 if (mport->emd_vnic.ev_client_type != EFX_MPORT_VNIC_CLIENT_FUNCTION) { 2092 sfc_dbg(ctx->sa, "mport is not a function, skipping"); 2093 return 0; 2094 } 2095 if (mport->emd_vnic.ev_handle == ctx->mcdi_handle) { 2096 sfc_dbg(ctx->sa, "mport is this driver instance, skipping"); 2097 return 0; 2098 } 2099 2100 return sfc_process_mport_journal_entry(ctx, mport); 2101 } 2102 2103 static int 2104 sfc_process_mport_journal(struct sfc_adapter *sa) 2105 { 2106 struct sfc_mport_journal_ctx ctx; 2107 const efx_pcie_interface_t *controllers; 2108 size_t nb_controllers; 2109 efx_rc_t efx_rc; 2110 int rc; 2111 2112 memset(&ctx, 0, sizeof(ctx)); 2113 ctx.sa = sa; 2114 ctx.switch_domain_id = sa->mae.switch_domain_id; 2115 2116 efx_rc = efx_mcdi_get_own_client_handle(sa->nic, &ctx.mcdi_handle); 2117 if (efx_rc != 0) { 2118 sfc_err(sa, "failed to get own MCDI handle"); 2119 SFC_ASSERT(efx_rc > 0); 2120 return efx_rc; 2121 } 2122 2123 rc = sfc_mae_switch_domain_controllers(ctx.switch_domain_id, 2124 &controllers, &nb_controllers); 2125 if (rc != 0) { 2126 sfc_err(sa, "failed to get controller mapping"); 2127 return rc; 2128 } 2129 2130 ctx.controllers_assigned = controllers != NULL; 2131 ctx.controllers = NULL; 2132 ctx.nb_controllers = 0; 2133 2134 efx_rc = efx_mae_read_mport_journal(sa->nic, 2135 sfc_process_mport_journal_cb, &ctx); 2136 if (efx_rc != 0) { 2137 sfc_err(sa, "failed to process MAE mport journal"); 2138 SFC_ASSERT(efx_rc > 0); 2139 return efx_rc; 2140 } 2141 2142 if (controllers == NULL) { 2143 rc = sfc_mae_switch_domain_map_controllers(ctx.switch_domain_id, 2144 ctx.controllers, 2145 ctx.nb_controllers); 2146 if (rc != 0) 2147 return rc; 2148 } 2149 2150 return 0; 2151 } 2152 2153 static void 2154 sfc_count_representors_cb(enum sfc_mae_switch_port_type type, 2155 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2156 uint16_t ethdev_port_id __rte_unused, 2157 const efx_mport_sel_t *entity_mportp __rte_unused, 2158 uint16_t switch_port_id __rte_unused, 2159 union sfc_mae_switch_port_data *port_datap 2160 __rte_unused, 2161 void *user_datap) 2162 { 2163 int *counter = user_datap; 2164 2165 SFC_ASSERT(counter != NULL); 2166 2167 if (type == SFC_MAE_SWITCH_PORT_REPRESENTOR) 2168 (*counter)++; 2169 } 2170 2171 struct sfc_get_representors_ctx { 2172 struct rte_eth_representor_info *info; 2173 struct sfc_adapter *sa; 2174 uint16_t switch_domain_id; 2175 const efx_pcie_interface_t *controllers; 2176 size_t nb_controllers; 2177 }; 2178 2179 static void 2180 sfc_get_representors_cb(enum sfc_mae_switch_port_type type, 2181 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2182 uint16_t ethdev_port_id __rte_unused, 2183 const efx_mport_sel_t *entity_mportp __rte_unused, 2184 uint16_t switch_port_id, 2185 union sfc_mae_switch_port_data *port_datap, 2186 void *user_datap) 2187 { 2188 struct sfc_get_representors_ctx *ctx = user_datap; 2189 struct rte_eth_representor_range *range; 2190 int ret; 2191 int rc; 2192 2193 SFC_ASSERT(ctx != NULL); 2194 SFC_ASSERT(ctx->info != NULL); 2195 SFC_ASSERT(ctx->sa != NULL); 2196 2197 if (type != SFC_MAE_SWITCH_PORT_REPRESENTOR) { 2198 sfc_dbg(ctx->sa, "not a representor, skipping"); 2199 return; 2200 } 2201 if (ctx->info->nb_ranges >= ctx->info->nb_ranges_alloc) { 2202 sfc_dbg(ctx->sa, "info structure is full already"); 2203 return; 2204 } 2205 2206 range = &ctx->info->ranges[ctx->info->nb_ranges]; 2207 rc = sfc_mae_switch_controller_from_mapping(ctx->controllers, 2208 ctx->nb_controllers, 2209 port_datap->repr.intf, 2210 &range->controller); 2211 if (rc != 0) { 2212 sfc_err(ctx->sa, "invalid representor controller: %d", 2213 port_datap->repr.intf); 2214 range->controller = -1; 2215 } 2216 range->pf = port_datap->repr.pf; 2217 range->id_base = switch_port_id; 2218 range->id_end = switch_port_id; 2219 2220 if (port_datap->repr.vf != EFX_PCI_VF_INVALID) { 2221 range->type = RTE_ETH_REPRESENTOR_VF; 2222 range->vf = port_datap->repr.vf; 2223 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2224 "c%dpf%dvf%d", range->controller, range->pf, 2225 range->vf); 2226 } else { 2227 range->type = RTE_ETH_REPRESENTOR_PF; 2228 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2229 "c%dpf%d", range->controller, range->pf); 2230 } 2231 if (ret >= RTE_DEV_NAME_MAX_LEN) { 2232 sfc_err(ctx->sa, "representor name has been truncated: %s", 2233 range->name); 2234 } 2235 2236 ctx->info->nb_ranges++; 2237 } 2238 2239 static int 2240 sfc_representor_info_get(struct rte_eth_dev *dev, 2241 struct rte_eth_representor_info *info) 2242 { 2243 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2244 struct sfc_get_representors_ctx get_repr_ctx; 2245 const efx_nic_cfg_t *nic_cfg; 2246 uint16_t switch_domain_id; 2247 uint32_t nb_repr; 2248 int controller; 2249 int rc; 2250 2251 sfc_adapter_lock(sa); 2252 2253 if (sa->mae.status != SFC_MAE_STATUS_SUPPORTED) { 2254 sfc_adapter_unlock(sa); 2255 return -ENOTSUP; 2256 } 2257 2258 rc = sfc_process_mport_journal(sa); 2259 if (rc != 0) { 2260 sfc_adapter_unlock(sa); 2261 SFC_ASSERT(rc > 0); 2262 return -rc; 2263 } 2264 2265 switch_domain_id = sa->mae.switch_domain_id; 2266 2267 nb_repr = 0; 2268 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2269 sfc_count_representors_cb, 2270 &nb_repr); 2271 if (rc != 0) { 2272 sfc_adapter_unlock(sa); 2273 SFC_ASSERT(rc > 0); 2274 return -rc; 2275 } 2276 2277 if (info == NULL) { 2278 sfc_adapter_unlock(sa); 2279 return nb_repr; 2280 } 2281 2282 rc = sfc_mae_switch_domain_controllers(switch_domain_id, 2283 &get_repr_ctx.controllers, 2284 &get_repr_ctx.nb_controllers); 2285 if (rc != 0) { 2286 sfc_adapter_unlock(sa); 2287 SFC_ASSERT(rc > 0); 2288 return -rc; 2289 } 2290 2291 nic_cfg = efx_nic_cfg_get(sa->nic); 2292 2293 rc = sfc_mae_switch_domain_get_controller(switch_domain_id, 2294 nic_cfg->enc_intf, 2295 &controller); 2296 if (rc != 0) { 2297 sfc_err(sa, "invalid controller: %d", nic_cfg->enc_intf); 2298 controller = -1; 2299 } 2300 2301 info->controller = controller; 2302 info->pf = nic_cfg->enc_pf; 2303 2304 get_repr_ctx.info = info; 2305 get_repr_ctx.sa = sa; 2306 get_repr_ctx.switch_domain_id = switch_domain_id; 2307 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2308 sfc_get_representors_cb, 2309 &get_repr_ctx); 2310 if (rc != 0) { 2311 sfc_adapter_unlock(sa); 2312 SFC_ASSERT(rc > 0); 2313 return -rc; 2314 } 2315 2316 sfc_adapter_unlock(sa); 2317 return nb_repr; 2318 } 2319 2320 static int 2321 sfc_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 2322 { 2323 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2324 uint64_t supported = 0; 2325 2326 sfc_adapter_lock(sa); 2327 2328 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_FLAG) != 0) 2329 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 2330 2331 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_MARK) != 0) 2332 supported |= RTE_ETH_RX_METADATA_USER_MARK; 2333 2334 if (sfc_flow_tunnel_is_supported(sa)) 2335 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 2336 2337 sa->negotiated_rx_metadata = supported & *features; 2338 *features = sa->negotiated_rx_metadata; 2339 2340 sfc_adapter_unlock(sa); 2341 2342 return 0; 2343 } 2344 2345 static const struct eth_dev_ops sfc_eth_dev_ops = { 2346 .dev_configure = sfc_dev_configure, 2347 .dev_start = sfc_dev_start, 2348 .dev_stop = sfc_dev_stop, 2349 .dev_set_link_up = sfc_dev_set_link_up, 2350 .dev_set_link_down = sfc_dev_set_link_down, 2351 .dev_close = sfc_dev_close, 2352 .promiscuous_enable = sfc_dev_promisc_enable, 2353 .promiscuous_disable = sfc_dev_promisc_disable, 2354 .allmulticast_enable = sfc_dev_allmulti_enable, 2355 .allmulticast_disable = sfc_dev_allmulti_disable, 2356 .link_update = sfc_dev_link_update, 2357 .stats_get = sfc_stats_get, 2358 .stats_reset = sfc_stats_reset, 2359 .xstats_get = sfc_xstats_get, 2360 .xstats_reset = sfc_stats_reset, 2361 .xstats_get_names = sfc_xstats_get_names, 2362 .dev_infos_get = sfc_dev_infos_get, 2363 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2364 .mtu_set = sfc_dev_set_mtu, 2365 .rx_queue_start = sfc_rx_queue_start, 2366 .rx_queue_stop = sfc_rx_queue_stop, 2367 .tx_queue_start = sfc_tx_queue_start, 2368 .tx_queue_stop = sfc_tx_queue_stop, 2369 .rx_queue_setup = sfc_rx_queue_setup, 2370 .rx_queue_release = sfc_rx_queue_release, 2371 .rx_queue_intr_enable = sfc_rx_queue_intr_enable, 2372 .rx_queue_intr_disable = sfc_rx_queue_intr_disable, 2373 .tx_queue_setup = sfc_tx_queue_setup, 2374 .tx_queue_release = sfc_tx_queue_release, 2375 .flow_ctrl_get = sfc_flow_ctrl_get, 2376 .flow_ctrl_set = sfc_flow_ctrl_set, 2377 .mac_addr_set = sfc_mac_addr_set, 2378 .udp_tunnel_port_add = sfc_dev_udp_tunnel_port_add, 2379 .udp_tunnel_port_del = sfc_dev_udp_tunnel_port_del, 2380 .reta_update = sfc_dev_rss_reta_update, 2381 .reta_query = sfc_dev_rss_reta_query, 2382 .rss_hash_update = sfc_dev_rss_hash_update, 2383 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2384 .flow_ops_get = sfc_dev_flow_ops_get, 2385 .set_mc_addr_list = sfc_set_mc_addr_list, 2386 .rxq_info_get = sfc_rx_queue_info_get, 2387 .txq_info_get = sfc_tx_queue_info_get, 2388 .fw_version_get = sfc_fw_version_get, 2389 .xstats_get_by_id = sfc_xstats_get_by_id, 2390 .xstats_get_names_by_id = sfc_xstats_get_names_by_id, 2391 .pool_ops_supported = sfc_pool_ops_supported, 2392 .representor_info_get = sfc_representor_info_get, 2393 .rx_metadata_negotiate = sfc_rx_metadata_negotiate, 2394 }; 2395 2396 struct sfc_ethdev_init_data { 2397 uint16_t nb_representors; 2398 }; 2399 2400 /** 2401 * Duplicate a string in potentially shared memory required for 2402 * multi-process support. 2403 * 2404 * strdup() allocates from process-local heap/memory. 2405 */ 2406 static char * 2407 sfc_strdup(const char *str) 2408 { 2409 size_t size; 2410 char *copy; 2411 2412 if (str == NULL) 2413 return NULL; 2414 2415 size = strlen(str) + 1; 2416 copy = rte_malloc(__func__, size, 0); 2417 if (copy != NULL) 2418 rte_memcpy(copy, str, size); 2419 2420 return copy; 2421 } 2422 2423 static int 2424 sfc_eth_dev_set_ops(struct rte_eth_dev *dev) 2425 { 2426 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2427 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2428 const struct sfc_dp_rx *dp_rx; 2429 const struct sfc_dp_tx *dp_tx; 2430 const efx_nic_cfg_t *encp; 2431 unsigned int avail_caps = 0; 2432 const char *rx_name = NULL; 2433 const char *tx_name = NULL; 2434 int rc; 2435 2436 switch (sa->family) { 2437 case EFX_FAMILY_HUNTINGTON: 2438 case EFX_FAMILY_MEDFORD: 2439 case EFX_FAMILY_MEDFORD2: 2440 avail_caps |= SFC_DP_HW_FW_CAP_EF10; 2441 avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX; 2442 avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX; 2443 break; 2444 case EFX_FAMILY_RIVERHEAD: 2445 avail_caps |= SFC_DP_HW_FW_CAP_EF100; 2446 break; 2447 default: 2448 break; 2449 } 2450 2451 encp = efx_nic_cfg_get(sa->nic); 2452 if (encp->enc_rx_es_super_buffer_supported) 2453 avail_caps |= SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER; 2454 2455 rc = sfc_kvargs_process(sa, SFC_KVARG_RX_DATAPATH, 2456 sfc_kvarg_string_handler, &rx_name); 2457 if (rc != 0) 2458 goto fail_kvarg_rx_datapath; 2459 2460 if (rx_name != NULL) { 2461 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, rx_name); 2462 if (dp_rx == NULL) { 2463 sfc_err(sa, "Rx datapath %s not found", rx_name); 2464 rc = ENOENT; 2465 goto fail_dp_rx; 2466 } 2467 if (!sfc_dp_match_hw_fw_caps(&dp_rx->dp, avail_caps)) { 2468 sfc_err(sa, 2469 "Insufficient Hw/FW capabilities to use Rx datapath %s", 2470 rx_name); 2471 rc = EINVAL; 2472 goto fail_dp_rx_caps; 2473 } 2474 } else { 2475 dp_rx = sfc_dp_find_rx_by_caps(&sfc_dp_head, avail_caps); 2476 if (dp_rx == NULL) { 2477 sfc_err(sa, "Rx datapath by caps %#x not found", 2478 avail_caps); 2479 rc = ENOENT; 2480 goto fail_dp_rx; 2481 } 2482 } 2483 2484 sas->dp_rx_name = sfc_strdup(dp_rx->dp.name); 2485 if (sas->dp_rx_name == NULL) { 2486 rc = ENOMEM; 2487 goto fail_dp_rx_name; 2488 } 2489 2490 if (strcmp(dp_rx->dp.name, SFC_KVARG_DATAPATH_EF10_ESSB) == 0) { 2491 /* FLAG and MARK are always available from Rx prefix. */ 2492 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_FLAG; 2493 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_MARK; 2494 } 2495 2496 sfc_notice(sa, "use %s Rx datapath", sas->dp_rx_name); 2497 2498 rc = sfc_kvargs_process(sa, SFC_KVARG_TX_DATAPATH, 2499 sfc_kvarg_string_handler, &tx_name); 2500 if (rc != 0) 2501 goto fail_kvarg_tx_datapath; 2502 2503 if (tx_name != NULL) { 2504 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, tx_name); 2505 if (dp_tx == NULL) { 2506 sfc_err(sa, "Tx datapath %s not found", tx_name); 2507 rc = ENOENT; 2508 goto fail_dp_tx; 2509 } 2510 if (!sfc_dp_match_hw_fw_caps(&dp_tx->dp, avail_caps)) { 2511 sfc_err(sa, 2512 "Insufficient Hw/FW capabilities to use Tx datapath %s", 2513 tx_name); 2514 rc = EINVAL; 2515 goto fail_dp_tx_caps; 2516 } 2517 } else { 2518 dp_tx = sfc_dp_find_tx_by_caps(&sfc_dp_head, avail_caps); 2519 if (dp_tx == NULL) { 2520 sfc_err(sa, "Tx datapath by caps %#x not found", 2521 avail_caps); 2522 rc = ENOENT; 2523 goto fail_dp_tx; 2524 } 2525 } 2526 2527 sas->dp_tx_name = sfc_strdup(dp_tx->dp.name); 2528 if (sas->dp_tx_name == NULL) { 2529 rc = ENOMEM; 2530 goto fail_dp_tx_name; 2531 } 2532 2533 sfc_notice(sa, "use %s Tx datapath", sas->dp_tx_name); 2534 2535 sa->priv.dp_rx = dp_rx; 2536 sa->priv.dp_tx = dp_tx; 2537 2538 dev->rx_pkt_burst = dp_rx->pkt_burst; 2539 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2540 dev->tx_pkt_burst = dp_tx->pkt_burst; 2541 2542 dev->rx_queue_count = sfc_rx_queue_count; 2543 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2544 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2545 dev->dev_ops = &sfc_eth_dev_ops; 2546 2547 return 0; 2548 2549 fail_dp_tx_name: 2550 fail_dp_tx_caps: 2551 fail_dp_tx: 2552 fail_kvarg_tx_datapath: 2553 rte_free(sas->dp_rx_name); 2554 sas->dp_rx_name = NULL; 2555 2556 fail_dp_rx_name: 2557 fail_dp_rx_caps: 2558 fail_dp_rx: 2559 fail_kvarg_rx_datapath: 2560 return rc; 2561 } 2562 2563 static void 2564 sfc_eth_dev_clear_ops(struct rte_eth_dev *dev) 2565 { 2566 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2567 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2568 2569 dev->dev_ops = NULL; 2570 dev->tx_pkt_prepare = NULL; 2571 dev->rx_pkt_burst = NULL; 2572 dev->tx_pkt_burst = NULL; 2573 2574 rte_free(sas->dp_tx_name); 2575 sas->dp_tx_name = NULL; 2576 sa->priv.dp_tx = NULL; 2577 2578 rte_free(sas->dp_rx_name); 2579 sas->dp_rx_name = NULL; 2580 sa->priv.dp_rx = NULL; 2581 } 2582 2583 static const struct eth_dev_ops sfc_eth_dev_secondary_ops = { 2584 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2585 .reta_query = sfc_dev_rss_reta_query, 2586 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2587 .rxq_info_get = sfc_rx_queue_info_get, 2588 .txq_info_get = sfc_tx_queue_info_get, 2589 }; 2590 2591 static int 2592 sfc_eth_dev_secondary_init(struct rte_eth_dev *dev, uint32_t logtype_main) 2593 { 2594 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2595 struct sfc_adapter_priv *sap; 2596 const struct sfc_dp_rx *dp_rx; 2597 const struct sfc_dp_tx *dp_tx; 2598 int rc; 2599 2600 /* 2601 * Allocate process private data from heap, since it should not 2602 * be located in shared memory allocated using rte_malloc() API. 2603 */ 2604 sap = calloc(1, sizeof(*sap)); 2605 if (sap == NULL) { 2606 rc = ENOMEM; 2607 goto fail_alloc_priv; 2608 } 2609 2610 sap->logtype_main = logtype_main; 2611 2612 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, sas->dp_rx_name); 2613 if (dp_rx == NULL) { 2614 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2615 "cannot find %s Rx datapath", sas->dp_rx_name); 2616 rc = ENOENT; 2617 goto fail_dp_rx; 2618 } 2619 if (~dp_rx->features & SFC_DP_RX_FEAT_MULTI_PROCESS) { 2620 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2621 "%s Rx datapath does not support multi-process", 2622 sas->dp_rx_name); 2623 rc = EINVAL; 2624 goto fail_dp_rx_multi_process; 2625 } 2626 2627 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, sas->dp_tx_name); 2628 if (dp_tx == NULL) { 2629 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2630 "cannot find %s Tx datapath", sas->dp_tx_name); 2631 rc = ENOENT; 2632 goto fail_dp_tx; 2633 } 2634 if (~dp_tx->features & SFC_DP_TX_FEAT_MULTI_PROCESS) { 2635 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 2636 "%s Tx datapath does not support multi-process", 2637 sas->dp_tx_name); 2638 rc = EINVAL; 2639 goto fail_dp_tx_multi_process; 2640 } 2641 2642 sap->dp_rx = dp_rx; 2643 sap->dp_tx = dp_tx; 2644 2645 dev->process_private = sap; 2646 dev->rx_pkt_burst = dp_rx->pkt_burst; 2647 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2648 dev->tx_pkt_burst = dp_tx->pkt_burst; 2649 dev->rx_queue_count = sfc_rx_queue_count; 2650 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2651 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2652 dev->dev_ops = &sfc_eth_dev_secondary_ops; 2653 2654 return 0; 2655 2656 fail_dp_tx_multi_process: 2657 fail_dp_tx: 2658 fail_dp_rx_multi_process: 2659 fail_dp_rx: 2660 free(sap); 2661 2662 fail_alloc_priv: 2663 return rc; 2664 } 2665 2666 static void 2667 sfc_register_dp(void) 2668 { 2669 /* Register once */ 2670 if (TAILQ_EMPTY(&sfc_dp_head)) { 2671 /* Prefer EF10 datapath */ 2672 sfc_dp_register(&sfc_dp_head, &sfc_ef100_rx.dp); 2673 sfc_dp_register(&sfc_dp_head, &sfc_ef10_essb_rx.dp); 2674 sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp); 2675 sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp); 2676 2677 sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp); 2678 sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp); 2679 sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp); 2680 sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp); 2681 } 2682 } 2683 2684 static int 2685 sfc_parse_switch_mode(struct sfc_adapter *sa, bool has_representors) 2686 { 2687 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 2688 const char *switch_mode = NULL; 2689 int rc; 2690 2691 sfc_log_init(sa, "entry"); 2692 2693 rc = sfc_kvargs_process(sa, SFC_KVARG_SWITCH_MODE, 2694 sfc_kvarg_string_handler, &switch_mode); 2695 if (rc != 0) 2696 goto fail_kvargs; 2697 2698 if (switch_mode == NULL) { 2699 sa->switchdev = encp->enc_mae_supported && 2700 (!encp->enc_datapath_cap_evb || 2701 has_representors); 2702 } else if (strcasecmp(switch_mode, SFC_KVARG_SWITCH_MODE_LEGACY) == 0) { 2703 sa->switchdev = false; 2704 } else if (strcasecmp(switch_mode, 2705 SFC_KVARG_SWITCH_MODE_SWITCHDEV) == 0) { 2706 sa->switchdev = true; 2707 } else { 2708 sfc_err(sa, "invalid switch mode device argument '%s'", 2709 switch_mode); 2710 rc = EINVAL; 2711 goto fail_mode; 2712 } 2713 2714 sfc_log_init(sa, "done"); 2715 2716 return 0; 2717 2718 fail_mode: 2719 fail_kvargs: 2720 sfc_log_init(sa, "failed: %s", rte_strerror(rc)); 2721 2722 return rc; 2723 } 2724 2725 static int 2726 sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params) 2727 { 2728 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2729 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2730 struct sfc_ethdev_init_data *init_data = init_params; 2731 uint32_t logtype_main; 2732 struct sfc_adapter *sa; 2733 int rc; 2734 const efx_nic_cfg_t *encp; 2735 const struct rte_ether_addr *from; 2736 int ret; 2737 2738 if (sfc_efx_dev_class_get(pci_dev->device.devargs) != 2739 SFC_EFX_DEV_CLASS_NET) { 2740 SFC_GENERIC_LOG(DEBUG, 2741 "Incompatible device class: skip probing, should be probed by other sfc driver."); 2742 return 1; 2743 } 2744 2745 rc = sfc_dp_mport_register(); 2746 if (rc != 0) 2747 return rc; 2748 2749 sfc_register_dp(); 2750 2751 logtype_main = sfc_register_logtype(&pci_dev->addr, 2752 SFC_LOGTYPE_MAIN_STR, 2753 RTE_LOG_NOTICE); 2754 2755 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2756 return -sfc_eth_dev_secondary_init(dev, logtype_main); 2757 2758 /* Required for logging */ 2759 ret = snprintf(sas->log_prefix, sizeof(sas->log_prefix), 2760 "PMD: sfc_efx " PCI_PRI_FMT " #%" PRIu16 ": ", 2761 pci_dev->addr.domain, pci_dev->addr.bus, 2762 pci_dev->addr.devid, pci_dev->addr.function, 2763 dev->data->port_id); 2764 if (ret < 0 || ret >= (int)sizeof(sas->log_prefix)) { 2765 SFC_GENERIC_LOG(ERR, 2766 "reserved log prefix is too short for " PCI_PRI_FMT, 2767 pci_dev->addr.domain, pci_dev->addr.bus, 2768 pci_dev->addr.devid, pci_dev->addr.function); 2769 return -EINVAL; 2770 } 2771 sas->pci_addr = pci_dev->addr; 2772 sas->port_id = dev->data->port_id; 2773 2774 /* 2775 * Allocate process private data from heap, since it should not 2776 * be located in shared memory allocated using rte_malloc() API. 2777 */ 2778 sa = calloc(1, sizeof(*sa)); 2779 if (sa == NULL) { 2780 rc = ENOMEM; 2781 goto fail_alloc_sa; 2782 } 2783 2784 dev->process_private = sa; 2785 2786 /* Required for logging */ 2787 sa->priv.shared = sas; 2788 sa->priv.logtype_main = logtype_main; 2789 2790 sa->eth_dev = dev; 2791 2792 /* Copy PCI device info to the dev->data */ 2793 rte_eth_copy_pci_info(dev, pci_dev); 2794 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 2795 2796 rc = sfc_kvargs_parse(sa); 2797 if (rc != 0) 2798 goto fail_kvargs_parse; 2799 2800 sfc_log_init(sa, "entry"); 2801 2802 dev->data->mac_addrs = rte_zmalloc("sfc", RTE_ETHER_ADDR_LEN, 0); 2803 if (dev->data->mac_addrs == NULL) { 2804 rc = ENOMEM; 2805 goto fail_mac_addrs; 2806 } 2807 2808 sfc_adapter_lock_init(sa); 2809 sfc_adapter_lock(sa); 2810 2811 sfc_log_init(sa, "probing"); 2812 rc = sfc_probe(sa); 2813 if (rc != 0) 2814 goto fail_probe; 2815 2816 /* 2817 * Selecting a default switch mode requires the NIC to be probed and 2818 * to have its capabilities filled in. 2819 */ 2820 rc = sfc_parse_switch_mode(sa, init_data->nb_representors > 0); 2821 if (rc != 0) 2822 goto fail_switch_mode; 2823 2824 sfc_log_init(sa, "set device ops"); 2825 rc = sfc_eth_dev_set_ops(dev); 2826 if (rc != 0) 2827 goto fail_set_ops; 2828 2829 sfc_log_init(sa, "attaching"); 2830 rc = sfc_attach(sa); 2831 if (rc != 0) 2832 goto fail_attach; 2833 2834 if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_SUPPORTED) { 2835 sfc_err(sa, 2836 "failed to enable switchdev mode without MAE support"); 2837 rc = ENOTSUP; 2838 goto fail_switchdev_no_mae; 2839 } 2840 2841 encp = efx_nic_cfg_get(sa->nic); 2842 2843 /* 2844 * The arguments are really reverse order in comparison to 2845 * Linux kernel. Copy from NIC config to Ethernet device data. 2846 */ 2847 from = (const struct rte_ether_addr *)(encp->enc_mac_addr); 2848 rte_ether_addr_copy(from, &dev->data->mac_addrs[0]); 2849 2850 sfc_adapter_unlock(sa); 2851 2852 sfc_log_init(sa, "done"); 2853 return 0; 2854 2855 fail_switchdev_no_mae: 2856 sfc_detach(sa); 2857 2858 fail_attach: 2859 sfc_eth_dev_clear_ops(dev); 2860 2861 fail_set_ops: 2862 fail_switch_mode: 2863 sfc_unprobe(sa); 2864 2865 fail_probe: 2866 sfc_adapter_unlock(sa); 2867 sfc_adapter_lock_fini(sa); 2868 rte_free(dev->data->mac_addrs); 2869 dev->data->mac_addrs = NULL; 2870 2871 fail_mac_addrs: 2872 sfc_kvargs_cleanup(sa); 2873 2874 fail_kvargs_parse: 2875 sfc_log_init(sa, "failed %d", rc); 2876 dev->process_private = NULL; 2877 free(sa); 2878 2879 fail_alloc_sa: 2880 SFC_ASSERT(rc > 0); 2881 return -rc; 2882 } 2883 2884 static int 2885 sfc_eth_dev_uninit(struct rte_eth_dev *dev) 2886 { 2887 sfc_dev_close(dev); 2888 2889 return 0; 2890 } 2891 2892 static const struct rte_pci_id pci_id_sfc_efx_map[] = { 2893 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE) }, 2894 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE_VF) }, 2895 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT) }, 2896 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT_VF) }, 2897 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD) }, 2898 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) }, 2899 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) }, 2900 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) }, 2901 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) }, 2902 { .vendor_id = 0 /* sentinel */ } 2903 }; 2904 2905 static int 2906 sfc_parse_rte_devargs(const char *args, struct rte_eth_devargs *devargs) 2907 { 2908 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 2909 int rc; 2910 2911 if (args != NULL) { 2912 rc = rte_eth_devargs_parse(args, ð_da); 2913 if (rc != 0) { 2914 SFC_GENERIC_LOG(ERR, 2915 "Failed to parse generic devargs '%s'", 2916 args); 2917 return rc; 2918 } 2919 } 2920 2921 *devargs = eth_da; 2922 2923 return 0; 2924 } 2925 2926 static int 2927 sfc_eth_dev_find_or_create(struct rte_pci_device *pci_dev, 2928 struct sfc_ethdev_init_data *init_data, 2929 struct rte_eth_dev **devp, 2930 bool *dev_created) 2931 { 2932 struct rte_eth_dev *dev; 2933 bool created = false; 2934 int rc; 2935 2936 dev = rte_eth_dev_allocated(pci_dev->device.name); 2937 if (dev == NULL) { 2938 rc = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 2939 sizeof(struct sfc_adapter_shared), 2940 eth_dev_pci_specific_init, pci_dev, 2941 sfc_eth_dev_init, init_data); 2942 if (rc != 0) { 2943 SFC_GENERIC_LOG(ERR, "Failed to create sfc ethdev '%s'", 2944 pci_dev->device.name); 2945 return rc; 2946 } 2947 2948 created = true; 2949 2950 dev = rte_eth_dev_allocated(pci_dev->device.name); 2951 if (dev == NULL) { 2952 SFC_GENERIC_LOG(ERR, 2953 "Failed to find allocated sfc ethdev '%s'", 2954 pci_dev->device.name); 2955 return -ENODEV; 2956 } 2957 } 2958 2959 *devp = dev; 2960 *dev_created = created; 2961 2962 return 0; 2963 } 2964 2965 static int 2966 sfc_eth_dev_create_repr(struct sfc_adapter *sa, 2967 efx_pcie_interface_t controller, 2968 uint16_t port, 2969 uint16_t repr_port, 2970 enum rte_eth_representor_type type) 2971 { 2972 struct sfc_repr_entity_info entity; 2973 efx_mport_sel_t mport_sel; 2974 int rc; 2975 2976 switch (type) { 2977 case RTE_ETH_REPRESENTOR_NONE: 2978 return 0; 2979 case RTE_ETH_REPRESENTOR_VF: 2980 case RTE_ETH_REPRESENTOR_PF: 2981 break; 2982 case RTE_ETH_REPRESENTOR_SF: 2983 sfc_err(sa, "SF representors are not supported"); 2984 return ENOTSUP; 2985 default: 2986 sfc_err(sa, "unknown representor type: %d", type); 2987 return ENOTSUP; 2988 } 2989 2990 rc = efx_mae_mport_by_pcie_mh_function(controller, 2991 port, 2992 repr_port, 2993 &mport_sel); 2994 if (rc != 0) { 2995 sfc_err(sa, 2996 "failed to get m-port selector for controller %u port %u repr_port %u: %s", 2997 controller, port, repr_port, rte_strerror(-rc)); 2998 return rc; 2999 } 3000 3001 memset(&entity, 0, sizeof(entity)); 3002 entity.type = type; 3003 entity.intf = controller; 3004 entity.pf = port; 3005 entity.vf = repr_port; 3006 3007 rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id, 3008 &mport_sel); 3009 if (rc != 0) { 3010 sfc_err(sa, 3011 "failed to create representor for controller %u port %u repr_port %u: %s", 3012 controller, port, repr_port, rte_strerror(-rc)); 3013 return rc; 3014 } 3015 3016 return 0; 3017 } 3018 3019 static int 3020 sfc_eth_dev_create_repr_port(struct sfc_adapter *sa, 3021 const struct rte_eth_devargs *eth_da, 3022 efx_pcie_interface_t controller, 3023 uint16_t port) 3024 { 3025 int first_error = 0; 3026 uint16_t i; 3027 int rc; 3028 3029 if (eth_da->type == RTE_ETH_REPRESENTOR_PF) { 3030 return sfc_eth_dev_create_repr(sa, controller, port, 3031 EFX_PCI_VF_INVALID, 3032 eth_da->type); 3033 } 3034 3035 for (i = 0; i < eth_da->nb_representor_ports; i++) { 3036 rc = sfc_eth_dev_create_repr(sa, controller, port, 3037 eth_da->representor_ports[i], 3038 eth_da->type); 3039 if (rc != 0 && first_error == 0) 3040 first_error = rc; 3041 } 3042 3043 return first_error; 3044 } 3045 3046 static int 3047 sfc_eth_dev_create_repr_controller(struct sfc_adapter *sa, 3048 const struct rte_eth_devargs *eth_da, 3049 efx_pcie_interface_t controller) 3050 { 3051 const efx_nic_cfg_t *encp; 3052 int first_error = 0; 3053 uint16_t default_port; 3054 uint16_t i; 3055 int rc; 3056 3057 if (eth_da->nb_ports == 0) { 3058 encp = efx_nic_cfg_get(sa->nic); 3059 default_port = encp->enc_intf == controller ? encp->enc_pf : 0; 3060 return sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3061 default_port); 3062 } 3063 3064 for (i = 0; i < eth_da->nb_ports; i++) { 3065 rc = sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3066 eth_da->ports[i]); 3067 if (rc != 0 && first_error == 0) 3068 first_error = rc; 3069 } 3070 3071 return first_error; 3072 } 3073 3074 static int 3075 sfc_eth_dev_create_representors(struct rte_eth_dev *dev, 3076 const struct rte_eth_devargs *eth_da) 3077 { 3078 efx_pcie_interface_t intf; 3079 const efx_nic_cfg_t *encp; 3080 struct sfc_adapter *sa; 3081 uint16_t switch_domain_id; 3082 uint16_t i; 3083 int rc; 3084 3085 sa = sfc_adapter_by_eth_dev(dev); 3086 switch_domain_id = sa->mae.switch_domain_id; 3087 3088 switch (eth_da->type) { 3089 case RTE_ETH_REPRESENTOR_NONE: 3090 return 0; 3091 case RTE_ETH_REPRESENTOR_PF: 3092 case RTE_ETH_REPRESENTOR_VF: 3093 break; 3094 case RTE_ETH_REPRESENTOR_SF: 3095 sfc_err(sa, "SF representors are not supported"); 3096 return -ENOTSUP; 3097 default: 3098 sfc_err(sa, "unknown representor type: %d", 3099 eth_da->type); 3100 return -ENOTSUP; 3101 } 3102 3103 if (!sa->switchdev) { 3104 sfc_err(sa, "cannot create representors in non-switchdev mode"); 3105 return -EINVAL; 3106 } 3107 3108 if (!sfc_repr_available(sfc_sa2shared(sa))) { 3109 sfc_err(sa, "cannot create representors: unsupported"); 3110 3111 return -ENOTSUP; 3112 } 3113 3114 /* 3115 * This is needed to construct the DPDK controller -> EFX interface 3116 * mapping. 3117 */ 3118 sfc_adapter_lock(sa); 3119 rc = sfc_process_mport_journal(sa); 3120 sfc_adapter_unlock(sa); 3121 if (rc != 0) { 3122 SFC_ASSERT(rc > 0); 3123 return -rc; 3124 } 3125 3126 if (eth_da->nb_mh_controllers > 0) { 3127 for (i = 0; i < eth_da->nb_mh_controllers; i++) { 3128 rc = sfc_mae_switch_domain_get_intf(switch_domain_id, 3129 eth_da->mh_controllers[i], 3130 &intf); 3131 if (rc != 0) { 3132 sfc_err(sa, "failed to get representor"); 3133 continue; 3134 } 3135 sfc_eth_dev_create_repr_controller(sa, eth_da, intf); 3136 } 3137 } else { 3138 encp = efx_nic_cfg_get(sa->nic); 3139 sfc_eth_dev_create_repr_controller(sa, eth_da, encp->enc_intf); 3140 } 3141 3142 return 0; 3143 } 3144 3145 static int sfc_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3146 struct rte_pci_device *pci_dev) 3147 { 3148 struct sfc_ethdev_init_data init_data; 3149 struct rte_eth_devargs eth_da; 3150 struct rte_eth_dev *dev; 3151 bool dev_created; 3152 int rc; 3153 3154 if (pci_dev->device.devargs != NULL) { 3155 rc = sfc_parse_rte_devargs(pci_dev->device.devargs->args, 3156 ð_da); 3157 if (rc != 0) 3158 return rc; 3159 } else { 3160 memset(ð_da, 0, sizeof(eth_da)); 3161 } 3162 3163 /* If no VF representors specified, check for PF ones */ 3164 if (eth_da.nb_representor_ports > 0) 3165 init_data.nb_representors = eth_da.nb_representor_ports; 3166 else 3167 init_data.nb_representors = eth_da.nb_ports; 3168 3169 if (init_data.nb_representors > 0 && 3170 rte_eal_process_type() != RTE_PROC_PRIMARY) { 3171 SFC_GENERIC_LOG(ERR, 3172 "Create representors from secondary process not supported, dev '%s'", 3173 pci_dev->device.name); 3174 return -ENOTSUP; 3175 } 3176 3177 /* 3178 * Driver supports RTE_PCI_DRV_PROBE_AGAIN. Hence create device only 3179 * if it does not already exist. Re-probing an existing device is 3180 * expected to allow additional representors to be configured. 3181 */ 3182 rc = sfc_eth_dev_find_or_create(pci_dev, &init_data, &dev, 3183 &dev_created); 3184 if (rc != 0) 3185 return rc; 3186 3187 rc = sfc_eth_dev_create_representors(dev, ð_da); 3188 if (rc != 0) { 3189 if (dev_created) 3190 (void)rte_eth_dev_destroy(dev, sfc_eth_dev_uninit); 3191 3192 return rc; 3193 } 3194 3195 return 0; 3196 } 3197 3198 static int sfc_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3199 { 3200 return rte_eth_dev_pci_generic_remove(pci_dev, sfc_eth_dev_uninit); 3201 } 3202 3203 static struct rte_pci_driver sfc_efx_pmd = { 3204 .id_table = pci_id_sfc_efx_map, 3205 .drv_flags = 3206 RTE_PCI_DRV_INTR_LSC | 3207 RTE_PCI_DRV_NEED_MAPPING | 3208 RTE_PCI_DRV_PROBE_AGAIN, 3209 .probe = sfc_eth_dev_pci_probe, 3210 .remove = sfc_eth_dev_pci_remove, 3211 }; 3212 3213 RTE_PMD_REGISTER_PCI(net_sfc_efx, sfc_efx_pmd); 3214 RTE_PMD_REGISTER_PCI_TABLE(net_sfc_efx, pci_id_sfc_efx_map); 3215 RTE_PMD_REGISTER_KMOD_DEP(net_sfc_efx, "* igb_uio | uio_pci_generic | vfio-pci"); 3216 RTE_PMD_REGISTER_PARAM_STRING(net_sfc_efx, 3217 SFC_KVARG_SWITCH_MODE "=" SFC_KVARG_VALUES_SWITCH_MODE " " 3218 SFC_KVARG_RX_DATAPATH "=" SFC_KVARG_VALUES_RX_DATAPATH " " 3219 SFC_KVARG_TX_DATAPATH "=" SFC_KVARG_VALUES_TX_DATAPATH " " 3220 SFC_KVARG_PERF_PROFILE "=" SFC_KVARG_VALUES_PERF_PROFILE " " 3221 SFC_KVARG_FW_VARIANT "=" SFC_KVARG_VALUES_FW_VARIANT " " 3222 SFC_KVARG_RXD_WAIT_TIMEOUT_NS "=<long> " 3223 SFC_KVARG_STATS_UPDATE_PERIOD_MS "=<long>"); 3224 3225 RTE_INIT(sfc_driver_register_logtype) 3226 { 3227 int ret; 3228 3229 ret = rte_log_register_type_and_pick_level(SFC_LOGTYPE_PREFIX "driver", 3230 RTE_LOG_NOTICE); 3231 sfc_logtype_driver = (ret < 0) ? RTE_LOGTYPE_PMD : ret; 3232 } 3233