1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <dev_driver.h> 11 #include <ethdev_driver.h> 12 #include <ethdev_pci.h> 13 #include <rte_pci.h> 14 #include <bus_pci_driver.h> 15 #include <rte_errno.h> 16 #include <rte_string_fns.h> 17 #include <rte_ether.h> 18 19 #include "efx.h" 20 21 #include "sfc.h" 22 #include "sfc_debug.h" 23 #include "sfc_log.h" 24 #include "sfc_kvargs.h" 25 #include "sfc_ev.h" 26 #include "sfc_rx.h" 27 #include "sfc_tx.h" 28 #include "sfc_flow.h" 29 #include "sfc_flow_tunnel.h" 30 #include "sfc_dp.h" 31 #include "sfc_dp_rx.h" 32 #include "sfc_repr.h" 33 #include "sfc_sw_stats.h" 34 #include "sfc_switch.h" 35 #include "sfc_nic_dma.h" 36 37 #define SFC_XSTAT_ID_INVALID_VAL UINT64_MAX 38 #define SFC_XSTAT_ID_INVALID_NAME '\0' 39 40 uint32_t sfc_logtype_driver; 41 42 static struct sfc_dp_list sfc_dp_head = 43 TAILQ_HEAD_INITIALIZER(sfc_dp_head); 44 45 46 static void sfc_eth_dev_clear_ops(struct rte_eth_dev *dev); 47 48 49 static int 50 sfc_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 51 { 52 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 53 efx_nic_fw_info_t enfi; 54 int ret; 55 int rc; 56 57 rc = efx_nic_get_fw_version(sa->nic, &enfi); 58 if (rc != 0) 59 return -rc; 60 61 ret = snprintf(fw_version, fw_size, 62 "%" PRIu16 ".%" PRIu16 ".%" PRIu16 ".%" PRIu16, 63 enfi.enfi_mc_fw_version[0], enfi.enfi_mc_fw_version[1], 64 enfi.enfi_mc_fw_version[2], enfi.enfi_mc_fw_version[3]); 65 if (ret < 0) 66 return ret; 67 68 if (enfi.enfi_dpcpu_fw_ids_valid) { 69 size_t dpcpu_fw_ids_offset = MIN(fw_size - 1, (size_t)ret); 70 int ret_extra; 71 72 ret_extra = snprintf(fw_version + dpcpu_fw_ids_offset, 73 fw_size - dpcpu_fw_ids_offset, 74 " rx%" PRIx16 " tx%" PRIx16, 75 enfi.enfi_rx_dpcpu_fw_id, 76 enfi.enfi_tx_dpcpu_fw_id); 77 if (ret_extra < 0) 78 return ret_extra; 79 80 ret += ret_extra; 81 } 82 83 if (fw_size < (size_t)(++ret)) 84 return ret; 85 else 86 return 0; 87 } 88 89 static int 90 sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 91 { 92 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 93 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 94 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 95 struct sfc_rss *rss = &sas->rss; 96 struct sfc_mae *mae = &sa->mae; 97 98 sfc_log_init(sa, "entry"); 99 100 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 101 dev_info->max_mtu = EFX_MAC_SDU_MAX; 102 103 dev_info->max_rx_pktlen = EFX_MAC_PDU_MAX; 104 105 dev_info->max_vfs = sa->sriov.num_vfs; 106 107 /* Autonegotiation may be disabled */ 108 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 109 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX)) 110 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_1G; 111 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX)) 112 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10G; 113 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX)) 114 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G; 115 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX)) 116 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 117 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX)) 118 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G; 119 if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX)) 120 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G; 121 122 dev_info->max_rx_queues = sa->rxq_max; 123 dev_info->max_tx_queues = sa->txq_max; 124 125 /* By default packets are dropped if no descriptors are available */ 126 dev_info->default_rxconf.rx_drop_en = 1; 127 128 dev_info->rx_queue_offload_capa = sfc_rx_get_queue_offload_caps(sa); 129 130 /* 131 * rx_offload_capa includes both device and queue offloads since 132 * the latter may be requested on a per device basis which makes 133 * sense when some offloads are needed to be set on all queues. 134 */ 135 dev_info->rx_offload_capa = sfc_rx_get_dev_offload_caps(sa) | 136 dev_info->rx_queue_offload_capa; 137 138 dev_info->tx_queue_offload_capa = sfc_tx_get_queue_offload_caps(sa); 139 140 /* 141 * tx_offload_capa includes both device and queue offloads since 142 * the latter may be requested on a per device basis which makes 143 * sense when some offloads are needed to be set on all queues. 144 */ 145 dev_info->tx_offload_capa = sfc_tx_get_dev_offload_caps(sa) | 146 dev_info->tx_queue_offload_capa; 147 148 if (rss->context_type != EFX_RX_SCALE_UNAVAILABLE) { 149 uint64_t rte_hf = 0; 150 unsigned int i; 151 152 for (i = 0; i < rss->hf_map_nb_entries; ++i) 153 rte_hf |= rss->hf_map[i].rte; 154 155 dev_info->reta_size = EFX_RSS_TBL_SIZE; 156 dev_info->hash_key_size = EFX_RSS_KEY_SIZE; 157 dev_info->flow_type_rss_offloads = rte_hf; 158 } 159 160 /* Initialize to hardware limits */ 161 dev_info->rx_desc_lim.nb_max = sa->rxq_max_entries; 162 dev_info->rx_desc_lim.nb_min = sa->rxq_min_entries; 163 /* The RXQ hardware requires that the descriptor count is a power 164 * of 2, but rx_desc_lim cannot properly describe that constraint. 165 */ 166 dev_info->rx_desc_lim.nb_align = sa->rxq_min_entries; 167 168 /* Initialize to hardware limits */ 169 dev_info->tx_desc_lim.nb_max = sa->txq_max_entries; 170 dev_info->tx_desc_lim.nb_min = sa->txq_min_entries; 171 /* 172 * The TXQ hardware requires that the descriptor count is a power 173 * of 2, but tx_desc_lim cannot properly describe that constraint 174 */ 175 dev_info->tx_desc_lim.nb_align = sa->txq_min_entries; 176 177 if (sap->dp_rx->get_dev_info != NULL) 178 sap->dp_rx->get_dev_info(dev_info); 179 if (sap->dp_tx->get_dev_info != NULL) 180 sap->dp_tx->get_dev_info(dev_info); 181 182 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 183 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 184 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 185 186 if (mae->status == SFC_MAE_STATUS_SUPPORTED || 187 mae->status == SFC_MAE_STATUS_ADMIN) { 188 dev_info->switch_info.name = dev->device->driver->name; 189 dev_info->switch_info.domain_id = mae->switch_domain_id; 190 dev_info->switch_info.port_id = mae->switch_port_id; 191 } 192 193 return 0; 194 } 195 196 static const uint32_t * 197 sfc_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 198 { 199 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 200 201 return sap->dp_rx->supported_ptypes_get(sap->shared->tunnel_encaps, 202 no_of_elements); 203 } 204 205 static int 206 sfc_dev_configure(struct rte_eth_dev *dev) 207 { 208 struct rte_eth_dev_data *dev_data = dev->data; 209 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 210 int rc; 211 212 sfc_log_init(sa, "entry n_rxq=%u n_txq=%u", 213 dev_data->nb_rx_queues, dev_data->nb_tx_queues); 214 215 sfc_adapter_lock(sa); 216 switch (sa->state) { 217 case SFC_ETHDEV_CONFIGURED: 218 /* FALLTHROUGH */ 219 case SFC_ETHDEV_INITIALIZED: 220 rc = sfc_configure(sa); 221 break; 222 default: 223 sfc_err(sa, "unexpected adapter state %u to configure", 224 sa->state); 225 rc = EINVAL; 226 break; 227 } 228 sfc_adapter_unlock(sa); 229 230 sfc_log_init(sa, "done %d", rc); 231 SFC_ASSERT(rc >= 0); 232 return -rc; 233 } 234 235 static int 236 sfc_dev_start(struct rte_eth_dev *dev) 237 { 238 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 239 int rc; 240 241 sfc_log_init(sa, "entry"); 242 243 sfc_adapter_lock(sa); 244 rc = sfc_start(sa); 245 sfc_adapter_unlock(sa); 246 247 sfc_log_init(sa, "done %d", rc); 248 SFC_ASSERT(rc >= 0); 249 return -rc; 250 } 251 252 static void 253 sfc_dev_get_rte_link(struct rte_eth_dev *dev, int wait_to_complete, 254 struct rte_eth_link *link) 255 { 256 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 257 258 SFC_ASSERT(link != NULL); 259 260 if (sa->state != SFC_ETHDEV_STARTED) { 261 sfc_port_link_mode_to_info(EFX_LINK_UNKNOWN, link); 262 } else if (wait_to_complete) { 263 efx_link_mode_t link_mode; 264 265 if (efx_port_poll(sa->nic, &link_mode) != 0) 266 link_mode = EFX_LINK_UNKNOWN; 267 sfc_port_link_mode_to_info(link_mode, link); 268 } else { 269 sfc_ev_mgmt_qpoll(sa); 270 rte_eth_linkstatus_get(dev, link); 271 } 272 } 273 274 static int 275 sfc_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 276 { 277 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 278 struct rte_eth_link current_link; 279 int ret; 280 281 sfc_log_init(sa, "entry"); 282 283 sfc_dev_get_rte_link(dev, wait_to_complete, ¤t_link); 284 285 ret = rte_eth_linkstatus_set(dev, ¤t_link); 286 if (ret == 0) 287 sfc_notice(sa, "Link status is %s", 288 current_link.link_status ? "UP" : "DOWN"); 289 290 return ret; 291 } 292 293 static int 294 sfc_dev_stop(struct rte_eth_dev *dev) 295 { 296 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 297 298 sfc_log_init(sa, "entry"); 299 300 sfc_adapter_lock(sa); 301 sfc_stop(sa); 302 sfc_adapter_unlock(sa); 303 304 sfc_log_init(sa, "done"); 305 306 return 0; 307 } 308 309 static int 310 sfc_dev_set_link_up(struct rte_eth_dev *dev) 311 { 312 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 313 int rc; 314 315 sfc_log_init(sa, "entry"); 316 317 sfc_adapter_lock(sa); 318 rc = sfc_start(sa); 319 sfc_adapter_unlock(sa); 320 321 SFC_ASSERT(rc >= 0); 322 return -rc; 323 } 324 325 static int 326 sfc_dev_set_link_down(struct rte_eth_dev *dev) 327 { 328 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 329 330 sfc_log_init(sa, "entry"); 331 332 sfc_adapter_lock(sa); 333 sfc_stop(sa); 334 sfc_adapter_unlock(sa); 335 336 return 0; 337 } 338 339 static void 340 sfc_eth_dev_secondary_clear_ops(struct rte_eth_dev *dev) 341 { 342 free(dev->process_private); 343 rte_eth_dev_release_port(dev); 344 } 345 346 static int 347 sfc_dev_close(struct rte_eth_dev *dev) 348 { 349 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 350 351 sfc_log_init(sa, "entry"); 352 353 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 354 sfc_eth_dev_secondary_clear_ops(dev); 355 return 0; 356 } 357 358 sfc_pre_detach(sa); 359 360 sfc_adapter_lock(sa); 361 switch (sa->state) { 362 case SFC_ETHDEV_STARTED: 363 sfc_stop(sa); 364 SFC_ASSERT(sa->state == SFC_ETHDEV_CONFIGURED); 365 /* FALLTHROUGH */ 366 case SFC_ETHDEV_CONFIGURED: 367 sfc_close(sa); 368 SFC_ASSERT(sa->state == SFC_ETHDEV_INITIALIZED); 369 /* FALLTHROUGH */ 370 case SFC_ETHDEV_INITIALIZED: 371 break; 372 default: 373 sfc_err(sa, "unexpected adapter state %u on close", sa->state); 374 break; 375 } 376 377 /* 378 * Cleanup all resources. 379 * Rollback primary process sfc_eth_dev_init() below. 380 */ 381 382 sfc_eth_dev_clear_ops(dev); 383 384 sfc_nic_dma_detach(sa); 385 sfc_detach(sa); 386 sfc_unprobe(sa); 387 388 sfc_kvargs_cleanup(sa); 389 390 sfc_adapter_unlock(sa); 391 sfc_adapter_lock_fini(sa); 392 393 sfc_log_init(sa, "done"); 394 395 /* Required for logging, so cleanup last */ 396 sa->eth_dev = NULL; 397 398 free(sa); 399 400 return 0; 401 } 402 403 static int 404 sfc_dev_filter_set(struct rte_eth_dev *dev, enum sfc_dev_filter_mode mode, 405 boolean_t enabled) 406 { 407 struct sfc_port *port; 408 boolean_t *toggle; 409 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 410 boolean_t allmulti = (mode == SFC_DEV_FILTER_MODE_ALLMULTI); 411 const char *desc = (allmulti) ? "all-multi" : "promiscuous"; 412 int rc = 0; 413 414 sfc_adapter_lock(sa); 415 416 port = &sa->port; 417 toggle = (allmulti) ? (&port->allmulti) : (&port->promisc); 418 419 if (*toggle != enabled) { 420 *toggle = enabled; 421 422 if (sfc_sa2shared(sa)->isolated) { 423 sfc_warn(sa, "isolated mode is active on the port"); 424 sfc_warn(sa, "the change is to be applied on the next " 425 "start provided that isolated mode is " 426 "disabled prior the next start"); 427 } else if ((sa->state == SFC_ETHDEV_STARTED) && 428 ((rc = sfc_set_rx_mode(sa)) != 0)) { 429 *toggle = !(enabled); 430 sfc_warn(sa, "Failed to %s %s mode, rc = %d", 431 ((enabled) ? "enable" : "disable"), desc, rc); 432 433 /* 434 * For promiscuous and all-multicast filters a 435 * permission failure should be reported as an 436 * unsupported filter. 437 */ 438 if (rc == EPERM) 439 rc = ENOTSUP; 440 } 441 } 442 443 sfc_adapter_unlock(sa); 444 return rc; 445 } 446 447 static int 448 sfc_dev_promisc_enable(struct rte_eth_dev *dev) 449 { 450 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_TRUE); 451 452 SFC_ASSERT(rc >= 0); 453 return -rc; 454 } 455 456 static int 457 sfc_dev_promisc_disable(struct rte_eth_dev *dev) 458 { 459 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_PROMISC, B_FALSE); 460 461 SFC_ASSERT(rc >= 0); 462 return -rc; 463 } 464 465 static int 466 sfc_dev_allmulti_enable(struct rte_eth_dev *dev) 467 { 468 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_TRUE); 469 470 SFC_ASSERT(rc >= 0); 471 return -rc; 472 } 473 474 static int 475 sfc_dev_allmulti_disable(struct rte_eth_dev *dev) 476 { 477 int rc = sfc_dev_filter_set(dev, SFC_DEV_FILTER_MODE_ALLMULTI, B_FALSE); 478 479 SFC_ASSERT(rc >= 0); 480 return -rc; 481 } 482 483 static int 484 sfc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 485 uint16_t nb_rx_desc, unsigned int socket_id, 486 const struct rte_eth_rxconf *rx_conf, 487 struct rte_mempool *mb_pool) 488 { 489 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 490 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 491 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 492 struct sfc_rxq_info *rxq_info; 493 sfc_sw_index_t sw_index; 494 int rc; 495 496 sfc_log_init(sa, "RxQ=%u nb_rx_desc=%u socket_id=%u", 497 ethdev_qid, nb_rx_desc, socket_id); 498 499 sfc_adapter_lock(sa); 500 501 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 502 rc = sfc_rx_qinit(sa, sw_index, nb_rx_desc, socket_id, 503 rx_conf, mb_pool); 504 if (rc != 0) 505 goto fail_rx_qinit; 506 507 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 508 dev->data->rx_queues[ethdev_qid] = rxq_info->dp; 509 510 sfc_adapter_unlock(sa); 511 512 return 0; 513 514 fail_rx_qinit: 515 sfc_adapter_unlock(sa); 516 SFC_ASSERT(rc > 0); 517 return -rc; 518 } 519 520 static void 521 sfc_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 522 { 523 struct sfc_dp_rxq *dp_rxq = dev->data->rx_queues[qid]; 524 struct sfc_rxq *rxq; 525 struct sfc_adapter *sa; 526 sfc_sw_index_t sw_index; 527 528 if (dp_rxq == NULL) 529 return; 530 531 rxq = sfc_rxq_by_dp_rxq(dp_rxq); 532 sa = rxq->evq->sa; 533 sfc_adapter_lock(sa); 534 535 sw_index = dp_rxq->dpq.queue_id; 536 537 sfc_log_init(sa, "RxQ=%u", sw_index); 538 539 sfc_rx_qfini(sa, sw_index); 540 541 sfc_adapter_unlock(sa); 542 } 543 544 static int 545 sfc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t ethdev_qid, 546 uint16_t nb_tx_desc, unsigned int socket_id, 547 const struct rte_eth_txconf *tx_conf) 548 { 549 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 550 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 551 struct sfc_txq_info *txq_info; 552 sfc_sw_index_t sw_index; 553 int rc; 554 555 sfc_log_init(sa, "TxQ = %u, nb_tx_desc = %u, socket_id = %u", 556 ethdev_qid, nb_tx_desc, socket_id); 557 558 sfc_adapter_lock(sa); 559 560 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 561 rc = sfc_tx_qinit(sa, sw_index, nb_tx_desc, socket_id, tx_conf); 562 if (rc != 0) 563 goto fail_tx_qinit; 564 565 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 566 dev->data->tx_queues[ethdev_qid] = txq_info->dp; 567 568 sfc_adapter_unlock(sa); 569 return 0; 570 571 fail_tx_qinit: 572 sfc_adapter_unlock(sa); 573 SFC_ASSERT(rc > 0); 574 return -rc; 575 } 576 577 static void 578 sfc_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 579 { 580 struct sfc_dp_txq *dp_txq = dev->data->tx_queues[qid]; 581 struct sfc_txq *txq; 582 sfc_sw_index_t sw_index; 583 struct sfc_adapter *sa; 584 585 if (dp_txq == NULL) 586 return; 587 588 txq = sfc_txq_by_dp_txq(dp_txq); 589 sw_index = dp_txq->dpq.queue_id; 590 591 SFC_ASSERT(txq->evq != NULL); 592 sa = txq->evq->sa; 593 594 sfc_log_init(sa, "TxQ = %u", sw_index); 595 596 sfc_adapter_lock(sa); 597 598 sfc_tx_qfini(sa, sw_index); 599 600 sfc_adapter_unlock(sa); 601 } 602 603 static void 604 sfc_stats_get_dp_rx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 605 { 606 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 607 uint64_t pkts_sum = 0; 608 uint64_t bytes_sum = 0; 609 unsigned int i; 610 611 for (i = 0; i < sas->ethdev_rxq_count; ++i) { 612 struct sfc_rxq_info *rxq_info; 613 614 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, i); 615 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 616 union sfc_pkts_bytes qstats; 617 618 sfc_pkts_bytes_get(&rxq_info->dp->dpq.stats, &qstats); 619 pkts_sum += qstats.pkts - 620 sa->sw_stats.reset_rx_pkts[i]; 621 bytes_sum += qstats.bytes - 622 sa->sw_stats.reset_rx_bytes[i]; 623 } 624 } 625 626 *pkts = pkts_sum; 627 *bytes = bytes_sum; 628 } 629 630 static void 631 sfc_stats_get_dp_tx(struct sfc_adapter *sa, uint64_t *pkts, uint64_t *bytes) 632 { 633 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 634 uint64_t pkts_sum = 0; 635 uint64_t bytes_sum = 0; 636 unsigned int i; 637 638 for (i = 0; i < sas->ethdev_txq_count; ++i) { 639 struct sfc_txq_info *txq_info; 640 641 txq_info = sfc_txq_info_by_ethdev_qid(sas, i); 642 if (txq_info->state & SFC_TXQ_INITIALIZED) { 643 union sfc_pkts_bytes qstats; 644 645 sfc_pkts_bytes_get(&txq_info->dp->dpq.stats, &qstats); 646 pkts_sum += qstats.pkts - 647 sa->sw_stats.reset_tx_pkts[i]; 648 bytes_sum += qstats.bytes - 649 sa->sw_stats.reset_tx_bytes[i]; 650 } 651 } 652 653 *pkts = pkts_sum; 654 *bytes = bytes_sum; 655 } 656 657 /* 658 * Some statistics are computed as A - B where A and B each increase 659 * monotonically with some hardware counter(s) and the counters are read 660 * asynchronously. 661 * 662 * If packet X is counted in A, but not counted in B yet, computed value is 663 * greater than real. 664 * 665 * If packet X is not counted in A at the moment of reading the counter, 666 * but counted in B at the moment of reading the counter, computed value 667 * is less than real. 668 * 669 * However, counter which grows backward is worse evil than slightly wrong 670 * value. So, let's try to guarantee that it never happens except may be 671 * the case when the MAC stats are zeroed as a result of a NIC reset. 672 */ 673 static void 674 sfc_update_diff_stat(uint64_t *stat, uint64_t newval) 675 { 676 if ((int64_t)(newval - *stat) > 0 || newval == 0) 677 *stat = newval; 678 } 679 680 static int 681 sfc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 682 { 683 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 684 bool have_dp_rx_stats = sap->dp_rx->features & SFC_DP_RX_FEAT_STATS; 685 bool have_dp_tx_stats = sap->dp_tx->features & SFC_DP_TX_FEAT_STATS; 686 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 687 struct sfc_port *port = &sa->port; 688 uint64_t *mac_stats; 689 int ret; 690 691 sfc_adapter_lock(sa); 692 693 if (have_dp_rx_stats) { 694 sfc_stats_get_dp_rx(sa, &stats->ipackets, &stats->ibytes); 695 if (dev->data->dev_conf.rxmode.offloads & 696 RTE_ETH_RX_OFFLOAD_KEEP_CRC) { 697 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 698 } 699 } 700 if (have_dp_tx_stats) 701 sfc_stats_get_dp_tx(sa, &stats->opackets, &stats->obytes); 702 703 ret = sfc_port_update_mac_stats(sa, B_FALSE); 704 if (ret != 0) 705 goto unlock; 706 707 mac_stats = port->mac_stats_buf; 708 709 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, 710 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS)) { 711 if (!have_dp_rx_stats) { 712 stats->ipackets = 713 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS] + 714 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS] + 715 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]; 716 stats->ibytes = 717 mac_stats[EFX_MAC_VADAPTER_RX_UNICAST_BYTES] + 718 mac_stats[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES] + 719 mac_stats[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]; 720 721 /* CRC is included in these stats, but shouldn't be */ 722 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN; 723 } 724 if (!have_dp_tx_stats) { 725 stats->opackets = 726 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS] + 727 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS] + 728 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]; 729 stats->obytes = 730 mac_stats[EFX_MAC_VADAPTER_TX_UNICAST_BYTES] + 731 mac_stats[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES] + 732 mac_stats[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]; 733 734 /* CRC is included in these stats, but shouldn't be */ 735 stats->obytes -= stats->opackets * RTE_ETHER_CRC_LEN; 736 } 737 stats->imissed = mac_stats[EFX_MAC_VADAPTER_RX_BAD_PACKETS]; 738 stats->oerrors = mac_stats[EFX_MAC_VADAPTER_TX_BAD_PACKETS]; 739 } else { 740 if (!have_dp_tx_stats) { 741 stats->opackets = mac_stats[EFX_MAC_TX_PKTS]; 742 stats->obytes = mac_stats[EFX_MAC_TX_OCTETS] - 743 mac_stats[EFX_MAC_TX_PKTS] * RTE_ETHER_CRC_LEN; 744 } 745 746 /* 747 * Take into account stats which are whenever supported 748 * on EF10. If some stat is not supported by current 749 * firmware variant or HW revision, it is guaranteed 750 * to be zero in mac_stats. 751 */ 752 stats->imissed = 753 mac_stats[EFX_MAC_RX_NODESC_DROP_CNT] + 754 mac_stats[EFX_MAC_PM_TRUNC_BB_OVERFLOW] + 755 mac_stats[EFX_MAC_PM_DISCARD_BB_OVERFLOW] + 756 mac_stats[EFX_MAC_PM_TRUNC_VFIFO_FULL] + 757 mac_stats[EFX_MAC_PM_DISCARD_VFIFO_FULL] + 758 mac_stats[EFX_MAC_PM_TRUNC_QBB] + 759 mac_stats[EFX_MAC_PM_DISCARD_QBB] + 760 mac_stats[EFX_MAC_PM_DISCARD_MAPPING] + 761 mac_stats[EFX_MAC_RXDP_Q_DISABLED_PKTS] + 762 mac_stats[EFX_MAC_RXDP_DI_DROPPED_PKTS]; 763 stats->ierrors = 764 mac_stats[EFX_MAC_RX_FCS_ERRORS] + 765 mac_stats[EFX_MAC_RX_ALIGN_ERRORS] + 766 mac_stats[EFX_MAC_RX_JABBER_PKTS]; 767 /* no oerrors counters supported on EF10 */ 768 769 if (!have_dp_rx_stats) { 770 /* Exclude missed, errors and pauses from Rx packets */ 771 sfc_update_diff_stat(&port->ipackets, 772 mac_stats[EFX_MAC_RX_PKTS] - 773 mac_stats[EFX_MAC_RX_PAUSE_PKTS] - 774 stats->imissed - stats->ierrors); 775 stats->ipackets = port->ipackets; 776 stats->ibytes = mac_stats[EFX_MAC_RX_OCTETS] - 777 mac_stats[EFX_MAC_RX_PKTS] * RTE_ETHER_CRC_LEN; 778 } 779 } 780 781 unlock: 782 sfc_adapter_unlock(sa); 783 SFC_ASSERT(ret >= 0); 784 return -ret; 785 } 786 787 static int 788 sfc_stats_reset(struct rte_eth_dev *dev) 789 { 790 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 791 struct sfc_port *port = &sa->port; 792 int rc; 793 794 sfc_adapter_lock(sa); 795 796 if (sa->state != SFC_ETHDEV_STARTED) { 797 /* 798 * The operation cannot be done if port is not started; it 799 * will be scheduled to be done during the next port start 800 */ 801 port->mac_stats_reset_pending = B_TRUE; 802 sfc_adapter_unlock(sa); 803 return 0; 804 } 805 806 rc = sfc_port_reset_mac_stats(sa); 807 if (rc != 0) 808 sfc_err(sa, "failed to reset statistics (rc = %d)", rc); 809 810 sfc_sw_xstats_reset(sa); 811 812 sfc_adapter_unlock(sa); 813 814 SFC_ASSERT(rc >= 0); 815 return -rc; 816 } 817 818 static unsigned int 819 sfc_xstats_get_nb_supported(struct sfc_adapter *sa) 820 { 821 struct sfc_port *port = &sa->port; 822 unsigned int nb_supported; 823 824 sfc_adapter_lock(sa); 825 nb_supported = port->mac_stats_nb_supported + 826 sfc_sw_xstats_get_nb_supported(sa); 827 sfc_adapter_unlock(sa); 828 829 return nb_supported; 830 } 831 832 static int 833 sfc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 834 unsigned int xstats_count) 835 { 836 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 837 unsigned int nb_written = 0; 838 unsigned int nb_supported = 0; 839 int rc; 840 841 if (unlikely(xstats == NULL)) 842 return sfc_xstats_get_nb_supported(sa); 843 844 rc = sfc_port_get_mac_stats(sa, xstats, xstats_count, &nb_written); 845 if (rc < 0) 846 return rc; 847 848 nb_supported = rc; 849 sfc_sw_xstats_get_vals(sa, xstats, xstats_count, &nb_written, 850 &nb_supported); 851 852 return nb_supported; 853 } 854 855 static int 856 sfc_xstats_get_names(struct rte_eth_dev *dev, 857 struct rte_eth_xstat_name *xstats_names, 858 unsigned int xstats_count) 859 { 860 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 861 struct sfc_port *port = &sa->port; 862 unsigned int i; 863 unsigned int nstats = 0; 864 unsigned int nb_written = 0; 865 int ret; 866 867 if (unlikely(xstats_names == NULL)) 868 return sfc_xstats_get_nb_supported(sa); 869 870 for (i = 0; i < EFX_MAC_NSTATS; ++i) { 871 if (EFX_MAC_STAT_SUPPORTED(port->mac_stats_mask, i)) { 872 if (nstats < xstats_count) { 873 strlcpy(xstats_names[nstats].name, 874 efx_mac_stat_name(sa->nic, i), 875 sizeof(xstats_names[0].name)); 876 nb_written++; 877 } 878 nstats++; 879 } 880 } 881 882 ret = sfc_sw_xstats_get_names(sa, xstats_names, xstats_count, 883 &nb_written, &nstats); 884 if (ret != 0) { 885 SFC_ASSERT(ret < 0); 886 return ret; 887 } 888 889 return nstats; 890 } 891 892 static int 893 sfc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 894 uint64_t *values, unsigned int n) 895 { 896 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 897 struct sfc_port *port = &sa->port; 898 unsigned int nb_supported; 899 unsigned int i; 900 int rc; 901 902 if (unlikely(ids == NULL || values == NULL)) 903 return -EINVAL; 904 905 /* 906 * Values array could be filled in nonsequential order. Fill values with 907 * constant indicating invalid ID first. 908 */ 909 for (i = 0; i < n; i++) 910 values[i] = SFC_XSTAT_ID_INVALID_VAL; 911 912 rc = sfc_port_get_mac_stats_by_id(sa, ids, values, n); 913 if (rc != 0) 914 return rc; 915 916 nb_supported = port->mac_stats_nb_supported; 917 sfc_sw_xstats_get_vals_by_id(sa, ids, values, n, &nb_supported); 918 919 /* Return number of written stats before invalid ID is encountered. */ 920 for (i = 0; i < n; i++) { 921 if (values[i] == SFC_XSTAT_ID_INVALID_VAL) 922 return i; 923 } 924 925 return n; 926 } 927 928 static int 929 sfc_xstats_get_names_by_id(struct rte_eth_dev *dev, 930 const uint64_t *ids, 931 struct rte_eth_xstat_name *xstats_names, 932 unsigned int size) 933 { 934 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 935 struct sfc_port *port = &sa->port; 936 unsigned int nb_supported; 937 unsigned int i; 938 int ret; 939 940 if (unlikely(xstats_names == NULL && ids != NULL) || 941 unlikely(xstats_names != NULL && ids == NULL)) 942 return -EINVAL; 943 944 if (unlikely(xstats_names == NULL && ids == NULL)) 945 return sfc_xstats_get_nb_supported(sa); 946 947 /* 948 * Names array could be filled in nonsequential order. Fill names with 949 * string indicating invalid ID first. 950 */ 951 for (i = 0; i < size; i++) 952 xstats_names[i].name[0] = SFC_XSTAT_ID_INVALID_NAME; 953 954 sfc_adapter_lock(sa); 955 956 SFC_ASSERT(port->mac_stats_nb_supported <= 957 RTE_DIM(port->mac_stats_by_id)); 958 959 for (i = 0; i < size; i++) { 960 if (ids[i] < port->mac_stats_nb_supported) { 961 strlcpy(xstats_names[i].name, 962 efx_mac_stat_name(sa->nic, 963 port->mac_stats_by_id[ids[i]]), 964 sizeof(xstats_names[0].name)); 965 } 966 } 967 968 nb_supported = port->mac_stats_nb_supported; 969 970 sfc_adapter_unlock(sa); 971 972 ret = sfc_sw_xstats_get_names_by_id(sa, ids, xstats_names, size, 973 &nb_supported); 974 if (ret != 0) { 975 SFC_ASSERT(ret < 0); 976 return ret; 977 } 978 979 /* Return number of written names before invalid ID is encountered. */ 980 for (i = 0; i < size; i++) { 981 if (xstats_names[i].name[0] == SFC_XSTAT_ID_INVALID_NAME) 982 return i; 983 } 984 985 return size; 986 } 987 988 static int 989 sfc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 990 { 991 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 992 unsigned int wanted_fc, link_fc; 993 994 memset(fc_conf, 0, sizeof(*fc_conf)); 995 996 sfc_adapter_lock(sa); 997 998 if (sa->state == SFC_ETHDEV_STARTED) 999 efx_mac_fcntl_get(sa->nic, &wanted_fc, &link_fc); 1000 else 1001 link_fc = sa->port.flow_ctrl; 1002 1003 switch (link_fc) { 1004 case 0: 1005 fc_conf->mode = RTE_ETH_FC_NONE; 1006 break; 1007 case EFX_FCNTL_RESPOND: 1008 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1009 break; 1010 case EFX_FCNTL_GENERATE: 1011 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1012 break; 1013 case (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE): 1014 fc_conf->mode = RTE_ETH_FC_FULL; 1015 break; 1016 default: 1017 sfc_err(sa, "%s: unexpected flow control value %#x", 1018 __func__, link_fc); 1019 } 1020 1021 fc_conf->autoneg = sa->port.flow_ctrl_autoneg; 1022 1023 sfc_adapter_unlock(sa); 1024 1025 return 0; 1026 } 1027 1028 static int 1029 sfc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1030 { 1031 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1032 struct sfc_port *port = &sa->port; 1033 unsigned int fcntl; 1034 int rc; 1035 1036 if (fc_conf->high_water != 0 || fc_conf->low_water != 0 || 1037 fc_conf->pause_time != 0 || fc_conf->send_xon != 0 || 1038 fc_conf->mac_ctrl_frame_fwd != 0) { 1039 sfc_err(sa, "unsupported flow control settings specified"); 1040 rc = EINVAL; 1041 goto fail_inval; 1042 } 1043 1044 switch (fc_conf->mode) { 1045 case RTE_ETH_FC_NONE: 1046 fcntl = 0; 1047 break; 1048 case RTE_ETH_FC_RX_PAUSE: 1049 fcntl = EFX_FCNTL_RESPOND; 1050 break; 1051 case RTE_ETH_FC_TX_PAUSE: 1052 fcntl = EFX_FCNTL_GENERATE; 1053 break; 1054 case RTE_ETH_FC_FULL: 1055 fcntl = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 1056 break; 1057 default: 1058 rc = EINVAL; 1059 goto fail_inval; 1060 } 1061 1062 sfc_adapter_lock(sa); 1063 1064 if (sa->state == SFC_ETHDEV_STARTED) { 1065 rc = efx_mac_fcntl_set(sa->nic, fcntl, fc_conf->autoneg); 1066 if (rc != 0) 1067 goto fail_mac_fcntl_set; 1068 } 1069 1070 port->flow_ctrl = fcntl; 1071 port->flow_ctrl_autoneg = fc_conf->autoneg; 1072 1073 sfc_adapter_unlock(sa); 1074 1075 return 0; 1076 1077 fail_mac_fcntl_set: 1078 sfc_adapter_unlock(sa); 1079 fail_inval: 1080 SFC_ASSERT(rc > 0); 1081 return -rc; 1082 } 1083 1084 static int 1085 sfc_check_scatter_on_all_rx_queues(struct sfc_adapter *sa, size_t pdu) 1086 { 1087 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1088 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1089 boolean_t scatter_enabled; 1090 const char *error; 1091 unsigned int i; 1092 1093 for (i = 0; i < sas->rxq_count; i++) { 1094 if ((sas->rxq_info[i].state & SFC_RXQ_INITIALIZED) == 0) 1095 continue; 1096 1097 scatter_enabled = (sas->rxq_info[i].type_flags & 1098 EFX_RXQ_FLAG_SCATTER); 1099 1100 if (!sfc_rx_check_scatter(pdu, sa->rxq_ctrl[i].buf_size, 1101 encp->enc_rx_prefix_size, 1102 scatter_enabled, 1103 encp->enc_rx_scatter_max, &error)) { 1104 sfc_err(sa, "MTU check for RxQ %u failed: %s", i, 1105 error); 1106 return EINVAL; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int 1114 sfc_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1115 { 1116 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1117 size_t pdu = EFX_MAC_PDU(mtu); 1118 size_t old_pdu; 1119 int rc; 1120 1121 sfc_log_init(sa, "mtu=%u", mtu); 1122 1123 rc = EINVAL; 1124 if (pdu < EFX_MAC_PDU_MIN) { 1125 sfc_err(sa, "too small MTU %u (PDU size %u less than min %u)", 1126 (unsigned int)mtu, (unsigned int)pdu, 1127 EFX_MAC_PDU_MIN); 1128 goto fail_inval; 1129 } 1130 if (pdu > EFX_MAC_PDU_MAX) { 1131 sfc_err(sa, "too big MTU %u (PDU size %u greater than max %u)", 1132 (unsigned int)mtu, (unsigned int)pdu, 1133 (unsigned int)EFX_MAC_PDU_MAX); 1134 goto fail_inval; 1135 } 1136 1137 sfc_adapter_lock(sa); 1138 1139 rc = sfc_check_scatter_on_all_rx_queues(sa, pdu); 1140 if (rc != 0) 1141 goto fail_check_scatter; 1142 1143 if (pdu != sa->port.pdu) { 1144 if (sa->state == SFC_ETHDEV_STARTED) { 1145 sfc_stop(sa); 1146 1147 old_pdu = sa->port.pdu; 1148 sa->port.pdu = pdu; 1149 rc = sfc_start(sa); 1150 if (rc != 0) 1151 goto fail_start; 1152 } else { 1153 sa->port.pdu = pdu; 1154 } 1155 } 1156 1157 sfc_adapter_unlock(sa); 1158 1159 sfc_log_init(sa, "done"); 1160 return 0; 1161 1162 fail_start: 1163 sa->port.pdu = old_pdu; 1164 if (sfc_start(sa) != 0) 1165 sfc_err(sa, "cannot start with neither new (%u) nor old (%u) " 1166 "PDU max size - port is stopped", 1167 (unsigned int)pdu, (unsigned int)old_pdu); 1168 1169 fail_check_scatter: 1170 sfc_adapter_unlock(sa); 1171 1172 fail_inval: 1173 sfc_log_init(sa, "failed %d", rc); 1174 SFC_ASSERT(rc > 0); 1175 return -rc; 1176 } 1177 static int 1178 sfc_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 1179 { 1180 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1181 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1182 struct sfc_port *port = &sa->port; 1183 struct rte_ether_addr *old_addr = &dev->data->mac_addrs[0]; 1184 int rc = 0; 1185 1186 sfc_adapter_lock(sa); 1187 1188 if (rte_is_same_ether_addr(mac_addr, &port->default_mac_addr)) 1189 goto unlock; 1190 1191 /* 1192 * Copy the address to the device private data so that 1193 * it could be recalled in the case of adapter restart. 1194 */ 1195 rte_ether_addr_copy(mac_addr, &port->default_mac_addr); 1196 1197 /* 1198 * Neither of the two following checks can return 1199 * an error. The new MAC address is preserved in 1200 * the device private data and can be activated 1201 * on the next port start if the user prevents 1202 * isolated mode from being enabled. 1203 */ 1204 if (sfc_sa2shared(sa)->isolated) { 1205 sfc_warn(sa, "isolated mode is active on the port"); 1206 sfc_warn(sa, "will not set MAC address"); 1207 goto unlock; 1208 } 1209 1210 if (sa->state != SFC_ETHDEV_STARTED) { 1211 sfc_notice(sa, "the port is not started"); 1212 sfc_notice(sa, "the new MAC address will be set on port start"); 1213 1214 goto unlock; 1215 } 1216 1217 if (encp->enc_allow_set_mac_with_installed_filters) { 1218 rc = efx_mac_addr_set(sa->nic, mac_addr->addr_bytes); 1219 if (rc != 0) { 1220 sfc_err(sa, "cannot set MAC address (rc = %u)", rc); 1221 goto unlock; 1222 } 1223 1224 /* 1225 * Changing the MAC address by means of MCDI request 1226 * has no effect on received traffic, therefore 1227 * we also need to update unicast filters 1228 */ 1229 rc = sfc_set_rx_mode_unchecked(sa); 1230 if (rc != 0) { 1231 sfc_err(sa, "cannot set filter (rc = %u)", rc); 1232 /* Rollback the old address */ 1233 (void)efx_mac_addr_set(sa->nic, old_addr->addr_bytes); 1234 (void)sfc_set_rx_mode_unchecked(sa); 1235 } 1236 } else { 1237 sfc_warn(sa, "cannot set MAC address with filters installed"); 1238 sfc_warn(sa, "adapter will be restarted to pick the new MAC"); 1239 sfc_warn(sa, "(some traffic may be dropped)"); 1240 1241 /* 1242 * Since setting MAC address with filters installed is not 1243 * allowed on the adapter, the new MAC address will be set 1244 * by means of adapter restart. sfc_start() shall retrieve 1245 * the new address from the device private data and set it. 1246 */ 1247 sfc_stop(sa); 1248 rc = sfc_start(sa); 1249 if (rc != 0) 1250 sfc_err(sa, "cannot restart adapter (rc = %u)", rc); 1251 } 1252 1253 unlock: 1254 if (rc != 0) 1255 rte_ether_addr_copy(old_addr, &port->default_mac_addr); 1256 1257 sfc_adapter_unlock(sa); 1258 1259 SFC_ASSERT(rc >= 0); 1260 return -rc; 1261 } 1262 1263 1264 static int 1265 sfc_set_mc_addr_list(struct rte_eth_dev *dev, 1266 struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr) 1267 { 1268 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1269 struct sfc_port *port = &sa->port; 1270 uint8_t *mc_addrs = port->mcast_addrs; 1271 int rc; 1272 unsigned int i; 1273 1274 if (sfc_sa2shared(sa)->isolated) { 1275 sfc_err(sa, "isolated mode is active on the port"); 1276 sfc_err(sa, "will not set multicast address list"); 1277 return -ENOTSUP; 1278 } 1279 1280 if (mc_addrs == NULL) 1281 return -ENOBUFS; 1282 1283 if (nb_mc_addr > port->max_mcast_addrs) { 1284 sfc_err(sa, "too many multicast addresses: %u > %u", 1285 nb_mc_addr, port->max_mcast_addrs); 1286 return -EINVAL; 1287 } 1288 1289 for (i = 0; i < nb_mc_addr; ++i) { 1290 rte_memcpy(mc_addrs, mc_addr_set[i].addr_bytes, 1291 EFX_MAC_ADDR_LEN); 1292 mc_addrs += EFX_MAC_ADDR_LEN; 1293 } 1294 1295 port->nb_mcast_addrs = nb_mc_addr; 1296 1297 if (sa->state != SFC_ETHDEV_STARTED) 1298 return 0; 1299 1300 rc = efx_mac_multicast_list_set(sa->nic, port->mcast_addrs, 1301 port->nb_mcast_addrs); 1302 if (rc != 0) 1303 sfc_err(sa, "cannot set multicast address list (rc = %u)", rc); 1304 1305 SFC_ASSERT(rc >= 0); 1306 return -rc; 1307 } 1308 1309 /* 1310 * The function is used by the secondary process as well. It must not 1311 * use any process-local pointers from the adapter data. 1312 */ 1313 static void 1314 sfc_rx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1315 struct rte_eth_rxq_info *qinfo) 1316 { 1317 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1318 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1319 struct sfc_rxq_info *rxq_info; 1320 1321 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1322 1323 qinfo->mp = rxq_info->refill_mb_pool; 1324 qinfo->conf.rx_free_thresh = rxq_info->refill_threshold; 1325 qinfo->conf.rx_drop_en = 1; 1326 qinfo->conf.rx_deferred_start = rxq_info->deferred_start; 1327 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 1328 if (rxq_info->type_flags & EFX_RXQ_FLAG_SCATTER) { 1329 qinfo->conf.offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; 1330 qinfo->scattered_rx = 1; 1331 } 1332 qinfo->nb_desc = rxq_info->entries; 1333 } 1334 1335 /* 1336 * The function is used by the secondary process as well. It must not 1337 * use any process-local pointers from the adapter data. 1338 */ 1339 static void 1340 sfc_tx_queue_info_get(struct rte_eth_dev *dev, uint16_t ethdev_qid, 1341 struct rte_eth_txq_info *qinfo) 1342 { 1343 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1344 struct sfc_txq_info *txq_info; 1345 1346 SFC_ASSERT(ethdev_qid < sas->ethdev_txq_count); 1347 1348 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1349 1350 memset(qinfo, 0, sizeof(*qinfo)); 1351 1352 qinfo->conf.offloads = txq_info->offloads; 1353 qinfo->conf.tx_free_thresh = txq_info->free_thresh; 1354 qinfo->conf.tx_deferred_start = txq_info->deferred_start; 1355 qinfo->nb_desc = txq_info->entries; 1356 } 1357 1358 /* 1359 * The function is used by the secondary process as well. It must not 1360 * use any process-local pointers from the adapter data. 1361 */ 1362 static uint32_t 1363 sfc_rx_queue_count(void *rx_queue) 1364 { 1365 struct sfc_dp_rxq *dp_rxq = rx_queue; 1366 const struct sfc_dp_rx *dp_rx; 1367 struct sfc_rxq_info *rxq_info; 1368 1369 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1370 rxq_info = sfc_rxq_info_by_dp_rxq(dp_rxq); 1371 1372 if ((rxq_info->state & SFC_RXQ_STARTED) == 0) 1373 return 0; 1374 1375 return dp_rx->qdesc_npending(dp_rxq); 1376 } 1377 1378 /* 1379 * The function is used by the secondary process as well. It must not 1380 * use any process-local pointers from the adapter data. 1381 */ 1382 static int 1383 sfc_rx_descriptor_status(void *queue, uint16_t offset) 1384 { 1385 struct sfc_dp_rxq *dp_rxq = queue; 1386 const struct sfc_dp_rx *dp_rx; 1387 1388 dp_rx = sfc_dp_rx_by_dp_rxq(dp_rxq); 1389 1390 return dp_rx->qdesc_status(dp_rxq, offset); 1391 } 1392 1393 /* 1394 * The function is used by the secondary process as well. It must not 1395 * use any process-local pointers from the adapter data. 1396 */ 1397 static int 1398 sfc_tx_descriptor_status(void *queue, uint16_t offset) 1399 { 1400 struct sfc_dp_txq *dp_txq = queue; 1401 const struct sfc_dp_tx *dp_tx; 1402 1403 dp_tx = sfc_dp_tx_by_dp_txq(dp_txq); 1404 1405 return dp_tx->qdesc_status(dp_txq, offset); 1406 } 1407 1408 static int 1409 sfc_rx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1410 { 1411 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1412 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1413 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1414 struct sfc_rxq_info *rxq_info; 1415 sfc_sw_index_t sw_index; 1416 int rc; 1417 1418 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1419 1420 sfc_adapter_lock(sa); 1421 1422 rc = EINVAL; 1423 if (sa->state != SFC_ETHDEV_STARTED) 1424 goto fail_not_started; 1425 1426 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1427 if (rxq_info->state != SFC_RXQ_INITIALIZED) 1428 goto fail_not_setup; 1429 1430 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1431 rc = sfc_rx_qstart(sa, sw_index); 1432 if (rc != 0) 1433 goto fail_rx_qstart; 1434 1435 rxq_info->deferred_started = B_TRUE; 1436 1437 sfc_adapter_unlock(sa); 1438 1439 return 0; 1440 1441 fail_rx_qstart: 1442 fail_not_setup: 1443 fail_not_started: 1444 sfc_adapter_unlock(sa); 1445 SFC_ASSERT(rc > 0); 1446 return -rc; 1447 } 1448 1449 static int 1450 sfc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1451 { 1452 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1453 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1454 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1455 struct sfc_rxq_info *rxq_info; 1456 sfc_sw_index_t sw_index; 1457 1458 sfc_log_init(sa, "RxQ=%u", ethdev_qid); 1459 1460 sfc_adapter_lock(sa); 1461 1462 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, sfc_ethdev_qid); 1463 sfc_rx_qstop(sa, sw_index); 1464 1465 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1466 rxq_info->deferred_started = B_FALSE; 1467 1468 sfc_adapter_unlock(sa); 1469 1470 return 0; 1471 } 1472 1473 static int 1474 sfc_tx_queue_start(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1475 { 1476 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1477 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1478 struct sfc_txq_info *txq_info; 1479 sfc_sw_index_t sw_index; 1480 int rc; 1481 1482 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1483 1484 sfc_adapter_lock(sa); 1485 1486 rc = EINVAL; 1487 if (sa->state != SFC_ETHDEV_STARTED) 1488 goto fail_not_started; 1489 1490 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1491 if (txq_info->state != SFC_TXQ_INITIALIZED) 1492 goto fail_not_setup; 1493 1494 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1495 rc = sfc_tx_qstart(sa, sw_index); 1496 if (rc != 0) 1497 goto fail_tx_qstart; 1498 1499 txq_info->deferred_started = B_TRUE; 1500 1501 sfc_adapter_unlock(sa); 1502 return 0; 1503 1504 fail_tx_qstart: 1505 1506 fail_not_setup: 1507 fail_not_started: 1508 sfc_adapter_unlock(sa); 1509 SFC_ASSERT(rc > 0); 1510 return -rc; 1511 } 1512 1513 static int 1514 sfc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1515 { 1516 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1517 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1518 struct sfc_txq_info *txq_info; 1519 sfc_sw_index_t sw_index; 1520 1521 sfc_log_init(sa, "TxQ = %u", ethdev_qid); 1522 1523 sfc_adapter_lock(sa); 1524 1525 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 1526 sfc_tx_qstop(sa, sw_index); 1527 1528 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 1529 txq_info->deferred_started = B_FALSE; 1530 1531 sfc_adapter_unlock(sa); 1532 return 0; 1533 } 1534 1535 static efx_tunnel_protocol_t 1536 sfc_tunnel_rte_type_to_efx_udp_proto(enum rte_eth_tunnel_type rte_type) 1537 { 1538 switch (rte_type) { 1539 case RTE_ETH_TUNNEL_TYPE_VXLAN: 1540 return EFX_TUNNEL_PROTOCOL_VXLAN; 1541 case RTE_ETH_TUNNEL_TYPE_GENEVE: 1542 return EFX_TUNNEL_PROTOCOL_GENEVE; 1543 default: 1544 return EFX_TUNNEL_NPROTOS; 1545 } 1546 } 1547 1548 enum sfc_udp_tunnel_op_e { 1549 SFC_UDP_TUNNEL_ADD_PORT, 1550 SFC_UDP_TUNNEL_DEL_PORT, 1551 }; 1552 1553 static int 1554 sfc_dev_udp_tunnel_op(struct rte_eth_dev *dev, 1555 struct rte_eth_udp_tunnel *tunnel_udp, 1556 enum sfc_udp_tunnel_op_e op) 1557 { 1558 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1559 efx_tunnel_protocol_t tunnel_proto; 1560 int rc; 1561 1562 sfc_log_init(sa, "%s udp_port=%u prot_type=%u", 1563 (op == SFC_UDP_TUNNEL_ADD_PORT) ? "add" : 1564 (op == SFC_UDP_TUNNEL_DEL_PORT) ? "delete" : "unknown", 1565 tunnel_udp->udp_port, tunnel_udp->prot_type); 1566 1567 tunnel_proto = 1568 sfc_tunnel_rte_type_to_efx_udp_proto(tunnel_udp->prot_type); 1569 if (tunnel_proto >= EFX_TUNNEL_NPROTOS) { 1570 rc = ENOTSUP; 1571 goto fail_bad_proto; 1572 } 1573 1574 sfc_adapter_lock(sa); 1575 1576 switch (op) { 1577 case SFC_UDP_TUNNEL_ADD_PORT: 1578 rc = efx_tunnel_config_udp_add(sa->nic, 1579 tunnel_udp->udp_port, 1580 tunnel_proto); 1581 break; 1582 case SFC_UDP_TUNNEL_DEL_PORT: 1583 rc = efx_tunnel_config_udp_remove(sa->nic, 1584 tunnel_udp->udp_port, 1585 tunnel_proto); 1586 break; 1587 default: 1588 rc = EINVAL; 1589 goto fail_bad_op; 1590 } 1591 1592 if (rc != 0) 1593 goto fail_op; 1594 1595 if (sa->state == SFC_ETHDEV_STARTED) { 1596 rc = efx_tunnel_reconfigure(sa->nic); 1597 if (rc == EAGAIN) { 1598 /* 1599 * Configuration is accepted by FW and MC reboot 1600 * is initiated to apply the changes. MC reboot 1601 * will be handled in a usual way (MC reboot 1602 * event on management event queue and adapter 1603 * restart). 1604 */ 1605 rc = 0; 1606 } else if (rc != 0) { 1607 goto fail_reconfigure; 1608 } 1609 } 1610 1611 sfc_adapter_unlock(sa); 1612 return 0; 1613 1614 fail_reconfigure: 1615 /* Remove/restore entry since the change makes the trouble */ 1616 switch (op) { 1617 case SFC_UDP_TUNNEL_ADD_PORT: 1618 (void)efx_tunnel_config_udp_remove(sa->nic, 1619 tunnel_udp->udp_port, 1620 tunnel_proto); 1621 break; 1622 case SFC_UDP_TUNNEL_DEL_PORT: 1623 (void)efx_tunnel_config_udp_add(sa->nic, 1624 tunnel_udp->udp_port, 1625 tunnel_proto); 1626 break; 1627 } 1628 1629 fail_op: 1630 fail_bad_op: 1631 sfc_adapter_unlock(sa); 1632 1633 fail_bad_proto: 1634 SFC_ASSERT(rc > 0); 1635 return -rc; 1636 } 1637 1638 static int 1639 sfc_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 1640 struct rte_eth_udp_tunnel *tunnel_udp) 1641 { 1642 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_ADD_PORT); 1643 } 1644 1645 static int 1646 sfc_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 1647 struct rte_eth_udp_tunnel *tunnel_udp) 1648 { 1649 return sfc_dev_udp_tunnel_op(dev, tunnel_udp, SFC_UDP_TUNNEL_DEL_PORT); 1650 } 1651 1652 /* 1653 * The function is used by the secondary process as well. It must not 1654 * use any process-local pointers from the adapter data. 1655 */ 1656 static int 1657 sfc_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1658 struct rte_eth_rss_conf *rss_conf) 1659 { 1660 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1661 struct sfc_rss *rss = &sas->rss; 1662 1663 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) 1664 return -ENOTSUP; 1665 1666 /* 1667 * Mapping of hash configuration between RTE and EFX is not one-to-one, 1668 * hence, conversion is done here to derive a correct set of RTE_ETH_RSS 1669 * flags which corresponds to the active EFX configuration stored 1670 * locally in 'sfc_adapter' and kept up-to-date 1671 */ 1672 rss_conf->rss_hf = sfc_rx_hf_efx_to_rte(rss, rss->hash_types); 1673 rss_conf->rss_key_len = EFX_RSS_KEY_SIZE; 1674 if (rss_conf->rss_key != NULL) 1675 rte_memcpy(rss_conf->rss_key, rss->key, EFX_RSS_KEY_SIZE); 1676 1677 return 0; 1678 } 1679 1680 static int 1681 sfc_dev_rss_hash_update(struct rte_eth_dev *dev, 1682 struct rte_eth_rss_conf *rss_conf) 1683 { 1684 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1685 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1686 unsigned int efx_hash_types; 1687 unsigned int n_contexts; 1688 unsigned int mode_i = 0; 1689 unsigned int key_i = 0; 1690 uint32_t contexts[2]; 1691 unsigned int i = 0; 1692 int rc = 0; 1693 1694 if (sfc_sa2shared(sa)->isolated) 1695 return -ENOTSUP; 1696 1697 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1698 sfc_err(sa, "RSS is not available"); 1699 return -ENOTSUP; 1700 } 1701 1702 if (rss->channels == 0) { 1703 sfc_err(sa, "RSS is not configured"); 1704 return -EINVAL; 1705 } 1706 1707 if ((rss_conf->rss_key != NULL) && 1708 (rss_conf->rss_key_len != sizeof(rss->key))) { 1709 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1710 sizeof(rss->key)); 1711 return -EINVAL; 1712 } 1713 1714 sfc_adapter_lock(sa); 1715 1716 rc = sfc_rx_hf_rte_to_efx(sa, rss_conf->rss_hf, &efx_hash_types); 1717 if (rc != 0) 1718 goto fail_rx_hf_rte_to_efx; 1719 1720 contexts[0] = EFX_RSS_CONTEXT_DEFAULT; 1721 contexts[1] = rss->dummy_ctx.nic_handle; 1722 n_contexts = (rss->dummy_ctx.nic_handle_refcnt == 0) ? 1 : 2; 1723 1724 for (mode_i = 0; mode_i < n_contexts; mode_i++) { 1725 rc = efx_rx_scale_mode_set(sa->nic, contexts[mode_i], 1726 rss->hash_alg, efx_hash_types, 1727 B_TRUE); 1728 if (rc != 0) 1729 goto fail_scale_mode_set; 1730 } 1731 1732 if (rss_conf->rss_key != NULL) { 1733 if (sa->state == SFC_ETHDEV_STARTED) { 1734 for (key_i = 0; key_i < n_contexts; key_i++) { 1735 rc = efx_rx_scale_key_set(sa->nic, 1736 contexts[key_i], 1737 rss_conf->rss_key, 1738 sizeof(rss->key)); 1739 if (rc != 0) 1740 goto fail_scale_key_set; 1741 } 1742 } 1743 1744 rte_memcpy(rss->key, rss_conf->rss_key, sizeof(rss->key)); 1745 } 1746 1747 rss->hash_types = efx_hash_types; 1748 1749 sfc_adapter_unlock(sa); 1750 1751 return 0; 1752 1753 fail_scale_key_set: 1754 for (i = 0; i < key_i; i++) { 1755 if (efx_rx_scale_key_set(sa->nic, contexts[i], rss->key, 1756 sizeof(rss->key)) != 0) 1757 sfc_err(sa, "failed to restore RSS key"); 1758 } 1759 1760 fail_scale_mode_set: 1761 for (i = 0; i < mode_i; i++) { 1762 if (efx_rx_scale_mode_set(sa->nic, contexts[i], 1763 EFX_RX_HASHALG_TOEPLITZ, 1764 rss->hash_types, B_TRUE) != 0) 1765 sfc_err(sa, "failed to restore RSS mode"); 1766 } 1767 1768 fail_rx_hf_rte_to_efx: 1769 sfc_adapter_unlock(sa); 1770 return -rc; 1771 } 1772 1773 /* 1774 * The function is used by the secondary process as well. It must not 1775 * use any process-local pointers from the adapter data. 1776 */ 1777 static int 1778 sfc_dev_rss_reta_query(struct rte_eth_dev *dev, 1779 struct rte_eth_rss_reta_entry64 *reta_conf, 1780 uint16_t reta_size) 1781 { 1782 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1783 struct sfc_rss *rss = &sas->rss; 1784 int entry; 1785 1786 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE || sas->isolated) 1787 return -ENOTSUP; 1788 1789 if (rss->channels == 0) 1790 return -EINVAL; 1791 1792 if (reta_size != EFX_RSS_TBL_SIZE) 1793 return -EINVAL; 1794 1795 for (entry = 0; entry < reta_size; entry++) { 1796 int grp = entry / RTE_ETH_RETA_GROUP_SIZE; 1797 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1798 1799 if ((reta_conf[grp].mask >> grp_idx) & 1) 1800 reta_conf[grp].reta[grp_idx] = rss->tbl[entry]; 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int 1807 sfc_dev_rss_reta_update(struct rte_eth_dev *dev, 1808 struct rte_eth_rss_reta_entry64 *reta_conf, 1809 uint16_t reta_size) 1810 { 1811 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 1812 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1813 unsigned int *rss_tbl_new; 1814 uint16_t entry; 1815 int rc = 0; 1816 1817 1818 if (sfc_sa2shared(sa)->isolated) 1819 return -ENOTSUP; 1820 1821 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1822 sfc_err(sa, "RSS is not available"); 1823 return -ENOTSUP; 1824 } 1825 1826 if (rss->channels == 0) { 1827 sfc_err(sa, "RSS is not configured"); 1828 return -EINVAL; 1829 } 1830 1831 if (reta_size != EFX_RSS_TBL_SIZE) { 1832 sfc_err(sa, "RETA size is wrong (should be %u)", 1833 EFX_RSS_TBL_SIZE); 1834 return -EINVAL; 1835 } 1836 1837 rss_tbl_new = rte_zmalloc("rss_tbl_new", sizeof(rss->tbl), 0); 1838 if (rss_tbl_new == NULL) 1839 return -ENOMEM; 1840 1841 sfc_adapter_lock(sa); 1842 1843 rte_memcpy(rss_tbl_new, rss->tbl, sizeof(rss->tbl)); 1844 1845 for (entry = 0; entry < reta_size; entry++) { 1846 int grp_idx = entry % RTE_ETH_RETA_GROUP_SIZE; 1847 struct rte_eth_rss_reta_entry64 *grp; 1848 1849 grp = &reta_conf[entry / RTE_ETH_RETA_GROUP_SIZE]; 1850 1851 if (grp->mask & (1ull << grp_idx)) { 1852 if (grp->reta[grp_idx] >= rss->channels) { 1853 rc = EINVAL; 1854 goto bad_reta_entry; 1855 } 1856 rss_tbl_new[entry] = grp->reta[grp_idx]; 1857 } 1858 } 1859 1860 if (sa->state == SFC_ETHDEV_STARTED) { 1861 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1862 rss_tbl_new, EFX_RSS_TBL_SIZE); 1863 if (rc != 0) 1864 goto fail_scale_tbl_set; 1865 } 1866 1867 rte_memcpy(rss->tbl, rss_tbl_new, sizeof(rss->tbl)); 1868 1869 fail_scale_tbl_set: 1870 bad_reta_entry: 1871 sfc_adapter_unlock(sa); 1872 1873 rte_free(rss_tbl_new); 1874 1875 SFC_ASSERT(rc >= 0); 1876 return -rc; 1877 } 1878 1879 static int 1880 sfc_dev_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 1881 const struct rte_flow_ops **ops) 1882 { 1883 *ops = &sfc_flow_ops; 1884 return 0; 1885 } 1886 1887 static int 1888 sfc_pool_ops_supported(struct rte_eth_dev *dev, const char *pool) 1889 { 1890 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1891 1892 /* 1893 * If Rx datapath does not provide callback to check mempool, 1894 * all pools are supported. 1895 */ 1896 if (sap->dp_rx->pool_ops_supported == NULL) 1897 return 1; 1898 1899 return sap->dp_rx->pool_ops_supported(pool); 1900 } 1901 1902 static int 1903 sfc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1904 { 1905 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1906 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1907 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1908 struct sfc_rxq_info *rxq_info; 1909 1910 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1911 1912 return sap->dp_rx->intr_enable(rxq_info->dp); 1913 } 1914 1915 static int 1916 sfc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t ethdev_qid) 1917 { 1918 const struct sfc_adapter_priv *sap = sfc_adapter_priv_by_eth_dev(dev); 1919 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 1920 sfc_ethdev_qid_t sfc_ethdev_qid = ethdev_qid; 1921 struct sfc_rxq_info *rxq_info; 1922 1923 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, sfc_ethdev_qid); 1924 1925 return sap->dp_rx->intr_disable(rxq_info->dp); 1926 } 1927 1928 struct sfc_mport_journal_ctx { 1929 struct sfc_adapter *sa; 1930 uint16_t switch_domain_id; 1931 uint32_t mcdi_handle; 1932 bool controllers_assigned; 1933 efx_pcie_interface_t *controllers; 1934 size_t nb_controllers; 1935 }; 1936 1937 static int 1938 sfc_journal_ctx_add_controller(struct sfc_mport_journal_ctx *ctx, 1939 efx_pcie_interface_t intf) 1940 { 1941 efx_pcie_interface_t *new_controllers; 1942 size_t i, target; 1943 size_t new_size; 1944 1945 if (ctx->controllers == NULL) { 1946 ctx->controllers = rte_malloc("sfc_controller_mapping", 1947 sizeof(ctx->controllers[0]), 0); 1948 if (ctx->controllers == NULL) 1949 return ENOMEM; 1950 1951 ctx->controllers[0] = intf; 1952 ctx->nb_controllers = 1; 1953 1954 return 0; 1955 } 1956 1957 for (i = 0; i < ctx->nb_controllers; i++) { 1958 if (ctx->controllers[i] == intf) 1959 return 0; 1960 if (ctx->controllers[i] > intf) 1961 break; 1962 } 1963 target = i; 1964 1965 ctx->nb_controllers += 1; 1966 new_size = ctx->nb_controllers * sizeof(ctx->controllers[0]); 1967 1968 new_controllers = rte_realloc(ctx->controllers, new_size, 0); 1969 if (new_controllers == NULL) { 1970 rte_free(ctx->controllers); 1971 return ENOMEM; 1972 } 1973 ctx->controllers = new_controllers; 1974 1975 for (i = target + 1; i < ctx->nb_controllers; i++) 1976 ctx->controllers[i] = ctx->controllers[i - 1]; 1977 1978 ctx->controllers[target] = intf; 1979 1980 return 0; 1981 } 1982 1983 static efx_rc_t 1984 sfc_process_mport_journal_entry(struct sfc_mport_journal_ctx *ctx, 1985 efx_mport_desc_t *mport) 1986 { 1987 struct sfc_mae_switch_port_request req; 1988 efx_mport_sel_t entity_selector; 1989 efx_mport_sel_t ethdev_mport; 1990 uint16_t switch_port_id; 1991 efx_rc_t efx_rc; 1992 int rc; 1993 1994 sfc_dbg(ctx->sa, 1995 "processing mport id %u (controller %u pf %u vf %u)", 1996 mport->emd_id.id, mport->emd_vnic.ev_intf, 1997 mport->emd_vnic.ev_pf, mport->emd_vnic.ev_vf); 1998 efx_mae_mport_invalid(ðdev_mport); 1999 2000 if (!ctx->controllers_assigned) { 2001 rc = sfc_journal_ctx_add_controller(ctx, 2002 mport->emd_vnic.ev_intf); 2003 if (rc != 0) 2004 return rc; 2005 } 2006 2007 /* Build Mport selector */ 2008 efx_rc = efx_mae_mport_by_pcie_mh_function(mport->emd_vnic.ev_intf, 2009 mport->emd_vnic.ev_pf, 2010 mport->emd_vnic.ev_vf, 2011 &entity_selector); 2012 if (efx_rc != 0) { 2013 sfc_err(ctx->sa, "failed to build entity mport selector for c%upf%uvf%u", 2014 mport->emd_vnic.ev_intf, 2015 mport->emd_vnic.ev_pf, 2016 mport->emd_vnic.ev_vf); 2017 return efx_rc; 2018 } 2019 2020 rc = sfc_mae_switch_port_id_by_entity(ctx->switch_domain_id, 2021 &entity_selector, 2022 SFC_MAE_SWITCH_PORT_REPRESENTOR, 2023 &switch_port_id); 2024 switch (rc) { 2025 case 0: 2026 /* Already registered */ 2027 break; 2028 case ENOENT: 2029 /* 2030 * No representor has been created for this entity. 2031 * Create a dummy switch registry entry with an invalid ethdev 2032 * mport selector. When a corresponding representor is created, 2033 * this entry will be updated. 2034 */ 2035 req.type = SFC_MAE_SWITCH_PORT_REPRESENTOR; 2036 req.entity_mportp = &entity_selector; 2037 req.ethdev_mportp = ðdev_mport; 2038 req.ethdev_port_id = RTE_MAX_ETHPORTS; 2039 req.port_data.repr.intf = mport->emd_vnic.ev_intf; 2040 req.port_data.repr.pf = mport->emd_vnic.ev_pf; 2041 req.port_data.repr.vf = mport->emd_vnic.ev_vf; 2042 2043 rc = sfc_mae_assign_switch_port(ctx->switch_domain_id, 2044 &req, &switch_port_id); 2045 if (rc != 0) { 2046 sfc_err(ctx->sa, 2047 "failed to assign MAE switch port for c%upf%uvf%u: %s", 2048 mport->emd_vnic.ev_intf, 2049 mport->emd_vnic.ev_pf, 2050 mport->emd_vnic.ev_vf, 2051 rte_strerror(rc)); 2052 return rc; 2053 } 2054 break; 2055 default: 2056 sfc_err(ctx->sa, "failed to find MAE switch port for c%upf%uvf%u: %s", 2057 mport->emd_vnic.ev_intf, 2058 mport->emd_vnic.ev_pf, 2059 mport->emd_vnic.ev_vf, 2060 rte_strerror(rc)); 2061 return rc; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static efx_rc_t 2068 sfc_process_mport_journal_cb(void *data, efx_mport_desc_t *mport, 2069 size_t mport_len) 2070 { 2071 struct sfc_mport_journal_ctx *ctx = data; 2072 2073 if (ctx == NULL || ctx->sa == NULL) { 2074 SFC_GENERIC_LOG(ERR, "received NULL context or SFC adapter"); 2075 return EINVAL; 2076 } 2077 2078 if (mport_len != sizeof(*mport)) { 2079 sfc_err(ctx->sa, "actual and expected mport buffer sizes differ"); 2080 return EINVAL; 2081 } 2082 2083 SFC_ASSERT(sfc_adapter_is_locked(ctx->sa)); 2084 2085 /* 2086 * If a zombie flag is set, it means the mport has been marked for 2087 * deletion and cannot be used for any new operations. The mport will 2088 * be destroyed completely once all references to it are released. 2089 */ 2090 if (mport->emd_zombie) { 2091 sfc_dbg(ctx->sa, "mport is a zombie, skipping"); 2092 return 0; 2093 } 2094 if (mport->emd_type != EFX_MPORT_TYPE_VNIC) { 2095 sfc_dbg(ctx->sa, "mport is not a VNIC, skipping"); 2096 return 0; 2097 } 2098 if (mport->emd_vnic.ev_client_type != EFX_MPORT_VNIC_CLIENT_FUNCTION) { 2099 sfc_dbg(ctx->sa, "mport is not a function, skipping"); 2100 return 0; 2101 } 2102 if (mport->emd_vnic.ev_handle == ctx->mcdi_handle) { 2103 sfc_dbg(ctx->sa, "mport is this driver instance, skipping"); 2104 return 0; 2105 } 2106 2107 return sfc_process_mport_journal_entry(ctx, mport); 2108 } 2109 2110 static int 2111 sfc_process_mport_journal(struct sfc_adapter *sa) 2112 { 2113 struct sfc_mport_journal_ctx ctx; 2114 const efx_pcie_interface_t *controllers; 2115 size_t nb_controllers; 2116 efx_rc_t efx_rc; 2117 int rc; 2118 2119 memset(&ctx, 0, sizeof(ctx)); 2120 ctx.sa = sa; 2121 ctx.switch_domain_id = sa->mae.switch_domain_id; 2122 2123 efx_rc = efx_mcdi_get_own_client_handle(sa->nic, &ctx.mcdi_handle); 2124 if (efx_rc != 0) { 2125 sfc_err(sa, "failed to get own MCDI handle"); 2126 SFC_ASSERT(efx_rc > 0); 2127 return efx_rc; 2128 } 2129 2130 rc = sfc_mae_switch_domain_controllers(ctx.switch_domain_id, 2131 &controllers, &nb_controllers); 2132 if (rc != 0) { 2133 sfc_err(sa, "failed to get controller mapping"); 2134 return rc; 2135 } 2136 2137 ctx.controllers_assigned = controllers != NULL; 2138 ctx.controllers = NULL; 2139 ctx.nb_controllers = 0; 2140 2141 efx_rc = efx_mae_read_mport_journal(sa->nic, 2142 sfc_process_mport_journal_cb, &ctx); 2143 if (efx_rc != 0) { 2144 sfc_err(sa, "failed to process MAE mport journal"); 2145 SFC_ASSERT(efx_rc > 0); 2146 return efx_rc; 2147 } 2148 2149 if (controllers == NULL) { 2150 rc = sfc_mae_switch_domain_map_controllers(ctx.switch_domain_id, 2151 ctx.controllers, 2152 ctx.nb_controllers); 2153 if (rc != 0) 2154 return rc; 2155 } 2156 2157 return 0; 2158 } 2159 2160 static void 2161 sfc_count_representors_cb(enum sfc_mae_switch_port_type type, 2162 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2163 uint16_t ethdev_port_id __rte_unused, 2164 const efx_mport_sel_t *entity_mportp __rte_unused, 2165 uint16_t switch_port_id __rte_unused, 2166 union sfc_mae_switch_port_data *port_datap 2167 __rte_unused, 2168 void *user_datap) 2169 { 2170 int *counter = user_datap; 2171 2172 SFC_ASSERT(counter != NULL); 2173 2174 if (type == SFC_MAE_SWITCH_PORT_REPRESENTOR) 2175 (*counter)++; 2176 } 2177 2178 struct sfc_get_representors_ctx { 2179 struct rte_eth_representor_info *info; 2180 struct sfc_adapter *sa; 2181 uint16_t switch_domain_id; 2182 const efx_pcie_interface_t *controllers; 2183 size_t nb_controllers; 2184 }; 2185 2186 static void 2187 sfc_get_representors_cb(enum sfc_mae_switch_port_type type, 2188 const efx_mport_sel_t *ethdev_mportp __rte_unused, 2189 uint16_t ethdev_port_id __rte_unused, 2190 const efx_mport_sel_t *entity_mportp __rte_unused, 2191 uint16_t switch_port_id, 2192 union sfc_mae_switch_port_data *port_datap, 2193 void *user_datap) 2194 { 2195 struct sfc_get_representors_ctx *ctx = user_datap; 2196 struct rte_eth_representor_range *range; 2197 int ret; 2198 int rc; 2199 2200 SFC_ASSERT(ctx != NULL); 2201 SFC_ASSERT(ctx->info != NULL); 2202 SFC_ASSERT(ctx->sa != NULL); 2203 2204 if (type != SFC_MAE_SWITCH_PORT_REPRESENTOR) { 2205 sfc_dbg(ctx->sa, "not a representor, skipping"); 2206 return; 2207 } 2208 if (ctx->info->nb_ranges >= ctx->info->nb_ranges_alloc) { 2209 sfc_dbg(ctx->sa, "info structure is full already"); 2210 return; 2211 } 2212 2213 range = &ctx->info->ranges[ctx->info->nb_ranges]; 2214 rc = sfc_mae_switch_controller_from_mapping(ctx->controllers, 2215 ctx->nb_controllers, 2216 port_datap->repr.intf, 2217 &range->controller); 2218 if (rc != 0) { 2219 sfc_err(ctx->sa, "invalid representor controller: %d", 2220 port_datap->repr.intf); 2221 range->controller = -1; 2222 } 2223 range->pf = port_datap->repr.pf; 2224 range->id_base = switch_port_id; 2225 range->id_end = switch_port_id; 2226 2227 if (port_datap->repr.vf != EFX_PCI_VF_INVALID) { 2228 range->type = RTE_ETH_REPRESENTOR_VF; 2229 range->vf = port_datap->repr.vf; 2230 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2231 "c%dpf%dvf%d", range->controller, range->pf, 2232 range->vf); 2233 } else { 2234 range->type = RTE_ETH_REPRESENTOR_PF; 2235 ret = snprintf(range->name, RTE_DEV_NAME_MAX_LEN, 2236 "c%dpf%d", range->controller, range->pf); 2237 } 2238 if (ret >= RTE_DEV_NAME_MAX_LEN) { 2239 sfc_err(ctx->sa, "representor name has been truncated: %s", 2240 range->name); 2241 } 2242 2243 ctx->info->nb_ranges++; 2244 } 2245 2246 static int 2247 sfc_representor_info_get(struct rte_eth_dev *dev, 2248 struct rte_eth_representor_info *info) 2249 { 2250 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2251 struct sfc_get_representors_ctx get_repr_ctx; 2252 const efx_nic_cfg_t *nic_cfg; 2253 uint16_t switch_domain_id; 2254 uint32_t nb_repr; 2255 int controller; 2256 int rc; 2257 2258 sfc_adapter_lock(sa); 2259 2260 if (sa->mae.status != SFC_MAE_STATUS_ADMIN) { 2261 sfc_adapter_unlock(sa); 2262 return -ENOTSUP; 2263 } 2264 2265 rc = sfc_process_mport_journal(sa); 2266 if (rc != 0) { 2267 sfc_adapter_unlock(sa); 2268 SFC_ASSERT(rc > 0); 2269 return -rc; 2270 } 2271 2272 switch_domain_id = sa->mae.switch_domain_id; 2273 2274 nb_repr = 0; 2275 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2276 sfc_count_representors_cb, 2277 &nb_repr); 2278 if (rc != 0) { 2279 sfc_adapter_unlock(sa); 2280 SFC_ASSERT(rc > 0); 2281 return -rc; 2282 } 2283 2284 if (info == NULL) { 2285 sfc_adapter_unlock(sa); 2286 return nb_repr; 2287 } 2288 2289 rc = sfc_mae_switch_domain_controllers(switch_domain_id, 2290 &get_repr_ctx.controllers, 2291 &get_repr_ctx.nb_controllers); 2292 if (rc != 0) { 2293 sfc_adapter_unlock(sa); 2294 SFC_ASSERT(rc > 0); 2295 return -rc; 2296 } 2297 2298 nic_cfg = efx_nic_cfg_get(sa->nic); 2299 2300 rc = sfc_mae_switch_domain_get_controller(switch_domain_id, 2301 nic_cfg->enc_intf, 2302 &controller); 2303 if (rc != 0) { 2304 sfc_err(sa, "invalid controller: %d", nic_cfg->enc_intf); 2305 controller = -1; 2306 } 2307 2308 info->controller = controller; 2309 info->pf = nic_cfg->enc_pf; 2310 2311 get_repr_ctx.info = info; 2312 get_repr_ctx.sa = sa; 2313 get_repr_ctx.switch_domain_id = switch_domain_id; 2314 rc = sfc_mae_switch_ports_iterate(switch_domain_id, 2315 sfc_get_representors_cb, 2316 &get_repr_ctx); 2317 if (rc != 0) { 2318 sfc_adapter_unlock(sa); 2319 SFC_ASSERT(rc > 0); 2320 return -rc; 2321 } 2322 2323 sfc_adapter_unlock(sa); 2324 return nb_repr; 2325 } 2326 2327 static int 2328 sfc_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 2329 { 2330 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2331 uint64_t supported = 0; 2332 2333 sfc_adapter_lock(sa); 2334 2335 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_FLAG) != 0) 2336 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 2337 2338 if ((sa->priv.dp_rx->features & SFC_DP_RX_FEAT_FLOW_MARK) != 0) 2339 supported |= RTE_ETH_RX_METADATA_USER_MARK; 2340 2341 if (sfc_ft_is_supported(sa)) 2342 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 2343 2344 sa->negotiated_rx_metadata = supported & *features; 2345 *features = sa->negotiated_rx_metadata; 2346 2347 sfc_adapter_unlock(sa); 2348 2349 return 0; 2350 } 2351 2352 static unsigned int 2353 sfc_fec_get_capa_speed_to_fec(uint32_t supported_caps, 2354 struct rte_eth_fec_capa *speed_fec_capa) 2355 { 2356 unsigned int num = 0; 2357 bool baser = false; 2358 bool rs = false; 2359 2360 if (supported_caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC)) 2361 baser = true; 2362 if (supported_caps & EFX_PHY_CAP_FEC_BIT(RS_FEC)) 2363 rs = true; 2364 2365 /* 2366 * NOFEC and AUTO FEC modes are always supported. 2367 * FW does not provide information about the supported 2368 * FEC modes per the link speed. 2369 * Supported FEC depends on supported link speeds and 2370 * supported FEC modes by a device. 2371 */ 2372 if (supported_caps & (1u << EFX_PHY_CAP_10000FDX)) { 2373 if (speed_fec_capa != NULL) { 2374 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_10G; 2375 speed_fec_capa[num].capa = 2376 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2377 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2378 if (baser) { 2379 speed_fec_capa[num].capa |= 2380 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2381 } 2382 } 2383 num++; 2384 } 2385 if (supported_caps & (1u << EFX_PHY_CAP_25000FDX)) { 2386 if (speed_fec_capa != NULL) { 2387 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_25G; 2388 speed_fec_capa[num].capa = 2389 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2390 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2391 if (baser) { 2392 speed_fec_capa[num].capa |= 2393 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2394 } 2395 if (rs) { 2396 speed_fec_capa[num].capa |= 2397 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2398 } 2399 } 2400 num++; 2401 } 2402 if (supported_caps & (1u << EFX_PHY_CAP_40000FDX)) { 2403 if (speed_fec_capa != NULL) { 2404 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_40G; 2405 speed_fec_capa[num].capa = 2406 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2407 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2408 if (baser) { 2409 speed_fec_capa[num].capa |= 2410 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2411 } 2412 } 2413 num++; 2414 } 2415 if (supported_caps & (1u << EFX_PHY_CAP_50000FDX)) { 2416 if (speed_fec_capa != NULL) { 2417 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_50G; 2418 speed_fec_capa[num].capa = 2419 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2420 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2421 if (baser) { 2422 speed_fec_capa[num].capa |= 2423 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 2424 } 2425 if (rs) { 2426 speed_fec_capa[num].capa |= 2427 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2428 } 2429 } 2430 num++; 2431 } 2432 if (supported_caps & (1u << EFX_PHY_CAP_100000FDX)) { 2433 if (speed_fec_capa != NULL) { 2434 speed_fec_capa[num].speed = RTE_ETH_SPEED_NUM_100G; 2435 speed_fec_capa[num].capa = 2436 RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 2437 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 2438 if (rs) { 2439 speed_fec_capa[num].capa |= 2440 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 2441 } 2442 } 2443 num++; 2444 } 2445 2446 return num; 2447 } 2448 2449 static int 2450 sfc_fec_get_capability(struct rte_eth_dev *dev, 2451 struct rte_eth_fec_capa *speed_fec_capa, 2452 unsigned int num) 2453 { 2454 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2455 unsigned int num_entries; 2456 uint32_t supported_caps; 2457 2458 sfc_adapter_lock(sa); 2459 2460 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &supported_caps); 2461 2462 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, NULL); 2463 if (speed_fec_capa == NULL || num < num_entries) 2464 goto adapter_unlock; 2465 2466 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, 2467 speed_fec_capa); 2468 2469 adapter_unlock: 2470 sfc_adapter_unlock(sa); 2471 2472 return num_entries; 2473 } 2474 2475 static uint32_t 2476 sfc_efx_caps_to_fec(uint32_t caps, bool is_25g) 2477 { 2478 bool rs_req = caps & EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED); 2479 bool rs = caps & EFX_PHY_CAP_FEC_BIT(RS_FEC); 2480 bool baser_req; 2481 bool baser; 2482 2483 if (is_25g) { 2484 baser = caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC); 2485 baser_req = caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED); 2486 } else { 2487 baser = caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC); 2488 baser_req = caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED); 2489 } 2490 2491 if (!baser && !rs) 2492 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC); 2493 2494 if (rs_req) 2495 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS); 2496 2497 if (baser_req) 2498 return RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER); 2499 2500 return 0; 2501 } 2502 2503 static int 2504 sfc_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 2505 { 2506 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2507 struct sfc_port *port = &sa->port; 2508 struct rte_eth_link current_link; 2509 efx_phy_fec_type_t active_fec; 2510 bool is_25g = false; 2511 int rc = 0; 2512 2513 sfc_adapter_lock(sa); 2514 2515 sfc_dev_get_rte_link(dev, 1, ¤t_link); 2516 2517 if (current_link.link_status == RTE_ETH_LINK_DOWN) { 2518 uint32_t speed = current_link.link_speed; 2519 2520 if (port->fec_auto) { 2521 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO); 2522 goto adapter_unlock; 2523 } 2524 2525 is_25g = (speed == RTE_ETH_SPEED_NUM_25G || 2526 speed == RTE_ETH_SPEED_NUM_50G); 2527 2528 *fec_capa = sfc_efx_caps_to_fec(port->fec_cfg, is_25g); 2529 if (*fec_capa == 0) 2530 rc = ENOTSUP; 2531 2532 goto adapter_unlock; 2533 } 2534 2535 rc = efx_phy_fec_type_get(sa->nic, &active_fec); 2536 if (rc != 0) 2537 goto adapter_unlock; 2538 2539 switch (active_fec) { 2540 case EFX_PHY_FEC_NONE: 2541 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC); 2542 break; 2543 case EFX_PHY_FEC_BASER: 2544 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER); 2545 break; 2546 case EFX_PHY_FEC_RS: 2547 *fec_capa = RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS); 2548 break; 2549 default: 2550 rc = ENOTSUP; 2551 break; 2552 } 2553 2554 adapter_unlock: 2555 sfc_adapter_unlock(sa); 2556 2557 if (rc != 0) 2558 sfc_err(sa, "failed to get FEC mode"); 2559 2560 SFC_ASSERT(rc >= 0); 2561 return -rc; 2562 } 2563 2564 static int 2565 sfc_fec_capa_check(struct rte_eth_dev *dev, uint32_t fec_capa, 2566 uint32_t supported_caps) 2567 { 2568 struct rte_eth_fec_capa *speed_fec_capa; 2569 struct rte_eth_link current_link; 2570 bool is_supported = false; 2571 unsigned int num_entries; 2572 bool auto_fec = false; 2573 unsigned int i; 2574 2575 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2576 2577 if (sa->state != SFC_ETHDEV_STARTED) 2578 return 0; 2579 2580 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) { 2581 auto_fec = true; 2582 fec_capa &= ~RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO); 2583 } 2584 2585 /* 2586 * If only the AUTO bit is set, the decision on which FEC 2587 * mode to use will be made by HW/FW or driver. 2588 */ 2589 if (auto_fec && fec_capa == 0) 2590 return 0; 2591 2592 sfc_dev_get_rte_link(dev, 1, ¤t_link); 2593 2594 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, NULL); 2595 if (num_entries == 0) 2596 return ENOTSUP; 2597 2598 speed_fec_capa = rte_calloc("fec_capa", num_entries, 2599 sizeof(*speed_fec_capa), 0); 2600 num_entries = sfc_fec_get_capa_speed_to_fec(supported_caps, 2601 speed_fec_capa); 2602 2603 for (i = 0; i < num_entries; i++) { 2604 if (speed_fec_capa[i].speed == current_link.link_speed) { 2605 if ((fec_capa & speed_fec_capa[i].capa) != 0) 2606 is_supported = true; 2607 2608 break; 2609 } 2610 } 2611 2612 rte_free(speed_fec_capa); 2613 2614 if (is_supported) 2615 return 0; 2616 2617 return ENOTSUP; 2618 } 2619 2620 static int 2621 sfc_fec_capa_to_efx(uint32_t supported_caps, uint32_t fec_capa, 2622 uint32_t *efx_fec_caps) 2623 { 2624 bool fec_is_set = false; 2625 bool auto_fec = false; 2626 bool nofec = false; 2627 uint32_t ret = 0; 2628 2629 if (efx_fec_caps == NULL) 2630 return EINVAL; 2631 2632 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) 2633 auto_fec = true; 2634 2635 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_NOFEC)) 2636 nofec = true; 2637 2638 if (fec_capa == RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) { 2639 ret |= (EFX_PHY_CAP_FEC_BIT(BASER_FEC) | 2640 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | 2641 EFX_PHY_CAP_FEC_BIT(RS_FEC)) & supported_caps; 2642 goto done; 2643 } 2644 2645 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_RS)) { 2646 fec_is_set = true; 2647 2648 if (supported_caps & EFX_PHY_CAP_FEC_BIT(RS_FEC)) { 2649 ret |= EFX_PHY_CAP_FEC_BIT(RS_FEC) | 2650 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED); 2651 } 2652 } 2653 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_BASER)) { 2654 if (!auto_fec && fec_is_set) 2655 return EINVAL; 2656 2657 if (supported_caps & EFX_PHY_CAP_FEC_BIT(BASER_FEC)) { 2658 ret |= EFX_PHY_CAP_FEC_BIT(BASER_FEC) | 2659 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED); 2660 } 2661 if (supported_caps & EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC)) { 2662 ret |= EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | 2663 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED); 2664 } 2665 } 2666 2667 if (ret == 0 && !nofec) 2668 return ENOTSUP; 2669 2670 done: 2671 *efx_fec_caps = ret; 2672 return 0; 2673 } 2674 2675 static int 2676 sfc_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 2677 { 2678 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2679 struct sfc_port *port = &sa->port; 2680 uint32_t supported_caps; 2681 uint32_t efx_fec_caps; 2682 uint32_t updated_caps; 2683 int rc = 0; 2684 2685 sfc_adapter_lock(sa); 2686 2687 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_PERM, &supported_caps); 2688 2689 rc = sfc_fec_capa_check(dev, fec_capa, supported_caps); 2690 if (rc != 0) 2691 goto adapter_unlock; 2692 2693 rc = sfc_fec_capa_to_efx(supported_caps, fec_capa, &efx_fec_caps); 2694 if (rc != 0) 2695 goto adapter_unlock; 2696 2697 if (sa->state == SFC_ETHDEV_STARTED) { 2698 efx_phy_adv_cap_get(sa->nic, EFX_PHY_CAP_CURRENT, 2699 &updated_caps); 2700 updated_caps = updated_caps & ~EFX_PHY_CAP_FEC_MASK; 2701 updated_caps |= efx_fec_caps; 2702 2703 rc = efx_phy_adv_cap_set(sa->nic, updated_caps); 2704 if (rc != 0) 2705 goto adapter_unlock; 2706 } 2707 2708 port->fec_cfg = efx_fec_caps; 2709 /* 2710 * There is no chance to recognize AUTO mode from the 2711 * saved FEC capabilities as AUTO mode can have the same 2712 * set of bits as any other mode from the EFX point of view. 2713 * Save it in the proper variable. 2714 */ 2715 if (fec_capa & RTE_ETH_FEC_MODE_TO_CAPA(RTE_ETH_FEC_AUTO)) 2716 port->fec_auto = true; 2717 else 2718 port->fec_auto = false; 2719 2720 adapter_unlock: 2721 sfc_adapter_unlock(sa); 2722 2723 SFC_ASSERT(rc >= 0); 2724 return -rc; 2725 } 2726 2727 static const struct eth_dev_ops sfc_eth_dev_ops = { 2728 .dev_configure = sfc_dev_configure, 2729 .dev_start = sfc_dev_start, 2730 .dev_stop = sfc_dev_stop, 2731 .dev_set_link_up = sfc_dev_set_link_up, 2732 .dev_set_link_down = sfc_dev_set_link_down, 2733 .dev_close = sfc_dev_close, 2734 .promiscuous_enable = sfc_dev_promisc_enable, 2735 .promiscuous_disable = sfc_dev_promisc_disable, 2736 .allmulticast_enable = sfc_dev_allmulti_enable, 2737 .allmulticast_disable = sfc_dev_allmulti_disable, 2738 .link_update = sfc_dev_link_update, 2739 .stats_get = sfc_stats_get, 2740 .stats_reset = sfc_stats_reset, 2741 .xstats_get = sfc_xstats_get, 2742 .xstats_reset = sfc_stats_reset, 2743 .xstats_get_names = sfc_xstats_get_names, 2744 .dev_infos_get = sfc_dev_infos_get, 2745 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2746 .mtu_set = sfc_dev_set_mtu, 2747 .rx_queue_start = sfc_rx_queue_start, 2748 .rx_queue_stop = sfc_rx_queue_stop, 2749 .tx_queue_start = sfc_tx_queue_start, 2750 .tx_queue_stop = sfc_tx_queue_stop, 2751 .rx_queue_setup = sfc_rx_queue_setup, 2752 .rx_queue_release = sfc_rx_queue_release, 2753 .rx_queue_intr_enable = sfc_rx_queue_intr_enable, 2754 .rx_queue_intr_disable = sfc_rx_queue_intr_disable, 2755 .tx_queue_setup = sfc_tx_queue_setup, 2756 .tx_queue_release = sfc_tx_queue_release, 2757 .flow_ctrl_get = sfc_flow_ctrl_get, 2758 .flow_ctrl_set = sfc_flow_ctrl_set, 2759 .mac_addr_set = sfc_mac_addr_set, 2760 .udp_tunnel_port_add = sfc_dev_udp_tunnel_port_add, 2761 .udp_tunnel_port_del = sfc_dev_udp_tunnel_port_del, 2762 .reta_update = sfc_dev_rss_reta_update, 2763 .reta_query = sfc_dev_rss_reta_query, 2764 .rss_hash_update = sfc_dev_rss_hash_update, 2765 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2766 .flow_ops_get = sfc_dev_flow_ops_get, 2767 .set_mc_addr_list = sfc_set_mc_addr_list, 2768 .rxq_info_get = sfc_rx_queue_info_get, 2769 .txq_info_get = sfc_tx_queue_info_get, 2770 .fw_version_get = sfc_fw_version_get, 2771 .xstats_get_by_id = sfc_xstats_get_by_id, 2772 .xstats_get_names_by_id = sfc_xstats_get_names_by_id, 2773 .pool_ops_supported = sfc_pool_ops_supported, 2774 .representor_info_get = sfc_representor_info_get, 2775 .rx_metadata_negotiate = sfc_rx_metadata_negotiate, 2776 .fec_get_capability = sfc_fec_get_capability, 2777 .fec_get = sfc_fec_get, 2778 .fec_set = sfc_fec_set, 2779 }; 2780 2781 struct sfc_ethdev_init_data { 2782 uint16_t nb_representors; 2783 }; 2784 2785 /** 2786 * Duplicate a string in potentially shared memory required for 2787 * multi-process support. 2788 * 2789 * strdup() allocates from process-local heap/memory. 2790 */ 2791 static char * 2792 sfc_strdup(const char *str) 2793 { 2794 size_t size; 2795 char *copy; 2796 2797 if (str == NULL) 2798 return NULL; 2799 2800 size = strlen(str) + 1; 2801 copy = rte_malloc(__func__, size, 0); 2802 if (copy != NULL) 2803 rte_memcpy(copy, str, size); 2804 2805 return copy; 2806 } 2807 2808 static int 2809 sfc_eth_dev_set_ops(struct rte_eth_dev *dev) 2810 { 2811 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2812 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2813 const struct sfc_dp_rx *dp_rx; 2814 const struct sfc_dp_tx *dp_tx; 2815 const efx_nic_cfg_t *encp; 2816 unsigned int avail_caps = 0; 2817 const char *rx_name = NULL; 2818 const char *tx_name = NULL; 2819 int rc; 2820 2821 switch (sa->family) { 2822 case EFX_FAMILY_HUNTINGTON: 2823 case EFX_FAMILY_MEDFORD: 2824 case EFX_FAMILY_MEDFORD2: 2825 avail_caps |= SFC_DP_HW_FW_CAP_EF10; 2826 avail_caps |= SFC_DP_HW_FW_CAP_RX_EFX; 2827 avail_caps |= SFC_DP_HW_FW_CAP_TX_EFX; 2828 break; 2829 case EFX_FAMILY_RIVERHEAD: 2830 avail_caps |= SFC_DP_HW_FW_CAP_EF100; 2831 break; 2832 default: 2833 break; 2834 } 2835 2836 encp = efx_nic_cfg_get(sa->nic); 2837 if (encp->enc_rx_es_super_buffer_supported) 2838 avail_caps |= SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER; 2839 2840 rc = sfc_kvargs_process(sa, SFC_KVARG_RX_DATAPATH, 2841 sfc_kvarg_string_handler, &rx_name); 2842 if (rc != 0) 2843 goto fail_kvarg_rx_datapath; 2844 2845 if (rx_name != NULL) { 2846 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, rx_name); 2847 if (dp_rx == NULL) { 2848 sfc_err(sa, "Rx datapath %s not found", rx_name); 2849 rc = ENOENT; 2850 goto fail_dp_rx; 2851 } 2852 if (!sfc_dp_match_hw_fw_caps(&dp_rx->dp, avail_caps)) { 2853 sfc_err(sa, 2854 "Insufficient Hw/FW capabilities to use Rx datapath %s", 2855 rx_name); 2856 rc = EINVAL; 2857 goto fail_dp_rx_caps; 2858 } 2859 } else { 2860 dp_rx = sfc_dp_find_rx_by_caps(&sfc_dp_head, avail_caps); 2861 if (dp_rx == NULL) { 2862 sfc_err(sa, "Rx datapath by caps %#x not found", 2863 avail_caps); 2864 rc = ENOENT; 2865 goto fail_dp_rx; 2866 } 2867 } 2868 2869 sas->dp_rx_name = sfc_strdup(dp_rx->dp.name); 2870 if (sas->dp_rx_name == NULL) { 2871 rc = ENOMEM; 2872 goto fail_dp_rx_name; 2873 } 2874 2875 if (strcmp(dp_rx->dp.name, SFC_KVARG_DATAPATH_EF10_ESSB) == 0) { 2876 /* FLAG and MARK are always available from Rx prefix. */ 2877 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_FLAG; 2878 sa->negotiated_rx_metadata |= RTE_ETH_RX_METADATA_USER_MARK; 2879 } 2880 2881 sfc_notice(sa, "use %s Rx datapath", sas->dp_rx_name); 2882 2883 rc = sfc_kvargs_process(sa, SFC_KVARG_TX_DATAPATH, 2884 sfc_kvarg_string_handler, &tx_name); 2885 if (rc != 0) 2886 goto fail_kvarg_tx_datapath; 2887 2888 if (tx_name != NULL) { 2889 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, tx_name); 2890 if (dp_tx == NULL) { 2891 sfc_err(sa, "Tx datapath %s not found", tx_name); 2892 rc = ENOENT; 2893 goto fail_dp_tx; 2894 } 2895 if (!sfc_dp_match_hw_fw_caps(&dp_tx->dp, avail_caps)) { 2896 sfc_err(sa, 2897 "Insufficient Hw/FW capabilities to use Tx datapath %s", 2898 tx_name); 2899 rc = EINVAL; 2900 goto fail_dp_tx_caps; 2901 } 2902 } else { 2903 dp_tx = sfc_dp_find_tx_by_caps(&sfc_dp_head, avail_caps); 2904 if (dp_tx == NULL) { 2905 sfc_err(sa, "Tx datapath by caps %#x not found", 2906 avail_caps); 2907 rc = ENOENT; 2908 goto fail_dp_tx; 2909 } 2910 } 2911 2912 sas->dp_tx_name = sfc_strdup(dp_tx->dp.name); 2913 if (sas->dp_tx_name == NULL) { 2914 rc = ENOMEM; 2915 goto fail_dp_tx_name; 2916 } 2917 2918 sfc_notice(sa, "use %s Tx datapath", sas->dp_tx_name); 2919 2920 sa->priv.dp_rx = dp_rx; 2921 sa->priv.dp_tx = dp_tx; 2922 2923 dev->rx_pkt_burst = dp_rx->pkt_burst; 2924 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 2925 dev->tx_pkt_burst = dp_tx->pkt_burst; 2926 2927 dev->rx_queue_count = sfc_rx_queue_count; 2928 dev->rx_descriptor_status = sfc_rx_descriptor_status; 2929 dev->tx_descriptor_status = sfc_tx_descriptor_status; 2930 dev->dev_ops = &sfc_eth_dev_ops; 2931 2932 return 0; 2933 2934 fail_dp_tx_name: 2935 fail_dp_tx_caps: 2936 fail_dp_tx: 2937 fail_kvarg_tx_datapath: 2938 rte_free(sas->dp_rx_name); 2939 sas->dp_rx_name = NULL; 2940 2941 fail_dp_rx_name: 2942 fail_dp_rx_caps: 2943 fail_dp_rx: 2944 fail_kvarg_rx_datapath: 2945 return rc; 2946 } 2947 2948 static void 2949 sfc_eth_dev_clear_ops(struct rte_eth_dev *dev) 2950 { 2951 struct sfc_adapter *sa = sfc_adapter_by_eth_dev(dev); 2952 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2953 2954 dev->dev_ops = NULL; 2955 dev->tx_pkt_prepare = NULL; 2956 dev->rx_pkt_burst = NULL; 2957 dev->tx_pkt_burst = NULL; 2958 2959 rte_free(sas->dp_tx_name); 2960 sas->dp_tx_name = NULL; 2961 sa->priv.dp_tx = NULL; 2962 2963 rte_free(sas->dp_rx_name); 2964 sas->dp_rx_name = NULL; 2965 sa->priv.dp_rx = NULL; 2966 } 2967 2968 static const struct eth_dev_ops sfc_eth_dev_secondary_ops = { 2969 .dev_supported_ptypes_get = sfc_dev_supported_ptypes_get, 2970 .reta_query = sfc_dev_rss_reta_query, 2971 .rss_hash_conf_get = sfc_dev_rss_hash_conf_get, 2972 .rxq_info_get = sfc_rx_queue_info_get, 2973 .txq_info_get = sfc_tx_queue_info_get, 2974 }; 2975 2976 static int 2977 sfc_eth_dev_secondary_init(struct rte_eth_dev *dev, uint32_t logtype_main) 2978 { 2979 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 2980 struct sfc_adapter_priv *sap; 2981 const struct sfc_dp_rx *dp_rx; 2982 const struct sfc_dp_tx *dp_tx; 2983 int rc; 2984 2985 /* 2986 * Allocate process private data from heap, since it should not 2987 * be located in shared memory allocated using rte_malloc() API. 2988 */ 2989 sap = calloc(1, sizeof(*sap)); 2990 if (sap == NULL) { 2991 rc = ENOMEM; 2992 goto fail_alloc_priv; 2993 } 2994 2995 sap->logtype_main = logtype_main; 2996 2997 dp_rx = sfc_dp_find_rx_by_name(&sfc_dp_head, sas->dp_rx_name); 2998 if (dp_rx == NULL) { 2999 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3000 "cannot find %s Rx datapath", sas->dp_rx_name); 3001 rc = ENOENT; 3002 goto fail_dp_rx; 3003 } 3004 if (~dp_rx->features & SFC_DP_RX_FEAT_MULTI_PROCESS) { 3005 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3006 "%s Rx datapath does not support multi-process", 3007 sas->dp_rx_name); 3008 rc = EINVAL; 3009 goto fail_dp_rx_multi_process; 3010 } 3011 3012 dp_tx = sfc_dp_find_tx_by_name(&sfc_dp_head, sas->dp_tx_name); 3013 if (dp_tx == NULL) { 3014 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3015 "cannot find %s Tx datapath", sas->dp_tx_name); 3016 rc = ENOENT; 3017 goto fail_dp_tx; 3018 } 3019 if (~dp_tx->features & SFC_DP_TX_FEAT_MULTI_PROCESS) { 3020 SFC_LOG(sas, RTE_LOG_ERR, logtype_main, 3021 "%s Tx datapath does not support multi-process", 3022 sas->dp_tx_name); 3023 rc = EINVAL; 3024 goto fail_dp_tx_multi_process; 3025 } 3026 3027 sap->dp_rx = dp_rx; 3028 sap->dp_tx = dp_tx; 3029 3030 dev->process_private = sap; 3031 dev->rx_pkt_burst = dp_rx->pkt_burst; 3032 dev->tx_pkt_prepare = dp_tx->pkt_prepare; 3033 dev->tx_pkt_burst = dp_tx->pkt_burst; 3034 dev->rx_queue_count = sfc_rx_queue_count; 3035 dev->rx_descriptor_status = sfc_rx_descriptor_status; 3036 dev->tx_descriptor_status = sfc_tx_descriptor_status; 3037 dev->dev_ops = &sfc_eth_dev_secondary_ops; 3038 3039 return 0; 3040 3041 fail_dp_tx_multi_process: 3042 fail_dp_tx: 3043 fail_dp_rx_multi_process: 3044 fail_dp_rx: 3045 free(sap); 3046 3047 fail_alloc_priv: 3048 return rc; 3049 } 3050 3051 static void 3052 sfc_register_dp(void) 3053 { 3054 /* Register once */ 3055 if (TAILQ_EMPTY(&sfc_dp_head)) { 3056 /* Prefer EF10 datapath */ 3057 sfc_dp_register(&sfc_dp_head, &sfc_ef100_rx.dp); 3058 sfc_dp_register(&sfc_dp_head, &sfc_ef10_essb_rx.dp); 3059 sfc_dp_register(&sfc_dp_head, &sfc_ef10_rx.dp); 3060 sfc_dp_register(&sfc_dp_head, &sfc_efx_rx.dp); 3061 3062 sfc_dp_register(&sfc_dp_head, &sfc_ef100_tx.dp); 3063 sfc_dp_register(&sfc_dp_head, &sfc_ef10_tx.dp); 3064 sfc_dp_register(&sfc_dp_head, &sfc_efx_tx.dp); 3065 sfc_dp_register(&sfc_dp_head, &sfc_ef10_simple_tx.dp); 3066 } 3067 } 3068 3069 static int 3070 sfc_parse_switch_mode(struct sfc_adapter *sa, bool has_representors) 3071 { 3072 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 3073 const char *switch_mode = NULL; 3074 int rc; 3075 3076 sfc_log_init(sa, "entry"); 3077 3078 rc = sfc_kvargs_process(sa, SFC_KVARG_SWITCH_MODE, 3079 sfc_kvarg_string_handler, &switch_mode); 3080 if (rc != 0) 3081 goto fail_kvargs; 3082 3083 if (switch_mode == NULL) { 3084 sa->switchdev = encp->enc_mae_admin && 3085 (!encp->enc_datapath_cap_evb || 3086 has_representors); 3087 } else if (strcasecmp(switch_mode, SFC_KVARG_SWITCH_MODE_LEGACY) == 0) { 3088 sa->switchdev = false; 3089 } else if (strcasecmp(switch_mode, 3090 SFC_KVARG_SWITCH_MODE_SWITCHDEV) == 0) { 3091 sa->switchdev = true; 3092 } else { 3093 sfc_err(sa, "invalid switch mode device argument '%s'", 3094 switch_mode); 3095 rc = EINVAL; 3096 goto fail_mode; 3097 } 3098 3099 sfc_log_init(sa, "done"); 3100 3101 return 0; 3102 3103 fail_mode: 3104 fail_kvargs: 3105 sfc_log_init(sa, "failed: %s", rte_strerror(rc)); 3106 3107 return rc; 3108 } 3109 3110 static int 3111 sfc_eth_dev_init(struct rte_eth_dev *dev, void *init_params) 3112 { 3113 struct sfc_adapter_shared *sas = sfc_adapter_shared_by_eth_dev(dev); 3114 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3115 struct sfc_ethdev_init_data *init_data = init_params; 3116 uint32_t logtype_main; 3117 struct sfc_adapter *sa; 3118 int rc; 3119 const efx_nic_cfg_t *encp; 3120 const struct rte_ether_addr *from; 3121 int ret; 3122 3123 if (sfc_efx_dev_class_get(pci_dev->device.devargs) != 3124 SFC_EFX_DEV_CLASS_NET) { 3125 SFC_GENERIC_LOG(DEBUG, 3126 "Incompatible device class: skip probing, should be probed by other sfc driver."); 3127 return 1; 3128 } 3129 3130 rc = sfc_dp_mport_register(); 3131 if (rc != 0) 3132 return rc; 3133 3134 sfc_register_dp(); 3135 3136 logtype_main = sfc_register_logtype(&pci_dev->addr, 3137 SFC_LOGTYPE_MAIN_STR, 3138 RTE_LOG_NOTICE); 3139 3140 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3141 return -sfc_eth_dev_secondary_init(dev, logtype_main); 3142 3143 /* Required for logging */ 3144 ret = snprintf(sas->log_prefix, sizeof(sas->log_prefix), 3145 "PMD: sfc_efx " PCI_PRI_FMT " #%" PRIu16 ": ", 3146 pci_dev->addr.domain, pci_dev->addr.bus, 3147 pci_dev->addr.devid, pci_dev->addr.function, 3148 dev->data->port_id); 3149 if (ret < 0 || ret >= (int)sizeof(sas->log_prefix)) { 3150 SFC_GENERIC_LOG(ERR, 3151 "reserved log prefix is too short for " PCI_PRI_FMT, 3152 pci_dev->addr.domain, pci_dev->addr.bus, 3153 pci_dev->addr.devid, pci_dev->addr.function); 3154 return -EINVAL; 3155 } 3156 sas->pci_addr = pci_dev->addr; 3157 sas->port_id = dev->data->port_id; 3158 3159 /* 3160 * Allocate process private data from heap, since it should not 3161 * be located in shared memory allocated using rte_malloc() API. 3162 */ 3163 sa = calloc(1, sizeof(*sa)); 3164 if (sa == NULL) { 3165 rc = ENOMEM; 3166 goto fail_alloc_sa; 3167 } 3168 3169 dev->process_private = sa; 3170 3171 /* Required for logging */ 3172 sa->priv.shared = sas; 3173 sa->priv.logtype_main = logtype_main; 3174 3175 sa->eth_dev = dev; 3176 3177 /* Copy PCI device info to the dev->data */ 3178 rte_eth_copy_pci_info(dev, pci_dev); 3179 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3180 3181 rc = sfc_kvargs_parse(sa); 3182 if (rc != 0) 3183 goto fail_kvargs_parse; 3184 3185 sfc_log_init(sa, "entry"); 3186 3187 dev->data->mac_addrs = rte_zmalloc("sfc", RTE_ETHER_ADDR_LEN, 0); 3188 if (dev->data->mac_addrs == NULL) { 3189 rc = ENOMEM; 3190 goto fail_mac_addrs; 3191 } 3192 3193 sfc_adapter_lock_init(sa); 3194 sfc_adapter_lock(sa); 3195 3196 sfc_log_init(sa, "probing"); 3197 rc = sfc_probe(sa); 3198 if (rc != 0) 3199 goto fail_probe; 3200 3201 /* 3202 * Selecting a default switch mode requires the NIC to be probed and 3203 * to have its capabilities filled in. 3204 */ 3205 rc = sfc_parse_switch_mode(sa, init_data->nb_representors > 0); 3206 if (rc != 0) 3207 goto fail_switch_mode; 3208 3209 sfc_log_init(sa, "set device ops"); 3210 rc = sfc_eth_dev_set_ops(dev); 3211 if (rc != 0) 3212 goto fail_set_ops; 3213 3214 sfc_log_init(sa, "attaching"); 3215 rc = sfc_attach(sa); 3216 if (rc != 0) 3217 goto fail_attach; 3218 3219 if (sa->switchdev && sa->mae.status != SFC_MAE_STATUS_ADMIN) { 3220 sfc_err(sa, 3221 "failed to enable switchdev mode without admin MAE privilege"); 3222 rc = ENOTSUP; 3223 goto fail_switchdev_no_mae; 3224 } 3225 3226 encp = efx_nic_cfg_get(sa->nic); 3227 3228 /* 3229 * The arguments are really reverse order in comparison to 3230 * Linux kernel. Copy from NIC config to Ethernet device data. 3231 */ 3232 from = (const struct rte_ether_addr *)(encp->enc_mac_addr); 3233 rte_ether_addr_copy(from, &dev->data->mac_addrs[0]); 3234 3235 /* 3236 * Setup the NIC DMA mapping handler. All internal mempools 3237 * MUST be created on attach before this point, and the 3238 * adapter MUST NOT create mempools with the adapter lock 3239 * held after this point. 3240 */ 3241 rc = sfc_nic_dma_attach(sa); 3242 if (rc != 0) 3243 goto fail_nic_dma_attach; 3244 3245 sfc_adapter_unlock(sa); 3246 3247 sfc_log_init(sa, "done"); 3248 return 0; 3249 3250 fail_nic_dma_attach: 3251 fail_switchdev_no_mae: 3252 sfc_detach(sa); 3253 3254 fail_attach: 3255 sfc_eth_dev_clear_ops(dev); 3256 3257 fail_set_ops: 3258 fail_switch_mode: 3259 sfc_unprobe(sa); 3260 3261 fail_probe: 3262 sfc_adapter_unlock(sa); 3263 sfc_adapter_lock_fini(sa); 3264 rte_free(dev->data->mac_addrs); 3265 dev->data->mac_addrs = NULL; 3266 3267 fail_mac_addrs: 3268 sfc_kvargs_cleanup(sa); 3269 3270 fail_kvargs_parse: 3271 sfc_log_init(sa, "failed %d", rc); 3272 dev->process_private = NULL; 3273 free(sa); 3274 3275 fail_alloc_sa: 3276 SFC_ASSERT(rc > 0); 3277 return -rc; 3278 } 3279 3280 static int 3281 sfc_eth_dev_uninit(struct rte_eth_dev *dev) 3282 { 3283 sfc_dev_close(dev); 3284 3285 return 0; 3286 } 3287 3288 static const struct rte_pci_id pci_id_sfc_efx_map[] = { 3289 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE) }, 3290 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_FARMINGDALE_VF) }, 3291 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT) }, 3292 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_GREENPORT_VF) }, 3293 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD) }, 3294 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD_VF) }, 3295 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2) }, 3296 { RTE_PCI_DEVICE(EFX_PCI_VENID_SFC, EFX_PCI_DEVID_MEDFORD2_VF) }, 3297 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD) }, 3298 { RTE_PCI_DEVICE(EFX_PCI_VENID_XILINX, EFX_PCI_DEVID_RIVERHEAD_VF) }, 3299 { .vendor_id = 0 /* sentinel */ } 3300 }; 3301 3302 static int 3303 sfc_parse_rte_devargs(const char *args, struct rte_eth_devargs *devargs) 3304 { 3305 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 3306 int rc; 3307 3308 if (args != NULL) { 3309 rc = rte_eth_devargs_parse(args, ð_da, 1); 3310 if (rc < 0) { 3311 SFC_GENERIC_LOG(ERR, 3312 "Failed to parse generic devargs '%s'", 3313 args); 3314 return rc; 3315 } 3316 } 3317 3318 *devargs = eth_da; 3319 3320 return 0; 3321 } 3322 3323 static int 3324 sfc_eth_dev_find_or_create(struct rte_pci_device *pci_dev, 3325 struct sfc_ethdev_init_data *init_data, 3326 struct rte_eth_dev **devp, 3327 bool *dev_created) 3328 { 3329 struct rte_eth_dev *dev; 3330 bool created = false; 3331 int rc; 3332 3333 dev = rte_eth_dev_allocated(pci_dev->device.name); 3334 if (dev == NULL) { 3335 rc = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 3336 sizeof(struct sfc_adapter_shared), 3337 eth_dev_pci_specific_init, pci_dev, 3338 sfc_eth_dev_init, init_data); 3339 if (rc != 0) { 3340 SFC_GENERIC_LOG(ERR, "Failed to create sfc ethdev '%s'", 3341 pci_dev->device.name); 3342 return rc; 3343 } 3344 3345 created = true; 3346 3347 dev = rte_eth_dev_allocated(pci_dev->device.name); 3348 if (dev == NULL) { 3349 SFC_GENERIC_LOG(ERR, 3350 "Failed to find allocated sfc ethdev '%s'", 3351 pci_dev->device.name); 3352 return -ENODEV; 3353 } 3354 } 3355 3356 *devp = dev; 3357 *dev_created = created; 3358 3359 return 0; 3360 } 3361 3362 static int 3363 sfc_eth_dev_create_repr(struct sfc_adapter *sa, 3364 efx_pcie_interface_t controller, 3365 uint16_t port, 3366 uint16_t repr_port, 3367 enum rte_eth_representor_type type) 3368 { 3369 struct sfc_repr_entity_info entity; 3370 efx_mport_sel_t mport_sel; 3371 int rc; 3372 3373 switch (type) { 3374 case RTE_ETH_REPRESENTOR_NONE: 3375 return 0; 3376 case RTE_ETH_REPRESENTOR_VF: 3377 case RTE_ETH_REPRESENTOR_PF: 3378 break; 3379 case RTE_ETH_REPRESENTOR_SF: 3380 sfc_err(sa, "SF representors are not supported"); 3381 return ENOTSUP; 3382 default: 3383 sfc_err(sa, "unknown representor type: %d", type); 3384 return ENOTSUP; 3385 } 3386 3387 rc = efx_mae_mport_by_pcie_mh_function(controller, 3388 port, 3389 repr_port, 3390 &mport_sel); 3391 if (rc != 0) { 3392 sfc_err(sa, 3393 "failed to get m-port selector for controller %u port %u repr_port %u: %s", 3394 controller, port, repr_port, rte_strerror(-rc)); 3395 return rc; 3396 } 3397 3398 memset(&entity, 0, sizeof(entity)); 3399 entity.type = type; 3400 entity.intf = controller; 3401 entity.pf = port; 3402 entity.vf = repr_port; 3403 3404 rc = sfc_repr_create(sa->eth_dev, &entity, sa->mae.switch_domain_id, 3405 &mport_sel); 3406 if (rc != 0) { 3407 sfc_err(sa, 3408 "failed to create representor for controller %u port %u repr_port %u: %s", 3409 controller, port, repr_port, rte_strerror(-rc)); 3410 return rc; 3411 } 3412 3413 return 0; 3414 } 3415 3416 static int 3417 sfc_eth_dev_create_repr_port(struct sfc_adapter *sa, 3418 const struct rte_eth_devargs *eth_da, 3419 efx_pcie_interface_t controller, 3420 uint16_t port) 3421 { 3422 int first_error = 0; 3423 uint16_t i; 3424 int rc; 3425 3426 if (eth_da->type == RTE_ETH_REPRESENTOR_PF) { 3427 return sfc_eth_dev_create_repr(sa, controller, port, 3428 EFX_PCI_VF_INVALID, 3429 eth_da->type); 3430 } 3431 3432 for (i = 0; i < eth_da->nb_representor_ports; i++) { 3433 rc = sfc_eth_dev_create_repr(sa, controller, port, 3434 eth_da->representor_ports[i], 3435 eth_da->type); 3436 if (rc != 0 && first_error == 0) 3437 first_error = rc; 3438 } 3439 3440 return first_error; 3441 } 3442 3443 static int 3444 sfc_eth_dev_create_repr_controller(struct sfc_adapter *sa, 3445 const struct rte_eth_devargs *eth_da, 3446 efx_pcie_interface_t controller) 3447 { 3448 const efx_nic_cfg_t *encp; 3449 int first_error = 0; 3450 uint16_t default_port; 3451 uint16_t i; 3452 int rc; 3453 3454 if (eth_da->nb_ports == 0) { 3455 encp = efx_nic_cfg_get(sa->nic); 3456 default_port = encp->enc_intf == controller ? encp->enc_pf : 0; 3457 return sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3458 default_port); 3459 } 3460 3461 for (i = 0; i < eth_da->nb_ports; i++) { 3462 rc = sfc_eth_dev_create_repr_port(sa, eth_da, controller, 3463 eth_da->ports[i]); 3464 if (rc != 0 && first_error == 0) 3465 first_error = rc; 3466 } 3467 3468 return first_error; 3469 } 3470 3471 static int 3472 sfc_eth_dev_create_representors(struct rte_eth_dev *dev, 3473 const struct rte_eth_devargs *eth_da) 3474 { 3475 efx_pcie_interface_t intf; 3476 const efx_nic_cfg_t *encp; 3477 struct sfc_adapter *sa; 3478 uint16_t switch_domain_id; 3479 uint16_t i; 3480 int rc; 3481 3482 sa = sfc_adapter_by_eth_dev(dev); 3483 switch_domain_id = sa->mae.switch_domain_id; 3484 3485 switch (eth_da->type) { 3486 case RTE_ETH_REPRESENTOR_NONE: 3487 return 0; 3488 case RTE_ETH_REPRESENTOR_PF: 3489 case RTE_ETH_REPRESENTOR_VF: 3490 break; 3491 case RTE_ETH_REPRESENTOR_SF: 3492 sfc_err(sa, "SF representors are not supported"); 3493 return -ENOTSUP; 3494 default: 3495 sfc_err(sa, "unknown representor type: %d", 3496 eth_da->type); 3497 return -ENOTSUP; 3498 } 3499 3500 if (!sa->switchdev) { 3501 sfc_err(sa, "cannot create representors in non-switchdev mode"); 3502 return -EINVAL; 3503 } 3504 3505 if (!sfc_repr_available(sfc_sa2shared(sa))) { 3506 sfc_err(sa, "cannot create representors: unsupported"); 3507 3508 return -ENOTSUP; 3509 } 3510 3511 /* 3512 * This is needed to construct the DPDK controller -> EFX interface 3513 * mapping. 3514 */ 3515 sfc_adapter_lock(sa); 3516 rc = sfc_process_mport_journal(sa); 3517 sfc_adapter_unlock(sa); 3518 if (rc != 0) { 3519 SFC_ASSERT(rc > 0); 3520 return -rc; 3521 } 3522 3523 if (eth_da->nb_mh_controllers > 0) { 3524 for (i = 0; i < eth_da->nb_mh_controllers; i++) { 3525 rc = sfc_mae_switch_domain_get_intf(switch_domain_id, 3526 eth_da->mh_controllers[i], 3527 &intf); 3528 if (rc != 0) { 3529 sfc_err(sa, "failed to get representor"); 3530 continue; 3531 } 3532 sfc_eth_dev_create_repr_controller(sa, eth_da, intf); 3533 } 3534 } else { 3535 encp = efx_nic_cfg_get(sa->nic); 3536 sfc_eth_dev_create_repr_controller(sa, eth_da, encp->enc_intf); 3537 } 3538 3539 return 0; 3540 } 3541 3542 static int sfc_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3543 struct rte_pci_device *pci_dev) 3544 { 3545 struct sfc_ethdev_init_data init_data; 3546 struct rte_eth_devargs eth_da; 3547 struct rte_eth_dev *dev; 3548 bool dev_created; 3549 int rc; 3550 3551 if (pci_dev->device.devargs != NULL) { 3552 rc = sfc_parse_rte_devargs(pci_dev->device.devargs->args, 3553 ð_da); 3554 if (rc != 0) 3555 return rc; 3556 } else { 3557 memset(ð_da, 0, sizeof(eth_da)); 3558 } 3559 3560 /* If no VF representors specified, check for PF ones */ 3561 if (eth_da.nb_representor_ports > 0) 3562 init_data.nb_representors = eth_da.nb_representor_ports; 3563 else 3564 init_data.nb_representors = eth_da.nb_ports; 3565 3566 if (init_data.nb_representors > 0 && 3567 rte_eal_process_type() != RTE_PROC_PRIMARY) { 3568 SFC_GENERIC_LOG(ERR, 3569 "Create representors from secondary process not supported, dev '%s'", 3570 pci_dev->device.name); 3571 return -ENOTSUP; 3572 } 3573 3574 /* 3575 * Driver supports RTE_PCI_DRV_PROBE_AGAIN. Hence create device only 3576 * if it does not already exist. Re-probing an existing device is 3577 * expected to allow additional representors to be configured. 3578 */ 3579 rc = sfc_eth_dev_find_or_create(pci_dev, &init_data, &dev, 3580 &dev_created); 3581 if (rc != 0) 3582 return rc; 3583 3584 rc = sfc_eth_dev_create_representors(dev, ð_da); 3585 if (rc != 0) { 3586 if (dev_created) 3587 (void)rte_eth_dev_destroy(dev, sfc_eth_dev_uninit); 3588 3589 return rc; 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int sfc_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3596 { 3597 return rte_eth_dev_pci_generic_remove(pci_dev, sfc_eth_dev_uninit); 3598 } 3599 3600 static struct rte_pci_driver sfc_efx_pmd = { 3601 .id_table = pci_id_sfc_efx_map, 3602 .drv_flags = 3603 RTE_PCI_DRV_INTR_LSC | 3604 RTE_PCI_DRV_NEED_MAPPING | 3605 RTE_PCI_DRV_PROBE_AGAIN, 3606 .probe = sfc_eth_dev_pci_probe, 3607 .remove = sfc_eth_dev_pci_remove, 3608 }; 3609 3610 RTE_PMD_REGISTER_PCI(net_sfc_efx, sfc_efx_pmd); 3611 RTE_PMD_REGISTER_PCI_TABLE(net_sfc_efx, pci_id_sfc_efx_map); 3612 RTE_PMD_REGISTER_KMOD_DEP(net_sfc_efx, "* igb_uio | uio_pci_generic | vfio-pci"); 3613 RTE_PMD_REGISTER_PARAM_STRING(net_sfc_efx, 3614 SFC_KVARG_SWITCH_MODE "=" SFC_KVARG_VALUES_SWITCH_MODE " " 3615 SFC_KVARG_RX_DATAPATH "=" SFC_KVARG_VALUES_RX_DATAPATH " " 3616 SFC_KVARG_TX_DATAPATH "=" SFC_KVARG_VALUES_TX_DATAPATH " " 3617 SFC_KVARG_PERF_PROFILE "=" SFC_KVARG_VALUES_PERF_PROFILE " " 3618 SFC_KVARG_FW_VARIANT "=" SFC_KVARG_VALUES_FW_VARIANT " " 3619 SFC_KVARG_RXD_WAIT_TIMEOUT_NS "=<long> " 3620 SFC_KVARG_STATS_UPDATE_PERIOD_MS "=<long>"); 3621 3622 RTE_INIT(sfc_driver_register_logtype) 3623 { 3624 int ret; 3625 3626 ret = rte_log_register_type_and_pick_level(SFC_LOGTYPE_PREFIX "driver", 3627 RTE_LOG_NOTICE); 3628 sfc_logtype_driver = (ret < 0) ? RTE_LOGTYPE_EAL : ret; 3629 } 3630