1c121f008SAndrew Rybchenko /* SPDX-License-Identifier: BSD-3-Clause 2c121f008SAndrew Rybchenko * 3*a0147be5SAndrew Rybchenko * Copyright(c) 2019-2020 Xilinx, Inc. 4*a0147be5SAndrew Rybchenko * Copyright(c) 2018-2019 Solarflare Communications Inc. 5c121f008SAndrew Rybchenko * 6c121f008SAndrew Rybchenko * This software was jointly developed between OKTET Labs (under contract 7c121f008SAndrew Rybchenko * for Solarflare) and Solarflare Communications, Inc. 8c121f008SAndrew Rybchenko */ 9c121f008SAndrew Rybchenko 10c121f008SAndrew Rybchenko #ifndef _SFC_EF10_RX_EV_H 11c121f008SAndrew Rybchenko #define _SFC_EF10_RX_EV_H 12c121f008SAndrew Rybchenko 13c121f008SAndrew Rybchenko #include <rte_mbuf.h> 14c121f008SAndrew Rybchenko 15c121f008SAndrew Rybchenko #include "efx_types.h" 16c121f008SAndrew Rybchenko #include "efx_regs.h" 17c121f008SAndrew Rybchenko #include "efx_regs_ef10.h" 18c121f008SAndrew Rybchenko 19c121f008SAndrew Rybchenko #ifdef __cplusplus 20c121f008SAndrew Rybchenko extern "C" { 21c121f008SAndrew Rybchenko #endif 22c121f008SAndrew Rybchenko 23c121f008SAndrew Rybchenko static inline void 24c121f008SAndrew Rybchenko sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m, 25c121f008SAndrew Rybchenko uint64_t ol_mask) 26c121f008SAndrew Rybchenko { 27c121f008SAndrew Rybchenko uint32_t tun_ptype = 0; 28c121f008SAndrew Rybchenko /* Which event bit is mapped to PKT_RX_IP_CKSUM_* */ 29c121f008SAndrew Rybchenko int8_t ip_csum_err_bit; 30c121f008SAndrew Rybchenko /* Which event bit is mapped to PKT_RX_L4_CKSUM_* */ 31c121f008SAndrew Rybchenko int8_t l4_csum_err_bit; 32c121f008SAndrew Rybchenko uint32_t l2_ptype = 0; 33c121f008SAndrew Rybchenko uint32_t l3_ptype = 0; 34c121f008SAndrew Rybchenko uint32_t l4_ptype = 0; 35c121f008SAndrew Rybchenko uint64_t ol_flags = 0; 36c121f008SAndrew Rybchenko 37390f9b8dSAndrew Rybchenko if (unlikely(rx_ev.eq_u64[0] & 38390f9b8dSAndrew Rybchenko rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) | 39390f9b8dSAndrew Rybchenko (1ull << ESF_DZ_RX_ECRC_ERR_LBN) | 40aeeb5571SAndrew Rybchenko (1ull << ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))) { 41aeeb5571SAndrew Rybchenko /* Zero packet type is used as a marker to dicard bad packets */ 42c121f008SAndrew Rybchenko goto done; 43aeeb5571SAndrew Rybchenko } 44c121f008SAndrew Rybchenko 457ee7e57cSAndrew Rybchenko #if SFC_EF10_RX_EV_ENCAP_SUPPORT 46c121f008SAndrew Rybchenko switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) { 47c121f008SAndrew Rybchenko default: 48c121f008SAndrew Rybchenko /* Unexpected encapsulation tag class */ 49c121f008SAndrew Rybchenko SFC_ASSERT(false); 50c121f008SAndrew Rybchenko /* FALLTHROUGH */ 51c121f008SAndrew Rybchenko case ESE_EZ_ENCAP_HDR_NONE: 52c121f008SAndrew Rybchenko break; 53c121f008SAndrew Rybchenko case ESE_EZ_ENCAP_HDR_VXLAN: 54c121f008SAndrew Rybchenko /* 55c121f008SAndrew Rybchenko * It is definitely UDP, but we have no information 56c121f008SAndrew Rybchenko * about IPv4 vs IPv6 and VLAN tagging. 57c121f008SAndrew Rybchenko */ 58c121f008SAndrew Rybchenko tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP; 59c121f008SAndrew Rybchenko break; 60c121f008SAndrew Rybchenko case ESE_EZ_ENCAP_HDR_GRE: 61c121f008SAndrew Rybchenko /* 62c121f008SAndrew Rybchenko * We have no information about IPv4 vs IPv6 and VLAN tagging. 63c121f008SAndrew Rybchenko */ 64c121f008SAndrew Rybchenko tun_ptype = RTE_PTYPE_TUNNEL_NVGRE; 65c121f008SAndrew Rybchenko break; 66c121f008SAndrew Rybchenko } 677ee7e57cSAndrew Rybchenko #endif 68c121f008SAndrew Rybchenko 69c121f008SAndrew Rybchenko if (tun_ptype == 0) { 70c121f008SAndrew Rybchenko ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN; 71c121f008SAndrew Rybchenko l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN; 72c121f008SAndrew Rybchenko } else { 73c121f008SAndrew Rybchenko ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN; 74c121f008SAndrew Rybchenko l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN; 75c121f008SAndrew Rybchenko if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, 76c121f008SAndrew Rybchenko ESF_DZ_RX_IPCKSUM_ERR_LBN))) 77c121f008SAndrew Rybchenko ol_flags |= PKT_RX_EIP_CKSUM_BAD; 78c121f008SAndrew Rybchenko } 79c121f008SAndrew Rybchenko 80c121f008SAndrew Rybchenko switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) { 81c121f008SAndrew Rybchenko case ESE_DZ_ETH_TAG_CLASS_NONE: 82c121f008SAndrew Rybchenko l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER : 83c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L2_ETHER; 84c121f008SAndrew Rybchenko break; 85c121f008SAndrew Rybchenko case ESE_DZ_ETH_TAG_CLASS_VLAN1: 86c121f008SAndrew Rybchenko l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN : 87c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L2_ETHER_VLAN; 88c121f008SAndrew Rybchenko break; 89c121f008SAndrew Rybchenko case ESE_DZ_ETH_TAG_CLASS_VLAN2: 90c121f008SAndrew Rybchenko l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ : 91c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L2_ETHER_QINQ; 92c121f008SAndrew Rybchenko break; 93c121f008SAndrew Rybchenko default: 94c121f008SAndrew Rybchenko /* Unexpected Eth tag class */ 95c121f008SAndrew Rybchenko SFC_ASSERT(false); 96c121f008SAndrew Rybchenko } 97c121f008SAndrew Rybchenko 98c121f008SAndrew Rybchenko switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) { 99c121f008SAndrew Rybchenko case ESE_DZ_L3_CLASS_IP4_FRAG: 100c121f008SAndrew Rybchenko l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG : 101c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L4_FRAG; 102c121f008SAndrew Rybchenko /* FALLTHROUGH */ 103c121f008SAndrew Rybchenko case ESE_DZ_L3_CLASS_IP4: 104c121f008SAndrew Rybchenko l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 105c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 106c121f008SAndrew Rybchenko ol_flags |= PKT_RX_RSS_HASH | 107c121f008SAndrew Rybchenko ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ? 108c121f008SAndrew Rybchenko PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD); 109c121f008SAndrew Rybchenko break; 110c121f008SAndrew Rybchenko case ESE_DZ_L3_CLASS_IP6_FRAG: 111c121f008SAndrew Rybchenko l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG : 112c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L4_FRAG; 113c121f008SAndrew Rybchenko /* FALLTHROUGH */ 114c121f008SAndrew Rybchenko case ESE_DZ_L3_CLASS_IP6: 115c121f008SAndrew Rybchenko l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 116c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 117c121f008SAndrew Rybchenko ol_flags |= PKT_RX_RSS_HASH; 118c121f008SAndrew Rybchenko break; 119c121f008SAndrew Rybchenko case ESE_DZ_L3_CLASS_ARP: 120c121f008SAndrew Rybchenko /* Override Layer 2 packet type */ 121c121f008SAndrew Rybchenko /* There is no ARP classification for inner packets */ 122c121f008SAndrew Rybchenko if (tun_ptype == 0) 123c121f008SAndrew Rybchenko l2_ptype = RTE_PTYPE_L2_ETHER_ARP; 124c121f008SAndrew Rybchenko break; 125812bb208SAndrew Rybchenko case ESE_DZ_L3_CLASS_UNKNOWN: 126812bb208SAndrew Rybchenko break; 127c121f008SAndrew Rybchenko default: 128c121f008SAndrew Rybchenko /* Unexpected Layer 3 class */ 129c121f008SAndrew Rybchenko SFC_ASSERT(false); 130c121f008SAndrew Rybchenko } 131c121f008SAndrew Rybchenko 132c121f008SAndrew Rybchenko /* 133c121f008SAndrew Rybchenko * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only 134c121f008SAndrew Rybchenko * 2 bits wide on Medford2. Check it is safe to use the Medford2 field 135c121f008SAndrew Rybchenko * and values for all EF10 controllers. 136c121f008SAndrew Rybchenko */ 137c121f008SAndrew Rybchenko RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN); 138c121f008SAndrew Rybchenko switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) { 139c121f008SAndrew Rybchenko case ESE_FZ_L4_CLASS_TCP: 140c121f008SAndrew Rybchenko RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP); 141c121f008SAndrew Rybchenko l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP : 142c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L4_TCP; 143c121f008SAndrew Rybchenko ol_flags |= 144c121f008SAndrew Rybchenko (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ? 145c121f008SAndrew Rybchenko PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD; 146c121f008SAndrew Rybchenko break; 147c121f008SAndrew Rybchenko case ESE_FZ_L4_CLASS_UDP: 148c121f008SAndrew Rybchenko RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP); 149c121f008SAndrew Rybchenko l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP : 150c121f008SAndrew Rybchenko RTE_PTYPE_INNER_L4_UDP; 151c121f008SAndrew Rybchenko ol_flags |= 152c121f008SAndrew Rybchenko (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ? 153c121f008SAndrew Rybchenko PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD; 154c121f008SAndrew Rybchenko break; 155c121f008SAndrew Rybchenko case ESE_FZ_L4_CLASS_UNKNOWN: 156c121f008SAndrew Rybchenko RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN != 157c121f008SAndrew Rybchenko ESE_DE_L4_CLASS_UNKNOWN); 158c121f008SAndrew Rybchenko break; 159c121f008SAndrew Rybchenko default: 160c121f008SAndrew Rybchenko /* Unexpected Layer 4 class */ 161c121f008SAndrew Rybchenko SFC_ASSERT(false); 162c121f008SAndrew Rybchenko } 163c121f008SAndrew Rybchenko 164aeeb5571SAndrew Rybchenko SFC_ASSERT(l2_ptype != 0); 165aeeb5571SAndrew Rybchenko 166c121f008SAndrew Rybchenko done: 167c121f008SAndrew Rybchenko m->ol_flags = ol_flags & ol_mask; 168c121f008SAndrew Rybchenko m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype; 169c121f008SAndrew Rybchenko } 170c121f008SAndrew Rybchenko 171c121f008SAndrew Rybchenko 172c121f008SAndrew Rybchenko #ifdef __cplusplus 173c121f008SAndrew Rybchenko } 174c121f008SAndrew Rybchenko #endif 175c121f008SAndrew Rybchenko #endif /* _SFC_EF10_RX_EV_H */ 176