1619f6ebcSHoward Wang /* SPDX-License-Identifier: BSD-3-Clause 2619f6ebcSHoward Wang * Copyright(c) 2024 Realtek Corporation. All rights reserved 3619f6ebcSHoward Wang */ 4619f6ebcSHoward Wang 5619f6ebcSHoward Wang #ifndef R8169_PHY_H 6619f6ebcSHoward Wang #define R8169_PHY_H 7619f6ebcSHoward Wang 8619f6ebcSHoward Wang #include <stdint.h> 98e852260SHoward Wang #include <stdbool.h> 10619f6ebcSHoward Wang 11619f6ebcSHoward Wang #include <rte_ethdev.h> 12619f6ebcSHoward Wang #include <rte_ethdev_core.h> 13619f6ebcSHoward Wang 14619f6ebcSHoward Wang #include "r8169_compat.h" 15619f6ebcSHoward Wang #include "r8169_ethdev.h" 16619f6ebcSHoward Wang 1738589978SHoward Wang /* Generic MII registers. */ 1838589978SHoward Wang #define MII_BMCR 0x00 /* Basic mode control register */ 1938589978SHoward Wang #define MII_BMSR 0x01 /* Basic mode status register */ 2038589978SHoward Wang #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 2138589978SHoward Wang #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 2238589978SHoward Wang #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 2338589978SHoward Wang #define MII_LPA 0x05 /* Link partner ability reg */ 2438589978SHoward Wang #define MII_EXPANSION 0x06 /* Expansion register */ 2538589978SHoward Wang #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 2638589978SHoward Wang #define MII_STAT1000 0x0a /* 1000BASE-T status */ 2738589978SHoward Wang #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 2838589978SHoward Wang #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 2938589978SHoward Wang #define MII_ESTATUS 0x0f /* Extended Status */ 3038589978SHoward Wang #define MII_DCOUNTER 0x12 /* Disconnect counter */ 3138589978SHoward Wang #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 3238589978SHoward Wang #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 3338589978SHoward Wang #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 3438589978SHoward Wang #define MII_SREVISION 0x16 /* Silicon revision */ 3538589978SHoward Wang #define MII_RESV1 0x17 /* Reserved... */ 3638589978SHoward Wang #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 3738589978SHoward Wang #define MII_PHYADDR 0x19 /* PHY address */ 3838589978SHoward Wang #define MII_RESV2 0x1a /* Reserved... */ 3938589978SHoward Wang #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 4038589978SHoward Wang #define MII_NCONFIG 0x1c /* Network interface config */ 4138589978SHoward Wang 4238589978SHoward Wang /* Basic mode control register. */ 4338589978SHoward Wang #define BMCR_RESV 0x003f /* Unused... */ 4438589978SHoward Wang #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 4538589978SHoward Wang #define BMCR_CTST 0x0080 /* Collision test */ 4638589978SHoward Wang #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 4738589978SHoward Wang #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 4838589978SHoward Wang #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 4938589978SHoward Wang #define BMCR_PDOWN 0x0800 /* Enable low power state */ 5038589978SHoward Wang #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 5138589978SHoward Wang #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 5238589978SHoward Wang #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 5338589978SHoward Wang #define BMCR_RESET 0x8000 /* Reset to default state */ 5438589978SHoward Wang #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ 5538589978SHoward Wang 5638589978SHoward Wang /* Basic mode status register. */ 5738589978SHoward Wang #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 5838589978SHoward Wang #define BMSR_JCD 0x0002 /* Jabber detected */ 5938589978SHoward Wang #define BMSR_LSTATUS 0x0004 /* Link status */ 6038589978SHoward Wang #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 6138589978SHoward Wang #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 6238589978SHoward Wang #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 6338589978SHoward Wang #define BMSR_RESV 0x00c0 /* Unused... */ 6438589978SHoward Wang #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 6538589978SHoward Wang #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 6638589978SHoward Wang #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 6738589978SHoward Wang #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 6838589978SHoward Wang #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 6938589978SHoward Wang #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 7038589978SHoward Wang #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 7138589978SHoward Wang #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 7238589978SHoward Wang 7338589978SHoward Wang /* Advertisement control register. */ 7438589978SHoward Wang #define ADVERTISE_SLCT 0x001f /* Selector bits */ 7538589978SHoward Wang #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 7638589978SHoward Wang #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 7738589978SHoward Wang #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 7838589978SHoward Wang #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 7938589978SHoward Wang #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 8038589978SHoward Wang #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 8138589978SHoward Wang #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 8238589978SHoward Wang #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 8338589978SHoward Wang #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 8438589978SHoward Wang #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 8538589978SHoward Wang #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 8638589978SHoward Wang #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */ 8738589978SHoward Wang #define ADVERTISE_RESV 0x1000 /* Unused... */ 8838589978SHoward Wang #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 8938589978SHoward Wang #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 9038589978SHoward Wang #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 9138589978SHoward Wang 9238589978SHoward Wang /* 1000BASE-T Control register */ 9338589978SHoward Wang #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 9438589978SHoward Wang #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 9538589978SHoward Wang 9638589978SHoward Wang #define RTK_ADVERTISE_2500FULL 0x80 9738589978SHoward Wang #define RTK_ADVERTISE_5000FULL 0x100 9838589978SHoward Wang #define RTK_ADVERTISE_10000FULL 0x1000 9938589978SHoward Wang #define RTK_LPA_ADVERTISE_2500FULL 0x20 10038589978SHoward Wang #define RTK_LPA_ADVERTISE_5000FULL 0x40 10138589978SHoward Wang #define RTK_LPA_ADVERTISE_10000FULL 0x800 10238589978SHoward Wang 10338589978SHoward Wang #define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0) 10438589978SHoward Wang 10538589978SHoward Wang #define HW_SUPP_PHY_LINK_SPEED_5000M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 5000) 10638589978SHoward Wang 10738589978SHoward Wang #define MDIO_EEE_100TX 0x0002 10838589978SHoward Wang #define MDIO_EEE_1000T 0x0004 10938589978SHoward Wang #define MDIO_EEE_2_5GT 0x0001 11038589978SHoward Wang #define MDIO_EEE_5GT 0x0002 11138589978SHoward Wang 112619f6ebcSHoward Wang void rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); 113619f6ebcSHoward Wang void rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); 114619f6ebcSHoward Wang 115c4adac96SHoward Wang u32 rtl_mdio_direct_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr); 116c4adac96SHoward Wang void rtl_mdio_direct_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value); 117c4adac96SHoward Wang 118c4adac96SHoward Wang u32 rtl_mdio_read(struct rtl_hw *hw, u32 RegAddr); 119c4adac96SHoward Wang void rtl_mdio_write(struct rtl_hw *hw, u32 RegAddr, u32 value); 120c4adac96SHoward Wang 121c4adac96SHoward Wang void rtl_clear_and_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, 122c4adac96SHoward Wang u16 clearmask, u16 setmask); 123c4adac96SHoward Wang void rtl_clear_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); 124c4adac96SHoward Wang void rtl_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); 125c4adac96SHoward Wang 126c4adac96SHoward Wang void rtl_ephy_write(struct rtl_hw *hw, int addr, int value); 127c4adac96SHoward Wang 128c4adac96SHoward Wang void rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, 129c4adac96SHoward Wang u16 setmask); 130c4adac96SHoward Wang void rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); 131c4adac96SHoward Wang void rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); 132c4adac96SHoward Wang 1338e852260SHoward Wang bool rtl_set_phy_mcu_patch_request(struct rtl_hw *hw); 1348e852260SHoward Wang bool rtl_clear_phy_mcu_patch_request(struct rtl_hw *hw); 1358e852260SHoward Wang 1368e852260SHoward Wang void rtl_set_phy_mcu_ram_code(struct rtl_hw *hw, const u16 *ramcode, 1378e852260SHoward Wang u16 codesize); 1388e852260SHoward Wang 13938589978SHoward Wang void rtl_powerup_pll(struct rtl_hw *hw); 14038589978SHoward Wang void rtl_powerdown_pll(struct rtl_hw *hw); 14138589978SHoward Wang 14238589978SHoward Wang void rtl_hw_ephy_config(struct rtl_hw *hw); 14338589978SHoward Wang void rtl_hw_phy_config(struct rtl_hw *hw); 14438589978SHoward Wang 145*f7327670SHoward Wang int rtl_set_speed(struct rtl_hw *hw); 146*f7327670SHoward Wang 147619f6ebcSHoward Wang #endif /* R8169_PHY_H */ 148