1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include <rte_net.h> 10 #include "qede_rxtx.h" 11 12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq) 13 { 14 struct rte_mbuf *new_mb = NULL; 15 struct eth_rx_bd *rx_bd; 16 dma_addr_t mapping; 17 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq); 18 19 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool); 20 if (unlikely(!new_mb)) { 21 PMD_RX_LOG(ERR, rxq, 22 "Failed to allocate rx buffer " 23 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u", 24 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq), 25 rte_mempool_avail_count(rxq->mb_pool), 26 rte_mempool_in_use_count(rxq->mb_pool)); 27 return -ENOMEM; 28 } 29 rxq->sw_rx_ring[idx].mbuf = new_mb; 30 rxq->sw_rx_ring[idx].page_offset = 0; 31 mapping = rte_mbuf_data_iova_default(new_mb); 32 /* Advance PROD and get BD pointer */ 33 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring); 34 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping)); 35 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping)); 36 rxq->sw_rx_prod++; 37 return 0; 38 } 39 40 int 41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 42 uint16_t nb_desc, unsigned int socket_id, 43 __rte_unused const struct rte_eth_rxconf *rx_conf, 44 struct rte_mempool *mp) 45 { 46 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 47 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 48 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 49 struct qede_rx_queue *rxq; 50 uint16_t max_rx_pkt_len; 51 uint16_t bufsz; 52 size_t size; 53 int rc; 54 55 PMD_INIT_FUNC_TRACE(edev); 56 57 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */ 58 if (!rte_is_power_of_2(nb_desc)) { 59 DP_ERR(edev, "Ring size %u is not power of 2\n", 60 nb_desc); 61 return -EINVAL; 62 } 63 64 /* Free memory prior to re-allocation if needed... */ 65 if (dev->data->rx_queues[queue_idx] != NULL) { 66 qede_rx_queue_release(dev->data->rx_queues[queue_idx]); 67 dev->data->rx_queues[queue_idx] = NULL; 68 } 69 70 /* First allocate the rx queue data structure */ 71 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue), 72 RTE_CACHE_LINE_SIZE, socket_id); 73 74 if (!rxq) { 75 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u", 76 socket_id); 77 return -ENOMEM; 78 } 79 80 rxq->qdev = qdev; 81 rxq->mb_pool = mp; 82 rxq->nb_rx_desc = nb_desc; 83 rxq->queue_id = queue_idx; 84 rxq->port_id = dev->data->port_id; 85 86 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len; 87 88 /* Fix up RX buffer size */ 89 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 90 if ((rxmode->enable_scatter) || 91 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) { 92 if (!dev->data->scattered_rx) { 93 DP_INFO(edev, "Forcing scatter-gather mode\n"); 94 dev->data->scattered_rx = 1; 95 } 96 } 97 98 if (dev->data->scattered_rx) 99 rxq->rx_buf_size = bufsz + ETHER_HDR_LEN + 100 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD; 101 else 102 rxq->rx_buf_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD; 103 /* Align to cache-line size if needed */ 104 rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size); 105 106 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n", 107 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx); 108 109 /* Allocate the parallel driver ring for Rx buffers */ 110 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc; 111 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size, 112 RTE_CACHE_LINE_SIZE, socket_id); 113 if (!rxq->sw_rx_ring) { 114 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on" 115 " socket %u\n", socket_id); 116 rte_free(rxq); 117 return -ENOMEM; 118 } 119 120 /* Allocate FW Rx ring */ 121 rc = qdev->ops->common->chain_alloc(edev, 122 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE, 123 ECORE_CHAIN_MODE_NEXT_PTR, 124 ECORE_CHAIN_CNT_TYPE_U16, 125 rxq->nb_rx_desc, 126 sizeof(struct eth_rx_bd), 127 &rxq->rx_bd_ring, 128 NULL); 129 130 if (rc != ECORE_SUCCESS) { 131 DP_ERR(edev, "Memory allocation fails for RX BD ring" 132 " on socket %u\n", socket_id); 133 rte_free(rxq->sw_rx_ring); 134 rte_free(rxq); 135 return -ENOMEM; 136 } 137 138 /* Allocate FW completion ring */ 139 rc = qdev->ops->common->chain_alloc(edev, 140 ECORE_CHAIN_USE_TO_CONSUME, 141 ECORE_CHAIN_MODE_PBL, 142 ECORE_CHAIN_CNT_TYPE_U16, 143 rxq->nb_rx_desc, 144 sizeof(union eth_rx_cqe), 145 &rxq->rx_comp_ring, 146 NULL); 147 148 if (rc != ECORE_SUCCESS) { 149 DP_ERR(edev, "Memory allocation fails for RX CQE ring" 150 " on socket %u\n", socket_id); 151 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring); 152 rte_free(rxq->sw_rx_ring); 153 rte_free(rxq); 154 return -ENOMEM; 155 } 156 157 dev->data->rx_queues[queue_idx] = rxq; 158 qdev->fp_array[queue_idx].rxq = rxq; 159 160 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n", 161 queue_idx, nb_desc, qdev->mtu, socket_id); 162 163 return 0; 164 } 165 166 static void 167 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev, 168 struct qede_rx_queue *rxq) 169 { 170 DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id); 171 ecore_chain_reset(&rxq->rx_bd_ring); 172 ecore_chain_reset(&rxq->rx_comp_ring); 173 rxq->sw_rx_prod = 0; 174 rxq->sw_rx_cons = 0; 175 *rxq->hw_cons_ptr = 0; 176 } 177 178 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq) 179 { 180 uint16_t i; 181 182 if (rxq->sw_rx_ring) { 183 for (i = 0; i < rxq->nb_rx_desc; i++) { 184 if (rxq->sw_rx_ring[i].mbuf) { 185 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf); 186 rxq->sw_rx_ring[i].mbuf = NULL; 187 } 188 } 189 } 190 } 191 192 void qede_rx_queue_release(void *rx_queue) 193 { 194 struct qede_rx_queue *rxq = rx_queue; 195 196 if (rxq) { 197 qede_rx_queue_release_mbufs(rxq); 198 rte_free(rxq->sw_rx_ring); 199 rte_free(rxq); 200 } 201 } 202 203 /* Stops a given RX queue in the HW */ 204 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 205 { 206 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 207 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 208 struct ecore_hwfn *p_hwfn; 209 struct qede_rx_queue *rxq; 210 int hwfn_index; 211 int rc; 212 213 if (rx_queue_id < eth_dev->data->nb_rx_queues) { 214 rxq = eth_dev->data->rx_queues[rx_queue_id]; 215 hwfn_index = rx_queue_id % edev->num_hwfns; 216 p_hwfn = &edev->hwfns[hwfn_index]; 217 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle, 218 true, false); 219 if (rc != ECORE_SUCCESS) { 220 DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id); 221 return -1; 222 } 223 qede_rx_queue_release_mbufs(rxq); 224 qede_rx_queue_reset(qdev, rxq); 225 eth_dev->data->rx_queue_state[rx_queue_id] = 226 RTE_ETH_QUEUE_STATE_STOPPED; 227 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id); 228 } else { 229 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id); 230 rc = -EINVAL; 231 } 232 233 return rc; 234 } 235 236 int 237 qede_tx_queue_setup(struct rte_eth_dev *dev, 238 uint16_t queue_idx, 239 uint16_t nb_desc, 240 unsigned int socket_id, 241 const struct rte_eth_txconf *tx_conf) 242 { 243 struct qede_dev *qdev = dev->data->dev_private; 244 struct ecore_dev *edev = &qdev->edev; 245 struct qede_tx_queue *txq; 246 int rc; 247 248 PMD_INIT_FUNC_TRACE(edev); 249 250 if (!rte_is_power_of_2(nb_desc)) { 251 DP_ERR(edev, "Ring size %u is not power of 2\n", 252 nb_desc); 253 return -EINVAL; 254 } 255 256 /* Free memory prior to re-allocation if needed... */ 257 if (dev->data->tx_queues[queue_idx] != NULL) { 258 qede_tx_queue_release(dev->data->tx_queues[queue_idx]); 259 dev->data->tx_queues[queue_idx] = NULL; 260 } 261 262 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue), 263 RTE_CACHE_LINE_SIZE, socket_id); 264 265 if (txq == NULL) { 266 DP_ERR(edev, 267 "Unable to allocate memory for txq on socket %u", 268 socket_id); 269 return -ENOMEM; 270 } 271 272 txq->nb_tx_desc = nb_desc; 273 txq->qdev = qdev; 274 txq->port_id = dev->data->port_id; 275 276 rc = qdev->ops->common->chain_alloc(edev, 277 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE, 278 ECORE_CHAIN_MODE_PBL, 279 ECORE_CHAIN_CNT_TYPE_U16, 280 txq->nb_tx_desc, 281 sizeof(union eth_tx_bd_types), 282 &txq->tx_pbl, 283 NULL); 284 if (rc != ECORE_SUCCESS) { 285 DP_ERR(edev, 286 "Unable to allocate memory for txbd ring on socket %u", 287 socket_id); 288 qede_tx_queue_release(txq); 289 return -ENOMEM; 290 } 291 292 /* Allocate software ring */ 293 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring", 294 (sizeof(struct qede_tx_entry) * 295 txq->nb_tx_desc), 296 RTE_CACHE_LINE_SIZE, socket_id); 297 298 if (!txq->sw_tx_ring) { 299 DP_ERR(edev, 300 "Unable to allocate memory for txbd ring on socket %u", 301 socket_id); 302 qdev->ops->common->chain_free(edev, &txq->tx_pbl); 303 qede_tx_queue_release(txq); 304 return -ENOMEM; 305 } 306 307 txq->queue_id = queue_idx; 308 309 txq->nb_tx_avail = txq->nb_tx_desc; 310 311 txq->tx_free_thresh = 312 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh : 313 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH); 314 315 dev->data->tx_queues[queue_idx] = txq; 316 qdev->fp_array[queue_idx].txq = txq; 317 318 DP_INFO(edev, 319 "txq %u num_desc %u tx_free_thresh %u socket %u\n", 320 queue_idx, nb_desc, txq->tx_free_thresh, socket_id); 321 322 return 0; 323 } 324 325 static void 326 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev, 327 struct qede_tx_queue *txq) 328 { 329 DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id); 330 ecore_chain_reset(&txq->tx_pbl); 331 txq->sw_tx_cons = 0; 332 txq->sw_tx_prod = 0; 333 *txq->hw_cons_ptr = 0; 334 } 335 336 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq) 337 { 338 uint16_t i; 339 340 if (txq->sw_tx_ring) { 341 for (i = 0; i < txq->nb_tx_desc; i++) { 342 if (txq->sw_tx_ring[i].mbuf) { 343 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf); 344 txq->sw_tx_ring[i].mbuf = NULL; 345 } 346 } 347 } 348 } 349 350 void qede_tx_queue_release(void *tx_queue) 351 { 352 struct qede_tx_queue *txq = tx_queue; 353 354 if (txq) { 355 qede_tx_queue_release_mbufs(txq); 356 rte_free(txq->sw_tx_ring); 357 rte_free(txq); 358 } 359 } 360 361 /* This function allocates fast-path status block memory */ 362 static int 363 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info, 364 uint16_t sb_id) 365 { 366 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 367 struct status_block_e4 *sb_virt; 368 dma_addr_t sb_phys; 369 int rc; 370 371 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, 372 sizeof(struct status_block_e4)); 373 if (!sb_virt) { 374 DP_ERR(edev, "Status block allocation failed\n"); 375 return -ENOMEM; 376 } 377 rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt, 378 sb_phys, sb_id); 379 if (rc) { 380 DP_ERR(edev, "Status block initialization failed\n"); 381 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys, 382 sizeof(struct status_block_e4)); 383 return rc; 384 } 385 386 return 0; 387 } 388 389 int qede_alloc_fp_resc(struct qede_dev *qdev) 390 { 391 struct ecore_dev *edev = &qdev->edev; 392 struct qede_fastpath *fp; 393 uint32_t num_sbs; 394 uint16_t sb_idx; 395 396 if (IS_VF(edev)) 397 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs); 398 else 399 num_sbs = ecore_cxt_get_proto_cid_count 400 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL); 401 402 if (num_sbs == 0) { 403 DP_ERR(edev, "No status blocks available\n"); 404 return -EINVAL; 405 } 406 407 qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev), 408 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE); 409 410 if (!qdev->fp_array) { 411 DP_ERR(edev, "fp array allocation failed\n"); 412 return -ENOMEM; 413 } 414 415 memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) * 416 sizeof(*qdev->fp_array)); 417 418 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) { 419 fp = &qdev->fp_array[sb_idx]; 420 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info), 421 RTE_CACHE_LINE_SIZE); 422 if (!fp->sb_info) { 423 DP_ERR(edev, "FP sb_info allocation fails\n"); 424 return -1; 425 } 426 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) { 427 DP_ERR(edev, "FP status block allocation fails\n"); 428 return -1; 429 } 430 DP_INFO(edev, "sb_info idx 0x%x initialized\n", 431 fp->sb_info->igu_sb_id); 432 } 433 434 return 0; 435 } 436 437 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev) 438 { 439 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 440 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 441 struct qede_fastpath *fp; 442 struct qede_rx_queue *rxq; 443 struct qede_tx_queue *txq; 444 uint16_t sb_idx; 445 uint8_t i; 446 447 PMD_INIT_FUNC_TRACE(edev); 448 449 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) { 450 fp = &qdev->fp_array[sb_idx]; 451 DP_INFO(edev, "Free sb_info index 0x%x\n", 452 fp->sb_info->igu_sb_id); 453 if (fp->sb_info) { 454 OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt, 455 fp->sb_info->sb_phys, 456 sizeof(struct status_block_e4)); 457 rte_free(fp->sb_info); 458 fp->sb_info = NULL; 459 } 460 } 461 462 /* Free packet buffers and ring memories */ 463 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 464 if (eth_dev->data->rx_queues[i]) { 465 qede_rx_queue_release(eth_dev->data->rx_queues[i]); 466 rxq = eth_dev->data->rx_queues[i]; 467 qdev->ops->common->chain_free(edev, 468 &rxq->rx_bd_ring); 469 qdev->ops->common->chain_free(edev, 470 &rxq->rx_comp_ring); 471 eth_dev->data->rx_queues[i] = NULL; 472 } 473 } 474 475 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { 476 if (eth_dev->data->tx_queues[i]) { 477 txq = eth_dev->data->tx_queues[i]; 478 qede_tx_queue_release(eth_dev->data->tx_queues[i]); 479 qdev->ops->common->chain_free(edev, 480 &txq->tx_pbl); 481 eth_dev->data->tx_queues[i] = NULL; 482 } 483 } 484 485 if (qdev->fp_array) 486 rte_free(qdev->fp_array); 487 qdev->fp_array = NULL; 488 } 489 490 static inline void 491 qede_update_rx_prod(__rte_unused struct qede_dev *edev, 492 struct qede_rx_queue *rxq) 493 { 494 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring); 495 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring); 496 struct eth_rx_prod_data rx_prods = { 0 }; 497 498 /* Update producers */ 499 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod); 500 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod); 501 502 /* Make sure that the BD and SGE data is updated before updating the 503 * producers since FW might read the BD/SGE right after the producer 504 * is updated. 505 */ 506 rte_wmb(); 507 508 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods), 509 (uint32_t *)&rx_prods); 510 511 /* mmiowb is needed to synchronize doorbell writes from more than one 512 * processor. It guarantees that the write arrives to the device before 513 * the napi lock is released and another qede_poll is called (possibly 514 * on another CPU). Without this barrier, the next doorbell can bypass 515 * this doorbell. This is applicable to IA64/Altix systems. 516 */ 517 rte_wmb(); 518 519 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod); 520 } 521 522 /* Starts a given RX queue in HW */ 523 static int 524 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 525 { 526 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 527 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 528 struct ecore_queue_start_common_params params; 529 struct ecore_rxq_start_ret_params ret_params; 530 struct qede_rx_queue *rxq; 531 struct qede_fastpath *fp; 532 struct ecore_hwfn *p_hwfn; 533 dma_addr_t p_phys_table; 534 uint16_t page_cnt; 535 uint16_t j; 536 int hwfn_index; 537 int rc; 538 539 if (rx_queue_id < eth_dev->data->nb_rx_queues) { 540 fp = &qdev->fp_array[rx_queue_id]; 541 rxq = eth_dev->data->rx_queues[rx_queue_id]; 542 /* Allocate buffers for the Rx ring */ 543 for (j = 0; j < rxq->nb_rx_desc; j++) { 544 rc = qede_alloc_rx_buffer(rxq); 545 if (rc) { 546 DP_ERR(edev, "RX buffer allocation failed" 547 " for rxq = %u\n", rx_queue_id); 548 return -ENOMEM; 549 } 550 } 551 /* disable interrupts */ 552 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0); 553 /* Prepare ramrod */ 554 memset(¶ms, 0, sizeof(params)); 555 params.queue_id = rx_queue_id / edev->num_hwfns; 556 params.vport_id = 0; 557 params.stats_id = params.vport_id; 558 params.p_sb = fp->sb_info; 559 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n", 560 fp->rxq->queue_id, fp->sb_info->igu_sb_id); 561 params.sb_idx = RX_PI; 562 hwfn_index = rx_queue_id % edev->num_hwfns; 563 p_hwfn = &edev->hwfns[hwfn_index]; 564 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring); 565 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring); 566 memset(&ret_params, 0, sizeof(ret_params)); 567 rc = ecore_eth_rx_queue_start(p_hwfn, 568 p_hwfn->hw_info.opaque_fid, 569 ¶ms, fp->rxq->rx_buf_size, 570 fp->rxq->rx_bd_ring.p_phys_addr, 571 p_phys_table, page_cnt, 572 &ret_params); 573 if (rc) { 574 DP_ERR(edev, "RX queue %u could not be started, rc = %d\n", 575 rx_queue_id, rc); 576 return -1; 577 } 578 /* Update with the returned parameters */ 579 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod; 580 fp->rxq->handle = ret_params.p_handle; 581 582 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI]; 583 qede_update_rx_prod(qdev, fp->rxq); 584 eth_dev->data->rx_queue_state[rx_queue_id] = 585 RTE_ETH_QUEUE_STATE_STARTED; 586 DP_INFO(edev, "RX queue %u started\n", rx_queue_id); 587 } else { 588 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id); 589 rc = -EINVAL; 590 } 591 592 return rc; 593 } 594 595 static int 596 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 597 { 598 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 599 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 600 struct ecore_queue_start_common_params params; 601 struct ecore_txq_start_ret_params ret_params; 602 struct ecore_hwfn *p_hwfn; 603 dma_addr_t p_phys_table; 604 struct qede_tx_queue *txq; 605 struct qede_fastpath *fp; 606 uint16_t page_cnt; 607 int hwfn_index; 608 int rc; 609 610 if (tx_queue_id < eth_dev->data->nb_tx_queues) { 611 txq = eth_dev->data->tx_queues[tx_queue_id]; 612 fp = &qdev->fp_array[tx_queue_id]; 613 memset(¶ms, 0, sizeof(params)); 614 params.queue_id = tx_queue_id / edev->num_hwfns; 615 params.vport_id = 0; 616 params.stats_id = params.vport_id; 617 params.p_sb = fp->sb_info; 618 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n", 619 fp->txq->queue_id, fp->sb_info->igu_sb_id); 620 params.sb_idx = TX_PI(0); /* tc = 0 */ 621 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl); 622 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl); 623 hwfn_index = tx_queue_id % edev->num_hwfns; 624 p_hwfn = &edev->hwfns[hwfn_index]; 625 if (qdev->dev_info.is_legacy) 626 fp->txq->is_legacy = true; 627 rc = ecore_eth_tx_queue_start(p_hwfn, 628 p_hwfn->hw_info.opaque_fid, 629 ¶ms, 0 /* tc */, 630 p_phys_table, page_cnt, 631 &ret_params); 632 if (rc != ECORE_SUCCESS) { 633 DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n", 634 tx_queue_id, rc); 635 return -1; 636 } 637 txq->doorbell_addr = ret_params.p_doorbell; 638 txq->handle = ret_params.p_handle; 639 640 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)]; 641 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, 642 DB_DEST_XCM); 643 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, 644 DB_AGG_CMD_SET); 645 SET_FIELD(txq->tx_db.data.params, 646 ETH_DB_DATA_AGG_VAL_SEL, 647 DQ_XCM_ETH_TX_BD_PROD_CMD); 648 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD; 649 eth_dev->data->tx_queue_state[tx_queue_id] = 650 RTE_ETH_QUEUE_STATE_STARTED; 651 DP_INFO(edev, "TX queue %u started\n", tx_queue_id); 652 } else { 653 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id); 654 rc = -EINVAL; 655 } 656 657 return rc; 658 } 659 660 static inline void 661 qede_free_tx_pkt(struct qede_tx_queue *txq) 662 { 663 struct rte_mbuf *mbuf; 664 uint16_t nb_segs; 665 uint16_t idx; 666 667 idx = TX_CONS(txq); 668 mbuf = txq->sw_tx_ring[idx].mbuf; 669 if (mbuf) { 670 nb_segs = mbuf->nb_segs; 671 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs); 672 while (nb_segs) { 673 /* It's like consuming rxbuf in recv() */ 674 ecore_chain_consume(&txq->tx_pbl); 675 txq->nb_tx_avail++; 676 nb_segs--; 677 } 678 rte_pktmbuf_free(mbuf); 679 txq->sw_tx_ring[idx].mbuf = NULL; 680 txq->sw_tx_cons++; 681 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n"); 682 } else { 683 ecore_chain_consume(&txq->tx_pbl); 684 txq->nb_tx_avail++; 685 } 686 } 687 688 static inline void 689 qede_process_tx_compl(__rte_unused struct ecore_dev *edev, 690 struct qede_tx_queue *txq) 691 { 692 uint16_t hw_bd_cons; 693 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 694 uint16_t sw_tx_cons; 695 #endif 696 697 rte_compiler_barrier(); 698 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr); 699 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 700 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl); 701 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n", 702 abs(hw_bd_cons - sw_tx_cons)); 703 #endif 704 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) 705 qede_free_tx_pkt(txq); 706 } 707 708 static int qede_drain_txq(struct qede_dev *qdev, 709 struct qede_tx_queue *txq, bool allow_drain) 710 { 711 struct ecore_dev *edev = &qdev->edev; 712 int rc, cnt = 1000; 713 714 while (txq->sw_tx_cons != txq->sw_tx_prod) { 715 qede_process_tx_compl(edev, txq); 716 if (!cnt) { 717 if (allow_drain) { 718 DP_ERR(edev, "Tx queue[%u] is stuck," 719 "requesting MCP to drain\n", 720 txq->queue_id); 721 rc = qdev->ops->common->drain(edev); 722 if (rc) 723 return rc; 724 return qede_drain_txq(qdev, txq, false); 725 } 726 DP_ERR(edev, "Timeout waiting for tx queue[%d]:" 727 "PROD=%d, CONS=%d\n", 728 txq->queue_id, txq->sw_tx_prod, 729 txq->sw_tx_cons); 730 return -1; 731 } 732 cnt--; 733 DELAY(1000); 734 rte_compiler_barrier(); 735 } 736 737 /* FW finished processing, wait for HW to transmit all tx packets */ 738 DELAY(2000); 739 740 return 0; 741 } 742 743 /* Stops a given TX queue in the HW */ 744 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 745 { 746 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 747 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 748 struct ecore_hwfn *p_hwfn; 749 struct qede_tx_queue *txq; 750 int hwfn_index; 751 int rc; 752 753 if (tx_queue_id < eth_dev->data->nb_tx_queues) { 754 txq = eth_dev->data->tx_queues[tx_queue_id]; 755 /* Drain txq */ 756 if (qede_drain_txq(qdev, txq, true)) 757 return -1; /* For the lack of retcodes */ 758 /* Stop txq */ 759 hwfn_index = tx_queue_id % edev->num_hwfns; 760 p_hwfn = &edev->hwfns[hwfn_index]; 761 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle); 762 if (rc != ECORE_SUCCESS) { 763 DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id); 764 return -1; 765 } 766 qede_tx_queue_release_mbufs(txq); 767 qede_tx_queue_reset(qdev, txq); 768 eth_dev->data->tx_queue_state[tx_queue_id] = 769 RTE_ETH_QUEUE_STATE_STOPPED; 770 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id); 771 } else { 772 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id); 773 rc = -EINVAL; 774 } 775 776 return rc; 777 } 778 779 int qede_start_queues(struct rte_eth_dev *eth_dev) 780 { 781 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 782 uint8_t id; 783 int rc = -1; 784 785 for_each_rss(id) { 786 rc = qede_rx_queue_start(eth_dev, id); 787 if (rc != ECORE_SUCCESS) 788 return -1; 789 } 790 791 for_each_tss(id) { 792 rc = qede_tx_queue_start(eth_dev, id); 793 if (rc != ECORE_SUCCESS) 794 return -1; 795 } 796 797 return rc; 798 } 799 800 void qede_stop_queues(struct rte_eth_dev *eth_dev) 801 { 802 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 803 uint8_t id; 804 805 /* Stopping RX/TX queues */ 806 for_each_tss(id) { 807 qede_tx_queue_stop(eth_dev, id); 808 } 809 810 for_each_rss(id) { 811 qede_rx_queue_stop(eth_dev, id); 812 } 813 } 814 815 static inline bool qede_tunn_exist(uint16_t flag) 816 { 817 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK << 818 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag); 819 } 820 821 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag) 822 { 823 return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK << 824 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag); 825 } 826 827 /* 828 * qede_check_tunn_csum_l4: 829 * Returns: 830 * 1 : If L4 csum is enabled AND if the validation has failed. 831 * 0 : Otherwise 832 */ 833 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag) 834 { 835 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK << 836 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag) 837 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK << 838 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag); 839 840 return 0; 841 } 842 843 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag) 844 { 845 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK << 846 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) 847 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK << 848 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag); 849 850 return 0; 851 } 852 853 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */ 854 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m) 855 { 856 uint32_t packet_type = RTE_PTYPE_UNKNOWN; 857 struct ether_hdr *eth_hdr; 858 struct ipv4_hdr *ipv4_hdr; 859 struct ipv6_hdr *ipv6_hdr; 860 struct vlan_hdr *vlan_hdr; 861 uint16_t ethertype; 862 bool vlan_tagged = 0; 863 uint16_t len; 864 865 eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *); 866 len = sizeof(struct ether_hdr); 867 ethertype = rte_cpu_to_be_16(eth_hdr->ether_type); 868 869 /* Note: Valid only if VLAN stripping is disabled */ 870 if (ethertype == ETHER_TYPE_VLAN) { 871 vlan_tagged = 1; 872 vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1); 873 len += sizeof(struct vlan_hdr); 874 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto); 875 } 876 877 if (ethertype == ETHER_TYPE_IPv4) { 878 packet_type |= RTE_PTYPE_L3_IPV4; 879 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, len); 880 if (ipv4_hdr->next_proto_id == IPPROTO_TCP) 881 packet_type |= RTE_PTYPE_L4_TCP; 882 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP) 883 packet_type |= RTE_PTYPE_L4_UDP; 884 } else if (ethertype == ETHER_TYPE_IPv6) { 885 packet_type |= RTE_PTYPE_L3_IPV6; 886 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, len); 887 if (ipv6_hdr->proto == IPPROTO_TCP) 888 packet_type |= RTE_PTYPE_L4_TCP; 889 else if (ipv6_hdr->proto == IPPROTO_UDP) 890 packet_type |= RTE_PTYPE_L4_UDP; 891 } 892 893 if (vlan_tagged) 894 packet_type |= RTE_PTYPE_L2_ETHER_VLAN; 895 else 896 packet_type |= RTE_PTYPE_L2_ETHER; 897 898 return packet_type; 899 } 900 901 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags) 902 { 903 uint16_t val; 904 905 /* Lookup table */ 906 static const uint32_t 907 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = { 908 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 | 909 RTE_PTYPE_INNER_L2_ETHER, 910 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 | 911 RTE_PTYPE_INNER_L2_ETHER, 912 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 | 913 RTE_PTYPE_INNER_L4_TCP | 914 RTE_PTYPE_INNER_L2_ETHER, 915 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 | 916 RTE_PTYPE_INNER_L4_TCP | 917 RTE_PTYPE_INNER_L2_ETHER, 918 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 | 919 RTE_PTYPE_INNER_L4_UDP | 920 RTE_PTYPE_INNER_L2_ETHER, 921 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 | 922 RTE_PTYPE_INNER_L4_UDP | 923 RTE_PTYPE_INNER_L2_ETHER, 924 /* Frags with no VLAN */ 925 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 | 926 RTE_PTYPE_INNER_L4_FRAG | 927 RTE_PTYPE_INNER_L2_ETHER, 928 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 | 929 RTE_PTYPE_INNER_L4_FRAG | 930 RTE_PTYPE_INNER_L2_ETHER, 931 /* VLANs */ 932 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | 933 RTE_PTYPE_INNER_L2_ETHER_VLAN, 934 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | 935 RTE_PTYPE_INNER_L2_ETHER_VLAN, 936 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | 937 RTE_PTYPE_INNER_L4_TCP | 938 RTE_PTYPE_INNER_L2_ETHER_VLAN, 939 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | 940 RTE_PTYPE_INNER_L4_TCP | 941 RTE_PTYPE_INNER_L2_ETHER_VLAN, 942 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 | 943 RTE_PTYPE_INNER_L4_UDP | 944 RTE_PTYPE_INNER_L2_ETHER_VLAN, 945 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 | 946 RTE_PTYPE_INNER_L4_UDP | 947 RTE_PTYPE_INNER_L2_ETHER_VLAN, 948 /* Frags with VLAN */ 949 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 | 950 RTE_PTYPE_INNER_L4_FRAG | 951 RTE_PTYPE_INNER_L2_ETHER_VLAN, 952 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 | 953 RTE_PTYPE_INNER_L4_FRAG | 954 RTE_PTYPE_INNER_L2_ETHER_VLAN, 955 }; 956 957 /* Bits (0..3) provides L3/L4 protocol type */ 958 /* Bits (4,5) provides frag and VLAN info */ 959 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK << 960 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) | 961 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK << 962 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) | 963 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK << 964 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) | 965 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK << 966 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags; 967 968 if (val < QEDE_PKT_TYPE_MAX) 969 return ptype_lkup_tbl[val]; 970 971 return RTE_PTYPE_UNKNOWN; 972 } 973 974 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags) 975 { 976 uint16_t val; 977 978 /* Lookup table */ 979 static const uint32_t 980 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = { 981 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER, 982 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER, 983 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | 984 RTE_PTYPE_L4_TCP | 985 RTE_PTYPE_L2_ETHER, 986 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | 987 RTE_PTYPE_L4_TCP | 988 RTE_PTYPE_L2_ETHER, 989 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | 990 RTE_PTYPE_L4_UDP | 991 RTE_PTYPE_L2_ETHER, 992 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | 993 RTE_PTYPE_L4_UDP | 994 RTE_PTYPE_L2_ETHER, 995 /* Frags with no VLAN */ 996 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 | 997 RTE_PTYPE_L4_FRAG | 998 RTE_PTYPE_L2_ETHER, 999 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 | 1000 RTE_PTYPE_L4_FRAG | 1001 RTE_PTYPE_L2_ETHER, 1002 /* VLANs */ 1003 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 | 1004 RTE_PTYPE_L2_ETHER_VLAN, 1005 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 | 1006 RTE_PTYPE_L2_ETHER_VLAN, 1007 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 | 1008 RTE_PTYPE_L4_TCP | 1009 RTE_PTYPE_L2_ETHER_VLAN, 1010 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 | 1011 RTE_PTYPE_L4_TCP | 1012 RTE_PTYPE_L2_ETHER_VLAN, 1013 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 | 1014 RTE_PTYPE_L4_UDP | 1015 RTE_PTYPE_L2_ETHER_VLAN, 1016 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 | 1017 RTE_PTYPE_L4_UDP | 1018 RTE_PTYPE_L2_ETHER_VLAN, 1019 /* Frags with VLAN */ 1020 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 | 1021 RTE_PTYPE_L4_FRAG | 1022 RTE_PTYPE_L2_ETHER_VLAN, 1023 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 | 1024 RTE_PTYPE_L4_FRAG | 1025 RTE_PTYPE_L2_ETHER_VLAN, 1026 }; 1027 1028 /* Bits (0..3) provides L3/L4 protocol type */ 1029 /* Bits (4,5) provides frag and VLAN info */ 1030 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK << 1031 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) | 1032 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK << 1033 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) | 1034 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK << 1035 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) | 1036 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK << 1037 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags; 1038 1039 if (val < QEDE_PKT_TYPE_MAX) 1040 return ptype_lkup_tbl[val]; 1041 1042 return RTE_PTYPE_UNKNOWN; 1043 } 1044 1045 static inline uint8_t 1046 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag) 1047 { 1048 struct ipv4_hdr *ip; 1049 uint16_t pkt_csum; 1050 uint16_t calc_csum; 1051 uint16_t val; 1052 1053 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK << 1054 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag); 1055 1056 if (unlikely(val)) { 1057 m->packet_type = qede_rx_cqe_to_pkt_type(flag); 1058 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) { 1059 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, 1060 sizeof(struct ether_hdr)); 1061 pkt_csum = ip->hdr_checksum; 1062 ip->hdr_checksum = 0; 1063 calc_csum = rte_ipv4_cksum(ip); 1064 ip->hdr_checksum = pkt_csum; 1065 return (calc_csum != pkt_csum); 1066 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) { 1067 return 1; 1068 } 1069 } 1070 return 0; 1071 } 1072 1073 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq) 1074 { 1075 ecore_chain_consume(&rxq->rx_bd_ring); 1076 rxq->sw_rx_cons++; 1077 } 1078 1079 static inline void 1080 qede_reuse_page(__rte_unused struct qede_dev *qdev, 1081 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons) 1082 { 1083 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring); 1084 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq); 1085 struct qede_rx_entry *curr_prod; 1086 dma_addr_t new_mapping; 1087 1088 curr_prod = &rxq->sw_rx_ring[idx]; 1089 *curr_prod = *curr_cons; 1090 1091 new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) + 1092 curr_prod->page_offset; 1093 1094 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping)); 1095 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping)); 1096 1097 rxq->sw_rx_prod++; 1098 } 1099 1100 static inline void 1101 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, 1102 struct qede_dev *qdev, uint8_t count) 1103 { 1104 struct qede_rx_entry *curr_cons; 1105 1106 for (; count > 0; count--) { 1107 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)]; 1108 qede_reuse_page(qdev, rxq, curr_cons); 1109 qede_rx_bd_ring_consume(rxq); 1110 } 1111 } 1112 1113 static inline void 1114 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev, 1115 struct qede_rx_queue *rxq, 1116 uint8_t agg_index, uint16_t len) 1117 { 1118 struct qede_agg_info *tpa_info; 1119 struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */ 1120 uint16_t cons_idx; 1121 1122 /* Under certain conditions it is possible that FW may not consume 1123 * additional or new BD. So decision to consume the BD must be made 1124 * based on len_list[0]. 1125 */ 1126 if (rte_le_to_cpu_16(len)) { 1127 tpa_info = &rxq->tpa_info[agg_index]; 1128 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq); 1129 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf; 1130 assert(curr_frag); 1131 curr_frag->nb_segs = 1; 1132 curr_frag->pkt_len = rte_le_to_cpu_16(len); 1133 curr_frag->data_len = curr_frag->pkt_len; 1134 tpa_info->tpa_tail->next = curr_frag; 1135 tpa_info->tpa_tail = curr_frag; 1136 qede_rx_bd_ring_consume(rxq); 1137 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) { 1138 PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n"); 1139 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; 1140 rxq->rx_alloc_errors++; 1141 } 1142 } 1143 } 1144 1145 static inline void 1146 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev, 1147 struct qede_rx_queue *rxq, 1148 struct eth_fast_path_rx_tpa_cont_cqe *cqe) 1149 { 1150 PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n", 1151 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0])); 1152 /* only len_list[0] will have value */ 1153 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index, 1154 cqe->len_list[0]); 1155 } 1156 1157 static inline void 1158 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev, 1159 struct qede_rx_queue *rxq, 1160 struct eth_fast_path_rx_tpa_end_cqe *cqe) 1161 { 1162 struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */ 1163 1164 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index, 1165 cqe->len_list[0]); 1166 /* Update total length and frags based on end TPA */ 1167 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head; 1168 /* TODO: Add Sanity Checks */ 1169 rx_mb->nb_segs = cqe->num_of_bds; 1170 rx_mb->pkt_len = cqe->total_packet_len; 1171 1172 PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d" 1173 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason, 1174 rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs, 1175 rx_mb->pkt_len); 1176 } 1177 1178 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags) 1179 { 1180 uint32_t val; 1181 1182 /* Lookup table */ 1183 static const uint32_t 1184 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = { 1185 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN, 1186 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE, 1187 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE, 1188 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN, 1189 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] = 1190 RTE_PTYPE_TUNNEL_GENEVE, 1191 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] = 1192 RTE_PTYPE_TUNNEL_GRE, 1193 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] = 1194 RTE_PTYPE_TUNNEL_VXLAN, 1195 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] = 1196 RTE_PTYPE_TUNNEL_GENEVE, 1197 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] = 1198 RTE_PTYPE_TUNNEL_GRE, 1199 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] = 1200 RTE_PTYPE_TUNNEL_VXLAN, 1201 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] = 1202 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4, 1203 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] = 1204 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4, 1205 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] = 1206 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4, 1207 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] = 1208 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4, 1209 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] = 1210 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4, 1211 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] = 1212 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4, 1213 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] = 1214 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6, 1215 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] = 1216 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6, 1217 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] = 1218 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6, 1219 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] = 1220 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6, 1221 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] = 1222 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6, 1223 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] = 1224 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6, 1225 }; 1226 1227 /* Cover bits[4-0] to include tunn_type and next protocol */ 1228 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK << 1229 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) | 1230 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK << 1231 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags; 1232 1233 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE) 1234 return ptype_tunn_lkup_tbl[val]; 1235 else 1236 return RTE_PTYPE_UNKNOWN; 1237 } 1238 1239 static inline int 1240 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb, 1241 uint8_t num_segs, uint16_t pkt_len) 1242 { 1243 struct qede_rx_queue *rxq = p_rxq; 1244 struct qede_dev *qdev = rxq->qdev; 1245 register struct rte_mbuf *seg1 = NULL; 1246 register struct rte_mbuf *seg2 = NULL; 1247 uint16_t sw_rx_index; 1248 uint16_t cur_size; 1249 1250 seg1 = rx_mb; 1251 while (num_segs) { 1252 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size : 1253 pkt_len; 1254 if (unlikely(!cur_size)) { 1255 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs" 1256 " left for mapping jumbo\n", num_segs); 1257 qede_recycle_rx_bd_ring(rxq, qdev, num_segs); 1258 return -EINVAL; 1259 } 1260 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq); 1261 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf; 1262 qede_rx_bd_ring_consume(rxq); 1263 pkt_len -= cur_size; 1264 seg2->data_len = cur_size; 1265 seg1->next = seg2; 1266 seg1 = seg1->next; 1267 num_segs--; 1268 rxq->rx_segs++; 1269 } 1270 1271 return 0; 1272 } 1273 1274 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX 1275 static inline void 1276 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq, 1277 uint8_t bitfield) 1278 { 1279 PMD_RX_LOG(INFO, rxq, 1280 "len 0x%04x bf 0x%04x hash_val 0x%x" 1281 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s" 1282 " inner_l2=%s inner_l3=%s inner_l4=%s\n", 1283 m->data_len, bitfield, m->hash.rss, 1284 (unsigned long)m->ol_flags, 1285 rte_get_ptype_l2_name(m->packet_type), 1286 rte_get_ptype_l3_name(m->packet_type), 1287 rte_get_ptype_l4_name(m->packet_type), 1288 rte_get_ptype_tunnel_name(m->packet_type), 1289 rte_get_ptype_inner_l2_name(m->packet_type), 1290 rte_get_ptype_inner_l3_name(m->packet_type), 1291 rte_get_ptype_inner_l4_name(m->packet_type)); 1292 } 1293 #endif 1294 1295 uint16_t 1296 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 1297 { 1298 struct qede_rx_queue *rxq = p_rxq; 1299 struct qede_dev *qdev = rxq->qdev; 1300 struct ecore_dev *edev = &qdev->edev; 1301 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index; 1302 uint16_t rx_pkt = 0; 1303 union eth_rx_cqe *cqe; 1304 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL; 1305 register struct rte_mbuf *rx_mb = NULL; 1306 register struct rte_mbuf *seg1 = NULL; 1307 enum eth_rx_cqe_type cqe_type; 1308 uint16_t pkt_len = 0; /* Sum of all BD segments */ 1309 uint16_t len; /* Length of first BD */ 1310 uint8_t num_segs = 1; 1311 uint16_t preload_idx; 1312 uint16_t parse_flag; 1313 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX 1314 uint8_t bitfield_val; 1315 #endif 1316 uint8_t tunn_parse_flag; 1317 uint8_t j; 1318 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa; 1319 uint64_t ol_flags; 1320 uint32_t packet_type; 1321 uint16_t vlan_tci; 1322 bool tpa_start_flg; 1323 uint8_t offset, tpa_agg_idx, flags; 1324 struct qede_agg_info *tpa_info = NULL; 1325 uint32_t rss_hash; 1326 1327 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr); 1328 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring); 1329 1330 rte_rmb(); 1331 1332 if (hw_comp_cons == sw_comp_cons) 1333 return 0; 1334 1335 while (sw_comp_cons != hw_comp_cons) { 1336 ol_flags = 0; 1337 packet_type = RTE_PTYPE_UNKNOWN; 1338 vlan_tci = 0; 1339 tpa_start_flg = false; 1340 rss_hash = 0; 1341 1342 /* Get the CQE from the completion ring */ 1343 cqe = 1344 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring); 1345 cqe_type = cqe->fast_path_regular.type; 1346 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type); 1347 1348 switch (cqe_type) { 1349 case ETH_RX_CQE_TYPE_REGULAR: 1350 fp_cqe = &cqe->fast_path_regular; 1351 break; 1352 case ETH_RX_CQE_TYPE_TPA_START: 1353 cqe_start_tpa = &cqe->fast_path_tpa_start; 1354 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index]; 1355 tpa_start_flg = true; 1356 /* Mark it as LRO packet */ 1357 ol_flags |= PKT_RX_LRO; 1358 /* In split mode, seg_len is same as len_on_first_bd 1359 * and ext_bd_len_list will be empty since there are 1360 * no additional buffers 1361 */ 1362 PMD_RX_LOG(INFO, rxq, 1363 "TPA start[%d] - len_on_first_bd %d header %d" 1364 " [bd_list[0] %d], [seg_len %d]\n", 1365 cqe_start_tpa->tpa_agg_index, 1366 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd), 1367 cqe_start_tpa->header_len, 1368 rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]), 1369 rte_le_to_cpu_16(cqe_start_tpa->seg_len)); 1370 1371 break; 1372 case ETH_RX_CQE_TYPE_TPA_CONT: 1373 qede_rx_process_tpa_cont_cqe(qdev, rxq, 1374 &cqe->fast_path_tpa_cont); 1375 goto next_cqe; 1376 case ETH_RX_CQE_TYPE_TPA_END: 1377 qede_rx_process_tpa_end_cqe(qdev, rxq, 1378 &cqe->fast_path_tpa_end); 1379 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index; 1380 tpa_info = &rxq->tpa_info[tpa_agg_idx]; 1381 rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head; 1382 goto tpa_end; 1383 case ETH_RX_CQE_TYPE_SLOW_PATH: 1384 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n"); 1385 ecore_eth_cqe_completion( 1386 &edev->hwfns[rxq->queue_id % edev->num_hwfns], 1387 (struct eth_slow_path_rx_cqe *)cqe); 1388 /* fall-thru */ 1389 default: 1390 goto next_cqe; 1391 } 1392 1393 /* Get the data from the SW ring */ 1394 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq); 1395 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf; 1396 assert(rx_mb != NULL); 1397 1398 /* Handle regular CQE or TPA start CQE */ 1399 if (!tpa_start_flg) { 1400 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags); 1401 offset = fp_cqe->placement_offset; 1402 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd); 1403 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len); 1404 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag); 1405 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash); 1406 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX 1407 bitfield_val = fp_cqe->bitfields; 1408 #endif 1409 } else { 1410 parse_flag = 1411 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags); 1412 offset = cqe_start_tpa->placement_offset; 1413 /* seg_len = len_on_first_bd */ 1414 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd); 1415 vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag); 1416 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX 1417 bitfield_val = cqe_start_tpa->bitfields; 1418 #endif 1419 rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash); 1420 } 1421 if (qede_tunn_exist(parse_flag)) { 1422 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n"); 1423 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) { 1424 PMD_RX_LOG(ERR, rxq, 1425 "L4 csum failed, flags = 0x%x\n", 1426 parse_flag); 1427 rxq->rx_hw_errors++; 1428 ol_flags |= PKT_RX_L4_CKSUM_BAD; 1429 } else { 1430 ol_flags |= PKT_RX_L4_CKSUM_GOOD; 1431 } 1432 1433 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) { 1434 PMD_RX_LOG(ERR, rxq, 1435 "Outer L3 csum failed, flags = 0x%x\n", 1436 parse_flag); 1437 rxq->rx_hw_errors++; 1438 ol_flags |= PKT_RX_EIP_CKSUM_BAD; 1439 } else { 1440 ol_flags |= PKT_RX_IP_CKSUM_GOOD; 1441 } 1442 1443 if (tpa_start_flg) 1444 flags = cqe_start_tpa->tunnel_pars_flags.flags; 1445 else 1446 flags = fp_cqe->tunnel_pars_flags.flags; 1447 tunn_parse_flag = flags; 1448 1449 /* Tunnel_type */ 1450 packet_type = 1451 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag); 1452 1453 /* Inner header */ 1454 packet_type |= 1455 qede_rx_cqe_to_pkt_type_inner(parse_flag); 1456 1457 /* Outer L3/L4 types is not available in CQE */ 1458 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb); 1459 1460 /* Outer L3/L4 types is not available in CQE. 1461 * Need to add offset to parse correctly, 1462 */ 1463 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM; 1464 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb); 1465 } 1466 1467 /* Common handling for non-tunnel packets and for inner 1468 * headers in the case of tunnel. 1469 */ 1470 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) { 1471 PMD_RX_LOG(ERR, rxq, 1472 "L4 csum failed, flags = 0x%x\n", 1473 parse_flag); 1474 rxq->rx_hw_errors++; 1475 ol_flags |= PKT_RX_L4_CKSUM_BAD; 1476 } else { 1477 ol_flags |= PKT_RX_L4_CKSUM_GOOD; 1478 } 1479 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) { 1480 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n", 1481 parse_flag); 1482 rxq->rx_hw_errors++; 1483 ol_flags |= PKT_RX_IP_CKSUM_BAD; 1484 } else { 1485 ol_flags |= PKT_RX_IP_CKSUM_GOOD; 1486 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag); 1487 } 1488 1489 if (CQE_HAS_VLAN(parse_flag) || 1490 CQE_HAS_OUTER_VLAN(parse_flag)) { 1491 /* Note: FW doesn't indicate Q-in-Q packet */ 1492 ol_flags |= PKT_RX_VLAN; 1493 if (qdev->vlan_strip_flg) { 1494 ol_flags |= PKT_RX_VLAN_STRIPPED; 1495 rx_mb->vlan_tci = vlan_tci; 1496 } 1497 } 1498 1499 /* RSS Hash */ 1500 if (qdev->rss_enable) { 1501 ol_flags |= PKT_RX_RSS_HASH; 1502 rx_mb->hash.rss = rss_hash; 1503 } 1504 1505 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) { 1506 PMD_RX_LOG(ERR, rxq, 1507 "New buffer allocation failed," 1508 "dropping incoming packet\n"); 1509 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num); 1510 rte_eth_devices[rxq->port_id]. 1511 data->rx_mbuf_alloc_failed++; 1512 rxq->rx_alloc_errors++; 1513 break; 1514 } 1515 qede_rx_bd_ring_consume(rxq); 1516 1517 if (!tpa_start_flg && fp_cqe->bd_num > 1) { 1518 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs" 1519 " len on first: %04x Total Len: %04x", 1520 fp_cqe->bd_num, len, pkt_len); 1521 num_segs = fp_cqe->bd_num - 1; 1522 seg1 = rx_mb; 1523 if (qede_process_sg_pkts(p_rxq, seg1, num_segs, 1524 pkt_len - len)) 1525 goto next_cqe; 1526 for (j = 0; j < num_segs; j++) { 1527 if (qede_alloc_rx_buffer(rxq)) { 1528 PMD_RX_LOG(ERR, rxq, 1529 "Buffer allocation failed"); 1530 rte_eth_devices[rxq->port_id]. 1531 data->rx_mbuf_alloc_failed++; 1532 rxq->rx_alloc_errors++; 1533 break; 1534 } 1535 rxq->rx_segs++; 1536 } 1537 } 1538 rxq->rx_segs++; /* for the first segment */ 1539 1540 /* Prefetch next mbuf while processing current one. */ 1541 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq); 1542 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf); 1543 1544 /* Update rest of the MBUF fields */ 1545 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM; 1546 rx_mb->port = rxq->port_id; 1547 rx_mb->ol_flags = ol_flags; 1548 rx_mb->data_len = len; 1549 rx_mb->packet_type = packet_type; 1550 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX 1551 print_rx_bd_info(rx_mb, rxq, bitfield_val); 1552 #endif 1553 if (!tpa_start_flg) { 1554 rx_mb->nb_segs = fp_cqe->bd_num; 1555 rx_mb->pkt_len = pkt_len; 1556 } else { 1557 /* store ref to the updated mbuf */ 1558 tpa_info->tpa_head = rx_mb; 1559 tpa_info->tpa_tail = tpa_info->tpa_head; 1560 } 1561 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *)); 1562 tpa_end: 1563 if (!tpa_start_flg) { 1564 rx_pkts[rx_pkt] = rx_mb; 1565 rx_pkt++; 1566 } 1567 next_cqe: 1568 ecore_chain_recycle_consumed(&rxq->rx_comp_ring); 1569 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring); 1570 if (rx_pkt == nb_pkts) { 1571 PMD_RX_LOG(DEBUG, rxq, 1572 "Budget reached nb_pkts=%u received=%u", 1573 rx_pkt, nb_pkts); 1574 break; 1575 } 1576 } 1577 1578 qede_update_rx_prod(qdev, rxq); 1579 1580 rxq->rcv_pkts += rx_pkt; 1581 1582 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id()); 1583 1584 return rx_pkt; 1585 } 1586 1587 1588 /* Populate scatter gather buffer descriptor fields */ 1589 static inline uint16_t 1590 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg, 1591 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3, 1592 uint16_t start_seg) 1593 { 1594 struct qede_tx_queue *txq = p_txq; 1595 struct eth_tx_bd *tx_bd = NULL; 1596 dma_addr_t mapping; 1597 uint16_t nb_segs = 0; 1598 1599 /* Check for scattered buffers */ 1600 while (m_seg) { 1601 if (start_seg == 0) { 1602 if (!*bd2) { 1603 *bd2 = (struct eth_tx_2nd_bd *) 1604 ecore_chain_produce(&txq->tx_pbl); 1605 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd)); 1606 nb_segs++; 1607 } 1608 mapping = rte_mbuf_data_iova(m_seg); 1609 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len); 1610 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len); 1611 } else if (start_seg == 1) { 1612 if (!*bd3) { 1613 *bd3 = (struct eth_tx_3rd_bd *) 1614 ecore_chain_produce(&txq->tx_pbl); 1615 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd)); 1616 nb_segs++; 1617 } 1618 mapping = rte_mbuf_data_iova(m_seg); 1619 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len); 1620 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len); 1621 } else { 1622 tx_bd = (struct eth_tx_bd *) 1623 ecore_chain_produce(&txq->tx_pbl); 1624 memset(tx_bd, 0, sizeof(*tx_bd)); 1625 nb_segs++; 1626 mapping = rte_mbuf_data_iova(m_seg); 1627 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len); 1628 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len); 1629 } 1630 m_seg = m_seg->next; 1631 } 1632 1633 /* Return total scattered buffers */ 1634 return nb_segs; 1635 } 1636 1637 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 1638 static inline void 1639 print_tx_bd_info(struct qede_tx_queue *txq, 1640 struct eth_tx_1st_bd *bd1, 1641 struct eth_tx_2nd_bd *bd2, 1642 struct eth_tx_3rd_bd *bd3, 1643 uint64_t tx_ol_flags) 1644 { 1645 char ol_buf[256] = { 0 }; /* for verbose prints */ 1646 1647 if (bd1) 1648 PMD_TX_LOG(INFO, txq, 1649 "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x", 1650 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds, 1651 bd1->data.bd_flags.bitfields, 1652 rte_cpu_to_le_16(bd1->data.bitfields)); 1653 if (bd2) 1654 PMD_TX_LOG(INFO, txq, 1655 "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n", 1656 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1, 1657 bd2->data.bitfields2, bd2->data.tunn_ip_size); 1658 if (bd3) 1659 PMD_TX_LOG(INFO, txq, 1660 "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x " 1661 "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n", 1662 rte_cpu_to_le_16(bd3->nbytes), 1663 rte_cpu_to_le_16(bd3->data.bitfields), 1664 rte_cpu_to_le_16(bd3->data.lso_mss), 1665 bd3->data.tunn_l4_hdr_start_offset_w, 1666 bd3->data.tunn_hdr_size_w); 1667 1668 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf)); 1669 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf); 1670 } 1671 #endif 1672 1673 /* TX prepare to check packets meets TX conditions */ 1674 uint16_t 1675 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 1676 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts, 1677 uint16_t nb_pkts) 1678 { 1679 struct qede_tx_queue *txq = p_txq; 1680 #else 1681 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts, 1682 uint16_t nb_pkts) 1683 { 1684 #endif 1685 uint64_t ol_flags; 1686 struct rte_mbuf *m; 1687 uint16_t i; 1688 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 1689 int ret; 1690 #endif 1691 1692 for (i = 0; i < nb_pkts; i++) { 1693 m = tx_pkts[i]; 1694 ol_flags = m->ol_flags; 1695 if (ol_flags & PKT_TX_TCP_SEG) { 1696 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) { 1697 rte_errno = -EINVAL; 1698 break; 1699 } 1700 /* TBD: confirm its ~9700B for both ? */ 1701 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) { 1702 rte_errno = -EINVAL; 1703 break; 1704 } 1705 } else { 1706 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) { 1707 rte_errno = -EINVAL; 1708 break; 1709 } 1710 } 1711 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) { 1712 rte_errno = -ENOTSUP; 1713 break; 1714 } 1715 1716 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 1717 ret = rte_validate_tx_offload(m); 1718 if (ret != 0) { 1719 rte_errno = ret; 1720 break; 1721 } 1722 #endif 1723 } 1724 1725 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 1726 if (unlikely(i != nb_pkts)) 1727 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n", 1728 nb_pkts - i); 1729 #endif 1730 return i; 1731 } 1732 1733 #define MPLSINUDP_HDR_SIZE (12) 1734 1735 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 1736 static inline void 1737 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf, 1738 struct qede_tx_queue *txq) 1739 { 1740 if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff) 1741 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n"); 1742 if (((mbuf->outer_l2_len + mbuf->outer_l3_len + 1743 MPLSINUDP_HDR_SIZE) / 2) > 0xff) 1744 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n"); 1745 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) > 1746 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) 1747 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n"); 1748 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) > 1749 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) 1750 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n"); 1751 } 1752 #endif 1753 1754 uint16_t 1755 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 1756 { 1757 struct qede_tx_queue *txq = p_txq; 1758 struct qede_dev *qdev = txq->qdev; 1759 struct ecore_dev *edev = &qdev->edev; 1760 struct rte_mbuf *mbuf; 1761 struct rte_mbuf *m_seg = NULL; 1762 uint16_t nb_tx_pkts; 1763 uint16_t bd_prod; 1764 uint16_t idx; 1765 uint16_t nb_frags; 1766 uint16_t nb_pkt_sent = 0; 1767 uint8_t nbds; 1768 bool lso_flg; 1769 bool mplsoudp_flg; 1770 __rte_unused bool tunn_flg; 1771 bool tunn_ipv6_ext_flg; 1772 struct eth_tx_1st_bd *bd1; 1773 struct eth_tx_2nd_bd *bd2; 1774 struct eth_tx_3rd_bd *bd3; 1775 uint64_t tx_ol_flags; 1776 uint16_t hdr_size; 1777 /* BD1 */ 1778 uint16_t bd1_bf; 1779 uint8_t bd1_bd_flags_bf; 1780 uint16_t vlan; 1781 /* BD2 */ 1782 uint16_t bd2_bf1; 1783 uint16_t bd2_bf2; 1784 /* BD3 */ 1785 uint16_t mss; 1786 uint16_t bd3_bf; 1787 1788 uint8_t tunn_l4_hdr_start_offset; 1789 uint8_t tunn_hdr_size; 1790 uint8_t inner_l2_hdr_size; 1791 uint16_t inner_l4_hdr_offset; 1792 1793 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) { 1794 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u", 1795 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh); 1796 qede_process_tx_compl(edev, txq); 1797 } 1798 1799 nb_tx_pkts = nb_pkts; 1800 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl)); 1801 while (nb_tx_pkts--) { 1802 /* Init flags/values */ 1803 tunn_flg = false; 1804 lso_flg = false; 1805 nbds = 0; 1806 vlan = 0; 1807 bd1 = NULL; 1808 bd2 = NULL; 1809 bd3 = NULL; 1810 hdr_size = 0; 1811 bd1_bf = 0; 1812 bd1_bd_flags_bf = 0; 1813 bd2_bf1 = 0; 1814 bd2_bf2 = 0; 1815 mss = 0; 1816 bd3_bf = 0; 1817 mplsoudp_flg = false; 1818 tunn_ipv6_ext_flg = false; 1819 tunn_hdr_size = 0; 1820 tunn_l4_hdr_start_offset = 0; 1821 1822 mbuf = *tx_pkts++; 1823 assert(mbuf); 1824 1825 /* Check minimum TX BDS availability against available BDs */ 1826 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs)) 1827 break; 1828 1829 tx_ol_flags = mbuf->ol_flags; 1830 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT; 1831 1832 /* TX prepare would have already checked supported tunnel Tx 1833 * offloads. Don't rely on pkt_type marked by Rx, instead use 1834 * tx_ol_flags to decide. 1835 */ 1836 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) == 1837 PKT_TX_TUNNEL_VXLAN) || 1838 ((tx_ol_flags & PKT_TX_TUNNEL_MASK) == 1839 PKT_TX_TUNNEL_MPLSINUDP) || 1840 ((tx_ol_flags & PKT_TX_TUNNEL_MASK) == 1841 PKT_TX_TUNNEL_GENEVE)) { 1842 /* Check against max which is Tunnel IPv6 + ext */ 1843 if (unlikely(txq->nb_tx_avail < 1844 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT)) 1845 break; 1846 tunn_flg = true; 1847 /* First indicate its a tunnel pkt */ 1848 bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK << 1849 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT; 1850 /* Legacy FW had flipped behavior in regard to this bit 1851 * i.e. it needed to set to prevent FW from touching 1852 * encapsulated packets when it didn't need to. 1853 */ 1854 if (unlikely(txq->is_legacy)) { 1855 bd1_bf ^= 1 << 1856 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT; 1857 } 1858 1859 /* Outer IP checksum offload */ 1860 if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM | 1861 PKT_TX_OUTER_IPV4)) { 1862 bd1_bd_flags_bf |= 1863 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK << 1864 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT; 1865 } 1866 1867 /** 1868 * Currently, only inner checksum offload in MPLS-in-UDP 1869 * tunnel with one MPLS label is supported. Both outer 1870 * and inner layers lengths need to be provided in 1871 * mbuf. 1872 */ 1873 if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) == 1874 PKT_TX_TUNNEL_MPLSINUDP) { 1875 mplsoudp_flg = true; 1876 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 1877 qede_mpls_tunn_tx_sanity_check(mbuf, txq); 1878 #endif 1879 /* Outer L4 offset in two byte words */ 1880 tunn_l4_hdr_start_offset = 1881 (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2; 1882 /* Tunnel header size in two byte words */ 1883 tunn_hdr_size = (mbuf->outer_l2_len + 1884 mbuf->outer_l3_len + 1885 MPLSINUDP_HDR_SIZE) / 2; 1886 /* Inner L2 header size in two byte words */ 1887 inner_l2_hdr_size = (mbuf->l2_len - 1888 MPLSINUDP_HDR_SIZE) / 2; 1889 /* Inner L4 header offset from the beggining 1890 * of inner packet in two byte words 1891 */ 1892 inner_l4_hdr_offset = (mbuf->l2_len - 1893 MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2; 1894 1895 /* Inner L2 size and address type */ 1896 bd2_bf1 |= (inner_l2_hdr_size & 1897 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) << 1898 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT; 1899 bd2_bf1 |= (UNICAST_ADDRESS & 1900 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) << 1901 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT; 1902 /* Treated as IPv6+Ext */ 1903 bd2_bf1 |= 1904 1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT; 1905 1906 /* Mark inner IPv6 if present */ 1907 if (tx_ol_flags & PKT_TX_IPV6) 1908 bd2_bf1 |= 1909 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT; 1910 1911 /* Inner L4 offsets */ 1912 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) && 1913 (tx_ol_flags & (PKT_TX_UDP_CKSUM | 1914 PKT_TX_TCP_CKSUM))) { 1915 /* Determines if BD3 is needed */ 1916 tunn_ipv6_ext_flg = true; 1917 if ((tx_ol_flags & PKT_TX_L4_MASK) == 1918 PKT_TX_UDP_CKSUM) { 1919 bd2_bf1 |= 1920 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT; 1921 } 1922 1923 /* TODO other pseudo checksum modes are 1924 * not supported 1925 */ 1926 bd2_bf1 |= 1927 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH << 1928 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT; 1929 bd2_bf2 |= (inner_l4_hdr_offset & 1930 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) << 1931 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT; 1932 } 1933 } /* End MPLSoUDP */ 1934 } /* End Tunnel handling */ 1935 1936 if (tx_ol_flags & PKT_TX_TCP_SEG) { 1937 lso_flg = true; 1938 if (unlikely(txq->nb_tx_avail < 1939 ETH_TX_MIN_BDS_PER_LSO_PKT)) 1940 break; 1941 /* For LSO, packet header and payload must reside on 1942 * buffers pointed by different BDs. Using BD1 for HDR 1943 * and BD2 onwards for data. 1944 */ 1945 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len; 1946 if (tunn_flg) 1947 hdr_size += mbuf->outer_l2_len + 1948 mbuf->outer_l3_len; 1949 1950 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT; 1951 bd1_bd_flags_bf |= 1952 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT; 1953 /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */ 1954 bd1_bd_flags_bf |= 1955 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT; 1956 mss = rte_cpu_to_le_16(mbuf->tso_segsz); 1957 /* Using one header BD */ 1958 bd3_bf |= rte_cpu_to_le_16(1 << 1959 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT); 1960 } else { 1961 if (unlikely(txq->nb_tx_avail < 1962 ETH_TX_MIN_BDS_PER_NON_LSO_PKT)) 1963 break; 1964 bd1_bf |= 1965 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) 1966 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; 1967 } 1968 1969 /* Descriptor based VLAN insertion */ 1970 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) { 1971 vlan = rte_cpu_to_le_16(mbuf->vlan_tci); 1972 bd1_bd_flags_bf |= 1973 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT; 1974 } 1975 1976 /* Offload the IP checksum in the hardware */ 1977 if (tx_ol_flags & PKT_TX_IP_CKSUM) { 1978 bd1_bd_flags_bf |= 1979 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT; 1980 /* There's no DPDK flag to request outer-L4 csum 1981 * offload. But in the case of tunnel if inner L3 or L4 1982 * csum offload is requested then we need to force 1983 * recalculation of L4 tunnel header csum also. 1984 */ 1985 if (tunn_flg) { 1986 bd1_bd_flags_bf |= 1987 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK << 1988 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT; 1989 } 1990 } 1991 1992 /* L4 checksum offload (tcp or udp) */ 1993 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) && 1994 (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) { 1995 bd1_bd_flags_bf |= 1996 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT; 1997 /* There's no DPDK flag to request outer-L4 csum 1998 * offload. But in the case of tunnel if inner L3 or L4 1999 * csum offload is requested then we need to force 2000 * recalculation of L4 tunnel header csum also. 2001 */ 2002 if (tunn_flg) { 2003 bd1_bd_flags_bf |= 2004 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK << 2005 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT; 2006 } 2007 } 2008 2009 /* Fill the entry in the SW ring and the BDs in the FW ring */ 2010 idx = TX_PROD(txq); 2011 txq->sw_tx_ring[idx].mbuf = mbuf; 2012 2013 /* BD1 */ 2014 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl); 2015 memset(bd1, 0, sizeof(struct eth_tx_1st_bd)); 2016 nbds++; 2017 2018 /* Map MBUF linear data for DMA and set in the BD1 */ 2019 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf), 2020 mbuf->data_len); 2021 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf); 2022 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf; 2023 bd1->data.vlan = vlan; 2024 2025 if (lso_flg || mplsoudp_flg) { 2026 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce 2027 (&txq->tx_pbl); 2028 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd)); 2029 nbds++; 2030 2031 /* BD1 */ 2032 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf), 2033 hdr_size); 2034 /* BD2 */ 2035 QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size + 2036 rte_mbuf_data_iova(mbuf)), 2037 mbuf->data_len - hdr_size); 2038 bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1); 2039 if (mplsoudp_flg) { 2040 bd2->data.bitfields2 = 2041 rte_cpu_to_le_16(bd2_bf2); 2042 /* Outer L3 size */ 2043 bd2->data.tunn_ip_size = 2044 rte_cpu_to_le_16(mbuf->outer_l3_len); 2045 } 2046 /* BD3 */ 2047 if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) { 2048 bd3 = (struct eth_tx_3rd_bd *) 2049 ecore_chain_produce(&txq->tx_pbl); 2050 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd)); 2051 nbds++; 2052 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf); 2053 if (lso_flg) 2054 bd3->data.lso_mss = mss; 2055 if (mplsoudp_flg) { 2056 bd3->data.tunn_l4_hdr_start_offset_w = 2057 tunn_l4_hdr_start_offset; 2058 bd3->data.tunn_hdr_size_w = 2059 tunn_hdr_size; 2060 } 2061 } 2062 } 2063 2064 /* Handle fragmented MBUF */ 2065 m_seg = mbuf->next; 2066 2067 /* Encode scatter gather buffer descriptors if required */ 2068 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1); 2069 bd1->data.nbds = nbds + nb_frags; 2070 2071 txq->nb_tx_avail -= bd1->data.nbds; 2072 txq->sw_tx_prod++; 2073 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf); 2074 bd_prod = 2075 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl)); 2076 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX 2077 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags); 2078 #endif 2079 nb_pkt_sent++; 2080 txq->xmit_pkts++; 2081 } 2082 2083 /* Write value of prod idx into bd_prod */ 2084 txq->tx_db.data.bd_prod = bd_prod; 2085 rte_wmb(); 2086 rte_compiler_barrier(); 2087 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw); 2088 rte_wmb(); 2089 2090 /* Check again for Tx completions */ 2091 qede_process_tx_compl(edev, txq); 2092 2093 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d", 2094 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id()); 2095 2096 return nb_pkt_sent; 2097 } 2098 2099 uint16_t 2100 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq, 2101 __rte_unused struct rte_mbuf **pkts, 2102 __rte_unused uint16_t nb_pkts) 2103 { 2104 return 0; 2105 } 2106