1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include <limits.h> 10 #include <time.h> 11 #include <rte_alarm.h> 12 13 #include "qede_ethdev.h" 14 15 static uint8_t npar_tx_switching = 1; 16 17 /* Alarm timeout. */ 18 #define QEDE_ALARM_TIMEOUT_US 100000 19 20 /* Global variable to hold absolute path of fw file */ 21 char fw_file[PATH_MAX]; 22 23 const char *QEDE_DEFAULT_FIRMWARE = 24 "/lib/firmware/qed/qed_init_values-8.10.9.0.bin"; 25 26 static void 27 qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params) 28 { 29 int i; 30 31 for (i = 0; i < edev->num_hwfns; i++) { 32 struct ecore_hwfn *p_hwfn = &edev->hwfns[i]; 33 p_hwfn->pf_params = *params; 34 } 35 } 36 37 static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev) 38 { 39 edev->regview = pci_dev->mem_resource[0].addr; 40 edev->doorbells = pci_dev->mem_resource[2].addr; 41 } 42 43 static int 44 qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev, 45 enum qed_protocol protocol, uint32_t dp_module, 46 uint8_t dp_level, bool is_vf) 47 { 48 struct ecore_hw_prepare_params hw_prepare_params; 49 struct qede_dev *qdev = (struct qede_dev *)edev; 50 int rc; 51 52 ecore_init_struct(edev); 53 qdev->protocol = protocol; 54 if (is_vf) { 55 edev->b_is_vf = true; 56 edev->b_hw_channel = true; /* @DPDK */ 57 } 58 ecore_init_dp(edev, dp_module, dp_level, NULL); 59 qed_init_pci(edev, pci_dev); 60 61 memset(&hw_prepare_params, 0, sizeof(hw_prepare_params)); 62 hw_prepare_params.personality = ECORE_PCI_ETH; 63 hw_prepare_params.drv_resc_alloc = false; 64 hw_prepare_params.chk_reg_fifo = false; 65 rc = ecore_hw_prepare(edev, &hw_prepare_params); 66 if (rc) { 67 DP_ERR(edev, "hw prepare failed\n"); 68 return rc; 69 } 70 71 return rc; 72 } 73 74 static int qed_nic_setup(struct ecore_dev *edev) 75 { 76 int rc, i; 77 78 rc = ecore_resc_alloc(edev); 79 if (rc) 80 return rc; 81 82 DP_INFO(edev, "Allocated qed resources\n"); 83 ecore_resc_setup(edev); 84 85 return rc; 86 } 87 88 #ifdef CONFIG_ECORE_ZIPPED_FW 89 static int qed_alloc_stream_mem(struct ecore_dev *edev) 90 { 91 int i; 92 93 for_each_hwfn(edev, i) { 94 struct ecore_hwfn *p_hwfn = &edev->hwfns[i]; 95 96 p_hwfn->stream = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 97 sizeof(*p_hwfn->stream)); 98 if (!p_hwfn->stream) 99 return -ENOMEM; 100 } 101 102 return 0; 103 } 104 105 static void qed_free_stream_mem(struct ecore_dev *edev) 106 { 107 int i; 108 109 for_each_hwfn(edev, i) { 110 struct ecore_hwfn *p_hwfn = &edev->hwfns[i]; 111 112 if (!p_hwfn->stream) 113 return; 114 115 OSAL_FREE(p_hwfn->p_dev, p_hwfn->stream); 116 } 117 } 118 #endif 119 120 #ifdef CONFIG_ECORE_BINARY_FW 121 static int qed_load_firmware_data(struct ecore_dev *edev) 122 { 123 int fd; 124 struct stat st; 125 const char *fw = RTE_LIBRTE_QEDE_FW; 126 127 if (strcmp(fw, "") == 0) 128 strcpy(fw_file, QEDE_DEFAULT_FIRMWARE); 129 else 130 strcpy(fw_file, fw); 131 132 fd = open(fw_file, O_RDONLY); 133 if (fd < 0) { 134 DP_NOTICE(edev, false, "Can't open firmware file\n"); 135 return -ENOENT; 136 } 137 138 if (fstat(fd, &st) < 0) { 139 DP_NOTICE(edev, false, "Can't stat firmware file\n"); 140 return -1; 141 } 142 143 edev->firmware = rte_zmalloc("qede_fw", st.st_size, 144 RTE_CACHE_LINE_SIZE); 145 if (!edev->firmware) { 146 DP_NOTICE(edev, false, "Can't allocate memory for firmware\n"); 147 close(fd); 148 return -ENOMEM; 149 } 150 151 if (read(fd, edev->firmware, st.st_size) != st.st_size) { 152 DP_NOTICE(edev, false, "Can't read firmware data\n"); 153 close(fd); 154 return -1; 155 } 156 157 edev->fw_len = st.st_size; 158 if (edev->fw_len < 104) { 159 DP_NOTICE(edev, false, "Invalid fw size: %" PRIu64 "\n", 160 edev->fw_len); 161 return -EINVAL; 162 } 163 164 return 0; 165 } 166 #endif 167 168 static void qed_handle_bulletin_change(struct ecore_hwfn *hwfn) 169 { 170 uint8_t mac[ETH_ALEN], is_mac_exist, is_mac_forced; 171 172 is_mac_exist = ecore_vf_bulletin_get_forced_mac(hwfn, mac, 173 &is_mac_forced); 174 if (is_mac_exist && is_mac_forced) 175 rte_memcpy(hwfn->hw_info.hw_mac_addr, mac, ETH_ALEN); 176 177 /* Always update link configuration according to bulletin */ 178 qed_link_update(hwfn); 179 } 180 181 static void qede_vf_task(void *arg) 182 { 183 struct ecore_hwfn *p_hwfn = arg; 184 uint8_t change = 0; 185 186 /* Read the bulletin board, and re-schedule the task */ 187 ecore_vf_read_bulletin(p_hwfn, &change); 188 if (change) 189 qed_handle_bulletin_change(p_hwfn); 190 191 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task, p_hwfn); 192 } 193 194 static void qed_start_iov_task(struct ecore_dev *edev) 195 { 196 struct ecore_hwfn *p_hwfn; 197 int i; 198 199 for_each_hwfn(edev, i) { 200 p_hwfn = &edev->hwfns[i]; 201 if (!IS_PF(edev)) 202 rte_eal_alarm_set(QEDE_ALARM_TIMEOUT_US, qede_vf_task, 203 p_hwfn); 204 } 205 } 206 207 static void qed_stop_iov_task(struct ecore_dev *edev) 208 { 209 struct ecore_hwfn *p_hwfn; 210 int i; 211 212 for_each_hwfn(edev, i) { 213 p_hwfn = &edev->hwfns[i]; 214 if (!IS_PF(edev)) 215 rte_eal_alarm_cancel(qede_vf_task, p_hwfn); 216 } 217 } 218 static int qed_slowpath_start(struct ecore_dev *edev, 219 struct qed_slowpath_params *params) 220 { 221 bool allow_npar_tx_switching; 222 const uint8_t *data = NULL; 223 struct ecore_hwfn *hwfn; 224 struct ecore_mcp_drv_version drv_version; 225 struct ecore_hw_init_params hw_init_params; 226 struct qede_dev *qdev = (struct qede_dev *)edev; 227 int rc; 228 #ifdef QED_ENC_SUPPORTED 229 struct ecore_tunn_start_params tunn_info; 230 #endif 231 232 #ifdef CONFIG_ECORE_BINARY_FW 233 if (IS_PF(edev)) { 234 rc = qed_load_firmware_data(edev); 235 if (rc) { 236 DP_NOTICE(edev, true, 237 "Failed to find fw file %s\n", fw_file); 238 goto err; 239 } 240 } 241 #endif 242 243 rc = qed_nic_setup(edev); 244 if (rc) 245 goto err; 246 247 /* set int_coalescing_mode */ 248 edev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE; 249 250 #ifdef CONFIG_ECORE_ZIPPED_FW 251 if (IS_PF(edev)) { 252 /* Allocate stream for unzipping */ 253 rc = qed_alloc_stream_mem(edev); 254 if (rc) { 255 DP_NOTICE(edev, true, 256 "Failed to allocate stream memory\n"); 257 goto err2; 258 } 259 } 260 261 qed_start_iov_task(edev); 262 #endif 263 264 #ifdef CONFIG_ECORE_BINARY_FW 265 if (IS_PF(edev)) 266 data = (const uint8_t *)edev->firmware + sizeof(u32); 267 #endif 268 269 allow_npar_tx_switching = npar_tx_switching ? true : false; 270 271 /* Start the slowpath */ 272 memset(&hw_init_params, 0, sizeof(hw_init_params)); 273 #ifdef QED_ENC_SUPPORTED 274 memset(&tunn_info, 0, sizeof(tunn_info)); 275 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN | 276 1 << QED_MODE_L2GRE_TUNN | 277 1 << QED_MODE_IPGRE_TUNN | 278 1 << QED_MODE_L2GENEVE_TUNN | 1 << QED_MODE_IPGENEVE_TUNN; 279 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN; 280 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN; 281 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN; 282 hw_init_params.p_tunn = &tunn_info; 283 #endif 284 hw_init_params.b_hw_start = true; 285 hw_init_params.int_mode = ECORE_INT_MODE_MSIX; 286 hw_init_params.allow_npar_tx_switch = allow_npar_tx_switching; 287 hw_init_params.bin_fw_data = data; 288 hw_init_params.epoch = (u32)time(NULL); 289 rc = ecore_hw_init(edev, &hw_init_params); 290 if (rc) { 291 DP_ERR(edev, "ecore_hw_init failed\n"); 292 goto err2; 293 } 294 295 DP_INFO(edev, "HW inited and function started\n"); 296 297 if (IS_PF(edev)) { 298 hwfn = ECORE_LEADING_HWFN(edev); 299 drv_version.version = (params->drv_major << 24) | 300 (params->drv_minor << 16) | 301 (params->drv_rev << 8) | (params->drv_eng); 302 /* TBD: strlcpy() */ 303 strncpy((char *)drv_version.name, (const char *)params->name, 304 MCP_DRV_VER_STR_SIZE - 4); 305 rc = ecore_mcp_send_drv_version(hwfn, hwfn->p_main_ptt, 306 &drv_version); 307 if (rc) { 308 DP_NOTICE(edev, true, 309 "Failed sending drv version command\n"); 310 return rc; 311 } 312 } 313 314 ecore_reset_vport_stats(edev); 315 316 return 0; 317 318 ecore_hw_stop(edev); 319 err2: 320 ecore_resc_free(edev); 321 err: 322 #ifdef CONFIG_ECORE_BINARY_FW 323 if (IS_PF(edev)) { 324 if (edev->firmware) 325 rte_free(edev->firmware); 326 edev->firmware = NULL; 327 } 328 #endif 329 qed_stop_iov_task(edev); 330 331 return rc; 332 } 333 334 static int 335 qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info) 336 { 337 struct ecore_ptt *ptt = NULL; 338 339 memset(dev_info, 0, sizeof(struct qed_dev_info)); 340 dev_info->num_hwfns = edev->num_hwfns; 341 dev_info->is_mf_default = IS_MF_DEFAULT(&edev->hwfns[0]); 342 rte_memcpy(&dev_info->hw_mac, &edev->hwfns[0].hw_info.hw_mac_addr, 343 ETHER_ADDR_LEN); 344 345 if (IS_PF(edev)) { 346 dev_info->fw_major = FW_MAJOR_VERSION; 347 dev_info->fw_minor = FW_MINOR_VERSION; 348 dev_info->fw_rev = FW_REVISION_VERSION; 349 dev_info->fw_eng = FW_ENGINEERING_VERSION; 350 dev_info->mf_mode = edev->mf_mode; 351 dev_info->tx_switching = false; 352 } else { 353 ecore_vf_get_fw_version(&edev->hwfns[0], &dev_info->fw_major, 354 &dev_info->fw_minor, &dev_info->fw_rev, 355 &dev_info->fw_eng); 356 } 357 358 if (IS_PF(edev)) { 359 ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev)); 360 if (ptt) { 361 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt, 362 &dev_info->mfw_rev, NULL); 363 364 ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt, 365 &dev_info->flash_size); 366 367 /* Workaround to allow PHY-read commands for 368 * B0 bringup. 369 */ 370 if (ECORE_IS_BB_B0(edev)) 371 dev_info->flash_size = 0xffffffff; 372 373 ecore_ptt_release(ECORE_LEADING_HWFN(edev), ptt); 374 } 375 } else { 376 ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt, 377 &dev_info->mfw_rev, NULL); 378 } 379 380 return 0; 381 } 382 383 int 384 qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info) 385 { 386 struct qede_dev *qdev = (struct qede_dev *)edev; 387 uint8_t queues = 0; 388 int i; 389 390 memset(info, 0, sizeof(*info)); 391 392 info->num_tc = 1 /* @@@TBD aelior MULTI_COS */; 393 394 if (IS_PF(edev)) { 395 int max_vf_vlan_filters = 0; 396 397 info->num_queues = 0; 398 for_each_hwfn(edev, i) 399 info->num_queues += 400 FEAT_NUM(&edev->hwfns[i], ECORE_PF_L2_QUE); 401 402 if (edev->p_iov_info) 403 max_vf_vlan_filters = edev->p_iov_info->total_vfs * 404 ECORE_ETH_VF_NUM_VLAN_FILTERS; 405 info->num_vlan_filters = RESC_NUM(&edev->hwfns[0], ECORE_VLAN) - 406 max_vf_vlan_filters; 407 408 rte_memcpy(&info->port_mac, &edev->hwfns[0].hw_info.hw_mac_addr, 409 ETHER_ADDR_LEN); 410 } else { 411 ecore_vf_get_num_rxqs(ECORE_LEADING_HWFN(edev), 412 &info->num_queues); 413 if (edev->num_hwfns > 1) { 414 ecore_vf_get_num_rxqs(&edev->hwfns[1], &queues); 415 info->num_queues += queues; 416 /* Restrict 100G VF to advertise 16 queues till the 417 * required support is available to go beyond 16. 418 */ 419 info->num_queues = RTE_MIN(info->num_queues, 420 ECORE_MAX_VF_CHAINS_PER_PF); 421 } 422 423 ecore_vf_get_num_vlan_filters(&edev->hwfns[0], 424 (u8 *)&info->num_vlan_filters); 425 426 ecore_vf_get_port_mac(&edev->hwfns[0], 427 (uint8_t *)&info->port_mac); 428 } 429 430 qed_fill_dev_info(edev, &info->common); 431 432 if (IS_VF(edev)) 433 memset(&info->common.hw_mac, 0, ETHER_ADDR_LEN); 434 435 return 0; 436 } 437 438 static void 439 qed_set_id(struct ecore_dev *edev, char name[NAME_SIZE], 440 const char ver_str[NAME_SIZE]) 441 { 442 int i; 443 444 rte_memcpy(edev->name, name, NAME_SIZE); 445 for_each_hwfn(edev, i) { 446 snprintf(edev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i); 447 } 448 memcpy(edev->ver_str, ver_str, NAME_SIZE); 449 edev->drv_type = DRV_ID_DRV_TYPE_LINUX; 450 } 451 452 static uint32_t 453 qed_sb_init(struct ecore_dev *edev, struct ecore_sb_info *sb_info, 454 void *sb_virt_addr, dma_addr_t sb_phy_addr, 455 uint16_t sb_id, enum qed_sb_type type) 456 { 457 struct ecore_hwfn *p_hwfn; 458 int hwfn_index; 459 uint16_t rel_sb_id; 460 uint8_t n_hwfns; 461 uint32_t rc; 462 463 /* RoCE uses single engine and CMT uses two engines. When using both 464 * we force only a single engine. Storage uses only engine 0 too. 465 */ 466 if (type == QED_SB_TYPE_L2_QUEUE) 467 n_hwfns = edev->num_hwfns; 468 else 469 n_hwfns = 1; 470 471 hwfn_index = sb_id % n_hwfns; 472 p_hwfn = &edev->hwfns[hwfn_index]; 473 rel_sb_id = sb_id / n_hwfns; 474 475 DP_INFO(edev, "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n", 476 hwfn_index, rel_sb_id, sb_id); 477 478 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info, 479 sb_virt_addr, sb_phy_addr, rel_sb_id); 480 481 return rc; 482 } 483 484 static void qed_fill_link(struct ecore_hwfn *hwfn, 485 struct qed_link_output *if_link) 486 { 487 struct ecore_mcp_link_params params; 488 struct ecore_mcp_link_state link; 489 struct ecore_mcp_link_capabilities link_caps; 490 uint32_t media_type; 491 uint8_t change = 0; 492 493 memset(if_link, 0, sizeof(*if_link)); 494 495 /* Prepare source inputs */ 496 if (IS_PF(hwfn->p_dev)) { 497 rte_memcpy(¶ms, ecore_mcp_get_link_params(hwfn), 498 sizeof(params)); 499 rte_memcpy(&link, ecore_mcp_get_link_state(hwfn), sizeof(link)); 500 rte_memcpy(&link_caps, ecore_mcp_get_link_capabilities(hwfn), 501 sizeof(link_caps)); 502 } else { 503 ecore_vf_read_bulletin(hwfn, &change); 504 ecore_vf_get_link_params(hwfn, ¶ms); 505 ecore_vf_get_link_state(hwfn, &link); 506 ecore_vf_get_link_caps(hwfn, &link_caps); 507 } 508 509 /* Set the link parameters to pass to protocol driver */ 510 if (link.link_up) 511 if_link->link_up = true; 512 513 if (link.link_up) 514 if_link->speed = link.speed; 515 516 if_link->duplex = QEDE_DUPLEX_FULL; 517 518 /* Fill up the native advertised speed cap mask */ 519 if_link->adv_speed = params.speed.advertised_speeds; 520 521 if (params.speed.autoneg) 522 if_link->supported_caps |= QEDE_SUPPORTED_AUTONEG; 523 524 if (params.pause.autoneg || params.pause.forced_rx || 525 params.pause.forced_tx) 526 if_link->supported_caps |= QEDE_SUPPORTED_PAUSE; 527 528 if (params.pause.autoneg) 529 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 530 531 if (params.pause.forced_rx) 532 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE; 533 534 if (params.pause.forced_tx) 535 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; 536 } 537 538 static void 539 qed_get_current_link(struct ecore_dev *edev, struct qed_link_output *if_link) 540 { 541 qed_fill_link(&edev->hwfns[0], if_link); 542 543 #ifdef CONFIG_QED_SRIOV 544 for_each_hwfn(cdev, i) 545 qed_inform_vf_link_state(&cdev->hwfns[i]); 546 #endif 547 } 548 549 static int qed_set_link(struct ecore_dev *edev, struct qed_link_params *params) 550 { 551 struct ecore_hwfn *hwfn; 552 struct ecore_ptt *ptt; 553 struct ecore_mcp_link_params *link_params; 554 int rc; 555 556 if (IS_VF(edev)) 557 return 0; 558 559 /* The link should be set only once per PF */ 560 hwfn = &edev->hwfns[0]; 561 562 ptt = ecore_ptt_acquire(hwfn); 563 if (!ptt) 564 return -EBUSY; 565 566 link_params = ecore_mcp_get_link_params(hwfn); 567 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) 568 link_params->speed.autoneg = params->autoneg; 569 570 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { 571 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 572 link_params->pause.autoneg = true; 573 else 574 link_params->pause.autoneg = false; 575 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE) 576 link_params->pause.forced_rx = true; 577 else 578 link_params->pause.forced_rx = false; 579 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE) 580 link_params->pause.forced_tx = true; 581 else 582 link_params->pause.forced_tx = false; 583 } 584 585 rc = ecore_mcp_set_link(hwfn, ptt, params->link_up); 586 587 ecore_ptt_release(hwfn, ptt); 588 589 return rc; 590 } 591 592 void qed_link_update(struct ecore_hwfn *hwfn) 593 { 594 struct qed_link_output if_link; 595 596 qed_fill_link(hwfn, &if_link); 597 } 598 599 static int qed_drain(struct ecore_dev *edev) 600 { 601 struct ecore_hwfn *hwfn; 602 struct ecore_ptt *ptt; 603 int i, rc; 604 605 if (IS_VF(edev)) 606 return 0; 607 608 for_each_hwfn(edev, i) { 609 hwfn = &edev->hwfns[i]; 610 ptt = ecore_ptt_acquire(hwfn); 611 if (!ptt) { 612 DP_NOTICE(hwfn, true, "Failed to drain NIG; No PTT\n"); 613 return -EBUSY; 614 } 615 rc = ecore_mcp_drain(hwfn, ptt); 616 if (rc) 617 return rc; 618 ecore_ptt_release(hwfn, ptt); 619 } 620 621 return 0; 622 } 623 624 static int qed_nic_stop(struct ecore_dev *edev) 625 { 626 int i, rc; 627 628 rc = ecore_hw_stop(edev); 629 for (i = 0; i < edev->num_hwfns; i++) { 630 struct ecore_hwfn *p_hwfn = &edev->hwfns[i]; 631 632 if (p_hwfn->b_sp_dpc_enabled) 633 p_hwfn->b_sp_dpc_enabled = false; 634 } 635 return rc; 636 } 637 638 static int qed_nic_reset(struct ecore_dev *edev) 639 { 640 int rc; 641 642 rc = ecore_hw_reset(edev); 643 if (rc) 644 return rc; 645 646 ecore_resc_free(edev); 647 648 return 0; 649 } 650 651 static int qed_slowpath_stop(struct ecore_dev *edev) 652 { 653 #ifdef CONFIG_QED_SRIOV 654 int i; 655 #endif 656 657 if (!edev) 658 return -ENODEV; 659 660 if (IS_PF(edev)) { 661 #ifdef CONFIG_ECORE_ZIPPED_FW 662 qed_free_stream_mem(edev); 663 #endif 664 665 #ifdef CONFIG_QED_SRIOV 666 if (IS_QED_ETH_IF(edev)) 667 qed_sriov_disable(edev, true); 668 #endif 669 qed_nic_stop(edev); 670 } 671 672 qed_nic_reset(edev); 673 qed_stop_iov_task(edev); 674 675 return 0; 676 } 677 678 static void qed_remove(struct ecore_dev *edev) 679 { 680 if (!edev) 681 return; 682 683 ecore_hw_remove(edev); 684 } 685 686 const struct qed_common_ops qed_common_ops_pass = { 687 INIT_STRUCT_FIELD(probe, &qed_probe), 688 INIT_STRUCT_FIELD(update_pf_params, &qed_update_pf_params), 689 INIT_STRUCT_FIELD(slowpath_start, &qed_slowpath_start), 690 INIT_STRUCT_FIELD(set_id, &qed_set_id), 691 INIT_STRUCT_FIELD(chain_alloc, &ecore_chain_alloc), 692 INIT_STRUCT_FIELD(chain_free, &ecore_chain_free), 693 INIT_STRUCT_FIELD(sb_init, &qed_sb_init), 694 INIT_STRUCT_FIELD(get_link, &qed_get_current_link), 695 INIT_STRUCT_FIELD(set_link, &qed_set_link), 696 INIT_STRUCT_FIELD(drain, &qed_drain), 697 INIT_STRUCT_FIELD(slowpath_stop, &qed_slowpath_stop), 698 INIT_STRUCT_FIELD(remove, &qed_remove), 699 }; 700