1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 10 #ifndef _QEDE_ETHDEV_H_ 11 #define _QEDE_ETHDEV_H_ 12 13 #include <sys/queue.h> 14 15 #include <rte_ether.h> 16 #include <rte_ethdev_driver.h> 17 #include <rte_ethdev_pci.h> 18 #include <rte_dev.h> 19 #include <rte_ip.h> 20 21 /* ecore includes */ 22 #include "base/bcm_osal.h" 23 #include "base/ecore.h" 24 #include "base/ecore_dev_api.h" 25 #include "base/ecore_l2_api.h" 26 #include "base/ecore_vf_api.h" 27 #include "base/ecore_hsi_common.h" 28 #include "base/ecore_int_api.h" 29 #include "base/ecore_chain.h" 30 #include "base/ecore_status.h" 31 #include "base/ecore_hsi_eth.h" 32 #include "base/ecore_iov_api.h" 33 #include "base/ecore_cxt.h" 34 #include "base/nvm_cfg.h" 35 #include "base/ecore_sp_commands.h" 36 #include "base/ecore_l2.h" 37 38 #include "qede_logs.h" 39 #include "qede_if.h" 40 #include "qede_rxtx.h" 41 42 #define qede_stringify1(x...) #x 43 #define qede_stringify(x...) qede_stringify1(x) 44 45 /* Driver versions */ 46 #define QEDE_PMD_VER_PREFIX "QEDE PMD" 47 #define QEDE_PMD_VERSION_MAJOR 2 48 #define QEDE_PMD_VERSION_MINOR 8 49 #define QEDE_PMD_VERSION_REVISION 0 50 #define QEDE_PMD_VERSION_PATCH 1 51 52 #define QEDE_PMD_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \ 53 qede_stringify(QEDE_PMD_VERSION_MINOR) "." \ 54 qede_stringify(QEDE_PMD_VERSION_REVISION) "." \ 55 qede_stringify(QEDE_PMD_VERSION_PATCH) 56 57 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE 58 #define QEDE_PMD_VER_PREFIX "QEDE PMD" 59 60 61 #define QEDE_RSS_INDIR_INITED (1 << 0) 62 #define QEDE_RSS_KEY_INITED (1 << 1) 63 #define QEDE_RSS_CAPS_INITED (1 << 2) 64 65 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 66 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \ 67 (edev)->dev_info.num_tc) 68 69 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues) 70 #define QEDE_RSS_COUNT(qdev) ((qdev)->num_rx_queues) 71 #define QEDE_TSS_COUNT(qdev) ((qdev)->num_tx_queues) 72 73 #define QEDE_DUPLEX_FULL 1 74 #define QEDE_DUPLEX_HALF 2 75 #define QEDE_DUPLEX_UNKNOWN 0xff 76 77 #define QEDE_SUPPORTED_AUTONEG (1 << 6) 78 #define QEDE_SUPPORTED_PAUSE (1 << 13) 79 80 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private) 81 82 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev) 83 84 #define QEDE_INIT(eth_dev) { \ 85 struct qede_dev *qdev = eth_dev->data->dev_private; \ 86 struct ecore_dev *edev = &qdev->edev; \ 87 } 88 89 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/ 90 #define PCI_VENDOR_ID_QLOGIC 0x1077 91 92 #define CHIP_NUM_57980E 0x1634 93 #define CHIP_NUM_57980S 0x1629 94 #define CHIP_NUM_VF 0x1630 95 #define CHIP_NUM_57980S_40 0x1634 96 #define CHIP_NUM_57980S_25 0x1656 97 #define CHIP_NUM_57980S_IOV 0x1664 98 #define CHIP_NUM_57980S_100 0x1644 99 #define CHIP_NUM_57980S_50 0x1654 100 #define CHIP_NUM_AH_50G 0x8070 101 #define CHIP_NUM_AH_10G 0x8071 102 #define CHIP_NUM_AH_40G 0x8072 103 #define CHIP_NUM_AH_25G 0x8073 104 #define CHIP_NUM_AH_IOV 0x8090 105 106 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E 107 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S 108 #define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF 109 #define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40 110 #define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25 111 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV 112 #define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100 113 #define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50 114 #define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G 115 #define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G 116 #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G 117 #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G 118 #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV 119 120 121 122 extern char fw_file[]; 123 124 /* Number of PF connections - 32 RX + 32 TX */ 125 #define QEDE_PF_NUM_CONNS (64) 126 127 /* Maximum number of flowdir filters */ 128 #define QEDE_RFS_MAX_FLTR (256) 129 130 #define QEDE_MAX_MCAST_FILTERS (64) 131 132 enum qed_filter_rx_mode_type { 133 QED_FILTER_RX_MODE_TYPE_REGULAR, 134 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC, 135 QED_FILTER_RX_MODE_TYPE_PROMISC, 136 }; 137 138 struct qede_vlan_entry { 139 SLIST_ENTRY(qede_vlan_entry) list; 140 uint16_t vid; 141 }; 142 143 struct qede_mcast_entry { 144 struct ether_addr mac; 145 SLIST_ENTRY(qede_mcast_entry) list; 146 }; 147 148 struct qede_ucast_entry { 149 struct ether_addr mac; 150 uint16_t vlan; 151 uint16_t vni; 152 SLIST_ENTRY(qede_ucast_entry) list; 153 }; 154 155 struct qede_fdir_entry { 156 uint32_t soft_id; /* unused for now */ 157 uint16_t pkt_len; /* actual packet length to match */ 158 uint16_t rx_queue; /* queue to be steered to */ 159 const struct rte_memzone *mz; /* mz used to hold L2 frame */ 160 SLIST_ENTRY(qede_fdir_entry) list; 161 }; 162 163 struct qede_fdir_info { 164 struct ecore_arfs_config_params arfs; 165 uint16_t filter_count; 166 SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head; 167 }; 168 169 /* IANA assigned default UDP ports for encapsulation protocols */ 170 #define QEDE_VXLAN_DEF_PORT (4789) 171 #define QEDE_GENEVE_DEF_PORT (6081) 172 173 struct qede_tunn_params { 174 bool enable; 175 uint16_t num_filters; 176 uint16_t filter_type; 177 uint16_t udp_port; 178 }; 179 180 /* 181 * Structure to store private data for each port. 182 */ 183 struct qede_dev { 184 struct ecore_dev edev; 185 const struct qed_eth_ops *ops; 186 struct qed_dev_eth_info dev_info; 187 struct ecore_sb_info *sb_array; 188 struct qede_fastpath *fp_array; 189 uint16_t mtu; 190 bool enable_tx_switching; 191 bool rss_enable; 192 struct rte_eth_rss_conf rss_conf; 193 uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE]; 194 uint64_t rss_hf; 195 uint8_t rss_key_len; 196 bool enable_lro; 197 uint8_t num_rx_queues; 198 uint8_t num_tx_queues; 199 SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head; 200 uint16_t configured_vlans; 201 bool accept_any_vlan; 202 struct ether_addr primary_mac; 203 SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head; 204 uint16_t num_mc_addr; 205 SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head; 206 uint16_t num_uc_addr; 207 bool handle_hw_err; 208 struct qede_tunn_params vxlan; 209 struct qede_tunn_params geneve; 210 struct qede_tunn_params ipgre; 211 struct qede_fdir_info fdir_info; 212 bool vlan_strip_flg; 213 char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 214 bool vport_started; 215 int vlan_offload_mask; 216 void *ethdev; 217 }; 218 219 /* Non-static functions */ 220 int qede_config_rss(struct rte_eth_dev *eth_dev); 221 222 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 223 struct rte_eth_rss_conf *rss_conf); 224 225 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 226 struct rte_eth_rss_reta_entry64 *reta_conf, 227 uint16_t reta_size); 228 229 int qed_fill_eth_dev_info(struct ecore_dev *edev, 230 struct qed_dev_eth_info *info); 231 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up); 232 233 int qede_link_update(struct rte_eth_dev *eth_dev, 234 __rte_unused int wait_to_complete); 235 236 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type, 237 enum rte_filter_op op, void *arg); 238 239 int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev, 240 enum rte_filter_op filter_op, void *arg); 241 242 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev, 243 enum rte_filter_op filter_op, void *arg); 244 245 int qede_check_fdir_support(struct rte_eth_dev *eth_dev); 246 247 uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev, 248 struct rte_eth_fdir_filter *fdir, 249 void *buff, 250 struct ecore_arfs_config_params *params); 251 252 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev); 253 254 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg); 255 256 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu); 257 258 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg); 259 260 #endif /* _QEDE_ETHDEV_H_ */ 261