1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 8 #ifndef _QEDE_ETHDEV_H_ 9 #define _QEDE_ETHDEV_H_ 10 11 #include <sys/queue.h> 12 13 #include <rte_ether.h> 14 #include <rte_ethdev_driver.h> 15 #include <rte_ethdev_pci.h> 16 #include <rte_dev.h> 17 #include <rte_ip.h> 18 19 /* ecore includes */ 20 #include "base/bcm_osal.h" 21 #include "base/ecore.h" 22 #include "base/ecore_dev_api.h" 23 #include "base/ecore_l2_api.h" 24 #include "base/ecore_vf_api.h" 25 #include "base/ecore_hsi_common.h" 26 #include "base/ecore_int_api.h" 27 #include "base/ecore_chain.h" 28 #include "base/ecore_status.h" 29 #include "base/ecore_hsi_eth.h" 30 #include "base/ecore_iov_api.h" 31 #include "base/ecore_cxt.h" 32 #include "base/nvm_cfg.h" 33 #include "base/ecore_sp_commands.h" 34 #include "base/ecore_l2.h" 35 #include "base/ecore_vf.h" 36 37 #include "qede_logs.h" 38 #include "qede_if.h" 39 #include "qede_rxtx.h" 40 41 #define qede_stringify1(x...) #x 42 #define qede_stringify(x...) qede_stringify1(x) 43 44 /* Driver versions */ 45 #define QEDE_PMD_VER_PREFIX "QEDE PMD" 46 #define QEDE_PMD_VERSION_MAJOR 2 47 #define QEDE_PMD_VERSION_MINOR 9 48 #define QEDE_PMD_VERSION_REVISION 0 49 #define QEDE_PMD_VERSION_PATCH 1 50 51 #define QEDE_PMD_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \ 52 qede_stringify(QEDE_PMD_VERSION_MINOR) "." \ 53 qede_stringify(QEDE_PMD_VERSION_REVISION) "." \ 54 qede_stringify(QEDE_PMD_VERSION_PATCH) 55 56 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE 57 #define QEDE_PMD_VER_PREFIX "QEDE PMD" 58 59 60 #define QEDE_RSS_INDIR_INITED (1 << 0) 61 #define QEDE_RSS_KEY_INITED (1 << 1) 62 #define QEDE_RSS_CAPS_INITED (1 << 2) 63 64 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues) 65 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \ 66 (edev)->dev_info.num_tc) 67 68 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues) 69 #define QEDE_RSS_COUNT(qdev) ((qdev)->num_rx_queues) 70 #define QEDE_TSS_COUNT(qdev) ((qdev)->num_tx_queues) 71 72 #define QEDE_DUPLEX_FULL 1 73 #define QEDE_DUPLEX_HALF 2 74 #define QEDE_DUPLEX_UNKNOWN 0xff 75 76 #define QEDE_SUPPORTED_AUTONEG (1 << 6) 77 #define QEDE_SUPPORTED_PAUSE (1 << 13) 78 79 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private) 80 81 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev) 82 83 #define QEDE_INIT(eth_dev) { \ 84 struct qede_dev *qdev = eth_dev->data->dev_private; \ 85 struct ecore_dev *edev = &qdev->edev; \ 86 } 87 88 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/ 89 #define PCI_VENDOR_ID_QLOGIC 0x1077 90 91 #define CHIP_NUM_57980E 0x1634 92 #define CHIP_NUM_57980S 0x1629 93 #define CHIP_NUM_VF 0x1630 94 #define CHIP_NUM_57980S_40 0x1634 95 #define CHIP_NUM_57980S_25 0x1656 96 #define CHIP_NUM_57980S_IOV 0x1664 97 #define CHIP_NUM_57980S_100 0x1644 98 #define CHIP_NUM_57980S_50 0x1654 99 #define CHIP_NUM_AH_50G 0x8070 100 #define CHIP_NUM_AH_10G 0x8071 101 #define CHIP_NUM_AH_40G 0x8072 102 #define CHIP_NUM_AH_25G 0x8073 103 #define CHIP_NUM_AH_IOV 0x8090 104 105 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E 106 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S 107 #define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF 108 #define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40 109 #define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25 110 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV 111 #define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100 112 #define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50 113 #define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G 114 #define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G 115 #define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G 116 #define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G 117 #define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV 118 119 120 121 extern char fw_file[]; 122 123 /* Number of PF connections - 32 RX + 32 TX */ 124 #define QEDE_PF_NUM_CONNS (64) 125 126 /* Maximum number of flowdir filters */ 127 #define QEDE_RFS_MAX_FLTR (256) 128 129 #define QEDE_MAX_MCAST_FILTERS (64) 130 131 enum qed_filter_rx_mode_type { 132 QED_FILTER_RX_MODE_TYPE_REGULAR, 133 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC, 134 QED_FILTER_RX_MODE_TYPE_PROMISC, 135 }; 136 137 struct qede_vlan_entry { 138 SLIST_ENTRY(qede_vlan_entry) list; 139 uint16_t vid; 140 }; 141 142 struct qede_mcast_entry { 143 struct ether_addr mac; 144 SLIST_ENTRY(qede_mcast_entry) list; 145 }; 146 147 struct qede_ucast_entry { 148 struct ether_addr mac; 149 uint16_t vlan; 150 uint16_t vni; 151 SLIST_ENTRY(qede_ucast_entry) list; 152 }; 153 154 struct qede_fdir_entry { 155 uint32_t soft_id; /* unused for now */ 156 uint16_t pkt_len; /* actual packet length to match */ 157 uint16_t rx_queue; /* queue to be steered to */ 158 const struct rte_memzone *mz; /* mz used to hold L2 frame */ 159 SLIST_ENTRY(qede_fdir_entry) list; 160 }; 161 162 struct qede_fdir_info { 163 struct ecore_arfs_config_params arfs; 164 uint16_t filter_count; 165 SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head; 166 }; 167 168 /* IANA assigned default UDP ports for encapsulation protocols */ 169 #define QEDE_VXLAN_DEF_PORT (4789) 170 #define QEDE_GENEVE_DEF_PORT (6081) 171 172 struct qede_tunn_params { 173 bool enable; 174 uint16_t num_filters; 175 uint16_t filter_type; 176 uint16_t udp_port; 177 }; 178 179 /* 180 * Structure to store private data for each port. 181 */ 182 struct qede_dev { 183 struct ecore_dev edev; 184 const struct qed_eth_ops *ops; 185 struct qed_dev_eth_info dev_info; 186 struct ecore_sb_info *sb_array; 187 struct qede_fastpath *fp_array; 188 uint16_t mtu; 189 bool enable_tx_switching; 190 bool rss_enable; 191 struct rte_eth_rss_conf rss_conf; 192 uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE]; 193 uint64_t rss_hf; 194 uint8_t rss_key_len; 195 bool enable_lro; 196 uint8_t num_rx_queues; 197 uint8_t num_tx_queues; 198 SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head; 199 uint16_t configured_vlans; 200 bool accept_any_vlan; 201 struct ether_addr primary_mac; 202 SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head; 203 uint16_t num_mc_addr; 204 SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head; 205 uint16_t num_uc_addr; 206 bool handle_hw_err; 207 struct qede_tunn_params vxlan; 208 struct qede_tunn_params geneve; 209 struct qede_tunn_params ipgre; 210 struct qede_fdir_info fdir_info; 211 bool vlan_strip_flg; 212 char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 213 bool vport_started; 214 int vlan_offload_mask; 215 void *ethdev; 216 }; 217 218 /* Non-static functions */ 219 int qede_config_rss(struct rte_eth_dev *eth_dev); 220 221 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 222 struct rte_eth_rss_conf *rss_conf); 223 224 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 225 struct rte_eth_rss_reta_entry64 *reta_conf, 226 uint16_t reta_size); 227 228 int qed_fill_eth_dev_info(struct ecore_dev *edev, 229 struct qed_dev_eth_info *info); 230 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up); 231 232 int qede_link_update(struct rte_eth_dev *eth_dev, 233 __rte_unused int wait_to_complete); 234 235 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type, 236 enum rte_filter_op op, void *arg); 237 238 int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev, 239 enum rte_filter_op filter_op, void *arg); 240 241 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev, 242 enum rte_filter_op filter_op, void *arg); 243 244 int qede_check_fdir_support(struct rte_eth_dev *eth_dev); 245 246 uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev, 247 struct rte_eth_fdir_filter *fdir, 248 void *buff, 249 struct ecore_arfs_config_params *params); 250 251 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev); 252 253 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg); 254 255 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu); 256 257 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg); 258 259 #endif /* _QEDE_ETHDEV_H_ */ 260