1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 #include <rte_kvargs.h> 13 14 /* Globals */ 15 int qede_logtype_init; 16 int qede_logtype_driver; 17 18 static const struct qed_eth_ops *qed_ops; 19 static int64_t timer_period = 1; 20 21 /* VXLAN tunnel classification mapping */ 22 const struct _qede_udp_tunn_types { 23 uint16_t rte_filter_type; 24 enum ecore_filter_ucast_type qede_type; 25 enum ecore_tunn_clss qede_tunn_clss; 26 const char *string; 27 } qede_tunn_types[] = { 28 { 29 ETH_TUNNEL_FILTER_OMAC, 30 ECORE_FILTER_MAC, 31 ECORE_TUNN_CLSS_MAC_VLAN, 32 "outer-mac" 33 }, 34 { 35 ETH_TUNNEL_FILTER_TENID, 36 ECORE_FILTER_VNI, 37 ECORE_TUNN_CLSS_MAC_VNI, 38 "vni" 39 }, 40 { 41 ETH_TUNNEL_FILTER_IMAC, 42 ECORE_FILTER_INNER_MAC, 43 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 44 "inner-mac" 45 }, 46 { 47 ETH_TUNNEL_FILTER_IVLAN, 48 ECORE_FILTER_INNER_VLAN, 49 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 50 "inner-vlan" 51 }, 52 { 53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 54 ECORE_FILTER_MAC_VNI_PAIR, 55 ECORE_TUNN_CLSS_MAC_VNI, 56 "outer-mac and vni" 57 }, 58 { 59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 60 ECORE_FILTER_UNUSED, 61 MAX_ECORE_TUNN_CLSS, 62 "outer-mac and inner-mac" 63 }, 64 { 65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 66 ECORE_FILTER_UNUSED, 67 MAX_ECORE_TUNN_CLSS, 68 "outer-mac and inner-vlan" 69 }, 70 { 71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 72 ECORE_FILTER_INNER_MAC_VNI_PAIR, 73 ECORE_TUNN_CLSS_INNER_MAC_VNI, 74 "vni and inner-mac", 75 }, 76 { 77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 78 ECORE_FILTER_UNUSED, 79 MAX_ECORE_TUNN_CLSS, 80 "vni and inner-vlan", 81 }, 82 { 83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 84 ECORE_FILTER_INNER_PAIR, 85 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 86 "inner-mac and inner-vlan", 87 }, 88 { 89 ETH_TUNNEL_FILTER_OIP, 90 ECORE_FILTER_UNUSED, 91 MAX_ECORE_TUNN_CLSS, 92 "outer-IP" 93 }, 94 { 95 ETH_TUNNEL_FILTER_IIP, 96 ECORE_FILTER_UNUSED, 97 MAX_ECORE_TUNN_CLSS, 98 "inner-IP" 99 }, 100 { 101 RTE_TUNNEL_FILTER_IMAC_IVLAN, 102 ECORE_FILTER_UNUSED, 103 MAX_ECORE_TUNN_CLSS, 104 "IMAC_IVLAN" 105 }, 106 { 107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 108 ECORE_FILTER_UNUSED, 109 MAX_ECORE_TUNN_CLSS, 110 "IMAC_IVLAN_TENID" 111 }, 112 { 113 RTE_TUNNEL_FILTER_IMAC_TENID, 114 ECORE_FILTER_UNUSED, 115 MAX_ECORE_TUNN_CLSS, 116 "IMAC_TENID" 117 }, 118 { 119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 120 ECORE_FILTER_UNUSED, 121 MAX_ECORE_TUNN_CLSS, 122 "OMAC_TENID_IMAC" 123 }, 124 }; 125 126 struct rte_qede_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 uint64_t offset; 129 }; 130 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 132 {"rx_unicast_bytes", 133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)}, 134 {"rx_multicast_bytes", 135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)}, 136 {"rx_broadcast_bytes", 137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)}, 138 {"rx_unicast_packets", 139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)}, 140 {"rx_multicast_packets", 141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)}, 142 {"rx_broadcast_packets", 143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)}, 144 145 {"tx_unicast_bytes", 146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)}, 147 {"tx_multicast_bytes", 148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)}, 149 {"tx_broadcast_bytes", 150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)}, 151 {"tx_unicast_packets", 152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)}, 153 {"tx_multicast_packets", 154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)}, 155 {"tx_broadcast_packets", 156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)}, 157 158 {"rx_64_byte_packets", 159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)}, 160 {"rx_65_to_127_byte_packets", 161 offsetof(struct ecore_eth_stats_common, 162 rx_65_to_127_byte_packets)}, 163 {"rx_128_to_255_byte_packets", 164 offsetof(struct ecore_eth_stats_common, 165 rx_128_to_255_byte_packets)}, 166 {"rx_256_to_511_byte_packets", 167 offsetof(struct ecore_eth_stats_common, 168 rx_256_to_511_byte_packets)}, 169 {"rx_512_to_1023_byte_packets", 170 offsetof(struct ecore_eth_stats_common, 171 rx_512_to_1023_byte_packets)}, 172 {"rx_1024_to_1518_byte_packets", 173 offsetof(struct ecore_eth_stats_common, 174 rx_1024_to_1518_byte_packets)}, 175 {"tx_64_byte_packets", 176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)}, 177 {"tx_65_to_127_byte_packets", 178 offsetof(struct ecore_eth_stats_common, 179 tx_65_to_127_byte_packets)}, 180 {"tx_128_to_255_byte_packets", 181 offsetof(struct ecore_eth_stats_common, 182 tx_128_to_255_byte_packets)}, 183 {"tx_256_to_511_byte_packets", 184 offsetof(struct ecore_eth_stats_common, 185 tx_256_to_511_byte_packets)}, 186 {"tx_512_to_1023_byte_packets", 187 offsetof(struct ecore_eth_stats_common, 188 tx_512_to_1023_byte_packets)}, 189 {"tx_1024_to_1518_byte_packets", 190 offsetof(struct ecore_eth_stats_common, 191 tx_1024_to_1518_byte_packets)}, 192 193 {"rx_mac_crtl_frames", 194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)}, 195 {"tx_mac_control_frames", 196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)}, 197 {"rx_pause_frames", 198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)}, 199 {"tx_pause_frames", 200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)}, 201 {"rx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)}, 203 {"tx_priority_flow_control_frames", 204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)}, 205 206 {"rx_crc_errors", 207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)}, 208 {"rx_align_errors", 209 offsetof(struct ecore_eth_stats_common, rx_align_errors)}, 210 {"rx_carrier_errors", 211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)}, 212 {"rx_oversize_packet_errors", 213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)}, 214 {"rx_jabber_errors", 215 offsetof(struct ecore_eth_stats_common, rx_jabbers)}, 216 {"rx_undersize_packet_errors", 217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)}, 218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)}, 219 {"rx_host_buffer_not_available", 220 offsetof(struct ecore_eth_stats_common, no_buff_discards)}, 221 /* Number of packets discarded because they are bigger than MTU */ 222 {"rx_packet_too_big_discards", 223 offsetof(struct ecore_eth_stats_common, 224 packet_too_big_discard)}, 225 {"rx_ttl_zero_discards", 226 offsetof(struct ecore_eth_stats_common, ttl0_discard)}, 227 {"rx_multi_function_tag_filter_discards", 228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)}, 229 {"rx_mac_filter_discards", 230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)}, 231 {"rx_hw_buffer_truncates", 232 offsetof(struct ecore_eth_stats_common, brb_truncates)}, 233 {"rx_hw_buffer_discards", 234 offsetof(struct ecore_eth_stats_common, brb_discards)}, 235 {"tx_error_drop_packets", 236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)}, 237 238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)}, 239 {"rx_mac_unicast_packets", 240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)}, 241 {"rx_mac_multicast_packets", 242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)}, 243 {"rx_mac_broadcast_packets", 244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)}, 245 {"rx_mac_frames_ok", 246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)}, 247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)}, 248 {"tx_mac_unicast_packets", 249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)}, 250 {"tx_mac_multicast_packets", 251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)}, 252 {"tx_mac_broadcast_packets", 253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)}, 254 255 {"lro_coalesced_packets", 256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)}, 257 {"lro_coalesced_events", 258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)}, 259 {"lro_aborts_num", 260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)}, 261 {"lro_not_coalesced_packets", 262 offsetof(struct ecore_eth_stats_common, 263 tpa_not_coalesced_pkts)}, 264 {"lro_coalesced_bytes", 265 offsetof(struct ecore_eth_stats_common, 266 tpa_coalesced_bytes)}, 267 }; 268 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = { 270 {"rx_1519_to_1522_byte_packets", 271 offsetof(struct ecore_eth_stats, bb) + 272 offsetof(struct ecore_eth_stats_bb, 273 rx_1519_to_1522_byte_packets)}, 274 {"rx_1519_to_2047_byte_packets", 275 offsetof(struct ecore_eth_stats, bb) + 276 offsetof(struct ecore_eth_stats_bb, 277 rx_1519_to_2047_byte_packets)}, 278 {"rx_2048_to_4095_byte_packets", 279 offsetof(struct ecore_eth_stats, bb) + 280 offsetof(struct ecore_eth_stats_bb, 281 rx_2048_to_4095_byte_packets)}, 282 {"rx_4096_to_9216_byte_packets", 283 offsetof(struct ecore_eth_stats, bb) + 284 offsetof(struct ecore_eth_stats_bb, 285 rx_4096_to_9216_byte_packets)}, 286 {"rx_9217_to_16383_byte_packets", 287 offsetof(struct ecore_eth_stats, bb) + 288 offsetof(struct ecore_eth_stats_bb, 289 rx_9217_to_16383_byte_packets)}, 290 291 {"tx_1519_to_2047_byte_packets", 292 offsetof(struct ecore_eth_stats, bb) + 293 offsetof(struct ecore_eth_stats_bb, 294 tx_1519_to_2047_byte_packets)}, 295 {"tx_2048_to_4095_byte_packets", 296 offsetof(struct ecore_eth_stats, bb) + 297 offsetof(struct ecore_eth_stats_bb, 298 tx_2048_to_4095_byte_packets)}, 299 {"tx_4096_to_9216_byte_packets", 300 offsetof(struct ecore_eth_stats, bb) + 301 offsetof(struct ecore_eth_stats_bb, 302 tx_4096_to_9216_byte_packets)}, 303 {"tx_9217_to_16383_byte_packets", 304 offsetof(struct ecore_eth_stats, bb) + 305 offsetof(struct ecore_eth_stats_bb, 306 tx_9217_to_16383_byte_packets)}, 307 308 {"tx_lpi_entry_count", 309 offsetof(struct ecore_eth_stats, bb) + 310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)}, 311 {"tx_total_collisions", 312 offsetof(struct ecore_eth_stats, bb) + 313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)}, 314 }; 315 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = { 317 {"rx_1519_to_max_byte_packets", 318 offsetof(struct ecore_eth_stats, ah) + 319 offsetof(struct ecore_eth_stats_ah, 320 rx_1519_to_max_byte_packets)}, 321 {"tx_1519_to_max_byte_packets", 322 offsetof(struct ecore_eth_stats, ah) + 323 offsetof(struct ecore_eth_stats_ah, 324 tx_1519_to_max_byte_packets)}, 325 }; 326 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 328 {"rx_q_segments", 329 offsetof(struct qede_rx_queue, rx_segs)}, 330 {"rx_q_hw_errors", 331 offsetof(struct qede_rx_queue, rx_hw_errors)}, 332 {"rx_q_allocation_errors", 333 offsetof(struct qede_rx_queue, rx_alloc_errors)} 334 }; 335 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 337 { 338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 339 } 340 341 static void 342 qede_interrupt_handler(void *param) 343 { 344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 345 struct qede_dev *qdev = eth_dev->data->dev_private; 346 struct ecore_dev *edev = &qdev->edev; 347 348 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 349 if (rte_intr_enable(eth_dev->intr_handle)) 350 DP_ERR(edev, "rte_intr_enable failed\n"); 351 } 352 353 static void 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 355 { 356 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 357 qdev->ops = qed_ops; 358 } 359 360 static void qede_print_adapter_info(struct qede_dev *qdev) 361 { 362 struct ecore_dev *edev = &qdev->edev; 363 struct qed_dev_info *info = &qdev->dev_info.common; 364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 366 367 DP_INFO(edev, "*********************************\n"); 368 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 369 DP_INFO(edev, " Chip details : %s %c%d\n", 370 ECORE_IS_BB(edev) ? "BB" : "AH", 371 'A' + edev->chip_rev, 372 (int)edev->chip_metal); 373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 376 ver_str, QEDE_PMD_VERSION); 377 DP_INFO(edev, " Driver version : %s\n", drv_ver); 378 DP_INFO(edev, " Firmware version : %s\n", ver_str); 379 380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 381 "%d.%d.%d.%d", 382 (info->mfw_rev >> 24) & 0xff, 383 (info->mfw_rev >> 16) & 0xff, 384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 386 DP_INFO(edev, " Firmware file : %s\n", fw_file); 387 DP_INFO(edev, "*********************************\n"); 388 } 389 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats) 391 { 392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 393 unsigned int i = 0, j = 0, qid; 394 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 395 struct qede_tx_queue *txq; 396 397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n"); 398 399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 400 RTE_ETHDEV_QUEUE_STAT_CNTRS); 401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 402 RTE_ETHDEV_QUEUE_STAT_CNTRS); 403 404 for_each_rss(qid) { 405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 406 offsetof(struct qede_rx_queue, rcv_pkts), 0, 407 sizeof(uint64_t)); 408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 409 offsetof(struct qede_rx_queue, rx_hw_errors), 0, 410 sizeof(uint64_t)); 411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0, 413 sizeof(uint64_t)); 414 415 if (xstats) 416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++) 417 OSAL_MEMSET((((char *) 418 (qdev->fp_array[qid].rxq)) + 419 qede_rxq_xstats_strings[j].offset), 420 0, 421 sizeof(uint64_t)); 422 423 i++; 424 if (i == rxq_stat_cntrs) 425 break; 426 } 427 428 i = 0; 429 430 for_each_tss(qid) { 431 txq = qdev->fp_array[qid].txq; 432 433 OSAL_MEMSET((uint64_t *)(uintptr_t) 434 (((uint64_t)(uintptr_t)(txq)) + 435 offsetof(struct qede_tx_queue, xmit_pkts)), 0, 436 sizeof(uint64_t)); 437 438 i++; 439 if (i == txq_stat_cntrs) 440 break; 441 } 442 } 443 444 static int 445 qede_stop_vport(struct ecore_dev *edev) 446 { 447 struct ecore_hwfn *p_hwfn; 448 uint8_t vport_id; 449 int rc; 450 int i; 451 452 vport_id = 0; 453 for_each_hwfn(edev, i) { 454 p_hwfn = &edev->hwfns[i]; 455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 456 vport_id); 457 if (rc != ECORE_SUCCESS) { 458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 459 return rc; 460 } 461 } 462 463 DP_INFO(edev, "vport stopped\n"); 464 465 return 0; 466 } 467 468 static int 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 470 { 471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 472 struct ecore_sp_vport_start_params params; 473 struct ecore_hwfn *p_hwfn; 474 int rc; 475 int i; 476 477 if (qdev->vport_started) 478 qede_stop_vport(edev); 479 480 memset(¶ms, 0, sizeof(params)); 481 params.vport_id = 0; 482 params.mtu = mtu; 483 /* @DPDK - Disable FW placement */ 484 params.zero_placement_offset = 1; 485 for_each_hwfn(edev, i) { 486 p_hwfn = &edev->hwfns[i]; 487 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 488 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 489 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 490 if (rc != ECORE_SUCCESS) { 491 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 492 return rc; 493 } 494 } 495 ecore_reset_vport_stats(edev); 496 qdev->vport_started = true; 497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 498 499 return 0; 500 } 501 502 /* Activate or deactivate vport via vport-update */ 503 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 504 { 505 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 506 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 507 struct ecore_sp_vport_update_params params; 508 struct ecore_hwfn *p_hwfn; 509 uint8_t i; 510 int rc = -1; 511 512 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 513 params.vport_id = 0; 514 params.update_vport_active_rx_flg = 1; 515 params.update_vport_active_tx_flg = 1; 516 params.vport_active_rx_flg = flg; 517 params.vport_active_tx_flg = flg; 518 if (!qdev->enable_tx_switching) { 519 if (IS_VF(edev)) { 520 params.update_tx_switching_flg = 1; 521 params.tx_switching_flg = !flg; 522 DP_INFO(edev, "VF tx-switching is disabled\n"); 523 } 524 } 525 for_each_hwfn(edev, i) { 526 p_hwfn = &edev->hwfns[i]; 527 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 528 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 529 ECORE_SPQ_MODE_EBLOCK, NULL); 530 if (rc != ECORE_SUCCESS) { 531 DP_ERR(edev, "Failed to update vport\n"); 532 break; 533 } 534 } 535 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated"); 536 537 return rc; 538 } 539 540 static void 541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 542 uint16_t mtu, bool enable) 543 { 544 /* Enable LRO in split mode */ 545 sge_tpa_params->tpa_ipv4_en_flg = enable; 546 sge_tpa_params->tpa_ipv6_en_flg = enable; 547 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable; 548 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable; 549 /* set if tpa enable changes */ 550 sge_tpa_params->update_tpa_en_flg = 1; 551 /* set if tpa parameters should be handled */ 552 sge_tpa_params->update_tpa_param_flg = enable; 553 554 sge_tpa_params->max_buffers_per_cqe = 20; 555 /* Enable TPA in split mode. In this mode each TPA segment 556 * starts on the new BD, so there is one BD per segment. 557 */ 558 sge_tpa_params->tpa_pkt_split_flg = 1; 559 sge_tpa_params->tpa_hdr_data_split_flg = 0; 560 sge_tpa_params->tpa_gro_consistent_flg = 0; 561 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 562 sge_tpa_params->tpa_max_size = 0x7FFF; 563 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 564 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 565 } 566 567 /* Enable/disable LRO via vport-update */ 568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 569 { 570 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 572 struct ecore_sp_vport_update_params params; 573 struct ecore_sge_tpa_params tpa_params; 574 struct ecore_hwfn *p_hwfn; 575 int rc; 576 int i; 577 578 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 579 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 580 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 581 params.vport_id = 0; 582 params.sge_tpa_params = &tpa_params; 583 for_each_hwfn(edev, i) { 584 p_hwfn = &edev->hwfns[i]; 585 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 586 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 587 ECORE_SPQ_MODE_EBLOCK, NULL); 588 if (rc != ECORE_SUCCESS) { 589 DP_ERR(edev, "Failed to update LRO\n"); 590 return -1; 591 } 592 } 593 qdev->enable_lro = flg; 594 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 595 596 return 0; 597 } 598 599 /* Update MTU via vport-update without doing port restart. 600 * The vport must be deactivated before calling this API. 601 */ 602 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 603 { 604 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 605 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 606 struct ecore_sp_vport_update_params params; 607 struct ecore_hwfn *p_hwfn; 608 int rc; 609 int i; 610 611 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 612 params.vport_id = 0; 613 params.mtu = mtu; 614 params.vport_id = 0; 615 for_each_hwfn(edev, i) { 616 p_hwfn = &edev->hwfns[i]; 617 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 618 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 619 ECORE_SPQ_MODE_EBLOCK, NULL); 620 if (rc != ECORE_SUCCESS) { 621 DP_ERR(edev, "Failed to update MTU\n"); 622 return -1; 623 } 624 } 625 DP_INFO(edev, "MTU updated to %u\n", mtu); 626 627 return 0; 628 } 629 630 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 631 { 632 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 633 ucast->is_rx_filter = true; 634 ucast->is_tx_filter = true; 635 /* ucast->assert_on_error = true; - For debug */ 636 } 637 638 static int 639 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 640 enum qed_filter_rx_mode_type type) 641 { 642 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 643 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 644 struct ecore_filter_accept_flags flags; 645 646 memset(&flags, 0, sizeof(flags)); 647 648 flags.update_rx_mode_config = 1; 649 flags.update_tx_mode_config = 1; 650 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 651 ECORE_ACCEPT_MCAST_MATCHED | 652 ECORE_ACCEPT_BCAST; 653 654 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 655 ECORE_ACCEPT_MCAST_MATCHED | 656 ECORE_ACCEPT_BCAST; 657 658 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 659 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 660 if (IS_VF(edev)) { 661 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 662 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n"); 663 } 664 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 665 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 666 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC | 667 QED_FILTER_RX_MODE_TYPE_PROMISC)) { 668 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED | 669 ECORE_ACCEPT_MCAST_UNMATCHED; 670 } 671 672 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 673 ECORE_SPQ_MODE_CB, NULL); 674 } 675 676 static int 677 qede_tunnel_update(struct qede_dev *qdev, 678 struct ecore_tunnel_info *tunn_info) 679 { 680 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 681 enum _ecore_status_t rc = ECORE_INVAL; 682 struct ecore_hwfn *p_hwfn; 683 struct ecore_ptt *p_ptt; 684 int i; 685 686 for_each_hwfn(edev, i) { 687 p_hwfn = &edev->hwfns[i]; 688 if (IS_PF(edev)) { 689 p_ptt = ecore_ptt_acquire(p_hwfn); 690 if (!p_ptt) { 691 DP_ERR(p_hwfn, "Can't acquire PTT\n"); 692 return -EAGAIN; 693 } 694 } else { 695 p_ptt = NULL; 696 } 697 698 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, 699 tunn_info, ECORE_SPQ_MODE_CB, NULL); 700 if (IS_PF(edev)) 701 ecore_ptt_release(p_hwfn, p_ptt); 702 703 if (rc != ECORE_SUCCESS) 704 break; 705 } 706 707 return rc; 708 } 709 710 static int 711 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 712 bool enable) 713 { 714 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 715 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 716 enum _ecore_status_t rc = ECORE_INVAL; 717 struct ecore_tunnel_info tunn; 718 719 if (qdev->vxlan.enable == enable) 720 return ECORE_SUCCESS; 721 722 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 723 tunn.vxlan.b_update_mode = true; 724 tunn.vxlan.b_mode_enabled = enable; 725 tunn.b_update_rx_cls = true; 726 tunn.b_update_tx_cls = true; 727 tunn.vxlan.tun_cls = clss; 728 729 tunn.vxlan_port.b_update_port = true; 730 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0; 731 732 rc = qede_tunnel_update(qdev, &tunn); 733 if (rc == ECORE_SUCCESS) { 734 qdev->vxlan.enable = enable; 735 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0; 736 DP_INFO(edev, "vxlan is %s, UDP port = %d\n", 737 enable ? "enabled" : "disabled", qdev->vxlan.udp_port); 738 } else { 739 DP_ERR(edev, "Failed to update tunn_clss %u\n", 740 tunn.vxlan.tun_cls); 741 } 742 743 return rc; 744 } 745 746 static int 747 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 748 bool enable) 749 { 750 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 751 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 752 enum _ecore_status_t rc = ECORE_INVAL; 753 struct ecore_tunnel_info tunn; 754 755 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 756 tunn.l2_geneve.b_update_mode = true; 757 tunn.l2_geneve.b_mode_enabled = enable; 758 tunn.ip_geneve.b_update_mode = true; 759 tunn.ip_geneve.b_mode_enabled = enable; 760 tunn.l2_geneve.tun_cls = clss; 761 tunn.ip_geneve.tun_cls = clss; 762 tunn.b_update_rx_cls = true; 763 tunn.b_update_tx_cls = true; 764 765 tunn.geneve_port.b_update_port = true; 766 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0; 767 768 rc = qede_tunnel_update(qdev, &tunn); 769 if (rc == ECORE_SUCCESS) { 770 qdev->geneve.enable = enable; 771 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0; 772 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n", 773 enable ? "enabled" : "disabled", qdev->geneve.udp_port); 774 } else { 775 DP_ERR(edev, "Failed to update tunn_clss %u\n", 776 clss); 777 } 778 779 return rc; 780 } 781 782 static int 783 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 784 enum rte_eth_tunnel_type tunn_type, bool enable) 785 { 786 int rc = -EINVAL; 787 788 switch (tunn_type) { 789 case RTE_TUNNEL_TYPE_VXLAN: 790 rc = qede_vxlan_enable(eth_dev, clss, enable); 791 break; 792 case RTE_TUNNEL_TYPE_GENEVE: 793 rc = qede_geneve_enable(eth_dev, clss, enable); 794 break; 795 default: 796 rc = -EINVAL; 797 break; 798 } 799 800 return rc; 801 } 802 803 static int 804 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 805 bool add) 806 { 807 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 808 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 809 struct qede_ucast_entry *tmp = NULL; 810 struct qede_ucast_entry *u; 811 struct ether_addr *mac_addr; 812 813 mac_addr = (struct ether_addr *)ucast->mac; 814 if (add) { 815 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 816 if ((memcmp(mac_addr, &tmp->mac, 817 ETHER_ADDR_LEN) == 0) && 818 ucast->vni == tmp->vni && 819 ucast->vlan == tmp->vlan) { 820 DP_ERR(edev, "Unicast MAC is already added" 821 " with vlan = %u, vni = %u\n", 822 ucast->vlan, ucast->vni); 823 return -EEXIST; 824 } 825 } 826 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 827 RTE_CACHE_LINE_SIZE); 828 if (!u) { 829 DP_ERR(edev, "Did not allocate memory for ucast\n"); 830 return -ENOMEM; 831 } 832 ether_addr_copy(mac_addr, &u->mac); 833 u->vlan = ucast->vlan; 834 u->vni = ucast->vni; 835 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 836 qdev->num_uc_addr++; 837 } else { 838 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 839 if ((memcmp(mac_addr, &tmp->mac, 840 ETHER_ADDR_LEN) == 0) && 841 ucast->vlan == tmp->vlan && 842 ucast->vni == tmp->vni) 843 break; 844 } 845 if (tmp == NULL) { 846 DP_INFO(edev, "Unicast MAC is not found\n"); 847 return -EINVAL; 848 } 849 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 850 qdev->num_uc_addr--; 851 } 852 853 return 0; 854 } 855 856 static int 857 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast, 858 bool add) 859 { 860 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 861 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 862 struct ether_addr *mac_addr; 863 struct qede_mcast_entry *tmp = NULL; 864 struct qede_mcast_entry *m; 865 866 mac_addr = (struct ether_addr *)mcast->mac; 867 if (add) { 868 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 869 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) { 870 DP_ERR(edev, 871 "Multicast MAC is already added\n"); 872 return -EEXIST; 873 } 874 } 875 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 876 RTE_CACHE_LINE_SIZE); 877 if (!m) { 878 DP_ERR(edev, 879 "Did not allocate memory for mcast\n"); 880 return -ENOMEM; 881 } 882 ether_addr_copy(mac_addr, &m->mac); 883 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 884 qdev->num_mc_addr++; 885 } else { 886 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 887 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) 888 break; 889 } 890 if (tmp == NULL) { 891 DP_INFO(edev, "Multicast mac is not found\n"); 892 return -EINVAL; 893 } 894 SLIST_REMOVE(&qdev->mc_list_head, tmp, 895 qede_mcast_entry, list); 896 qdev->num_mc_addr--; 897 } 898 899 return 0; 900 } 901 902 static enum _ecore_status_t 903 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 904 bool add) 905 { 906 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 907 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 908 enum _ecore_status_t rc; 909 struct ecore_filter_mcast mcast; 910 struct qede_mcast_entry *tmp; 911 uint16_t j = 0; 912 913 /* Multicast */ 914 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) { 915 if (add) { 916 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) { 917 DP_ERR(edev, 918 "Mcast filter table limit exceeded, " 919 "Please enable mcast promisc mode\n"); 920 return -ECORE_INVAL; 921 } 922 } 923 rc = qede_mcast_filter(eth_dev, ucast, add); 924 if (rc == 0) { 925 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr); 926 memset(&mcast, 0, sizeof(mcast)); 927 mcast.num_mc_addrs = qdev->num_mc_addr; 928 mcast.opcode = ECORE_FILTER_ADD; 929 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 930 ether_addr_copy(&tmp->mac, 931 (struct ether_addr *)&mcast.mac[j]); 932 j++; 933 } 934 rc = ecore_filter_mcast_cmd(edev, &mcast, 935 ECORE_SPQ_MODE_CB, NULL); 936 } 937 if (rc != ECORE_SUCCESS) { 938 DP_ERR(edev, "Failed to add multicast filter" 939 " rc = %d, op = %d\n", rc, add); 940 } 941 } else { /* Unicast */ 942 if (add) { 943 if (qdev->num_uc_addr >= 944 qdev->dev_info.num_mac_filters) { 945 DP_ERR(edev, 946 "Ucast filter table limit exceeded," 947 " Please enable promisc mode\n"); 948 return -ECORE_INVAL; 949 } 950 } 951 rc = qede_ucast_filter(eth_dev, ucast, add); 952 if (rc == 0) 953 rc = ecore_filter_ucast_cmd(edev, ucast, 954 ECORE_SPQ_MODE_CB, NULL); 955 if (rc != ECORE_SUCCESS) { 956 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 957 rc, add); 958 } 959 } 960 961 return rc; 962 } 963 964 static int 965 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 966 __rte_unused uint32_t index, __rte_unused uint32_t pool) 967 { 968 struct ecore_filter_ucast ucast; 969 int re; 970 971 qede_set_ucast_cmn_params(&ucast); 972 ucast.type = ECORE_FILTER_MAC; 973 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 974 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 975 return re; 976 } 977 978 static void 979 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 980 { 981 struct qede_dev *qdev = eth_dev->data->dev_private; 982 struct ecore_dev *edev = &qdev->edev; 983 struct ecore_filter_ucast ucast; 984 985 PMD_INIT_FUNC_TRACE(edev); 986 987 if (index >= qdev->dev_info.num_mac_filters) { 988 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 989 index, qdev->dev_info.num_mac_filters); 990 return; 991 } 992 993 qede_set_ucast_cmn_params(&ucast); 994 ucast.opcode = ECORE_FILTER_REMOVE; 995 ucast.type = ECORE_FILTER_MAC; 996 997 /* Use the index maintained by rte */ 998 ether_addr_copy(ð_dev->data->mac_addrs[index], 999 (struct ether_addr *)&ucast.mac); 1000 1001 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 1002 } 1003 1004 static void 1005 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 1006 { 1007 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1008 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1009 1010 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 1011 mac_addr->addr_bytes)) { 1012 DP_ERR(edev, "Setting MAC address is not allowed\n"); 1013 ether_addr_copy(&qdev->primary_mac, 1014 ð_dev->data->mac_addrs[0]); 1015 return; 1016 } 1017 1018 qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 1019 } 1020 1021 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 1022 { 1023 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1024 struct ecore_sp_vport_update_params params; 1025 struct ecore_hwfn *p_hwfn; 1026 uint8_t i; 1027 int rc; 1028 1029 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1030 params.vport_id = 0; 1031 params.update_accept_any_vlan_flg = 1; 1032 params.accept_any_vlan = flg; 1033 for_each_hwfn(edev, i) { 1034 p_hwfn = &edev->hwfns[i]; 1035 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1036 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1037 ECORE_SPQ_MODE_EBLOCK, NULL); 1038 if (rc != ECORE_SUCCESS) { 1039 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 1040 return; 1041 } 1042 } 1043 1044 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 1045 } 1046 1047 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 1048 { 1049 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1050 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1051 struct ecore_sp_vport_update_params params; 1052 struct ecore_hwfn *p_hwfn; 1053 uint8_t i; 1054 int rc; 1055 1056 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1057 params.vport_id = 0; 1058 params.update_inner_vlan_removal_flg = 1; 1059 params.inner_vlan_removal_flg = flg; 1060 for_each_hwfn(edev, i) { 1061 p_hwfn = &edev->hwfns[i]; 1062 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1063 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1064 ECORE_SPQ_MODE_EBLOCK, NULL); 1065 if (rc != ECORE_SUCCESS) { 1066 DP_ERR(edev, "Failed to update vport\n"); 1067 return -1; 1068 } 1069 } 1070 1071 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 1072 return 0; 1073 } 1074 1075 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 1076 uint16_t vlan_id, int on) 1077 { 1078 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1079 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1080 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 1081 struct qede_vlan_entry *tmp = NULL; 1082 struct qede_vlan_entry *vlan; 1083 struct ecore_filter_ucast ucast; 1084 int rc; 1085 1086 if (on) { 1087 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 1088 DP_ERR(edev, "Reached max VLAN filter limit" 1089 " enabling accept_any_vlan\n"); 1090 qede_config_accept_any_vlan(qdev, true); 1091 return 0; 1092 } 1093 1094 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1095 if (tmp->vid == vlan_id) { 1096 DP_ERR(edev, "VLAN %u already configured\n", 1097 vlan_id); 1098 return -EEXIST; 1099 } 1100 } 1101 1102 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 1103 RTE_CACHE_LINE_SIZE); 1104 1105 if (!vlan) { 1106 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 1107 return -ENOMEM; 1108 } 1109 1110 qede_set_ucast_cmn_params(&ucast); 1111 ucast.opcode = ECORE_FILTER_ADD; 1112 ucast.type = ECORE_FILTER_VLAN; 1113 ucast.vlan = vlan_id; 1114 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1115 NULL); 1116 if (rc != 0) { 1117 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 1118 rc); 1119 rte_free(vlan); 1120 } else { 1121 vlan->vid = vlan_id; 1122 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 1123 qdev->configured_vlans++; 1124 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 1125 vlan_id, qdev->configured_vlans); 1126 } 1127 } else { 1128 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1129 if (tmp->vid == vlan_id) 1130 break; 1131 } 1132 1133 if (!tmp) { 1134 if (qdev->configured_vlans == 0) { 1135 DP_INFO(edev, 1136 "No VLAN filters configured yet\n"); 1137 return 0; 1138 } 1139 1140 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 1141 return -EINVAL; 1142 } 1143 1144 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 1145 1146 qede_set_ucast_cmn_params(&ucast); 1147 ucast.opcode = ECORE_FILTER_REMOVE; 1148 ucast.type = ECORE_FILTER_VLAN; 1149 ucast.vlan = vlan_id; 1150 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1151 NULL); 1152 if (rc != 0) { 1153 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 1154 vlan_id, rc); 1155 } else { 1156 qdev->configured_vlans--; 1157 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 1158 vlan_id, qdev->configured_vlans); 1159 } 1160 } 1161 1162 return rc; 1163 } 1164 1165 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 1166 { 1167 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1168 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1169 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1170 1171 if (mask & ETH_VLAN_STRIP_MASK) { 1172 if (rxmode->hw_vlan_strip) 1173 (void)qede_vlan_stripping(eth_dev, 1); 1174 else 1175 (void)qede_vlan_stripping(eth_dev, 0); 1176 } 1177 1178 if (mask & ETH_VLAN_FILTER_MASK) { 1179 /* VLAN filtering kicks in when a VLAN is added */ 1180 if (rxmode->hw_vlan_filter) { 1181 qede_vlan_filter_set(eth_dev, 0, 1); 1182 } else { 1183 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 1184 DP_ERR(edev, 1185 " Please remove existing VLAN filters" 1186 " before disabling VLAN filtering\n"); 1187 /* Signal app that VLAN filtering is still 1188 * enabled 1189 */ 1190 rxmode->hw_vlan_filter = true; 1191 } else { 1192 qede_vlan_filter_set(eth_dev, 0, 0); 1193 } 1194 } 1195 } 1196 1197 if (mask & ETH_VLAN_EXTEND_MASK) 1198 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 1199 " and classification is based on outer tag only\n"); 1200 1201 qdev->vlan_offload_mask = mask; 1202 1203 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 1204 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 1205 1206 return 0; 1207 } 1208 1209 static void qede_prandom_bytes(uint32_t *buff) 1210 { 1211 uint8_t i; 1212 1213 srand((unsigned int)time(NULL)); 1214 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 1215 buff[i] = rand(); 1216 } 1217 1218 int qede_config_rss(struct rte_eth_dev *eth_dev) 1219 { 1220 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1221 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1222 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 1223 struct rte_eth_rss_reta_entry64 reta_conf[2]; 1224 struct rte_eth_rss_conf rss_conf; 1225 uint32_t i, id, pos, q; 1226 1227 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 1228 if (!rss_conf.rss_key) { 1229 DP_INFO(edev, "Applying driver default key\n"); 1230 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1231 qede_prandom_bytes(&def_rss_key[0]); 1232 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 1233 } 1234 1235 /* Configure RSS hash */ 1236 if (qede_rss_hash_update(eth_dev, &rss_conf)) 1237 return -EINVAL; 1238 1239 /* Configure default RETA */ 1240 memset(reta_conf, 0, sizeof(reta_conf)); 1241 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 1242 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 1243 1244 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1245 id = i / RTE_RETA_GROUP_SIZE; 1246 pos = i % RTE_RETA_GROUP_SIZE; 1247 q = i % QEDE_RSS_COUNT(qdev); 1248 reta_conf[id].reta[pos] = q; 1249 } 1250 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1251 ECORE_RSS_IND_TABLE_SIZE)) 1252 return -EINVAL; 1253 1254 return 0; 1255 } 1256 1257 static void qede_fastpath_start(struct ecore_dev *edev) 1258 { 1259 struct ecore_hwfn *p_hwfn; 1260 int i; 1261 1262 for_each_hwfn(edev, i) { 1263 p_hwfn = &edev->hwfns[i]; 1264 ecore_hw_start_fastpath(p_hwfn); 1265 } 1266 } 1267 1268 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1269 { 1270 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1271 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1272 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1273 1274 PMD_INIT_FUNC_TRACE(edev); 1275 1276 /* Configure TPA parameters */ 1277 if (rxmode->enable_lro) { 1278 if (qede_enable_tpa(eth_dev, true)) 1279 return -EINVAL; 1280 /* Enable scatter mode for LRO */ 1281 if (!rxmode->enable_scatter) 1282 eth_dev->data->scattered_rx = 1; 1283 } 1284 1285 /* Start queues */ 1286 if (qede_start_queues(eth_dev)) 1287 goto err; 1288 1289 if (IS_PF(edev)) 1290 qede_reset_queue_stats(qdev, true); 1291 1292 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1293 * enabling RSS. Hence RSS configuration is deferred upto this point. 1294 * Also, we would like to retain similar behavior in PF case, so we 1295 * don't do PF/VF specific check here. 1296 */ 1297 if (rxmode->mq_mode == ETH_MQ_RX_RSS) 1298 if (qede_config_rss(eth_dev)) 1299 goto err; 1300 1301 /* Enable vport*/ 1302 if (qede_activate_vport(eth_dev, true)) 1303 goto err; 1304 1305 /* Update link status */ 1306 qede_link_update(eth_dev, 0); 1307 1308 /* Start/resume traffic */ 1309 qede_fastpath_start(edev); 1310 1311 DP_INFO(edev, "Device started\n"); 1312 1313 return 0; 1314 err: 1315 DP_ERR(edev, "Device start fails\n"); 1316 return -1; /* common error code is < 0 */ 1317 } 1318 1319 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1320 { 1321 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1322 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1323 1324 PMD_INIT_FUNC_TRACE(edev); 1325 1326 /* Disable vport */ 1327 if (qede_activate_vport(eth_dev, false)) 1328 return; 1329 1330 if (qdev->enable_lro) 1331 qede_enable_tpa(eth_dev, false); 1332 1333 /* Stop queues */ 1334 qede_stop_queues(eth_dev); 1335 1336 /* Disable traffic */ 1337 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1338 1339 DP_INFO(edev, "Device is stopped\n"); 1340 } 1341 1342 #define QEDE_TX_SWITCHING "vf_txswitch" 1343 1344 const char *valid_args[] = { 1345 QEDE_TX_SWITCHING, 1346 NULL, 1347 }; 1348 1349 static int qede_args_check(const char *key, const char *val, void *opaque) 1350 { 1351 unsigned long tmp; 1352 int ret = 0; 1353 struct rte_eth_dev *eth_dev = opaque; 1354 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1355 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1356 1357 errno = 0; 1358 tmp = strtoul(val, NULL, 0); 1359 if (errno) { 1360 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val); 1361 return errno; 1362 } 1363 1364 if (strcmp(QEDE_TX_SWITCHING, key) == 0) 1365 qdev->enable_tx_switching = !!tmp; 1366 1367 return ret; 1368 } 1369 1370 static int qede_args(struct rte_eth_dev *eth_dev) 1371 { 1372 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1373 struct rte_kvargs *kvlist; 1374 struct rte_devargs *devargs; 1375 int ret; 1376 int i; 1377 1378 devargs = pci_dev->device.devargs; 1379 if (!devargs) 1380 return 0; /* return success */ 1381 1382 kvlist = rte_kvargs_parse(devargs->args, valid_args); 1383 if (kvlist == NULL) 1384 return -EINVAL; 1385 1386 /* Process parameters. */ 1387 for (i = 0; (valid_args[i] != NULL); ++i) { 1388 if (rte_kvargs_count(kvlist, valid_args[i])) { 1389 ret = rte_kvargs_process(kvlist, valid_args[i], 1390 qede_args_check, eth_dev); 1391 if (ret != ECORE_SUCCESS) { 1392 rte_kvargs_free(kvlist); 1393 return ret; 1394 } 1395 } 1396 } 1397 rte_kvargs_free(kvlist); 1398 1399 return 0; 1400 } 1401 1402 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1403 { 1404 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1405 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1406 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1407 int ret; 1408 1409 PMD_INIT_FUNC_TRACE(edev); 1410 1411 /* Check requirements for 100G mode */ 1412 if (ECORE_IS_CMT(edev)) { 1413 if (eth_dev->data->nb_rx_queues < 2 || 1414 eth_dev->data->nb_tx_queues < 2) { 1415 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 1416 return -EINVAL; 1417 } 1418 1419 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 1420 (eth_dev->data->nb_tx_queues % 2 != 0)) { 1421 DP_ERR(edev, 1422 "100G mode needs even no. of RX/TX queues\n"); 1423 return -EINVAL; 1424 } 1425 } 1426 1427 /* We need to have min 1 RX queue.There is no min check in 1428 * rte_eth_dev_configure(), so we are checking it here. 1429 */ 1430 if (eth_dev->data->nb_rx_queues == 0) { 1431 DP_ERR(edev, "Minimum one RX queue is required\n"); 1432 return -EINVAL; 1433 } 1434 1435 /* Enable Tx switching by default */ 1436 qdev->enable_tx_switching = 1; 1437 1438 /* Parse devargs and fix up rxmode */ 1439 if (qede_args(eth_dev)) 1440 return -ENOTSUP; 1441 1442 /* Sanity checks and throw warnings */ 1443 if (rxmode->enable_scatter) 1444 eth_dev->data->scattered_rx = 1; 1445 1446 if (!rxmode->hw_strip_crc) 1447 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 1448 1449 if (!rxmode->hw_ip_checksum) 1450 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 1451 "in hw\n"); 1452 if (rxmode->header_split) 1453 DP_INFO(edev, "Header split enable is not supported\n"); 1454 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode == 1455 ETH_MQ_RX_RSS)) { 1456 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1457 return -ENOTSUP; 1458 } 1459 /* Flow director mode check */ 1460 if (qede_check_fdir_support(eth_dev)) 1461 return -ENOTSUP; 1462 1463 qede_dealloc_fp_resc(eth_dev); 1464 qdev->num_tx_queues = eth_dev->data->nb_tx_queues; 1465 qdev->num_rx_queues = eth_dev->data->nb_rx_queues; 1466 if (qede_alloc_fp_resc(qdev)) 1467 return -ENOMEM; 1468 1469 /* If jumbo enabled adjust MTU */ 1470 if (eth_dev->data->dev_conf.rxmode.jumbo_frame) 1471 eth_dev->data->mtu = 1472 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1473 ETHER_HDR_LEN - ETHER_CRC_LEN; 1474 1475 if (qede_start_vport(qdev, eth_dev->data->mtu)) 1476 return -1; 1477 qdev->mtu = eth_dev->data->mtu; 1478 1479 /* Enable VLAN offloads by default */ 1480 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1481 ETH_VLAN_FILTER_MASK | 1482 ETH_VLAN_EXTEND_MASK); 1483 if (ret) 1484 return ret; 1485 1486 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1487 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); 1488 1489 return 0; 1490 } 1491 1492 /* Info about HW descriptor ring limitations */ 1493 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1494 .nb_max = 0x8000, /* 32K */ 1495 .nb_min = 128, 1496 .nb_align = 128 /* lowest common multiple */ 1497 }; 1498 1499 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1500 .nb_max = 0x8000, /* 32K */ 1501 .nb_min = 256, 1502 .nb_align = 256, 1503 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1504 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1505 }; 1506 1507 static void 1508 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1509 struct rte_eth_dev_info *dev_info) 1510 { 1511 struct qede_dev *qdev = eth_dev->data->dev_private; 1512 struct ecore_dev *edev = &qdev->edev; 1513 struct qed_link_output link; 1514 uint32_t speed_cap = 0; 1515 1516 PMD_INIT_FUNC_TRACE(edev); 1517 1518 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1519 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1520 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1521 dev_info->rx_desc_lim = qede_rx_desc_lim; 1522 dev_info->tx_desc_lim = qede_tx_desc_lim; 1523 1524 if (IS_PF(edev)) 1525 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1526 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1527 else 1528 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1529 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1530 dev_info->max_tx_queues = dev_info->max_rx_queues; 1531 1532 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1533 dev_info->max_vfs = 0; 1534 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1535 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1536 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1537 1538 dev_info->default_txconf = (struct rte_eth_txconf) { 1539 .txq_flags = QEDE_TXQ_FLAGS, 1540 }; 1541 1542 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 1543 DEV_RX_OFFLOAD_IPV4_CKSUM | 1544 DEV_RX_OFFLOAD_UDP_CKSUM | 1545 DEV_RX_OFFLOAD_TCP_CKSUM | 1546 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1547 DEV_RX_OFFLOAD_TCP_LRO); 1548 1549 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1550 DEV_TX_OFFLOAD_IPV4_CKSUM | 1551 DEV_TX_OFFLOAD_UDP_CKSUM | 1552 DEV_TX_OFFLOAD_TCP_CKSUM | 1553 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1554 DEV_TX_OFFLOAD_TCP_TSO | 1555 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 1556 DEV_TX_OFFLOAD_GENEVE_TNL_TSO); 1557 1558 memset(&link, 0, sizeof(struct qed_link_output)); 1559 qdev->ops->common->get_link(edev, &link); 1560 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1561 speed_cap |= ETH_LINK_SPEED_1G; 1562 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1563 speed_cap |= ETH_LINK_SPEED_10G; 1564 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1565 speed_cap |= ETH_LINK_SPEED_25G; 1566 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1567 speed_cap |= ETH_LINK_SPEED_40G; 1568 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1569 speed_cap |= ETH_LINK_SPEED_50G; 1570 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1571 speed_cap |= ETH_LINK_SPEED_100G; 1572 dev_info->speed_capa = speed_cap; 1573 } 1574 1575 /* return 0 means link status changed, -1 means not changed */ 1576 int 1577 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1578 { 1579 struct qede_dev *qdev = eth_dev->data->dev_private; 1580 struct ecore_dev *edev = &qdev->edev; 1581 uint16_t link_duplex; 1582 struct qed_link_output link; 1583 struct rte_eth_link *curr = ð_dev->data->dev_link; 1584 1585 memset(&link, 0, sizeof(struct qed_link_output)); 1586 qdev->ops->common->get_link(edev, &link); 1587 1588 /* Link Speed */ 1589 curr->link_speed = link.speed; 1590 1591 /* Link Mode */ 1592 switch (link.duplex) { 1593 case QEDE_DUPLEX_HALF: 1594 link_duplex = ETH_LINK_HALF_DUPLEX; 1595 break; 1596 case QEDE_DUPLEX_FULL: 1597 link_duplex = ETH_LINK_FULL_DUPLEX; 1598 break; 1599 case QEDE_DUPLEX_UNKNOWN: 1600 default: 1601 link_duplex = -1; 1602 } 1603 curr->link_duplex = link_duplex; 1604 1605 /* Link Status */ 1606 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 1607 1608 /* AN */ 1609 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1610 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1611 1612 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1613 curr->link_speed, curr->link_duplex, 1614 curr->link_autoneg, curr->link_status); 1615 1616 /* return 0 means link status changed, -1 means not changed */ 1617 return ((curr->link_status == link.link_up) ? -1 : 0); 1618 } 1619 1620 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1621 { 1622 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1623 struct qede_dev *qdev = eth_dev->data->dev_private; 1624 struct ecore_dev *edev = &qdev->edev; 1625 1626 PMD_INIT_FUNC_TRACE(edev); 1627 #endif 1628 1629 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1630 1631 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1632 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1633 1634 qed_configure_filter_rx_mode(eth_dev, type); 1635 } 1636 1637 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1638 { 1639 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1640 struct qede_dev *qdev = eth_dev->data->dev_private; 1641 struct ecore_dev *edev = &qdev->edev; 1642 1643 PMD_INIT_FUNC_TRACE(edev); 1644 #endif 1645 1646 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1647 qed_configure_filter_rx_mode(eth_dev, 1648 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1649 else 1650 qed_configure_filter_rx_mode(eth_dev, 1651 QED_FILTER_RX_MODE_TYPE_REGULAR); 1652 } 1653 1654 static void qede_poll_sp_sb_cb(void *param) 1655 { 1656 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1657 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1658 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1659 int rc; 1660 1661 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1662 qede_interrupt_action(&edev->hwfns[1]); 1663 1664 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1665 qede_poll_sp_sb_cb, 1666 (void *)eth_dev); 1667 if (rc != 0) { 1668 DP_ERR(edev, "Unable to start periodic" 1669 " timer rc %d\n", rc); 1670 assert(false && "Unable to start periodic timer"); 1671 } 1672 } 1673 1674 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1675 { 1676 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1677 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1678 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1679 1680 PMD_INIT_FUNC_TRACE(edev); 1681 1682 /* dev_stop() shall cleanup fp resources in hw but without releasing 1683 * dma memories and sw structures so that dev_start() can be called 1684 * by the app without reconfiguration. However, in dev_close() we 1685 * can release all the resources and device can be brought up newly 1686 */ 1687 if (eth_dev->data->dev_started) 1688 qede_dev_stop(eth_dev); 1689 1690 qede_stop_vport(edev); 1691 qdev->vport_started = false; 1692 qede_fdir_dealloc_resc(eth_dev); 1693 qede_dealloc_fp_resc(eth_dev); 1694 1695 eth_dev->data->nb_rx_queues = 0; 1696 eth_dev->data->nb_tx_queues = 0; 1697 1698 /* Bring the link down */ 1699 qede_dev_set_link_state(eth_dev, false); 1700 qdev->ops->common->slowpath_stop(edev); 1701 qdev->ops->common->remove(edev); 1702 rte_intr_disable(&pci_dev->intr_handle); 1703 rte_intr_callback_unregister(&pci_dev->intr_handle, 1704 qede_interrupt_handler, (void *)eth_dev); 1705 if (ECORE_IS_CMT(edev)) 1706 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1707 } 1708 1709 static int 1710 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1711 { 1712 struct qede_dev *qdev = eth_dev->data->dev_private; 1713 struct ecore_dev *edev = &qdev->edev; 1714 struct ecore_eth_stats stats; 1715 unsigned int i = 0, j = 0, qid; 1716 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1717 struct qede_tx_queue *txq; 1718 1719 ecore_get_vport_stats(edev, &stats); 1720 1721 /* RX Stats */ 1722 eth_stats->ipackets = stats.common.rx_ucast_pkts + 1723 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts; 1724 1725 eth_stats->ibytes = stats.common.rx_ucast_bytes + 1726 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes; 1727 1728 eth_stats->ierrors = stats.common.rx_crc_errors + 1729 stats.common.rx_align_errors + 1730 stats.common.rx_carrier_errors + 1731 stats.common.rx_oversize_packets + 1732 stats.common.rx_jabbers + stats.common.rx_undersize_packets; 1733 1734 eth_stats->rx_nombuf = stats.common.no_buff_discards; 1735 1736 eth_stats->imissed = stats.common.mftag_filter_discards + 1737 stats.common.mac_filter_discards + 1738 stats.common.no_buff_discards + 1739 stats.common.brb_truncates + stats.common.brb_discards; 1740 1741 /* TX stats */ 1742 eth_stats->opackets = stats.common.tx_ucast_pkts + 1743 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts; 1744 1745 eth_stats->obytes = stats.common.tx_ucast_bytes + 1746 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes; 1747 1748 eth_stats->oerrors = stats.common.tx_err_drop_pkts; 1749 1750 /* Queue stats */ 1751 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1752 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1753 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1754 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1755 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) || 1756 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev))) 1757 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1758 "Not all the queue stats will be displayed. Set" 1759 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1760 " appropriately and retry.\n"); 1761 1762 for_each_rss(qid) { 1763 eth_stats->q_ipackets[i] = 1764 *(uint64_t *)( 1765 ((char *)(qdev->fp_array[qid].rxq)) + 1766 offsetof(struct qede_rx_queue, 1767 rcv_pkts)); 1768 eth_stats->q_errors[i] = 1769 *(uint64_t *)( 1770 ((char *)(qdev->fp_array[qid].rxq)) + 1771 offsetof(struct qede_rx_queue, 1772 rx_hw_errors)) + 1773 *(uint64_t *)( 1774 ((char *)(qdev->fp_array[qid].rxq)) + 1775 offsetof(struct qede_rx_queue, 1776 rx_alloc_errors)); 1777 i++; 1778 if (i == rxq_stat_cntrs) 1779 break; 1780 } 1781 1782 for_each_tss(qid) { 1783 txq = qdev->fp_array[qid].txq; 1784 eth_stats->q_opackets[j] = 1785 *((uint64_t *)(uintptr_t) 1786 (((uint64_t)(uintptr_t)(txq)) + 1787 offsetof(struct qede_tx_queue, 1788 xmit_pkts))); 1789 j++; 1790 if (j == txq_stat_cntrs) 1791 break; 1792 } 1793 1794 return 0; 1795 } 1796 1797 static unsigned 1798 qede_get_xstats_count(struct qede_dev *qdev) { 1799 if (ECORE_IS_BB(&qdev->edev)) 1800 return RTE_DIM(qede_xstats_strings) + 1801 RTE_DIM(qede_bb_xstats_strings) + 1802 (RTE_DIM(qede_rxq_xstats_strings) * 1803 RTE_MIN(QEDE_RSS_COUNT(qdev), 1804 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1805 else 1806 return RTE_DIM(qede_xstats_strings) + 1807 RTE_DIM(qede_ah_xstats_strings) + 1808 (RTE_DIM(qede_rxq_xstats_strings) * 1809 RTE_MIN(QEDE_RSS_COUNT(qdev), 1810 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1811 } 1812 1813 static int 1814 qede_get_xstats_names(struct rte_eth_dev *dev, 1815 struct rte_eth_xstat_name *xstats_names, 1816 __rte_unused unsigned int limit) 1817 { 1818 struct qede_dev *qdev = dev->data->dev_private; 1819 struct ecore_dev *edev = &qdev->edev; 1820 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1821 unsigned int i, qid, stat_idx = 0; 1822 unsigned int rxq_stat_cntrs; 1823 1824 if (xstats_names != NULL) { 1825 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1826 snprintf(xstats_names[stat_idx].name, 1827 sizeof(xstats_names[stat_idx].name), 1828 "%s", 1829 qede_xstats_strings[i].name); 1830 stat_idx++; 1831 } 1832 1833 if (ECORE_IS_BB(edev)) { 1834 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1835 snprintf(xstats_names[stat_idx].name, 1836 sizeof(xstats_names[stat_idx].name), 1837 "%s", 1838 qede_bb_xstats_strings[i].name); 1839 stat_idx++; 1840 } 1841 } else { 1842 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1843 snprintf(xstats_names[stat_idx].name, 1844 sizeof(xstats_names[stat_idx].name), 1845 "%s", 1846 qede_ah_xstats_strings[i].name); 1847 stat_idx++; 1848 } 1849 } 1850 1851 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1852 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1853 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1854 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1855 snprintf(xstats_names[stat_idx].name, 1856 sizeof(xstats_names[stat_idx].name), 1857 "%.4s%d%s", 1858 qede_rxq_xstats_strings[i].name, qid, 1859 qede_rxq_xstats_strings[i].name + 4); 1860 stat_idx++; 1861 } 1862 } 1863 } 1864 1865 return stat_cnt; 1866 } 1867 1868 static int 1869 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1870 unsigned int n) 1871 { 1872 struct qede_dev *qdev = dev->data->dev_private; 1873 struct ecore_dev *edev = &qdev->edev; 1874 struct ecore_eth_stats stats; 1875 const unsigned int num = qede_get_xstats_count(qdev); 1876 unsigned int i, qid, stat_idx = 0; 1877 unsigned int rxq_stat_cntrs; 1878 1879 if (n < num) 1880 return num; 1881 1882 ecore_get_vport_stats(edev, &stats); 1883 1884 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1885 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1886 qede_xstats_strings[i].offset); 1887 xstats[stat_idx].id = stat_idx; 1888 stat_idx++; 1889 } 1890 1891 if (ECORE_IS_BB(edev)) { 1892 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1893 xstats[stat_idx].value = 1894 *(uint64_t *)(((char *)&stats) + 1895 qede_bb_xstats_strings[i].offset); 1896 xstats[stat_idx].id = stat_idx; 1897 stat_idx++; 1898 } 1899 } else { 1900 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1901 xstats[stat_idx].value = 1902 *(uint64_t *)(((char *)&stats) + 1903 qede_ah_xstats_strings[i].offset); 1904 xstats[stat_idx].id = stat_idx; 1905 stat_idx++; 1906 } 1907 } 1908 1909 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1910 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1911 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1912 for_each_rss(qid) { 1913 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1914 xstats[stat_idx].value = *(uint64_t *)( 1915 ((char *)(qdev->fp_array[qid].rxq)) + 1916 qede_rxq_xstats_strings[i].offset); 1917 xstats[stat_idx].id = stat_idx; 1918 stat_idx++; 1919 } 1920 } 1921 } 1922 1923 return stat_idx; 1924 } 1925 1926 static void 1927 qede_reset_xstats(struct rte_eth_dev *dev) 1928 { 1929 struct qede_dev *qdev = dev->data->dev_private; 1930 struct ecore_dev *edev = &qdev->edev; 1931 1932 ecore_reset_vport_stats(edev); 1933 qede_reset_queue_stats(qdev, true); 1934 } 1935 1936 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1937 { 1938 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1939 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1940 struct qed_link_params link_params; 1941 int rc; 1942 1943 DP_INFO(edev, "setting link state %d\n", link_up); 1944 memset(&link_params, 0, sizeof(link_params)); 1945 link_params.link_up = link_up; 1946 rc = qdev->ops->common->set_link(edev, &link_params); 1947 if (rc != ECORE_SUCCESS) 1948 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1949 1950 return rc; 1951 } 1952 1953 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1954 { 1955 return qede_dev_set_link_state(eth_dev, true); 1956 } 1957 1958 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1959 { 1960 return qede_dev_set_link_state(eth_dev, false); 1961 } 1962 1963 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1964 { 1965 struct qede_dev *qdev = eth_dev->data->dev_private; 1966 struct ecore_dev *edev = &qdev->edev; 1967 1968 ecore_reset_vport_stats(edev); 1969 qede_reset_queue_stats(qdev, false); 1970 } 1971 1972 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1973 { 1974 enum qed_filter_rx_mode_type type = 1975 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1976 1977 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1978 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1979 1980 qed_configure_filter_rx_mode(eth_dev, type); 1981 } 1982 1983 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1984 { 1985 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1986 qed_configure_filter_rx_mode(eth_dev, 1987 QED_FILTER_RX_MODE_TYPE_PROMISC); 1988 else 1989 qed_configure_filter_rx_mode(eth_dev, 1990 QED_FILTER_RX_MODE_TYPE_REGULAR); 1991 } 1992 1993 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1994 struct rte_eth_fc_conf *fc_conf) 1995 { 1996 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1997 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1998 struct qed_link_output current_link; 1999 struct qed_link_params params; 2000 2001 memset(¤t_link, 0, sizeof(current_link)); 2002 qdev->ops->common->get_link(edev, ¤t_link); 2003 2004 memset(¶ms, 0, sizeof(params)); 2005 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 2006 if (fc_conf->autoneg) { 2007 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 2008 DP_ERR(edev, "Autoneg not supported\n"); 2009 return -EINVAL; 2010 } 2011 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 2012 } 2013 2014 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 2015 if (fc_conf->mode == RTE_FC_FULL) 2016 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 2017 QED_LINK_PAUSE_RX_ENABLE); 2018 if (fc_conf->mode == RTE_FC_TX_PAUSE) 2019 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 2020 if (fc_conf->mode == RTE_FC_RX_PAUSE) 2021 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 2022 2023 params.link_up = true; 2024 (void)qdev->ops->common->set_link(edev, ¶ms); 2025 2026 return 0; 2027 } 2028 2029 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 2030 struct rte_eth_fc_conf *fc_conf) 2031 { 2032 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2033 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2034 struct qed_link_output current_link; 2035 2036 memset(¤t_link, 0, sizeof(current_link)); 2037 qdev->ops->common->get_link(edev, ¤t_link); 2038 2039 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 2040 fc_conf->autoneg = true; 2041 2042 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 2043 QED_LINK_PAUSE_TX_ENABLE)) 2044 fc_conf->mode = RTE_FC_FULL; 2045 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 2046 fc_conf->mode = RTE_FC_RX_PAUSE; 2047 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 2048 fc_conf->mode = RTE_FC_TX_PAUSE; 2049 else 2050 fc_conf->mode = RTE_FC_NONE; 2051 2052 return 0; 2053 } 2054 2055 static const uint32_t * 2056 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 2057 { 2058 static const uint32_t ptypes[] = { 2059 RTE_PTYPE_L2_ETHER, 2060 RTE_PTYPE_L2_ETHER_VLAN, 2061 RTE_PTYPE_L3_IPV4, 2062 RTE_PTYPE_L3_IPV6, 2063 RTE_PTYPE_L4_TCP, 2064 RTE_PTYPE_L4_UDP, 2065 RTE_PTYPE_TUNNEL_VXLAN, 2066 RTE_PTYPE_L4_FRAG, 2067 RTE_PTYPE_TUNNEL_GENEVE, 2068 /* Inner */ 2069 RTE_PTYPE_INNER_L2_ETHER, 2070 RTE_PTYPE_INNER_L2_ETHER_VLAN, 2071 RTE_PTYPE_INNER_L3_IPV4, 2072 RTE_PTYPE_INNER_L3_IPV6, 2073 RTE_PTYPE_INNER_L4_TCP, 2074 RTE_PTYPE_INNER_L4_UDP, 2075 RTE_PTYPE_INNER_L4_FRAG, 2076 RTE_PTYPE_UNKNOWN 2077 }; 2078 2079 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 2080 return ptypes; 2081 2082 return NULL; 2083 } 2084 2085 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 2086 { 2087 *rss_caps = 0; 2088 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 2089 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 2090 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 2091 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 2092 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 2093 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 2094 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 2095 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 2096 } 2097 2098 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 2099 struct rte_eth_rss_conf *rss_conf) 2100 { 2101 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2102 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2103 struct ecore_sp_vport_update_params vport_update_params; 2104 struct ecore_rss_params rss_params; 2105 struct ecore_hwfn *p_hwfn; 2106 uint32_t *key = (uint32_t *)rss_conf->rss_key; 2107 uint64_t hf = rss_conf->rss_hf; 2108 uint8_t len = rss_conf->rss_key_len; 2109 uint8_t idx; 2110 uint8_t i; 2111 int rc; 2112 2113 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2114 memset(&rss_params, 0, sizeof(rss_params)); 2115 2116 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 2117 (unsigned long)hf, len, key); 2118 2119 if (hf != 0) { 2120 /* Enabling RSS */ 2121 DP_INFO(edev, "Enabling rss\n"); 2122 2123 /* RSS caps */ 2124 qede_init_rss_caps(&rss_params.rss_caps, hf); 2125 rss_params.update_rss_capabilities = 1; 2126 2127 /* RSS hash key */ 2128 if (key) { 2129 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 2130 DP_ERR(edev, "RSS key length exceeds limit\n"); 2131 return -EINVAL; 2132 } 2133 DP_INFO(edev, "Applying user supplied hash key\n"); 2134 rss_params.update_rss_key = 1; 2135 memcpy(&rss_params.rss_key, key, len); 2136 } 2137 rss_params.rss_enable = 1; 2138 } 2139 2140 rss_params.update_rss_config = 1; 2141 /* tbl_size has to be set with capabilities */ 2142 rss_params.rss_table_size_log = 7; 2143 vport_update_params.vport_id = 0; 2144 /* pass the L2 handles instead of qids */ 2145 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 2146 idx = qdev->rss_ind_table[i]; 2147 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 2148 } 2149 vport_update_params.rss_params = &rss_params; 2150 2151 for_each_hwfn(edev, i) { 2152 p_hwfn = &edev->hwfns[i]; 2153 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2154 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2155 ECORE_SPQ_MODE_EBLOCK, NULL); 2156 if (rc) { 2157 DP_ERR(edev, "vport-update for RSS failed\n"); 2158 return rc; 2159 } 2160 } 2161 qdev->rss_enable = rss_params.rss_enable; 2162 2163 /* Update local structure for hash query */ 2164 qdev->rss_conf.rss_hf = hf; 2165 qdev->rss_conf.rss_key_len = len; 2166 if (qdev->rss_enable) { 2167 if (qdev->rss_conf.rss_key == NULL) { 2168 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 2169 if (qdev->rss_conf.rss_key == NULL) { 2170 DP_ERR(edev, "No memory to store RSS key\n"); 2171 return -ENOMEM; 2172 } 2173 } 2174 if (key && len) { 2175 DP_INFO(edev, "Storing RSS key\n"); 2176 memcpy(qdev->rss_conf.rss_key, key, len); 2177 } 2178 } else if (!qdev->rss_enable && len == 0) { 2179 if (qdev->rss_conf.rss_key) { 2180 free(qdev->rss_conf.rss_key); 2181 qdev->rss_conf.rss_key = NULL; 2182 DP_INFO(edev, "Free RSS key\n"); 2183 } 2184 } 2185 2186 return 0; 2187 } 2188 2189 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 2190 struct rte_eth_rss_conf *rss_conf) 2191 { 2192 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2193 2194 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 2195 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 2196 2197 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 2198 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 2199 rss_conf->rss_key_len); 2200 return 0; 2201 } 2202 2203 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev, 2204 struct ecore_rss_params *rss) 2205 { 2206 int i, fn; 2207 bool rss_mode = 1; /* enable */ 2208 struct ecore_queue_cid *cid; 2209 struct ecore_rss_params *t_rss; 2210 2211 /* In regular scenario, we'd simply need to take input handlers. 2212 * But in CMT, we'd have to split the handlers according to the 2213 * engine they were configured on. We'd then have to understand 2214 * whether RSS is really required, since 2-queues on CMT doesn't 2215 * require RSS. 2216 */ 2217 2218 /* CMT should be round-robin */ 2219 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 2220 cid = rss->rss_ind_table[i]; 2221 2222 if (cid->p_owner == ECORE_LEADING_HWFN(edev)) 2223 t_rss = &rss[0]; 2224 else 2225 t_rss = &rss[1]; 2226 2227 t_rss->rss_ind_table[i / edev->num_hwfns] = cid; 2228 } 2229 2230 t_rss = &rss[1]; 2231 t_rss->update_rss_ind_table = 1; 2232 t_rss->rss_table_size_log = 7; 2233 t_rss->update_rss_config = 1; 2234 2235 /* Make sure RSS is actually required */ 2236 for_each_hwfn(edev, fn) { 2237 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns; 2238 i++) { 2239 if (rss[fn].rss_ind_table[i] != 2240 rss[fn].rss_ind_table[0]) 2241 break; 2242 } 2243 2244 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) { 2245 DP_INFO(edev, 2246 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2247 rss_mode = 0; 2248 goto out; 2249 } 2250 } 2251 2252 out: 2253 t_rss->rss_enable = rss_mode; 2254 2255 return rss_mode; 2256 } 2257 2258 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 2259 struct rte_eth_rss_reta_entry64 *reta_conf, 2260 uint16_t reta_size) 2261 { 2262 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2263 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2264 struct ecore_sp_vport_update_params vport_update_params; 2265 struct ecore_rss_params *params; 2266 struct ecore_hwfn *p_hwfn; 2267 uint16_t i, idx, shift; 2268 uint8_t entry; 2269 int rc = 0; 2270 2271 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2272 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 2273 reta_size); 2274 return -EINVAL; 2275 } 2276 2277 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2278 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns, 2279 RTE_CACHE_LINE_SIZE); 2280 if (params == NULL) { 2281 DP_ERR(edev, "failed to allocate memory\n"); 2282 return -ENOMEM; 2283 } 2284 2285 for (i = 0; i < reta_size; i++) { 2286 idx = i / RTE_RETA_GROUP_SIZE; 2287 shift = i % RTE_RETA_GROUP_SIZE; 2288 if (reta_conf[idx].mask & (1ULL << shift)) { 2289 entry = reta_conf[idx].reta[shift]; 2290 /* Pass rxq handles to ecore */ 2291 params->rss_ind_table[i] = 2292 qdev->fp_array[entry].rxq->handle; 2293 /* Update the local copy for RETA query command */ 2294 qdev->rss_ind_table[i] = entry; 2295 } 2296 } 2297 2298 params->update_rss_ind_table = 1; 2299 params->rss_table_size_log = 7; 2300 params->update_rss_config = 1; 2301 2302 /* Fix up RETA for CMT mode device */ 2303 if (ECORE_IS_CMT(edev)) 2304 qdev->rss_enable = qede_update_rss_parm_cmt(edev, 2305 params); 2306 vport_update_params.vport_id = 0; 2307 /* Use the current value of rss_enable */ 2308 params->rss_enable = qdev->rss_enable; 2309 vport_update_params.rss_params = params; 2310 2311 for_each_hwfn(edev, i) { 2312 p_hwfn = &edev->hwfns[i]; 2313 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2314 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2315 ECORE_SPQ_MODE_EBLOCK, NULL); 2316 if (rc) { 2317 DP_ERR(edev, "vport-update for RSS failed\n"); 2318 goto out; 2319 } 2320 } 2321 2322 out: 2323 rte_free(params); 2324 return rc; 2325 } 2326 2327 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 2328 struct rte_eth_rss_reta_entry64 *reta_conf, 2329 uint16_t reta_size) 2330 { 2331 struct qede_dev *qdev = eth_dev->data->dev_private; 2332 struct ecore_dev *edev = &qdev->edev; 2333 uint16_t i, idx, shift; 2334 uint8_t entry; 2335 2336 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2337 DP_ERR(edev, "reta_size %d is not supported\n", 2338 reta_size); 2339 return -EINVAL; 2340 } 2341 2342 for (i = 0; i < reta_size; i++) { 2343 idx = i / RTE_RETA_GROUP_SIZE; 2344 shift = i % RTE_RETA_GROUP_SIZE; 2345 if (reta_conf[idx].mask & (1ULL << shift)) { 2346 entry = qdev->rss_ind_table[i]; 2347 reta_conf[idx].reta[shift] = entry; 2348 } 2349 } 2350 2351 return 0; 2352 } 2353 2354 2355 2356 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 2357 { 2358 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 2359 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2360 struct rte_eth_dev_info dev_info = {0}; 2361 struct qede_fastpath *fp; 2362 uint32_t max_rx_pkt_len; 2363 uint32_t frame_size; 2364 uint16_t rx_buf_size; 2365 uint16_t bufsz; 2366 bool restart = false; 2367 int i; 2368 2369 PMD_INIT_FUNC_TRACE(edev); 2370 qede_dev_info_get(dev, &dev_info); 2371 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2372 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD; 2373 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { 2374 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n", 2375 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN - 2376 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD); 2377 return -EINVAL; 2378 } 2379 if (!dev->data->scattered_rx && 2380 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2381 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2382 dev->data->min_rx_buf_size); 2383 return -EINVAL; 2384 } 2385 /* Temporarily replace I/O functions with dummy ones. It cannot 2386 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 2387 */ 2388 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 2389 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 2390 if (dev->data->dev_started) { 2391 dev->data->dev_started = 0; 2392 qede_dev_stop(dev); 2393 restart = true; 2394 } 2395 rte_delay_ms(1000); 2396 qede_start_vport(qdev, mtu); /* Recreate vport */ 2397 qdev->mtu = mtu; 2398 2399 /* Fix up RX buf size for all queues of the port */ 2400 for_each_rss(i) { 2401 fp = &qdev->fp_array[i]; 2402 if (fp->rxq != NULL) { 2403 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2404 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2405 if (dev->data->scattered_rx) 2406 rx_buf_size = bufsz + ETHER_HDR_LEN + 2407 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD; 2408 else 2409 rx_buf_size = frame_size; 2410 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); 2411 fp->rxq->rx_buf_size = rx_buf_size; 2412 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size); 2413 } 2414 } 2415 if (max_rx_pkt_len > ETHER_MAX_LEN) 2416 dev->data->dev_conf.rxmode.jumbo_frame = 1; 2417 else 2418 dev->data->dev_conf.rxmode.jumbo_frame = 0; 2419 2420 /* Restore config lost due to vport stop */ 2421 qede_mac_addr_set(dev, &qdev->primary_mac); 2422 if (dev->data->promiscuous) 2423 qede_promiscuous_enable(dev); 2424 else 2425 qede_promiscuous_disable(dev); 2426 2427 if (dev->data->all_multicast) 2428 qede_allmulticast_enable(dev); 2429 else 2430 qede_allmulticast_disable(dev); 2431 2432 qede_vlan_offload_set(dev, qdev->vlan_offload_mask); 2433 2434 if (!dev->data->dev_started && restart) { 2435 qede_dev_start(dev); 2436 dev->data->dev_started = 1; 2437 } 2438 2439 /* update max frame size */ 2440 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len; 2441 /* Reassign back */ 2442 dev->rx_pkt_burst = qede_recv_pkts; 2443 dev->tx_pkt_burst = qede_xmit_pkts; 2444 2445 return 0; 2446 } 2447 2448 static int 2449 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 2450 struct rte_eth_udp_tunnel *tunnel_udp) 2451 { 2452 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2453 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2454 struct ecore_tunnel_info tunn; /* @DPDK */ 2455 uint16_t udp_port; 2456 int rc; 2457 2458 PMD_INIT_FUNC_TRACE(edev); 2459 2460 memset(&tunn, 0, sizeof(tunn)); 2461 2462 switch (tunnel_udp->prot_type) { 2463 case RTE_TUNNEL_TYPE_VXLAN: 2464 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) { 2465 DP_ERR(edev, "UDP port %u doesn't exist\n", 2466 tunnel_udp->udp_port); 2467 return ECORE_INVAL; 2468 } 2469 udp_port = 0; 2470 2471 tunn.vxlan_port.b_update_port = true; 2472 tunn.vxlan_port.port = udp_port; 2473 2474 rc = qede_tunnel_update(qdev, &tunn); 2475 if (rc != ECORE_SUCCESS) { 2476 DP_ERR(edev, "Unable to config UDP port %u\n", 2477 tunn.vxlan_port.port); 2478 return rc; 2479 } 2480 2481 qdev->vxlan.udp_port = udp_port; 2482 /* If the request is to delete UDP port and if the number of 2483 * VXLAN filters have reached 0 then VxLAN offload can be be 2484 * disabled. 2485 */ 2486 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0) 2487 return qede_vxlan_enable(eth_dev, 2488 ECORE_TUNN_CLSS_MAC_VLAN, false); 2489 2490 break; 2491 2492 case RTE_TUNNEL_TYPE_GENEVE: 2493 if (qdev->geneve.udp_port != tunnel_udp->udp_port) { 2494 DP_ERR(edev, "UDP port %u doesn't exist\n", 2495 tunnel_udp->udp_port); 2496 return ECORE_INVAL; 2497 } 2498 2499 udp_port = 0; 2500 2501 tunn.geneve_port.b_update_port = true; 2502 tunn.geneve_port.port = udp_port; 2503 2504 rc = qede_tunnel_update(qdev, &tunn); 2505 if (rc != ECORE_SUCCESS) { 2506 DP_ERR(edev, "Unable to config UDP port %u\n", 2507 tunn.vxlan_port.port); 2508 return rc; 2509 } 2510 2511 qdev->vxlan.udp_port = udp_port; 2512 /* If the request is to delete UDP port and if the number of 2513 * GENEVE filters have reached 0 then GENEVE offload can be be 2514 * disabled. 2515 */ 2516 if (qdev->geneve.enable && qdev->geneve.num_filters == 0) 2517 return qede_geneve_enable(eth_dev, 2518 ECORE_TUNN_CLSS_MAC_VLAN, false); 2519 2520 break; 2521 2522 default: 2523 return ECORE_INVAL; 2524 } 2525 2526 return 0; 2527 2528 } 2529 static int 2530 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 2531 struct rte_eth_udp_tunnel *tunnel_udp) 2532 { 2533 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2534 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2535 struct ecore_tunnel_info tunn; /* @DPDK */ 2536 uint16_t udp_port; 2537 int rc; 2538 2539 PMD_INIT_FUNC_TRACE(edev); 2540 2541 memset(&tunn, 0, sizeof(tunn)); 2542 2543 switch (tunnel_udp->prot_type) { 2544 case RTE_TUNNEL_TYPE_VXLAN: 2545 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) { 2546 DP_INFO(edev, 2547 "UDP port %u for VXLAN was already configured\n", 2548 tunnel_udp->udp_port); 2549 return ECORE_SUCCESS; 2550 } 2551 2552 /* Enable VxLAN tunnel with default MAC/VLAN classification if 2553 * it was not enabled while adding VXLAN filter before UDP port 2554 * update. 2555 */ 2556 if (!qdev->vxlan.enable) { 2557 rc = qede_vxlan_enable(eth_dev, 2558 ECORE_TUNN_CLSS_MAC_VLAN, true); 2559 if (rc != ECORE_SUCCESS) { 2560 DP_ERR(edev, "Failed to enable VXLAN " 2561 "prior to updating UDP port\n"); 2562 return rc; 2563 } 2564 } 2565 udp_port = tunnel_udp->udp_port; 2566 2567 tunn.vxlan_port.b_update_port = true; 2568 tunn.vxlan_port.port = udp_port; 2569 2570 rc = qede_tunnel_update(qdev, &tunn); 2571 if (rc != ECORE_SUCCESS) { 2572 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n", 2573 udp_port); 2574 return rc; 2575 } 2576 2577 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port); 2578 2579 qdev->vxlan.udp_port = udp_port; 2580 break; 2581 2582 case RTE_TUNNEL_TYPE_GENEVE: 2583 if (qdev->geneve.udp_port == tunnel_udp->udp_port) { 2584 DP_INFO(edev, 2585 "UDP port %u for GENEVE was already configured\n", 2586 tunnel_udp->udp_port); 2587 return ECORE_SUCCESS; 2588 } 2589 2590 /* Enable GENEVE tunnel with default MAC/VLAN classification if 2591 * it was not enabled while adding GENEVE filter before UDP port 2592 * update. 2593 */ 2594 if (!qdev->geneve.enable) { 2595 rc = qede_geneve_enable(eth_dev, 2596 ECORE_TUNN_CLSS_MAC_VLAN, true); 2597 if (rc != ECORE_SUCCESS) { 2598 DP_ERR(edev, "Failed to enable GENEVE " 2599 "prior to updating UDP port\n"); 2600 return rc; 2601 } 2602 } 2603 udp_port = tunnel_udp->udp_port; 2604 2605 tunn.geneve_port.b_update_port = true; 2606 tunn.geneve_port.port = udp_port; 2607 2608 rc = qede_tunnel_update(qdev, &tunn); 2609 if (rc != ECORE_SUCCESS) { 2610 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n", 2611 udp_port); 2612 return rc; 2613 } 2614 2615 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port); 2616 2617 qdev->geneve.udp_port = udp_port; 2618 break; 2619 2620 default: 2621 return ECORE_INVAL; 2622 } 2623 2624 return 0; 2625 } 2626 2627 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 2628 uint32_t *clss, char *str) 2629 { 2630 uint16_t j; 2631 *clss = MAX_ECORE_TUNN_CLSS; 2632 2633 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 2634 if (filter == qede_tunn_types[j].rte_filter_type) { 2635 *type = qede_tunn_types[j].qede_type; 2636 *clss = qede_tunn_types[j].qede_tunn_clss; 2637 strcpy(str, qede_tunn_types[j].string); 2638 return; 2639 } 2640 } 2641 } 2642 2643 static int 2644 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 2645 const struct rte_eth_tunnel_filter_conf *conf, 2646 uint32_t type) 2647 { 2648 /* Init commmon ucast params first */ 2649 qede_set_ucast_cmn_params(ucast); 2650 2651 /* Copy out the required fields based on classification type */ 2652 ucast->type = type; 2653 2654 switch (type) { 2655 case ECORE_FILTER_VNI: 2656 ucast->vni = conf->tenant_id; 2657 break; 2658 case ECORE_FILTER_INNER_VLAN: 2659 ucast->vlan = conf->inner_vlan; 2660 break; 2661 case ECORE_FILTER_MAC: 2662 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2663 ETHER_ADDR_LEN); 2664 break; 2665 case ECORE_FILTER_INNER_MAC: 2666 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2667 ETHER_ADDR_LEN); 2668 break; 2669 case ECORE_FILTER_MAC_VNI_PAIR: 2670 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2671 ETHER_ADDR_LEN); 2672 ucast->vni = conf->tenant_id; 2673 break; 2674 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 2675 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2676 ETHER_ADDR_LEN); 2677 ucast->vni = conf->tenant_id; 2678 break; 2679 case ECORE_FILTER_INNER_PAIR: 2680 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2681 ETHER_ADDR_LEN); 2682 ucast->vlan = conf->inner_vlan; 2683 break; 2684 default: 2685 return -EINVAL; 2686 } 2687 2688 return ECORE_SUCCESS; 2689 } 2690 2691 static int 2692 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2693 const struct rte_eth_tunnel_filter_conf *conf, 2694 __attribute__((unused)) enum rte_filter_op filter_op, 2695 enum ecore_tunn_clss *clss, 2696 bool add) 2697 { 2698 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2699 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2700 struct ecore_filter_ucast ucast = {0}; 2701 enum ecore_filter_ucast_type type; 2702 uint16_t filter_type = 0; 2703 char str[80]; 2704 int rc; 2705 2706 filter_type = conf->filter_type; 2707 /* Determine if the given filter classification is supported */ 2708 qede_get_ecore_tunn_params(filter_type, &type, clss, str); 2709 if (*clss == MAX_ECORE_TUNN_CLSS) { 2710 DP_ERR(edev, "Unsupported filter type\n"); 2711 return -EINVAL; 2712 } 2713 /* Init tunnel ucast params */ 2714 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2715 if (rc != ECORE_SUCCESS) { 2716 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n", 2717 conf->filter_type); 2718 return rc; 2719 } 2720 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2721 str, filter_op, ucast.type); 2722 2723 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE; 2724 2725 /* Skip MAC/VLAN if filter is based on VNI */ 2726 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2727 rc = qede_mac_int_ops(eth_dev, &ucast, add); 2728 if ((rc == 0) && add) { 2729 /* Enable accept anyvlan */ 2730 qede_config_accept_any_vlan(qdev, true); 2731 } 2732 } else { 2733 rc = qede_ucast_filter(eth_dev, &ucast, add); 2734 if (rc == 0) 2735 rc = ecore_filter_ucast_cmd(edev, &ucast, 2736 ECORE_SPQ_MODE_CB, NULL); 2737 } 2738 2739 return rc; 2740 } 2741 2742 static int 2743 qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2744 enum rte_filter_op filter_op, 2745 const struct rte_eth_tunnel_filter_conf *conf) 2746 { 2747 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2748 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2749 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS; 2750 bool add; 2751 int rc; 2752 2753 PMD_INIT_FUNC_TRACE(edev); 2754 2755 switch (filter_op) { 2756 case RTE_ETH_FILTER_ADD: 2757 add = true; 2758 break; 2759 case RTE_ETH_FILTER_DELETE: 2760 add = false; 2761 break; 2762 default: 2763 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 2764 return -EINVAL; 2765 } 2766 2767 if (IS_VF(edev)) 2768 return qede_tunn_enable(eth_dev, 2769 ECORE_TUNN_CLSS_MAC_VLAN, 2770 conf->tunnel_type, add); 2771 2772 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add); 2773 if (rc != ECORE_SUCCESS) 2774 return rc; 2775 2776 if (add) { 2777 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) { 2778 qdev->vxlan.num_filters++; 2779 qdev->vxlan.filter_type = conf->filter_type; 2780 } else { /* GENEVE */ 2781 qdev->geneve.num_filters++; 2782 qdev->geneve.filter_type = conf->filter_type; 2783 } 2784 2785 if (!qdev->vxlan.enable || !qdev->geneve.enable) 2786 return qede_tunn_enable(eth_dev, clss, 2787 conf->tunnel_type, 2788 true); 2789 } else { 2790 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) 2791 qdev->vxlan.num_filters--; 2792 else /*GENEVE*/ 2793 qdev->geneve.num_filters--; 2794 2795 /* Disable VXLAN if VXLAN filters become 0 */ 2796 if ((qdev->vxlan.num_filters == 0) || 2797 (qdev->geneve.num_filters == 0)) 2798 return qede_tunn_enable(eth_dev, clss, 2799 conf->tunnel_type, 2800 false); 2801 } 2802 2803 return 0; 2804 } 2805 2806 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 2807 enum rte_filter_type filter_type, 2808 enum rte_filter_op filter_op, 2809 void *arg) 2810 { 2811 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2812 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2813 struct rte_eth_tunnel_filter_conf *filter_conf = 2814 (struct rte_eth_tunnel_filter_conf *)arg; 2815 2816 switch (filter_type) { 2817 case RTE_ETH_FILTER_TUNNEL: 2818 switch (filter_conf->tunnel_type) { 2819 case RTE_TUNNEL_TYPE_VXLAN: 2820 case RTE_TUNNEL_TYPE_GENEVE: 2821 DP_INFO(edev, 2822 "Packet steering to the specified Rx queue" 2823 " is not supported with UDP tunneling"); 2824 return(qede_tunn_filter_config(eth_dev, filter_op, 2825 filter_conf)); 2826 /* Place holders for future tunneling support */ 2827 case RTE_TUNNEL_TYPE_TEREDO: 2828 case RTE_TUNNEL_TYPE_NVGRE: 2829 case RTE_TUNNEL_TYPE_IP_IN_GRE: 2830 case RTE_L2_TUNNEL_TYPE_E_TAG: 2831 DP_ERR(edev, "Unsupported tunnel type %d\n", 2832 filter_conf->tunnel_type); 2833 return -EINVAL; 2834 case RTE_TUNNEL_TYPE_NONE: 2835 default: 2836 return 0; 2837 } 2838 break; 2839 case RTE_ETH_FILTER_FDIR: 2840 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 2841 case RTE_ETH_FILTER_NTUPLE: 2842 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 2843 case RTE_ETH_FILTER_MACVLAN: 2844 case RTE_ETH_FILTER_ETHERTYPE: 2845 case RTE_ETH_FILTER_FLEXIBLE: 2846 case RTE_ETH_FILTER_SYN: 2847 case RTE_ETH_FILTER_HASH: 2848 case RTE_ETH_FILTER_L2_TUNNEL: 2849 case RTE_ETH_FILTER_MAX: 2850 default: 2851 DP_ERR(edev, "Unsupported filter type %d\n", 2852 filter_type); 2853 return -EINVAL; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static const struct eth_dev_ops qede_eth_dev_ops = { 2860 .dev_configure = qede_dev_configure, 2861 .dev_infos_get = qede_dev_info_get, 2862 .rx_queue_setup = qede_rx_queue_setup, 2863 .rx_queue_release = qede_rx_queue_release, 2864 .tx_queue_setup = qede_tx_queue_setup, 2865 .tx_queue_release = qede_tx_queue_release, 2866 .dev_start = qede_dev_start, 2867 .dev_set_link_up = qede_dev_set_link_up, 2868 .dev_set_link_down = qede_dev_set_link_down, 2869 .link_update = qede_link_update, 2870 .promiscuous_enable = qede_promiscuous_enable, 2871 .promiscuous_disable = qede_promiscuous_disable, 2872 .allmulticast_enable = qede_allmulticast_enable, 2873 .allmulticast_disable = qede_allmulticast_disable, 2874 .dev_stop = qede_dev_stop, 2875 .dev_close = qede_dev_close, 2876 .stats_get = qede_get_stats, 2877 .stats_reset = qede_reset_stats, 2878 .xstats_get = qede_get_xstats, 2879 .xstats_reset = qede_reset_xstats, 2880 .xstats_get_names = qede_get_xstats_names, 2881 .mac_addr_add = qede_mac_addr_add, 2882 .mac_addr_remove = qede_mac_addr_remove, 2883 .mac_addr_set = qede_mac_addr_set, 2884 .vlan_offload_set = qede_vlan_offload_set, 2885 .vlan_filter_set = qede_vlan_filter_set, 2886 .flow_ctrl_set = qede_flow_ctrl_set, 2887 .flow_ctrl_get = qede_flow_ctrl_get, 2888 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2889 .rss_hash_update = qede_rss_hash_update, 2890 .rss_hash_conf_get = qede_rss_hash_conf_get, 2891 .reta_update = qede_rss_reta_update, 2892 .reta_query = qede_rss_reta_query, 2893 .mtu_set = qede_set_mtu, 2894 .filter_ctrl = qede_dev_filter_ctrl, 2895 .udp_tunnel_port_add = qede_udp_dst_port_add, 2896 .udp_tunnel_port_del = qede_udp_dst_port_del, 2897 }; 2898 2899 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2900 .dev_configure = qede_dev_configure, 2901 .dev_infos_get = qede_dev_info_get, 2902 .rx_queue_setup = qede_rx_queue_setup, 2903 .rx_queue_release = qede_rx_queue_release, 2904 .tx_queue_setup = qede_tx_queue_setup, 2905 .tx_queue_release = qede_tx_queue_release, 2906 .dev_start = qede_dev_start, 2907 .dev_set_link_up = qede_dev_set_link_up, 2908 .dev_set_link_down = qede_dev_set_link_down, 2909 .link_update = qede_link_update, 2910 .promiscuous_enable = qede_promiscuous_enable, 2911 .promiscuous_disable = qede_promiscuous_disable, 2912 .allmulticast_enable = qede_allmulticast_enable, 2913 .allmulticast_disable = qede_allmulticast_disable, 2914 .dev_stop = qede_dev_stop, 2915 .dev_close = qede_dev_close, 2916 .stats_get = qede_get_stats, 2917 .stats_reset = qede_reset_stats, 2918 .xstats_get = qede_get_xstats, 2919 .xstats_reset = qede_reset_xstats, 2920 .xstats_get_names = qede_get_xstats_names, 2921 .vlan_offload_set = qede_vlan_offload_set, 2922 .vlan_filter_set = qede_vlan_filter_set, 2923 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2924 .rss_hash_update = qede_rss_hash_update, 2925 .rss_hash_conf_get = qede_rss_hash_conf_get, 2926 .reta_update = qede_rss_reta_update, 2927 .reta_query = qede_rss_reta_query, 2928 .mtu_set = qede_set_mtu, 2929 .udp_tunnel_port_add = qede_udp_dst_port_add, 2930 .udp_tunnel_port_del = qede_udp_dst_port_del, 2931 }; 2932 2933 static void qede_update_pf_params(struct ecore_dev *edev) 2934 { 2935 struct ecore_pf_params pf_params; 2936 2937 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2938 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2939 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 2940 qed_ops->common->update_pf_params(edev, &pf_params); 2941 } 2942 2943 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2944 { 2945 struct rte_pci_device *pci_dev; 2946 struct rte_pci_addr pci_addr; 2947 struct qede_dev *adapter; 2948 struct ecore_dev *edev; 2949 struct qed_dev_eth_info dev_info; 2950 struct qed_slowpath_params params; 2951 static bool do_once = true; 2952 uint8_t bulletin_change; 2953 uint8_t vf_mac[ETHER_ADDR_LEN]; 2954 uint8_t is_mac_forced; 2955 bool is_mac_exist; 2956 /* Fix up ecore debug level */ 2957 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2958 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2959 int rc; 2960 2961 /* Extract key data structures */ 2962 adapter = eth_dev->data->dev_private; 2963 adapter->ethdev = eth_dev; 2964 edev = &adapter->edev; 2965 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2966 pci_addr = pci_dev->addr; 2967 2968 PMD_INIT_FUNC_TRACE(edev); 2969 2970 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2971 pci_addr.bus, pci_addr.devid, pci_addr.function, 2972 eth_dev->data->port_id); 2973 2974 eth_dev->rx_pkt_burst = qede_recv_pkts; 2975 eth_dev->tx_pkt_burst = qede_xmit_pkts; 2976 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 2977 2978 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2979 DP_ERR(edev, "Skipping device init from secondary process\n"); 2980 return 0; 2981 } 2982 2983 rte_eth_copy_pci_info(eth_dev, pci_dev); 2984 2985 /* @DPDK */ 2986 edev->vendor_id = pci_dev->id.vendor_id; 2987 edev->device_id = pci_dev->id.device_id; 2988 2989 qed_ops = qed_get_eth_ops(); 2990 if (!qed_ops) { 2991 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2992 return -EINVAL; 2993 } 2994 2995 DP_INFO(edev, "Starting qede probe\n"); 2996 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 2997 dp_level, is_vf); 2998 if (rc != 0) { 2999 DP_ERR(edev, "qede probe failed rc %d\n", rc); 3000 return -ENODEV; 3001 } 3002 qede_update_pf_params(edev); 3003 rte_intr_callback_register(&pci_dev->intr_handle, 3004 qede_interrupt_handler, (void *)eth_dev); 3005 if (rte_intr_enable(&pci_dev->intr_handle)) { 3006 DP_ERR(edev, "rte_intr_enable() failed\n"); 3007 return -ENODEV; 3008 } 3009 3010 /* Start the Slowpath-process */ 3011 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 3012 params.int_mode = ECORE_INT_MODE_MSIX; 3013 params.drv_major = QEDE_PMD_VERSION_MAJOR; 3014 params.drv_minor = QEDE_PMD_VERSION_MINOR; 3015 params.drv_rev = QEDE_PMD_VERSION_REVISION; 3016 params.drv_eng = QEDE_PMD_VERSION_PATCH; 3017 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 3018 QEDE_PMD_DRV_VER_STR_SIZE); 3019 3020 /* For CMT mode device do periodic polling for slowpath events. 3021 * This is required since uio device uses only one MSI-x 3022 * interrupt vector but we need one for each engine. 3023 */ 3024 if (ECORE_IS_CMT(edev) && IS_PF(edev)) { 3025 rc = rte_eal_alarm_set(timer_period * US_PER_S, 3026 qede_poll_sp_sb_cb, 3027 (void *)eth_dev); 3028 if (rc != 0) { 3029 DP_ERR(edev, "Unable to start periodic" 3030 " timer rc %d\n", rc); 3031 return -EINVAL; 3032 } 3033 } 3034 3035 rc = qed_ops->common->slowpath_start(edev, ¶ms); 3036 if (rc) { 3037 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 3038 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3039 (void *)eth_dev); 3040 return -ENODEV; 3041 } 3042 3043 rc = qed_ops->fill_dev_info(edev, &dev_info); 3044 if (rc) { 3045 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 3046 qed_ops->common->slowpath_stop(edev); 3047 qed_ops->common->remove(edev); 3048 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3049 (void *)eth_dev); 3050 return -ENODEV; 3051 } 3052 3053 qede_alloc_etherdev(adapter, &dev_info); 3054 3055 adapter->ops->common->set_name(edev, edev->name); 3056 3057 if (!is_vf) 3058 adapter->dev_info.num_mac_filters = 3059 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 3060 ECORE_MAC); 3061 else 3062 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 3063 (uint32_t *)&adapter->dev_info.num_mac_filters); 3064 3065 /* Allocate memory for storing MAC addr */ 3066 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 3067 (ETHER_ADDR_LEN * 3068 adapter->dev_info.num_mac_filters), 3069 RTE_CACHE_LINE_SIZE); 3070 3071 if (eth_dev->data->mac_addrs == NULL) { 3072 DP_ERR(edev, "Failed to allocate MAC address\n"); 3073 qed_ops->common->slowpath_stop(edev); 3074 qed_ops->common->remove(edev); 3075 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3076 (void *)eth_dev); 3077 return -ENOMEM; 3078 } 3079 3080 if (!is_vf) { 3081 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 3082 hw_info.hw_mac_addr, 3083 ð_dev->data->mac_addrs[0]); 3084 ether_addr_copy(ð_dev->data->mac_addrs[0], 3085 &adapter->primary_mac); 3086 } else { 3087 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 3088 &bulletin_change); 3089 if (bulletin_change) { 3090 is_mac_exist = 3091 ecore_vf_bulletin_get_forced_mac( 3092 ECORE_LEADING_HWFN(edev), 3093 vf_mac, 3094 &is_mac_forced); 3095 if (is_mac_exist && is_mac_forced) { 3096 DP_INFO(edev, "VF macaddr received from PF\n"); 3097 ether_addr_copy((struct ether_addr *)&vf_mac, 3098 ð_dev->data->mac_addrs[0]); 3099 ether_addr_copy(ð_dev->data->mac_addrs[0], 3100 &adapter->primary_mac); 3101 } else { 3102 DP_ERR(edev, "No VF macaddr assigned\n"); 3103 } 3104 } 3105 } 3106 3107 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 3108 3109 if (do_once) { 3110 qede_print_adapter_info(adapter); 3111 do_once = false; 3112 } 3113 3114 /* Bring-up the link */ 3115 qede_dev_set_link_state(eth_dev, true); 3116 3117 adapter->num_tx_queues = 0; 3118 adapter->num_rx_queues = 0; 3119 SLIST_INIT(&adapter->fdir_info.fdir_list_head); 3120 SLIST_INIT(&adapter->vlan_list_head); 3121 SLIST_INIT(&adapter->uc_list_head); 3122 adapter->mtu = ETHER_MTU; 3123 adapter->vport_started = false; 3124 3125 /* VF tunnel offloads is enabled by default in PF driver */ 3126 adapter->vxlan.enable = true; 3127 adapter->vxlan.num_filters = 0; 3128 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC | 3129 ETH_TUNNEL_FILTER_IVLAN; 3130 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT; 3131 adapter->geneve.enable = true; 3132 adapter->vxlan.num_filters = 0; 3133 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC | 3134 ETH_TUNNEL_FILTER_IVLAN; 3135 adapter->vxlan.udp_port = QEDE_GENEVE_DEF_PORT; 3136 3137 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 3138 adapter->primary_mac.addr_bytes[0], 3139 adapter->primary_mac.addr_bytes[1], 3140 adapter->primary_mac.addr_bytes[2], 3141 adapter->primary_mac.addr_bytes[3], 3142 adapter->primary_mac.addr_bytes[4], 3143 adapter->primary_mac.addr_bytes[5]); 3144 3145 DP_INFO(edev, "Device initialized\n"); 3146 3147 return 0; 3148 } 3149 3150 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 3151 { 3152 return qede_common_dev_init(eth_dev, 1); 3153 } 3154 3155 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 3156 { 3157 return qede_common_dev_init(eth_dev, 0); 3158 } 3159 3160 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 3161 { 3162 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 3163 struct qede_dev *qdev = eth_dev->data->dev_private; 3164 struct ecore_dev *edev = &qdev->edev; 3165 3166 PMD_INIT_FUNC_TRACE(edev); 3167 #endif 3168 3169 /* only uninitialize in the primary process */ 3170 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3171 return 0; 3172 3173 /* safe to close dev here */ 3174 qede_dev_close(eth_dev); 3175 3176 eth_dev->dev_ops = NULL; 3177 eth_dev->rx_pkt_burst = NULL; 3178 eth_dev->tx_pkt_burst = NULL; 3179 3180 if (eth_dev->data->mac_addrs) 3181 rte_free(eth_dev->data->mac_addrs); 3182 3183 eth_dev->data->mac_addrs = NULL; 3184 3185 return 0; 3186 } 3187 3188 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3189 { 3190 return qede_dev_common_uninit(eth_dev); 3191 } 3192 3193 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3194 { 3195 return qede_dev_common_uninit(eth_dev); 3196 } 3197 3198 static const struct rte_pci_id pci_id_qedevf_map[] = { 3199 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3200 { 3201 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 3202 }, 3203 { 3204 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 3205 }, 3206 { 3207 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 3208 }, 3209 {.vendor_id = 0,} 3210 }; 3211 3212 static const struct rte_pci_id pci_id_qede_map[] = { 3213 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3214 { 3215 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 3216 }, 3217 { 3218 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 3219 }, 3220 { 3221 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 3222 }, 3223 { 3224 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 3225 }, 3226 { 3227 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 3228 }, 3229 { 3230 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 3231 }, 3232 { 3233 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 3234 }, 3235 { 3236 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 3237 }, 3238 { 3239 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 3240 }, 3241 { 3242 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 3243 }, 3244 {.vendor_id = 0,} 3245 }; 3246 3247 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3248 struct rte_pci_device *pci_dev) 3249 { 3250 return rte_eth_dev_pci_generic_probe(pci_dev, 3251 sizeof(struct qede_dev), qedevf_eth_dev_init); 3252 } 3253 3254 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3255 { 3256 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 3257 } 3258 3259 static struct rte_pci_driver rte_qedevf_pmd = { 3260 .id_table = pci_id_qedevf_map, 3261 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3262 .probe = qedevf_eth_dev_pci_probe, 3263 .remove = qedevf_eth_dev_pci_remove, 3264 }; 3265 3266 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3267 struct rte_pci_device *pci_dev) 3268 { 3269 return rte_eth_dev_pci_generic_probe(pci_dev, 3270 sizeof(struct qede_dev), qede_eth_dev_init); 3271 } 3272 3273 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3274 { 3275 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 3276 } 3277 3278 static struct rte_pci_driver rte_qede_pmd = { 3279 .id_table = pci_id_qede_map, 3280 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3281 .probe = qede_eth_dev_pci_probe, 3282 .remove = qede_eth_dev_pci_remove, 3283 }; 3284 3285 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 3286 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 3287 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 3288 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 3289 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 3290 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 3291 3292 RTE_INIT(qede_init_log); 3293 static void 3294 qede_init_log(void) 3295 { 3296 qede_logtype_init = rte_log_register("pmd.net.qede.init"); 3297 if (qede_logtype_init >= 0) 3298 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE); 3299 qede_logtype_driver = rte_log_register("pmd.net.qede.driver"); 3300 if (qede_logtype_driver >= 0) 3301 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE); 3302 } 3303