1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static const char *drivername = "qede pmd"; 16 static int64_t timer_period = 1; 17 18 struct rte_qede_xstats_name_off { 19 char name[RTE_ETH_XSTATS_NAME_SIZE]; 20 uint64_t offset; 21 }; 22 23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 24 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, 25 {"rx_multicast_bytes", 26 offsetof(struct ecore_eth_stats, rx_mcast_bytes)}, 27 {"rx_broadcast_bytes", 28 offsetof(struct ecore_eth_stats, rx_bcast_bytes)}, 29 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)}, 30 {"rx_multicast_packets", 31 offsetof(struct ecore_eth_stats, rx_mcast_pkts)}, 32 {"rx_broadcast_packets", 33 offsetof(struct ecore_eth_stats, rx_bcast_pkts)}, 34 35 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)}, 36 {"tx_multicast_bytes", 37 offsetof(struct ecore_eth_stats, tx_mcast_bytes)}, 38 {"tx_broadcast_bytes", 39 offsetof(struct ecore_eth_stats, tx_bcast_bytes)}, 40 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)}, 41 {"tx_multicast_packets", 42 offsetof(struct ecore_eth_stats, tx_mcast_pkts)}, 43 {"tx_broadcast_packets", 44 offsetof(struct ecore_eth_stats, tx_bcast_pkts)}, 45 46 {"rx_64_byte_packets", 47 offsetof(struct ecore_eth_stats, rx_64_byte_packets)}, 48 {"rx_65_to_127_byte_packets", 49 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)}, 50 {"rx_128_to_255_byte_packets", 51 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)}, 52 {"rx_256_to_511_byte_packets", 53 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)}, 54 {"rx_512_to_1023_byte_packets", 55 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)}, 56 {"rx_1024_to_1518_byte_packets", 57 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)}, 58 {"rx_1519_to_1522_byte_packets", 59 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)}, 60 {"rx_1519_to_2047_byte_packets", 61 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)}, 62 {"rx_2048_to_4095_byte_packets", 63 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)}, 64 {"rx_4096_to_9216_byte_packets", 65 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)}, 66 {"rx_9217_to_16383_byte_packets", 67 offsetof(struct ecore_eth_stats, 68 rx_9217_to_16383_byte_packets)}, 69 {"tx_64_byte_packets", 70 offsetof(struct ecore_eth_stats, tx_64_byte_packets)}, 71 {"tx_65_to_127_byte_packets", 72 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)}, 73 {"tx_128_to_255_byte_packets", 74 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)}, 75 {"tx_256_to_511_byte_packets", 76 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)}, 77 {"tx_512_to_1023_byte_packets", 78 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)}, 79 {"tx_1024_to_1518_byte_packets", 80 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)}, 81 {"trx_1519_to_1522_byte_packets", 82 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)}, 83 {"tx_2048_to_4095_byte_packets", 84 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)}, 85 {"tx_4096_to_9216_byte_packets", 86 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)}, 87 {"tx_9217_to_16383_byte_packets", 88 offsetof(struct ecore_eth_stats, 89 tx_9217_to_16383_byte_packets)}, 90 91 {"rx_mac_crtl_frames", 92 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)}, 93 {"tx_mac_control_frames", 94 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)}, 95 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)}, 96 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)}, 97 {"rx_priority_flow_control_frames", 98 offsetof(struct ecore_eth_stats, rx_pfc_frames)}, 99 {"tx_priority_flow_control_frames", 100 offsetof(struct ecore_eth_stats, tx_pfc_frames)}, 101 102 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)}, 103 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)}, 104 {"rx_carrier_errors", 105 offsetof(struct ecore_eth_stats, rx_carrier_errors)}, 106 {"rx_oversize_packet_errors", 107 offsetof(struct ecore_eth_stats, rx_oversize_packets)}, 108 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)}, 109 {"rx_undersize_packet_errors", 110 offsetof(struct ecore_eth_stats, rx_undersize_packets)}, 111 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)}, 112 {"rx_host_buffer_not_available", 113 offsetof(struct ecore_eth_stats, no_buff_discards)}, 114 /* Number of packets discarded because they are bigger than MTU */ 115 {"rx_packet_too_big_discards", 116 offsetof(struct ecore_eth_stats, packet_too_big_discard)}, 117 {"rx_ttl_zero_discards", 118 offsetof(struct ecore_eth_stats, ttl0_discard)}, 119 {"rx_multi_function_tag_filter_discards", 120 offsetof(struct ecore_eth_stats, mftag_filter_discards)}, 121 {"rx_mac_filter_discards", 122 offsetof(struct ecore_eth_stats, mac_filter_discards)}, 123 {"rx_hw_buffer_truncates", 124 offsetof(struct ecore_eth_stats, brb_truncates)}, 125 {"rx_hw_buffer_discards", 126 offsetof(struct ecore_eth_stats, brb_discards)}, 127 {"tx_lpi_entry_count", 128 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)}, 129 {"tx_total_collisions", 130 offsetof(struct ecore_eth_stats, tx_total_collisions)}, 131 {"tx_error_drop_packets", 132 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)}, 133 134 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)}, 135 {"rx_mac_unicast_packets", 136 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)}, 137 {"rx_mac_multicast_packets", 138 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)}, 139 {"rx_mac_broadcast_packets", 140 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)}, 141 {"rx_mac_frames_ok", 142 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)}, 143 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)}, 144 {"tx_mac_unicast_packets", 145 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)}, 146 {"tx_mac_multicast_packets", 147 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)}, 148 {"tx_mac_broadcast_packets", 149 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)}, 150 151 {"lro_coalesced_packets", 152 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)}, 153 {"lro_coalesced_events", 154 offsetof(struct ecore_eth_stats, tpa_coalesced_events)}, 155 {"lro_aborts_num", 156 offsetof(struct ecore_eth_stats, tpa_aborts_num)}, 157 {"lro_not_coalesced_packets", 158 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)}, 159 {"lro_coalesced_bytes", 160 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)}, 161 }; 162 163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 164 {"rx_q_segments", 165 offsetof(struct qede_rx_queue, rx_segs)}, 166 {"rx_q_hw_errors", 167 offsetof(struct qede_rx_queue, rx_hw_errors)}, 168 {"rx_q_allocation_errors", 169 offsetof(struct qede_rx_queue, rx_alloc_errors)} 170 }; 171 172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 173 { 174 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 175 } 176 177 static void 178 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param) 179 { 180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 181 struct qede_dev *qdev = eth_dev->data->dev_private; 182 struct ecore_dev *edev = &qdev->edev; 183 184 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 185 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) 186 DP_ERR(edev, "rte_intr_enable failed\n"); 187 } 188 189 static void 190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 191 { 192 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 193 qdev->num_tc = qdev->dev_info.num_tc; 194 qdev->ops = qed_ops; 195 } 196 197 static void qede_print_adapter_info(struct qede_dev *qdev) 198 { 199 struct ecore_dev *edev = &qdev->edev; 200 struct qed_dev_info *info = &qdev->dev_info.common; 201 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 202 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 203 204 DP_INFO(edev, "*********************************\n"); 205 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 206 DP_INFO(edev, " Chip details : %s%d\n", 207 ECORE_IS_BB(edev) ? "BB" : "AH", 208 CHIP_REV_IS_A0(edev) ? 0 : 1); 209 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 210 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 211 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 212 ver_str, QEDE_PMD_VERSION); 213 DP_INFO(edev, " Driver version : %s\n", drv_ver); 214 DP_INFO(edev, " Firmware version : %s\n", ver_str); 215 216 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 217 "%d.%d.%d.%d", 218 (info->mfw_rev >> 24) & 0xff, 219 (info->mfw_rev >> 16) & 0xff, 220 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 221 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 222 DP_INFO(edev, " Firmware file : %s\n", fw_file); 223 DP_INFO(edev, "*********************************\n"); 224 } 225 226 static int 227 qede_set_ucast_rx_mac(struct qede_dev *qdev, 228 enum qed_filter_xcast_params_type opcode, 229 uint8_t mac[ETHER_ADDR_LEN]) 230 { 231 struct ecore_dev *edev = &qdev->edev; 232 struct qed_filter_params filter_cmd; 233 234 memset(&filter_cmd, 0, sizeof(filter_cmd)); 235 filter_cmd.type = QED_FILTER_TYPE_UCAST; 236 filter_cmd.filter.ucast.type = opcode; 237 filter_cmd.filter.ucast.mac_valid = 1; 238 rte_memcpy(&filter_cmd.filter.ucast.mac[0], &mac[0], ETHER_ADDR_LEN); 239 return qdev->ops->filter_config(edev, &filter_cmd); 240 } 241 242 static void 243 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 244 uint32_t index, __rte_unused uint32_t pool) 245 { 246 struct qede_dev *qdev = eth_dev->data->dev_private; 247 struct ecore_dev *edev = &qdev->edev; 248 int rc; 249 250 PMD_INIT_FUNC_TRACE(edev); 251 252 if (index >= qdev->dev_info.num_mac_addrs) { 253 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 254 index, qdev->dev_info.num_mac_addrs); 255 return; 256 } 257 258 /* Adding macaddr even though promiscuous mode is set */ 259 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 260 DP_INFO(edev, "Port is in promisc mode, yet adding it\n"); 261 262 /* Add MAC filters according to the unicast secondary macs */ 263 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD, 264 mac_addr->addr_bytes); 265 if (rc) 266 DP_ERR(edev, "Unable to add macaddr rc=%d\n", rc); 267 } 268 269 static void 270 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 271 { 272 struct qede_dev *qdev = eth_dev->data->dev_private; 273 struct ecore_dev *edev = &qdev->edev; 274 struct ether_addr mac_addr; 275 int rc; 276 277 PMD_INIT_FUNC_TRACE(edev); 278 279 if (index >= qdev->dev_info.num_mac_addrs) { 280 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 281 index, qdev->dev_info.num_mac_addrs); 282 return; 283 } 284 285 /* Use the index maintained by rte */ 286 ether_addr_copy(ð_dev->data->mac_addrs[index], &mac_addr); 287 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL, 288 mac_addr.addr_bytes); 289 if (rc) 290 DP_ERR(edev, "Unable to remove macaddr rc=%d\n", rc); 291 } 292 293 static void 294 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 295 { 296 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 297 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 298 int rc; 299 300 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 301 mac_addr->addr_bytes)) { 302 DP_ERR(edev, "Setting MAC address is not allowed\n"); 303 ether_addr_copy(&qdev->primary_mac, 304 ð_dev->data->mac_addrs[0]); 305 return; 306 } 307 308 /* First remove the primary mac */ 309 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL, 310 qdev->primary_mac.addr_bytes); 311 312 if (rc) { 313 DP_ERR(edev, "Unable to remove current macaddr" 314 " Reverting to previous default mac\n"); 315 ether_addr_copy(&qdev->primary_mac, 316 ð_dev->data->mac_addrs[0]); 317 return; 318 } 319 320 /* Add new MAC */ 321 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD, 322 mac_addr->addr_bytes); 323 324 if (rc) 325 DP_ERR(edev, "Unable to add new default mac\n"); 326 else 327 ether_addr_copy(mac_addr, &qdev->primary_mac); 328 } 329 330 331 332 333 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action) 334 { 335 struct ecore_dev *edev = &qdev->edev; 336 struct qed_update_vport_params params = { 337 .vport_id = 0, 338 .accept_any_vlan = action, 339 .update_accept_any_vlan_flg = 1, 340 }; 341 int rc; 342 343 /* Proceed only if action actually needs to be performed */ 344 if (qdev->accept_any_vlan == action) 345 return; 346 347 rc = qdev->ops->vport_update(edev, ¶ms); 348 if (rc) { 349 DP_ERR(edev, "Failed to %s accept-any-vlan\n", 350 action ? "enable" : "disable"); 351 } else { 352 DP_INFO(edev, "%s accept-any-vlan\n", 353 action ? "enabled" : "disabled"); 354 qdev->accept_any_vlan = action; 355 } 356 } 357 358 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping) 359 { 360 struct qed_update_vport_params vport_update_params; 361 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 362 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 363 int rc; 364 365 memset(&vport_update_params, 0, sizeof(vport_update_params)); 366 vport_update_params.vport_id = 0; 367 vport_update_params.update_inner_vlan_removal_flg = 1; 368 vport_update_params.inner_vlan_removal_flg = set_stripping; 369 rc = qdev->ops->vport_update(edev, &vport_update_params); 370 if (rc) { 371 DP_ERR(edev, "Update V-PORT failed %d\n", rc); 372 return rc; 373 } 374 375 return 0; 376 } 377 378 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 379 { 380 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 381 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 382 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 383 384 if (mask & ETH_VLAN_STRIP_MASK) { 385 if (rxmode->hw_vlan_strip) 386 (void)qede_vlan_stripping(eth_dev, 1); 387 else 388 (void)qede_vlan_stripping(eth_dev, 0); 389 } 390 391 if (mask & ETH_VLAN_FILTER_MASK) { 392 /* VLAN filtering kicks in when a VLAN is added */ 393 if (rxmode->hw_vlan_filter) { 394 qede_vlan_filter_set(eth_dev, 0, 1); 395 } else { 396 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 397 DP_NOTICE(edev, false, 398 " Please remove existing VLAN filters" 399 " before disabling VLAN filtering\n"); 400 /* Signal app that VLAN filtering is still 401 * enabled 402 */ 403 rxmode->hw_vlan_filter = true; 404 } else { 405 qede_vlan_filter_set(eth_dev, 0, 0); 406 } 407 } 408 } 409 410 if (mask & ETH_VLAN_EXTEND_MASK) 411 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 412 " and classification is based on outer tag only\n"); 413 414 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 415 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 416 } 417 418 static int qede_set_ucast_rx_vlan(struct qede_dev *qdev, 419 enum qed_filter_xcast_params_type opcode, 420 uint16_t vid) 421 { 422 struct qed_filter_params filter_cmd; 423 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 424 425 memset(&filter_cmd, 0, sizeof(filter_cmd)); 426 filter_cmd.type = QED_FILTER_TYPE_UCAST; 427 filter_cmd.filter.ucast.type = opcode; 428 filter_cmd.filter.ucast.vlan_valid = 1; 429 filter_cmd.filter.ucast.vlan = vid; 430 431 return qdev->ops->filter_config(edev, &filter_cmd); 432 } 433 434 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 435 uint16_t vlan_id, int on) 436 { 437 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 438 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 439 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 440 struct qede_vlan_entry *tmp = NULL; 441 struct qede_vlan_entry *vlan; 442 int rc; 443 444 if (on) { 445 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 446 DP_INFO(edev, "Reached max VLAN filter limit" 447 " enabling accept_any_vlan\n"); 448 qede_config_accept_any_vlan(qdev, true); 449 return 0; 450 } 451 452 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 453 if (tmp->vid == vlan_id) { 454 DP_ERR(edev, "VLAN %u already configured\n", 455 vlan_id); 456 return -EEXIST; 457 } 458 } 459 460 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 461 RTE_CACHE_LINE_SIZE); 462 463 if (!vlan) { 464 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 465 return -ENOMEM; 466 } 467 468 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_ADD, 469 vlan_id); 470 if (rc) { 471 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 472 rc); 473 rte_free(vlan); 474 } else { 475 vlan->vid = vlan_id; 476 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 477 qdev->configured_vlans++; 478 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 479 vlan_id, qdev->configured_vlans); 480 } 481 } else { 482 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 483 if (tmp->vid == vlan_id) 484 break; 485 } 486 487 if (!tmp) { 488 if (qdev->configured_vlans == 0) { 489 DP_INFO(edev, 490 "No VLAN filters configured yet\n"); 491 return 0; 492 } 493 494 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 495 return -EINVAL; 496 } 497 498 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 499 500 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_DEL, 501 vlan_id); 502 if (rc) { 503 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 504 vlan_id, rc); 505 } else { 506 qdev->configured_vlans--; 507 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 508 vlan_id, qdev->configured_vlans); 509 } 510 } 511 512 return rc; 513 } 514 515 static int qede_init_vport(struct qede_dev *qdev) 516 { 517 struct ecore_dev *edev = &qdev->edev; 518 struct qed_start_vport_params start = {0}; 519 int rc; 520 521 start.remove_inner_vlan = 1; 522 start.gro_enable = 0; 523 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD; 524 start.vport_id = 0; 525 start.drop_ttl0 = false; 526 start.clear_stats = 1; 527 start.handle_ptp_pkts = 0; 528 529 rc = qdev->ops->vport_start(edev, &start); 530 if (rc) { 531 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 532 return rc; 533 } 534 535 DP_INFO(edev, 536 "Start vport ramrod passed, vport_id = %d, MTU = %u\n", 537 start.vport_id, ETHER_MTU); 538 539 return 0; 540 } 541 542 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 543 { 544 struct qede_dev *qdev = eth_dev->data->dev_private; 545 struct ecore_dev *edev = &qdev->edev; 546 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 547 int rc, i, j; 548 549 PMD_INIT_FUNC_TRACE(edev); 550 551 /* Check requirements for 100G mode */ 552 if (edev->num_hwfns > 1) { 553 if (eth_dev->data->nb_rx_queues < 2 || 554 eth_dev->data->nb_tx_queues < 2) { 555 DP_NOTICE(edev, false, 556 "100G mode needs min. 2 RX/TX queues\n"); 557 return -EINVAL; 558 } 559 560 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 561 (eth_dev->data->nb_tx_queues % 2 != 0)) { 562 DP_NOTICE(edev, false, 563 "100G mode needs even no. of RX/TX queues\n"); 564 return -EINVAL; 565 } 566 } 567 568 /* Sanity checks and throw warnings */ 569 if (rxmode->enable_scatter == 1) 570 eth_dev->data->scattered_rx = 1; 571 572 if (rxmode->enable_lro == 1) { 573 DP_INFO(edev, "LRO is not supported\n"); 574 return -EINVAL; 575 } 576 577 if (!rxmode->hw_strip_crc) 578 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 579 580 if (!rxmode->hw_ip_checksum) 581 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 582 "in hw\n"); 583 584 /* Check for the port restart case */ 585 if (qdev->state != QEDE_DEV_INIT) { 586 rc = qdev->ops->vport_stop(edev, 0); 587 if (rc != 0) 588 return rc; 589 qede_dealloc_fp_resc(eth_dev); 590 } 591 592 qdev->fp_num_tx = eth_dev->data->nb_tx_queues; 593 qdev->fp_num_rx = eth_dev->data->nb_rx_queues; 594 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx; 595 596 /* Fastpath status block should be initialized before sending 597 * VPORT-START in the case of VF. Anyway, do it for both VF/PF. 598 */ 599 rc = qede_alloc_fp_resc(qdev); 600 if (rc != 0) 601 return rc; 602 603 /* Issue VPORT-START with default config values to allow 604 * other port configurations early on. 605 */ 606 rc = qede_init_vport(qdev); 607 if (rc != 0) 608 return rc; 609 610 SLIST_INIT(&qdev->vlan_list_head); 611 612 /* Add primary mac for PF */ 613 if (IS_PF(edev)) 614 qede_mac_addr_set(eth_dev, &qdev->primary_mac); 615 616 /* Enable VLAN offloads by default */ 617 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 618 ETH_VLAN_FILTER_MASK | 619 ETH_VLAN_EXTEND_MASK); 620 621 qdev->state = QEDE_DEV_CONFIG; 622 623 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n", 624 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev), 625 qdev->num_tc); 626 627 return 0; 628 } 629 630 /* Info about HW descriptor ring limitations */ 631 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 632 .nb_max = NUM_RX_BDS_MAX, 633 .nb_min = 128, 634 .nb_align = 128 /* lowest common multiple */ 635 }; 636 637 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 638 .nb_max = NUM_TX_BDS_MAX, 639 .nb_min = 256, 640 .nb_align = 256 641 }; 642 643 static void 644 qede_dev_info_get(struct rte_eth_dev *eth_dev, 645 struct rte_eth_dev_info *dev_info) 646 { 647 struct qede_dev *qdev = eth_dev->data->dev_private; 648 struct ecore_dev *edev = &qdev->edev; 649 650 PMD_INIT_FUNC_TRACE(edev); 651 652 dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU + 653 QEDE_ETH_OVERHEAD); 654 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 655 dev_info->rx_desc_lim = qede_rx_desc_lim; 656 dev_info->tx_desc_lim = qede_tx_desc_lim; 657 dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev); 658 dev_info->max_tx_queues = dev_info->max_rx_queues; 659 dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs; 660 if (IS_VF(edev)) 661 dev_info->max_vfs = 0; 662 else 663 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev); 664 dev_info->driver_name = qdev->drv_ver; 665 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 666 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 667 668 dev_info->default_txconf = (struct rte_eth_txconf) { 669 .txq_flags = QEDE_TXQ_FLAGS, 670 }; 671 672 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 673 DEV_RX_OFFLOAD_IPV4_CKSUM | 674 DEV_RX_OFFLOAD_UDP_CKSUM | 675 DEV_RX_OFFLOAD_TCP_CKSUM); 676 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 677 DEV_TX_OFFLOAD_IPV4_CKSUM | 678 DEV_TX_OFFLOAD_UDP_CKSUM | 679 DEV_TX_OFFLOAD_TCP_CKSUM); 680 681 dev_info->speed_capa = ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G | 682 ETH_LINK_SPEED_100G; 683 } 684 685 /* return 0 means link status changed, -1 means not changed */ 686 static int 687 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 688 { 689 struct qede_dev *qdev = eth_dev->data->dev_private; 690 struct ecore_dev *edev = &qdev->edev; 691 uint16_t link_duplex; 692 struct qed_link_output link; 693 struct rte_eth_link *curr = ð_dev->data->dev_link; 694 695 memset(&link, 0, sizeof(struct qed_link_output)); 696 qdev->ops->common->get_link(edev, &link); 697 698 /* Link Speed */ 699 curr->link_speed = link.speed; 700 701 /* Link Mode */ 702 switch (link.duplex) { 703 case QEDE_DUPLEX_HALF: 704 link_duplex = ETH_LINK_HALF_DUPLEX; 705 break; 706 case QEDE_DUPLEX_FULL: 707 link_duplex = ETH_LINK_FULL_DUPLEX; 708 break; 709 case QEDE_DUPLEX_UNKNOWN: 710 default: 711 link_duplex = -1; 712 } 713 curr->link_duplex = link_duplex; 714 715 /* Link Status */ 716 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 717 718 /* AN */ 719 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 720 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 721 722 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 723 curr->link_speed, curr->link_duplex, 724 curr->link_autoneg, curr->link_status); 725 726 /* return 0 means link status changed, -1 means not changed */ 727 return ((curr->link_status == link.link_up) ? -1 : 0); 728 } 729 730 static void 731 qede_rx_mode_setting(struct rte_eth_dev *eth_dev, 732 enum qed_filter_rx_mode_type accept_flags) 733 { 734 struct qede_dev *qdev = eth_dev->data->dev_private; 735 struct ecore_dev *edev = &qdev->edev; 736 struct qed_filter_params rx_mode; 737 738 DP_INFO(edev, "%s mode %u\n", __func__, accept_flags); 739 740 memset(&rx_mode, 0, sizeof(struct qed_filter_params)); 741 rx_mode.type = QED_FILTER_TYPE_RX_MODE; 742 rx_mode.filter.accept_flags = accept_flags; 743 qdev->ops->filter_config(edev, &rx_mode); 744 } 745 746 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 747 { 748 struct qede_dev *qdev = eth_dev->data->dev_private; 749 struct ecore_dev *edev = &qdev->edev; 750 751 PMD_INIT_FUNC_TRACE(edev); 752 753 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 754 755 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 756 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 757 758 qede_rx_mode_setting(eth_dev, type); 759 } 760 761 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 762 { 763 struct qede_dev *qdev = eth_dev->data->dev_private; 764 struct ecore_dev *edev = &qdev->edev; 765 766 PMD_INIT_FUNC_TRACE(edev); 767 768 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 769 qede_rx_mode_setting(eth_dev, 770 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 771 else 772 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR); 773 } 774 775 static void qede_poll_sp_sb_cb(void *param) 776 { 777 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 778 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 779 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 780 int rc; 781 782 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 783 qede_interrupt_action(&edev->hwfns[1]); 784 785 rc = rte_eal_alarm_set(timer_period * US_PER_S, 786 qede_poll_sp_sb_cb, 787 (void *)eth_dev); 788 if (rc != 0) { 789 DP_ERR(edev, "Unable to start periodic" 790 " timer rc %d\n", rc); 791 assert(false && "Unable to start periodic timer"); 792 } 793 } 794 795 static void qede_dev_close(struct rte_eth_dev *eth_dev) 796 { 797 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 798 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 799 int rc; 800 801 PMD_INIT_FUNC_TRACE(edev); 802 803 /* dev_stop() shall cleanup fp resources in hw but without releasing 804 * dma memories and sw structures so that dev_start() can be called 805 * by the app without reconfiguration. However, in dev_close() we 806 * can release all the resources and device can be brought up newly 807 */ 808 if (qdev->state != QEDE_DEV_STOP) 809 qede_dev_stop(eth_dev); 810 else 811 DP_INFO(edev, "Device is already stopped\n"); 812 813 rc = qdev->ops->vport_stop(edev, 0); 814 if (rc != 0) 815 DP_ERR(edev, "Failed to stop VPORT\n"); 816 817 qede_dealloc_fp_resc(eth_dev); 818 819 qdev->ops->common->slowpath_stop(edev); 820 821 qdev->ops->common->remove(edev); 822 823 rte_intr_disable(ð_dev->pci_dev->intr_handle); 824 825 rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle, 826 qede_interrupt_handler, (void *)eth_dev); 827 828 if (edev->num_hwfns > 1) 829 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 830 831 qdev->state = QEDE_DEV_INIT; /* Go back to init state */ 832 } 833 834 static void 835 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 836 { 837 struct qede_dev *qdev = eth_dev->data->dev_private; 838 struct ecore_dev *edev = &qdev->edev; 839 struct ecore_eth_stats stats; 840 unsigned int i = 0, j = 0, qid; 841 struct qede_tx_queue *txq; 842 843 qdev->ops->get_vport_stats(edev, &stats); 844 845 /* RX Stats */ 846 eth_stats->ipackets = stats.rx_ucast_pkts + 847 stats.rx_mcast_pkts + stats.rx_bcast_pkts; 848 849 eth_stats->ibytes = stats.rx_ucast_bytes + 850 stats.rx_mcast_bytes + stats.rx_bcast_bytes; 851 852 eth_stats->ierrors = stats.rx_crc_errors + 853 stats.rx_align_errors + 854 stats.rx_carrier_errors + 855 stats.rx_oversize_packets + 856 stats.rx_jabbers + stats.rx_undersize_packets; 857 858 eth_stats->rx_nombuf = stats.no_buff_discards; 859 860 eth_stats->imissed = stats.mftag_filter_discards + 861 stats.mac_filter_discards + 862 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards; 863 864 /* TX stats */ 865 eth_stats->opackets = stats.tx_ucast_pkts + 866 stats.tx_mcast_pkts + stats.tx_bcast_pkts; 867 868 eth_stats->obytes = stats.tx_ucast_bytes + 869 stats.tx_mcast_bytes + stats.tx_bcast_bytes; 870 871 eth_stats->oerrors = stats.tx_err_drop_pkts; 872 873 /* Queue stats */ 874 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 875 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 876 eth_stats->q_ipackets[i] = 877 *(uint64_t *)( 878 ((char *)(qdev->fp_array[(qid)].rxq)) + 879 offsetof(struct qede_rx_queue, 880 rcv_pkts)); 881 eth_stats->q_errors[i] = 882 *(uint64_t *)( 883 ((char *)(qdev->fp_array[(qid)].rxq)) + 884 offsetof(struct qede_rx_queue, 885 rx_hw_errors)) + 886 *(uint64_t *)( 887 ((char *)(qdev->fp_array[(qid)].rxq)) + 888 offsetof(struct qede_rx_queue, 889 rx_alloc_errors)); 890 i++; 891 } 892 893 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) { 894 txq = qdev->fp_array[(qid)].txqs[0]; 895 eth_stats->q_opackets[j] = 896 *((uint64_t *)(uintptr_t) 897 (((uint64_t)(uintptr_t)(txq)) + 898 offsetof(struct qede_tx_queue, 899 xmit_pkts))); 900 j++; 901 } 902 } 903 } 904 905 static unsigned 906 qede_get_xstats_count(struct qede_dev *qdev) { 907 return RTE_DIM(qede_xstats_strings) + 908 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev)); 909 } 910 911 static int 912 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, 913 struct rte_eth_xstat_name *xstats_names, unsigned limit) 914 { 915 struct qede_dev *qdev = dev->data->dev_private; 916 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 917 unsigned int i, qid, stat_idx = 0; 918 919 if (xstats_names != NULL) { 920 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 921 snprintf(xstats_names[stat_idx].name, 922 sizeof(xstats_names[stat_idx].name), 923 "%s", 924 qede_xstats_strings[i].name); 925 stat_idx++; 926 } 927 928 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) { 929 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 930 snprintf(xstats_names[stat_idx].name, 931 sizeof(xstats_names[stat_idx].name), 932 "%.4s%d%s", 933 qede_rxq_xstats_strings[i].name, qid, 934 qede_rxq_xstats_strings[i].name + 4); 935 stat_idx++; 936 } 937 } 938 } 939 940 return stat_cnt; 941 } 942 943 static int 944 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 945 unsigned int n) 946 { 947 struct qede_dev *qdev = dev->data->dev_private; 948 struct ecore_dev *edev = &qdev->edev; 949 struct ecore_eth_stats stats; 950 const unsigned int num = qede_get_xstats_count(qdev); 951 unsigned int i, qid, stat_idx = 0; 952 953 if (n < num) 954 return num; 955 956 qdev->ops->get_vport_stats(edev, &stats); 957 958 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 959 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 960 qede_xstats_strings[i].offset); 961 stat_idx++; 962 } 963 964 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 965 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 966 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 967 xstats[stat_idx].value = *(uint64_t *)( 968 ((char *)(qdev->fp_array[(qid)].rxq)) + 969 qede_rxq_xstats_strings[i].offset); 970 stat_idx++; 971 } 972 } 973 } 974 975 return stat_idx; 976 } 977 978 static void 979 qede_reset_xstats(struct rte_eth_dev *dev) 980 { 981 struct qede_dev *qdev = dev->data->dev_private; 982 struct ecore_dev *edev = &qdev->edev; 983 984 ecore_reset_vport_stats(edev); 985 } 986 987 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 988 { 989 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 990 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 991 struct qed_link_params link_params; 992 int rc; 993 994 DP_INFO(edev, "setting link state %d\n", link_up); 995 memset(&link_params, 0, sizeof(link_params)); 996 link_params.link_up = link_up; 997 rc = qdev->ops->common->set_link(edev, &link_params); 998 if (rc != ECORE_SUCCESS) 999 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1000 1001 return rc; 1002 } 1003 1004 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1005 { 1006 return qede_dev_set_link_state(eth_dev, true); 1007 } 1008 1009 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1010 { 1011 return qede_dev_set_link_state(eth_dev, false); 1012 } 1013 1014 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1015 { 1016 struct qede_dev *qdev = eth_dev->data->dev_private; 1017 struct ecore_dev *edev = &qdev->edev; 1018 1019 ecore_reset_vport_stats(edev); 1020 } 1021 1022 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1023 { 1024 enum qed_filter_rx_mode_type type = 1025 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1026 1027 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1028 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1029 1030 qede_rx_mode_setting(eth_dev, type); 1031 } 1032 1033 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1034 { 1035 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1036 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_PROMISC); 1037 else 1038 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR); 1039 } 1040 1041 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1042 struct rte_eth_fc_conf *fc_conf) 1043 { 1044 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1045 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1046 struct qed_link_output current_link; 1047 struct qed_link_params params; 1048 1049 memset(¤t_link, 0, sizeof(current_link)); 1050 qdev->ops->common->get_link(edev, ¤t_link); 1051 1052 memset(¶ms, 0, sizeof(params)); 1053 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1054 if (fc_conf->autoneg) { 1055 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1056 DP_ERR(edev, "Autoneg not supported\n"); 1057 return -EINVAL; 1058 } 1059 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1060 } 1061 1062 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1063 if (fc_conf->mode == RTE_FC_FULL) 1064 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1065 QED_LINK_PAUSE_RX_ENABLE); 1066 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1067 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1068 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1069 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1070 1071 params.link_up = true; 1072 (void)qdev->ops->common->set_link(edev, ¶ms); 1073 1074 return 0; 1075 } 1076 1077 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1078 struct rte_eth_fc_conf *fc_conf) 1079 { 1080 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1081 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1082 struct qed_link_output current_link; 1083 1084 memset(¤t_link, 0, sizeof(current_link)); 1085 qdev->ops->common->get_link(edev, ¤t_link); 1086 1087 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1088 fc_conf->autoneg = true; 1089 1090 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1091 QED_LINK_PAUSE_TX_ENABLE)) 1092 fc_conf->mode = RTE_FC_FULL; 1093 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1094 fc_conf->mode = RTE_FC_RX_PAUSE; 1095 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1096 fc_conf->mode = RTE_FC_TX_PAUSE; 1097 else 1098 fc_conf->mode = RTE_FC_NONE; 1099 1100 return 0; 1101 } 1102 1103 static const uint32_t * 1104 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1105 { 1106 static const uint32_t ptypes[] = { 1107 RTE_PTYPE_L3_IPV4, 1108 RTE_PTYPE_L3_IPV6, 1109 RTE_PTYPE_UNKNOWN 1110 }; 1111 1112 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1113 return ptypes; 1114 1115 return NULL; 1116 } 1117 1118 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1119 { 1120 *rss_caps = 0; 1121 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1122 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1123 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1124 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1125 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1126 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1127 } 1128 1129 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1130 struct rte_eth_rss_conf *rss_conf) 1131 { 1132 struct qed_update_vport_params vport_update_params; 1133 struct qede_dev *qdev = eth_dev->data->dev_private; 1134 struct ecore_dev *edev = &qdev->edev; 1135 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1136 uint64_t hf = rss_conf->rss_hf; 1137 int i; 1138 1139 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1140 1141 if (hf != 0) { 1142 /* Enable RSS */ 1143 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf); 1144 memcpy(&vport_update_params.rss_params, &qdev->rss_params, 1145 sizeof(vport_update_params.rss_params)); 1146 if (key) 1147 memcpy(qdev->rss_params.rss_key, rss_conf->rss_key, 1148 rss_conf->rss_key_len); 1149 vport_update_params.update_rss_flg = 1; 1150 qdev->rss_enabled = 1; 1151 } else { 1152 /* Disable RSS */ 1153 qdev->rss_enabled = 0; 1154 } 1155 1156 /* If the mapping doesn't fit any supported, return */ 1157 if (qdev->rss_params.rss_caps == 0 && hf != 0) 1158 return -EINVAL; 1159 1160 DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ? 1161 "Enabling RSS" : "Disabling RSS"); 1162 1163 vport_update_params.vport_id = 0; 1164 1165 return qdev->ops->vport_update(edev, &vport_update_params); 1166 } 1167 1168 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1169 struct rte_eth_rss_conf *rss_conf) 1170 { 1171 struct qede_dev *qdev = eth_dev->data->dev_private; 1172 uint64_t hf; 1173 1174 if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key)) 1175 return -EINVAL; 1176 1177 if (rss_conf->rss_key) 1178 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key, 1179 sizeof(qdev->rss_params.rss_key)); 1180 1181 hf = 0; 1182 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4) ? 1183 ETH_RSS_IPV4 : 0; 1184 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? 1185 ETH_RSS_IPV6 : 0; 1186 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? 1187 ETH_RSS_IPV6_EX : 0; 1188 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ? 1189 ETH_RSS_NONFRAG_IPV4_TCP : 0; 1190 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? 1191 ETH_RSS_NONFRAG_IPV6_TCP : 0; 1192 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? 1193 ETH_RSS_IPV6_TCP_EX : 0; 1194 1195 rss_conf->rss_hf = hf; 1196 1197 return 0; 1198 } 1199 1200 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 1201 struct rte_eth_rss_reta_entry64 *reta_conf, 1202 uint16_t reta_size) 1203 { 1204 struct qed_update_vport_params vport_update_params; 1205 struct qede_dev *qdev = eth_dev->data->dev_private; 1206 struct ecore_dev *edev = &qdev->edev; 1207 uint16_t i, idx, shift; 1208 1209 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1210 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 1211 reta_size); 1212 return -EINVAL; 1213 } 1214 1215 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1216 memcpy(&vport_update_params.rss_params, &qdev->rss_params, 1217 sizeof(vport_update_params.rss_params)); 1218 1219 for (i = 0; i < reta_size; i++) { 1220 idx = i / RTE_RETA_GROUP_SIZE; 1221 shift = i % RTE_RETA_GROUP_SIZE; 1222 if (reta_conf[idx].mask & (1ULL << shift)) { 1223 uint8_t entry = reta_conf[idx].reta[shift]; 1224 qdev->rss_params.rss_ind_table[i] = entry; 1225 } 1226 } 1227 1228 vport_update_params.update_rss_flg = 1; 1229 vport_update_params.vport_id = 0; 1230 1231 return qdev->ops->vport_update(edev, &vport_update_params); 1232 } 1233 1234 int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 1235 struct rte_eth_rss_reta_entry64 *reta_conf, 1236 uint16_t reta_size) 1237 { 1238 struct qede_dev *qdev = eth_dev->data->dev_private; 1239 uint16_t i, idx, shift; 1240 1241 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1242 struct ecore_dev *edev = &qdev->edev; 1243 DP_ERR(edev, "reta_size %d is not supported\n", 1244 reta_size); 1245 } 1246 1247 for (i = 0; i < reta_size; i++) { 1248 idx = i / RTE_RETA_GROUP_SIZE; 1249 shift = i % RTE_RETA_GROUP_SIZE; 1250 if (reta_conf[idx].mask & (1ULL << shift)) { 1251 uint8_t entry = qdev->rss_params.rss_ind_table[i]; 1252 reta_conf[idx].reta[shift] = entry; 1253 } 1254 } 1255 1256 return 0; 1257 } 1258 1259 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1260 { 1261 uint32_t frame_size; 1262 struct qede_dev *qdev = dev->data->dev_private; 1263 struct rte_eth_dev_info dev_info = {0}; 1264 1265 qede_dev_info_get(dev, &dev_info); 1266 1267 /* VLAN_TAG = 4 */ 1268 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4; 1269 1270 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 1271 return -EINVAL; 1272 1273 if (!dev->data->scattered_rx && 1274 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 1275 return -EINVAL; 1276 1277 if (frame_size > ETHER_MAX_LEN) 1278 dev->data->dev_conf.rxmode.jumbo_frame = 1; 1279 else 1280 dev->data->dev_conf.rxmode.jumbo_frame = 0; 1281 1282 /* update max frame size */ 1283 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1284 qdev->mtu = mtu; 1285 qede_dev_stop(dev); 1286 qede_dev_start(dev); 1287 1288 return 0; 1289 } 1290 1291 static const struct eth_dev_ops qede_eth_dev_ops = { 1292 .dev_configure = qede_dev_configure, 1293 .dev_infos_get = qede_dev_info_get, 1294 .rx_queue_setup = qede_rx_queue_setup, 1295 .rx_queue_release = qede_rx_queue_release, 1296 .tx_queue_setup = qede_tx_queue_setup, 1297 .tx_queue_release = qede_tx_queue_release, 1298 .dev_start = qede_dev_start, 1299 .dev_set_link_up = qede_dev_set_link_up, 1300 .dev_set_link_down = qede_dev_set_link_down, 1301 .link_update = qede_link_update, 1302 .promiscuous_enable = qede_promiscuous_enable, 1303 .promiscuous_disable = qede_promiscuous_disable, 1304 .allmulticast_enable = qede_allmulticast_enable, 1305 .allmulticast_disable = qede_allmulticast_disable, 1306 .dev_stop = qede_dev_stop, 1307 .dev_close = qede_dev_close, 1308 .stats_get = qede_get_stats, 1309 .stats_reset = qede_reset_stats, 1310 .xstats_get = qede_get_xstats, 1311 .xstats_reset = qede_reset_xstats, 1312 .xstats_get_names = qede_get_xstats_names, 1313 .mac_addr_add = qede_mac_addr_add, 1314 .mac_addr_remove = qede_mac_addr_remove, 1315 .mac_addr_set = qede_mac_addr_set, 1316 .vlan_offload_set = qede_vlan_offload_set, 1317 .vlan_filter_set = qede_vlan_filter_set, 1318 .flow_ctrl_set = qede_flow_ctrl_set, 1319 .flow_ctrl_get = qede_flow_ctrl_get, 1320 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 1321 .rss_hash_update = qede_rss_hash_update, 1322 .rss_hash_conf_get = qede_rss_hash_conf_get, 1323 .reta_update = qede_rss_reta_update, 1324 .reta_query = qede_rss_reta_query, 1325 .mtu_set = qede_set_mtu, 1326 }; 1327 1328 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 1329 .dev_configure = qede_dev_configure, 1330 .dev_infos_get = qede_dev_info_get, 1331 .rx_queue_setup = qede_rx_queue_setup, 1332 .rx_queue_release = qede_rx_queue_release, 1333 .tx_queue_setup = qede_tx_queue_setup, 1334 .tx_queue_release = qede_tx_queue_release, 1335 .dev_start = qede_dev_start, 1336 .dev_set_link_up = qede_dev_set_link_up, 1337 .dev_set_link_down = qede_dev_set_link_down, 1338 .link_update = qede_link_update, 1339 .promiscuous_enable = qede_promiscuous_enable, 1340 .promiscuous_disable = qede_promiscuous_disable, 1341 .allmulticast_enable = qede_allmulticast_enable, 1342 .allmulticast_disable = qede_allmulticast_disable, 1343 .dev_stop = qede_dev_stop, 1344 .dev_close = qede_dev_close, 1345 .stats_get = qede_get_stats, 1346 .stats_reset = qede_reset_stats, 1347 .xstats_get = qede_get_xstats, 1348 .xstats_reset = qede_reset_xstats, 1349 .xstats_get_names = qede_get_xstats_names, 1350 .vlan_offload_set = qede_vlan_offload_set, 1351 .vlan_filter_set = qede_vlan_filter_set, 1352 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 1353 .rss_hash_update = qede_rss_hash_update, 1354 .rss_hash_conf_get = qede_rss_hash_conf_get, 1355 .reta_update = qede_rss_reta_update, 1356 .reta_query = qede_rss_reta_query, 1357 .mtu_set = qede_set_mtu, 1358 }; 1359 1360 static void qede_update_pf_params(struct ecore_dev *edev) 1361 { 1362 struct ecore_pf_params pf_params; 1363 /* 32 rx + 32 tx */ 1364 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 1365 pf_params.eth_pf_params.num_cons = 64; 1366 qed_ops->common->update_pf_params(edev, &pf_params); 1367 } 1368 1369 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 1370 { 1371 struct rte_pci_device *pci_dev; 1372 struct rte_pci_addr pci_addr; 1373 struct qede_dev *adapter; 1374 struct ecore_dev *edev; 1375 struct qed_dev_eth_info dev_info; 1376 struct qed_slowpath_params params; 1377 static bool do_once = true; 1378 uint8_t bulletin_change; 1379 uint8_t vf_mac[ETHER_ADDR_LEN]; 1380 uint8_t is_mac_forced; 1381 bool is_mac_exist; 1382 /* Fix up ecore debug level */ 1383 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 1384 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 1385 uint32_t max_mac_addrs; 1386 int rc; 1387 1388 /* Extract key data structures */ 1389 adapter = eth_dev->data->dev_private; 1390 edev = &adapter->edev; 1391 pci_addr = eth_dev->pci_dev->addr; 1392 1393 PMD_INIT_FUNC_TRACE(edev); 1394 1395 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 1396 pci_addr.bus, pci_addr.devid, pci_addr.function, 1397 eth_dev->data->port_id); 1398 1399 eth_dev->rx_pkt_burst = qede_recv_pkts; 1400 eth_dev->tx_pkt_burst = qede_xmit_pkts; 1401 1402 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1403 DP_NOTICE(edev, false, 1404 "Skipping device init from secondary process\n"); 1405 return 0; 1406 } 1407 1408 pci_dev = eth_dev->pci_dev; 1409 1410 rte_eth_copy_pci_info(eth_dev, pci_dev); 1411 1412 qed_ops = qed_get_eth_ops(); 1413 if (!qed_ops) { 1414 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 1415 return -EINVAL; 1416 } 1417 1418 DP_INFO(edev, "Starting qede probe\n"); 1419 1420 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH, 1421 dp_module, dp_level, is_vf); 1422 1423 if (rc != 0) { 1424 DP_ERR(edev, "qede probe failed rc %d\n", rc); 1425 return -ENODEV; 1426 } 1427 1428 qede_update_pf_params(edev); 1429 1430 rte_intr_callback_register(ð_dev->pci_dev->intr_handle, 1431 qede_interrupt_handler, (void *)eth_dev); 1432 1433 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) { 1434 DP_ERR(edev, "rte_intr_enable() failed\n"); 1435 return -ENODEV; 1436 } 1437 1438 /* Start the Slowpath-process */ 1439 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 1440 params.int_mode = ECORE_INT_MODE_MSIX; 1441 params.drv_major = QEDE_PMD_VERSION_MAJOR; 1442 params.drv_minor = QEDE_PMD_VERSION_MINOR; 1443 params.drv_rev = QEDE_PMD_VERSION_REVISION; 1444 params.drv_eng = QEDE_PMD_VERSION_PATCH; 1445 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 1446 QEDE_PMD_DRV_VER_STR_SIZE); 1447 1448 /* For CMT mode device do periodic polling for slowpath events. 1449 * This is required since uio device uses only one MSI-x 1450 * interrupt vector but we need one for each engine. 1451 */ 1452 if (edev->num_hwfns > 1 && IS_PF(edev)) { 1453 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1454 qede_poll_sp_sb_cb, 1455 (void *)eth_dev); 1456 if (rc != 0) { 1457 DP_ERR(edev, "Unable to start periodic" 1458 " timer rc %d\n", rc); 1459 return -EINVAL; 1460 } 1461 } 1462 1463 rc = qed_ops->common->slowpath_start(edev, ¶ms); 1464 if (rc) { 1465 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 1466 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1467 (void *)eth_dev); 1468 return -ENODEV; 1469 } 1470 1471 rc = qed_ops->fill_dev_info(edev, &dev_info); 1472 if (rc) { 1473 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 1474 qed_ops->common->slowpath_stop(edev); 1475 qed_ops->common->remove(edev); 1476 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1477 (void *)eth_dev); 1478 return -ENODEV; 1479 } 1480 1481 qede_alloc_etherdev(adapter, &dev_info); 1482 1483 adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION); 1484 1485 if (!is_vf) 1486 adapter->dev_info.num_mac_addrs = 1487 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 1488 ECORE_MAC); 1489 else 1490 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 1491 &adapter->dev_info.num_mac_addrs); 1492 1493 /* Allocate memory for storing MAC addr */ 1494 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 1495 (ETHER_ADDR_LEN * 1496 adapter->dev_info.num_mac_addrs), 1497 RTE_CACHE_LINE_SIZE); 1498 1499 if (eth_dev->data->mac_addrs == NULL) { 1500 DP_ERR(edev, "Failed to allocate MAC address\n"); 1501 qed_ops->common->slowpath_stop(edev); 1502 qed_ops->common->remove(edev); 1503 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1504 (void *)eth_dev); 1505 return -ENOMEM; 1506 } 1507 1508 if (!is_vf) { 1509 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 1510 hw_info.hw_mac_addr, 1511 ð_dev->data->mac_addrs[0]); 1512 ether_addr_copy(ð_dev->data->mac_addrs[0], 1513 &adapter->primary_mac); 1514 } else { 1515 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 1516 &bulletin_change); 1517 if (bulletin_change) { 1518 is_mac_exist = 1519 ecore_vf_bulletin_get_forced_mac( 1520 ECORE_LEADING_HWFN(edev), 1521 vf_mac, 1522 &is_mac_forced); 1523 if (is_mac_exist && is_mac_forced) { 1524 DP_INFO(edev, "VF macaddr received from PF\n"); 1525 ether_addr_copy((struct ether_addr *)&vf_mac, 1526 ð_dev->data->mac_addrs[0]); 1527 ether_addr_copy(ð_dev->data->mac_addrs[0], 1528 &adapter->primary_mac); 1529 } else { 1530 DP_NOTICE(edev, false, 1531 "No VF macaddr assigned\n"); 1532 } 1533 } 1534 } 1535 1536 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 1537 1538 if (do_once) { 1539 qede_print_adapter_info(adapter); 1540 do_once = false; 1541 } 1542 1543 adapter->state = QEDE_DEV_INIT; 1544 1545 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 1546 adapter->primary_mac.addr_bytes[0], 1547 adapter->primary_mac.addr_bytes[1], 1548 adapter->primary_mac.addr_bytes[2], 1549 adapter->primary_mac.addr_bytes[3], 1550 adapter->primary_mac.addr_bytes[4], 1551 adapter->primary_mac.addr_bytes[5]); 1552 1553 return rc; 1554 } 1555 1556 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 1557 { 1558 return qede_common_dev_init(eth_dev, 1); 1559 } 1560 1561 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 1562 { 1563 return qede_common_dev_init(eth_dev, 0); 1564 } 1565 1566 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 1567 { 1568 /* only uninitialize in the primary process */ 1569 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1570 return 0; 1571 1572 /* safe to close dev here */ 1573 qede_dev_close(eth_dev); 1574 1575 eth_dev->dev_ops = NULL; 1576 eth_dev->rx_pkt_burst = NULL; 1577 eth_dev->tx_pkt_burst = NULL; 1578 1579 if (eth_dev->data->mac_addrs) 1580 rte_free(eth_dev->data->mac_addrs); 1581 1582 eth_dev->data->mac_addrs = NULL; 1583 1584 return 0; 1585 } 1586 1587 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 1588 { 1589 return qede_dev_common_uninit(eth_dev); 1590 } 1591 1592 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 1593 { 1594 return qede_dev_common_uninit(eth_dev); 1595 } 1596 1597 static struct rte_pci_id pci_id_qedevf_map[] = { 1598 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 1599 { 1600 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF) 1601 }, 1602 { 1603 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV) 1604 }, 1605 {.vendor_id = 0,} 1606 }; 1607 1608 static struct rte_pci_id pci_id_qede_map[] = { 1609 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 1610 { 1611 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E) 1612 }, 1613 { 1614 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S) 1615 }, 1616 { 1617 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40) 1618 }, 1619 { 1620 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25) 1621 }, 1622 { 1623 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100) 1624 }, 1625 {.vendor_id = 0,} 1626 }; 1627 1628 static struct eth_driver rte_qedevf_pmd = { 1629 .pci_drv = { 1630 .id_table = pci_id_qedevf_map, 1631 .drv_flags = 1632 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1633 .probe = rte_eth_dev_pci_probe, 1634 .remove = rte_eth_dev_pci_remove, 1635 }, 1636 .eth_dev_init = qedevf_eth_dev_init, 1637 .eth_dev_uninit = qedevf_eth_dev_uninit, 1638 .dev_private_size = sizeof(struct qede_dev), 1639 }; 1640 1641 static struct eth_driver rte_qede_pmd = { 1642 .pci_drv = { 1643 .id_table = pci_id_qede_map, 1644 .drv_flags = 1645 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1646 .probe = rte_eth_dev_pci_probe, 1647 .remove = rte_eth_dev_pci_remove, 1648 }, 1649 .eth_dev_init = qede_eth_dev_init, 1650 .eth_dev_uninit = qede_eth_dev_uninit, 1651 .dev_private_size = sizeof(struct qede_dev), 1652 }; 1653 1654 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv); 1655 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 1656 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv); 1657 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 1658