1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static const char *drivername = "qede pmd"; 16 static int64_t timer_period = 1; 17 18 struct rte_qede_xstats_name_off { 19 char name[RTE_ETH_XSTATS_NAME_SIZE]; 20 uint64_t offset; 21 }; 22 23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 24 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, 25 {"rx_multicast_bytes", 26 offsetof(struct ecore_eth_stats, rx_mcast_bytes)}, 27 {"rx_broadcast_bytes", 28 offsetof(struct ecore_eth_stats, rx_bcast_bytes)}, 29 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)}, 30 {"rx_multicast_packets", 31 offsetof(struct ecore_eth_stats, rx_mcast_pkts)}, 32 {"rx_broadcast_packets", 33 offsetof(struct ecore_eth_stats, rx_bcast_pkts)}, 34 35 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)}, 36 {"tx_multicast_bytes", 37 offsetof(struct ecore_eth_stats, tx_mcast_bytes)}, 38 {"tx_broadcast_bytes", 39 offsetof(struct ecore_eth_stats, tx_bcast_bytes)}, 40 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)}, 41 {"tx_multicast_packets", 42 offsetof(struct ecore_eth_stats, tx_mcast_pkts)}, 43 {"tx_broadcast_packets", 44 offsetof(struct ecore_eth_stats, tx_bcast_pkts)}, 45 46 {"rx_64_byte_packets", 47 offsetof(struct ecore_eth_stats, rx_64_byte_packets)}, 48 {"rx_65_to_127_byte_packets", 49 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)}, 50 {"rx_128_to_255_byte_packets", 51 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)}, 52 {"rx_256_to_511_byte_packets", 53 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)}, 54 {"rx_512_to_1023_byte_packets", 55 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)}, 56 {"rx_1024_to_1518_byte_packets", 57 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)}, 58 {"rx_1519_to_1522_byte_packets", 59 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)}, 60 {"rx_1519_to_2047_byte_packets", 61 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)}, 62 {"rx_2048_to_4095_byte_packets", 63 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)}, 64 {"rx_4096_to_9216_byte_packets", 65 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)}, 66 {"rx_9217_to_16383_byte_packets", 67 offsetof(struct ecore_eth_stats, 68 rx_9217_to_16383_byte_packets)}, 69 {"tx_64_byte_packets", 70 offsetof(struct ecore_eth_stats, tx_64_byte_packets)}, 71 {"tx_65_to_127_byte_packets", 72 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)}, 73 {"tx_128_to_255_byte_packets", 74 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)}, 75 {"tx_256_to_511_byte_packets", 76 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)}, 77 {"tx_512_to_1023_byte_packets", 78 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)}, 79 {"tx_1024_to_1518_byte_packets", 80 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)}, 81 {"trx_1519_to_1522_byte_packets", 82 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)}, 83 {"tx_2048_to_4095_byte_packets", 84 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)}, 85 {"tx_4096_to_9216_byte_packets", 86 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)}, 87 {"tx_9217_to_16383_byte_packets", 88 offsetof(struct ecore_eth_stats, 89 tx_9217_to_16383_byte_packets)}, 90 91 {"rx_mac_crtl_frames", 92 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)}, 93 {"tx_mac_control_frames", 94 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)}, 95 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)}, 96 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)}, 97 {"rx_priority_flow_control_frames", 98 offsetof(struct ecore_eth_stats, rx_pfc_frames)}, 99 {"tx_priority_flow_control_frames", 100 offsetof(struct ecore_eth_stats, tx_pfc_frames)}, 101 102 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)}, 103 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)}, 104 {"rx_carrier_errors", 105 offsetof(struct ecore_eth_stats, rx_carrier_errors)}, 106 {"rx_oversize_packet_errors", 107 offsetof(struct ecore_eth_stats, rx_oversize_packets)}, 108 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)}, 109 {"rx_undersize_packet_errors", 110 offsetof(struct ecore_eth_stats, rx_undersize_packets)}, 111 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)}, 112 {"rx_host_buffer_not_available", 113 offsetof(struct ecore_eth_stats, no_buff_discards)}, 114 /* Number of packets discarded because they are bigger than MTU */ 115 {"rx_packet_too_big_discards", 116 offsetof(struct ecore_eth_stats, packet_too_big_discard)}, 117 {"rx_ttl_zero_discards", 118 offsetof(struct ecore_eth_stats, ttl0_discard)}, 119 {"rx_multi_function_tag_filter_discards", 120 offsetof(struct ecore_eth_stats, mftag_filter_discards)}, 121 {"rx_mac_filter_discards", 122 offsetof(struct ecore_eth_stats, mac_filter_discards)}, 123 {"rx_hw_buffer_truncates", 124 offsetof(struct ecore_eth_stats, brb_truncates)}, 125 {"rx_hw_buffer_discards", 126 offsetof(struct ecore_eth_stats, brb_discards)}, 127 {"tx_lpi_entry_count", 128 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)}, 129 {"tx_total_collisions", 130 offsetof(struct ecore_eth_stats, tx_total_collisions)}, 131 {"tx_error_drop_packets", 132 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)}, 133 134 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)}, 135 {"rx_mac_unicast_packets", 136 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)}, 137 {"rx_mac_multicast_packets", 138 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)}, 139 {"rx_mac_broadcast_packets", 140 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)}, 141 {"rx_mac_frames_ok", 142 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)}, 143 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)}, 144 {"tx_mac_unicast_packets", 145 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)}, 146 {"tx_mac_multicast_packets", 147 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)}, 148 {"tx_mac_broadcast_packets", 149 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)}, 150 151 {"lro_coalesced_packets", 152 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)}, 153 {"lro_coalesced_events", 154 offsetof(struct ecore_eth_stats, tpa_coalesced_events)}, 155 {"lro_aborts_num", 156 offsetof(struct ecore_eth_stats, tpa_aborts_num)}, 157 {"lro_not_coalesced_packets", 158 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)}, 159 {"lro_coalesced_bytes", 160 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)}, 161 }; 162 163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 164 {"rx_q_segments", 165 offsetof(struct qede_rx_queue, rx_segs)}, 166 {"rx_q_hw_errors", 167 offsetof(struct qede_rx_queue, rx_hw_errors)}, 168 {"rx_q_allocation_errors", 169 offsetof(struct qede_rx_queue, rx_alloc_errors)} 170 }; 171 172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 173 { 174 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 175 } 176 177 static void 178 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param) 179 { 180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 181 struct qede_dev *qdev = eth_dev->data->dev_private; 182 struct ecore_dev *edev = &qdev->edev; 183 184 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 185 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) 186 DP_ERR(edev, "rte_intr_enable failed\n"); 187 } 188 189 static void 190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 191 { 192 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 193 qdev->num_tc = qdev->dev_info.num_tc; 194 qdev->ops = qed_ops; 195 } 196 197 static void qede_print_adapter_info(struct qede_dev *qdev) 198 { 199 struct ecore_dev *edev = &qdev->edev; 200 struct qed_dev_info *info = &qdev->dev_info.common; 201 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 202 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 203 204 DP_INFO(edev, "*********************************\n"); 205 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 206 DP_INFO(edev, " Chip details : %s%d\n", 207 ECORE_IS_BB(edev) ? "BB" : "AH", 208 CHIP_REV_IS_A0(edev) ? 0 : 1); 209 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 210 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 211 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 212 ver_str, QEDE_PMD_VERSION); 213 DP_INFO(edev, " Driver version : %s\n", drv_ver); 214 DP_INFO(edev, " Firmware version : %s\n", ver_str); 215 216 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 217 "%d.%d.%d.%d", 218 (info->mfw_rev >> 24) & 0xff, 219 (info->mfw_rev >> 16) & 0xff, 220 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 221 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 222 DP_INFO(edev, " Firmware file : %s\n", fw_file); 223 DP_INFO(edev, "*********************************\n"); 224 } 225 226 static int 227 qede_set_ucast_rx_mac(struct qede_dev *qdev, 228 enum qed_filter_xcast_params_type opcode, 229 uint8_t mac[ETHER_ADDR_LEN]) 230 { 231 struct ecore_dev *edev = &qdev->edev; 232 struct qed_filter_params filter_cmd; 233 234 memset(&filter_cmd, 0, sizeof(filter_cmd)); 235 filter_cmd.type = QED_FILTER_TYPE_UCAST; 236 filter_cmd.filter.ucast.type = opcode; 237 filter_cmd.filter.ucast.mac_valid = 1; 238 rte_memcpy(&filter_cmd.filter.ucast.mac[0], &mac[0], ETHER_ADDR_LEN); 239 return qdev->ops->filter_config(edev, &filter_cmd); 240 } 241 242 static void 243 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 244 uint32_t index, __rte_unused uint32_t pool) 245 { 246 struct qede_dev *qdev = eth_dev->data->dev_private; 247 struct ecore_dev *edev = &qdev->edev; 248 int rc; 249 250 PMD_INIT_FUNC_TRACE(edev); 251 252 if (index >= qdev->dev_info.num_mac_addrs) { 253 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 254 index, qdev->dev_info.num_mac_addrs); 255 return; 256 } 257 258 /* Adding macaddr even though promiscuous mode is set */ 259 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 260 DP_INFO(edev, "Port is in promisc mode, yet adding it\n"); 261 262 /* Add MAC filters according to the unicast secondary macs */ 263 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD, 264 mac_addr->addr_bytes); 265 if (rc) 266 DP_ERR(edev, "Unable to add macaddr rc=%d\n", rc); 267 } 268 269 static void 270 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 271 { 272 struct qede_dev *qdev = eth_dev->data->dev_private; 273 struct ecore_dev *edev = &qdev->edev; 274 struct ether_addr mac_addr; 275 int rc; 276 277 PMD_INIT_FUNC_TRACE(edev); 278 279 if (index >= qdev->dev_info.num_mac_addrs) { 280 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 281 index, qdev->dev_info.num_mac_addrs); 282 return; 283 } 284 285 /* Use the index maintained by rte */ 286 ether_addr_copy(ð_dev->data->mac_addrs[index], &mac_addr); 287 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL, 288 mac_addr.addr_bytes); 289 if (rc) 290 DP_ERR(edev, "Unable to remove macaddr rc=%d\n", rc); 291 } 292 293 static void 294 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 295 { 296 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 297 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 298 int rc; 299 300 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 301 mac_addr->addr_bytes)) { 302 DP_ERR(edev, "Setting MAC address is not allowed\n"); 303 ether_addr_copy(&qdev->primary_mac, 304 ð_dev->data->mac_addrs[0]); 305 return; 306 } 307 308 /* First remove the primary mac */ 309 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL, 310 qdev->primary_mac.addr_bytes); 311 312 if (rc) { 313 DP_ERR(edev, "Unable to remove current macaddr" 314 " Reverting to previous default mac\n"); 315 ether_addr_copy(&qdev->primary_mac, 316 ð_dev->data->mac_addrs[0]); 317 return; 318 } 319 320 /* Add new MAC */ 321 rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD, 322 mac_addr->addr_bytes); 323 324 if (rc) 325 DP_ERR(edev, "Unable to add new default mac\n"); 326 else 327 ether_addr_copy(mac_addr, &qdev->primary_mac); 328 } 329 330 331 332 333 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action) 334 { 335 struct ecore_dev *edev = &qdev->edev; 336 struct qed_update_vport_params params = { 337 .vport_id = 0, 338 .accept_any_vlan = action, 339 .update_accept_any_vlan_flg = 1, 340 }; 341 int rc; 342 343 /* Proceed only if action actually needs to be performed */ 344 if (qdev->accept_any_vlan == action) 345 return; 346 347 rc = qdev->ops->vport_update(edev, ¶ms); 348 if (rc) { 349 DP_ERR(edev, "Failed to %s accept-any-vlan\n", 350 action ? "enable" : "disable"); 351 } else { 352 DP_INFO(edev, "%s accept-any-vlan\n", 353 action ? "enabled" : "disabled"); 354 qdev->accept_any_vlan = action; 355 } 356 } 357 358 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping) 359 { 360 struct qed_update_vport_params vport_update_params; 361 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 362 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 363 int rc; 364 365 memset(&vport_update_params, 0, sizeof(vport_update_params)); 366 vport_update_params.vport_id = 0; 367 vport_update_params.update_inner_vlan_removal_flg = 1; 368 vport_update_params.inner_vlan_removal_flg = set_stripping; 369 rc = qdev->ops->vport_update(edev, &vport_update_params); 370 if (rc) { 371 DP_ERR(edev, "Update V-PORT failed %d\n", rc); 372 return rc; 373 } 374 375 return 0; 376 } 377 378 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 379 { 380 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 381 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 382 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 383 384 if (mask & ETH_VLAN_STRIP_MASK) { 385 if (rxmode->hw_vlan_strip) 386 (void)qede_vlan_stripping(eth_dev, 1); 387 else 388 (void)qede_vlan_stripping(eth_dev, 0); 389 } 390 391 if (mask & ETH_VLAN_FILTER_MASK) { 392 /* VLAN filtering kicks in when a VLAN is added */ 393 if (rxmode->hw_vlan_filter) { 394 qede_vlan_filter_set(eth_dev, 0, 1); 395 } else { 396 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 397 DP_NOTICE(edev, false, 398 " Please remove existing VLAN filters" 399 " before disabling VLAN filtering\n"); 400 /* Signal app that VLAN filtering is still 401 * enabled 402 */ 403 rxmode->hw_vlan_filter = true; 404 } else { 405 qede_vlan_filter_set(eth_dev, 0, 0); 406 } 407 } 408 } 409 410 if (mask & ETH_VLAN_EXTEND_MASK) 411 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 412 " and classification is based on outer tag only\n"); 413 414 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 415 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 416 } 417 418 static int qede_set_ucast_rx_vlan(struct qede_dev *qdev, 419 enum qed_filter_xcast_params_type opcode, 420 uint16_t vid) 421 { 422 struct qed_filter_params filter_cmd; 423 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 424 425 memset(&filter_cmd, 0, sizeof(filter_cmd)); 426 filter_cmd.type = QED_FILTER_TYPE_UCAST; 427 filter_cmd.filter.ucast.type = opcode; 428 filter_cmd.filter.ucast.vlan_valid = 1; 429 filter_cmd.filter.ucast.vlan = vid; 430 431 return qdev->ops->filter_config(edev, &filter_cmd); 432 } 433 434 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 435 uint16_t vlan_id, int on) 436 { 437 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 438 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 439 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 440 struct qede_vlan_entry *tmp = NULL; 441 struct qede_vlan_entry *vlan; 442 int rc; 443 444 if (on) { 445 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 446 DP_INFO(edev, "Reached max VLAN filter limit" 447 " enabling accept_any_vlan\n"); 448 qede_config_accept_any_vlan(qdev, true); 449 return 0; 450 } 451 452 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 453 if (tmp->vid == vlan_id) { 454 DP_ERR(edev, "VLAN %u already configured\n", 455 vlan_id); 456 return -EEXIST; 457 } 458 } 459 460 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 461 RTE_CACHE_LINE_SIZE); 462 463 if (!vlan) { 464 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 465 return -ENOMEM; 466 } 467 468 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_ADD, 469 vlan_id); 470 if (rc) { 471 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 472 rc); 473 rte_free(vlan); 474 } else { 475 vlan->vid = vlan_id; 476 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 477 qdev->configured_vlans++; 478 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 479 vlan_id, qdev->configured_vlans); 480 } 481 } else { 482 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 483 if (tmp->vid == vlan_id) 484 break; 485 } 486 487 if (!tmp) { 488 if (qdev->configured_vlans == 0) { 489 DP_INFO(edev, 490 "No VLAN filters configured yet\n"); 491 return 0; 492 } 493 494 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 495 return -EINVAL; 496 } 497 498 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 499 500 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_DEL, 501 vlan_id); 502 if (rc) { 503 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 504 vlan_id, rc); 505 } else { 506 qdev->configured_vlans--; 507 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 508 vlan_id, qdev->configured_vlans); 509 } 510 } 511 512 return rc; 513 } 514 515 static int qede_init_vport(struct qede_dev *qdev) 516 { 517 struct ecore_dev *edev = &qdev->edev; 518 struct qed_start_vport_params start = {0}; 519 int rc; 520 521 start.remove_inner_vlan = 1; 522 start.gro_enable = 0; 523 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD; 524 start.vport_id = 0; 525 start.drop_ttl0 = false; 526 start.clear_stats = 1; 527 start.handle_ptp_pkts = 0; 528 529 rc = qdev->ops->vport_start(edev, &start); 530 if (rc) { 531 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 532 return rc; 533 } 534 535 DP_INFO(edev, 536 "Start vport ramrod passed, vport_id = %d, MTU = %u\n", 537 start.vport_id, ETHER_MTU); 538 539 return 0; 540 } 541 542 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 543 { 544 struct qede_dev *qdev = eth_dev->data->dev_private; 545 struct ecore_dev *edev = &qdev->edev; 546 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 547 int rc, i, j; 548 549 PMD_INIT_FUNC_TRACE(edev); 550 551 /* Check requirements for 100G mode */ 552 if (edev->num_hwfns > 1) { 553 if (eth_dev->data->nb_rx_queues < 2 || 554 eth_dev->data->nb_tx_queues < 2) { 555 DP_NOTICE(edev, false, 556 "100G mode needs min. 2 RX/TX queues\n"); 557 return -EINVAL; 558 } 559 560 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 561 (eth_dev->data->nb_tx_queues % 2 != 0)) { 562 DP_NOTICE(edev, false, 563 "100G mode needs even no. of RX/TX queues\n"); 564 return -EINVAL; 565 } 566 } 567 568 /* Sanity checks and throw warnings */ 569 if (rxmode->enable_scatter == 1) 570 eth_dev->data->scattered_rx = 1; 571 572 if (rxmode->enable_lro == 1) { 573 DP_INFO(edev, "LRO is not supported\n"); 574 return -EINVAL; 575 } 576 577 if (!rxmode->hw_strip_crc) 578 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 579 580 if (!rxmode->hw_ip_checksum) 581 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 582 "in hw\n"); 583 584 /* Check for the port restart case */ 585 if (qdev->state != QEDE_DEV_INIT) { 586 rc = qdev->ops->vport_stop(edev, 0); 587 if (rc != 0) 588 return rc; 589 qede_dealloc_fp_resc(eth_dev); 590 } 591 592 qdev->fp_num_tx = eth_dev->data->nb_tx_queues; 593 qdev->fp_num_rx = eth_dev->data->nb_rx_queues; 594 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx; 595 596 /* Fastpath status block should be initialized before sending 597 * VPORT-START in the case of VF. Anyway, do it for both VF/PF. 598 */ 599 rc = qede_alloc_fp_resc(qdev); 600 if (rc != 0) 601 return rc; 602 603 /* Issue VPORT-START with default config values to allow 604 * other port configurations early on. 605 */ 606 rc = qede_init_vport(qdev); 607 if (rc != 0) 608 return rc; 609 610 SLIST_INIT(&qdev->vlan_list_head); 611 612 /* Add primary mac for PF */ 613 if (IS_PF(edev)) 614 qede_mac_addr_set(eth_dev, &qdev->primary_mac); 615 616 /* Enable VLAN offloads by default */ 617 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 618 ETH_VLAN_FILTER_MASK | 619 ETH_VLAN_EXTEND_MASK); 620 621 qdev->state = QEDE_DEV_CONFIG; 622 623 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n", 624 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev), 625 qdev->num_tc); 626 627 return 0; 628 } 629 630 /* Info about HW descriptor ring limitations */ 631 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 632 .nb_max = NUM_RX_BDS_MAX, 633 .nb_min = 128, 634 .nb_align = 128 /* lowest common multiple */ 635 }; 636 637 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 638 .nb_max = NUM_TX_BDS_MAX, 639 .nb_min = 256, 640 .nb_align = 256 641 }; 642 643 static void 644 qede_dev_info_get(struct rte_eth_dev *eth_dev, 645 struct rte_eth_dev_info *dev_info) 646 { 647 struct qede_dev *qdev = eth_dev->data->dev_private; 648 struct ecore_dev *edev = &qdev->edev; 649 struct qed_link_output link; 650 651 PMD_INIT_FUNC_TRACE(edev); 652 653 dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU + 654 QEDE_ETH_OVERHEAD); 655 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 656 dev_info->rx_desc_lim = qede_rx_desc_lim; 657 dev_info->tx_desc_lim = qede_tx_desc_lim; 658 dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev); 659 dev_info->max_tx_queues = dev_info->max_rx_queues; 660 dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs; 661 if (IS_VF(edev)) 662 dev_info->max_vfs = 0; 663 else 664 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev); 665 dev_info->driver_name = qdev->drv_ver; 666 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 667 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 668 669 dev_info->default_txconf = (struct rte_eth_txconf) { 670 .txq_flags = QEDE_TXQ_FLAGS, 671 }; 672 673 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 674 DEV_RX_OFFLOAD_IPV4_CKSUM | 675 DEV_RX_OFFLOAD_UDP_CKSUM | 676 DEV_RX_OFFLOAD_TCP_CKSUM); 677 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 678 DEV_TX_OFFLOAD_IPV4_CKSUM | 679 DEV_TX_OFFLOAD_UDP_CKSUM | 680 DEV_TX_OFFLOAD_TCP_CKSUM); 681 682 memset(&link, 0, sizeof(struct qed_link_output)); 683 qdev->ops->common->get_link(edev, &link); 684 dev_info->speed_capa = rte_eth_speed_bitflag(link.adv_speed, 0); 685 } 686 687 /* return 0 means link status changed, -1 means not changed */ 688 static int 689 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 690 { 691 struct qede_dev *qdev = eth_dev->data->dev_private; 692 struct ecore_dev *edev = &qdev->edev; 693 uint16_t link_duplex; 694 struct qed_link_output link; 695 struct rte_eth_link *curr = ð_dev->data->dev_link; 696 697 memset(&link, 0, sizeof(struct qed_link_output)); 698 qdev->ops->common->get_link(edev, &link); 699 700 /* Link Speed */ 701 curr->link_speed = link.speed; 702 703 /* Link Mode */ 704 switch (link.duplex) { 705 case QEDE_DUPLEX_HALF: 706 link_duplex = ETH_LINK_HALF_DUPLEX; 707 break; 708 case QEDE_DUPLEX_FULL: 709 link_duplex = ETH_LINK_FULL_DUPLEX; 710 break; 711 case QEDE_DUPLEX_UNKNOWN: 712 default: 713 link_duplex = -1; 714 } 715 curr->link_duplex = link_duplex; 716 717 /* Link Status */ 718 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 719 720 /* AN */ 721 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 722 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 723 724 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 725 curr->link_speed, curr->link_duplex, 726 curr->link_autoneg, curr->link_status); 727 728 /* return 0 means link status changed, -1 means not changed */ 729 return ((curr->link_status == link.link_up) ? -1 : 0); 730 } 731 732 static void 733 qede_rx_mode_setting(struct rte_eth_dev *eth_dev, 734 enum qed_filter_rx_mode_type accept_flags) 735 { 736 struct qede_dev *qdev = eth_dev->data->dev_private; 737 struct ecore_dev *edev = &qdev->edev; 738 struct qed_filter_params rx_mode; 739 740 DP_INFO(edev, "%s mode %u\n", __func__, accept_flags); 741 742 memset(&rx_mode, 0, sizeof(struct qed_filter_params)); 743 rx_mode.type = QED_FILTER_TYPE_RX_MODE; 744 rx_mode.filter.accept_flags = accept_flags; 745 qdev->ops->filter_config(edev, &rx_mode); 746 } 747 748 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 749 { 750 struct qede_dev *qdev = eth_dev->data->dev_private; 751 struct ecore_dev *edev = &qdev->edev; 752 753 PMD_INIT_FUNC_TRACE(edev); 754 755 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 756 757 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 758 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 759 760 qede_rx_mode_setting(eth_dev, type); 761 } 762 763 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 764 { 765 struct qede_dev *qdev = eth_dev->data->dev_private; 766 struct ecore_dev *edev = &qdev->edev; 767 768 PMD_INIT_FUNC_TRACE(edev); 769 770 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 771 qede_rx_mode_setting(eth_dev, 772 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 773 else 774 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR); 775 } 776 777 static void qede_poll_sp_sb_cb(void *param) 778 { 779 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 780 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 781 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 782 int rc; 783 784 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 785 qede_interrupt_action(&edev->hwfns[1]); 786 787 rc = rte_eal_alarm_set(timer_period * US_PER_S, 788 qede_poll_sp_sb_cb, 789 (void *)eth_dev); 790 if (rc != 0) { 791 DP_ERR(edev, "Unable to start periodic" 792 " timer rc %d\n", rc); 793 assert(false && "Unable to start periodic timer"); 794 } 795 } 796 797 static void qede_dev_close(struct rte_eth_dev *eth_dev) 798 { 799 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 800 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 801 int rc; 802 803 PMD_INIT_FUNC_TRACE(edev); 804 805 /* dev_stop() shall cleanup fp resources in hw but without releasing 806 * dma memories and sw structures so that dev_start() can be called 807 * by the app without reconfiguration. However, in dev_close() we 808 * can release all the resources and device can be brought up newly 809 */ 810 if (qdev->state != QEDE_DEV_STOP) 811 qede_dev_stop(eth_dev); 812 else 813 DP_INFO(edev, "Device is already stopped\n"); 814 815 rc = qdev->ops->vport_stop(edev, 0); 816 if (rc != 0) 817 DP_ERR(edev, "Failed to stop VPORT\n"); 818 819 qede_dealloc_fp_resc(eth_dev); 820 821 qdev->ops->common->slowpath_stop(edev); 822 823 qdev->ops->common->remove(edev); 824 825 rte_intr_disable(ð_dev->pci_dev->intr_handle); 826 827 rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle, 828 qede_interrupt_handler, (void *)eth_dev); 829 830 if (edev->num_hwfns > 1) 831 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 832 833 qdev->state = QEDE_DEV_INIT; /* Go back to init state */ 834 } 835 836 static void 837 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 838 { 839 struct qede_dev *qdev = eth_dev->data->dev_private; 840 struct ecore_dev *edev = &qdev->edev; 841 struct ecore_eth_stats stats; 842 unsigned int i = 0, j = 0, qid; 843 struct qede_tx_queue *txq; 844 845 qdev->ops->get_vport_stats(edev, &stats); 846 847 /* RX Stats */ 848 eth_stats->ipackets = stats.rx_ucast_pkts + 849 stats.rx_mcast_pkts + stats.rx_bcast_pkts; 850 851 eth_stats->ibytes = stats.rx_ucast_bytes + 852 stats.rx_mcast_bytes + stats.rx_bcast_bytes; 853 854 eth_stats->ierrors = stats.rx_crc_errors + 855 stats.rx_align_errors + 856 stats.rx_carrier_errors + 857 stats.rx_oversize_packets + 858 stats.rx_jabbers + stats.rx_undersize_packets; 859 860 eth_stats->rx_nombuf = stats.no_buff_discards; 861 862 eth_stats->imissed = stats.mftag_filter_discards + 863 stats.mac_filter_discards + 864 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards; 865 866 /* TX stats */ 867 eth_stats->opackets = stats.tx_ucast_pkts + 868 stats.tx_mcast_pkts + stats.tx_bcast_pkts; 869 870 eth_stats->obytes = stats.tx_ucast_bytes + 871 stats.tx_mcast_bytes + stats.tx_bcast_bytes; 872 873 eth_stats->oerrors = stats.tx_err_drop_pkts; 874 875 /* Queue stats */ 876 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 877 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 878 eth_stats->q_ipackets[i] = 879 *(uint64_t *)( 880 ((char *)(qdev->fp_array[(qid)].rxq)) + 881 offsetof(struct qede_rx_queue, 882 rcv_pkts)); 883 eth_stats->q_errors[i] = 884 *(uint64_t *)( 885 ((char *)(qdev->fp_array[(qid)].rxq)) + 886 offsetof(struct qede_rx_queue, 887 rx_hw_errors)) + 888 *(uint64_t *)( 889 ((char *)(qdev->fp_array[(qid)].rxq)) + 890 offsetof(struct qede_rx_queue, 891 rx_alloc_errors)); 892 i++; 893 } 894 895 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) { 896 txq = qdev->fp_array[(qid)].txqs[0]; 897 eth_stats->q_opackets[j] = 898 *((uint64_t *)(uintptr_t) 899 (((uint64_t)(uintptr_t)(txq)) + 900 offsetof(struct qede_tx_queue, 901 xmit_pkts))); 902 j++; 903 } 904 } 905 } 906 907 static unsigned 908 qede_get_xstats_count(struct qede_dev *qdev) { 909 return RTE_DIM(qede_xstats_strings) + 910 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev)); 911 } 912 913 static int 914 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, 915 struct rte_eth_xstat_name *xstats_names, unsigned limit) 916 { 917 struct qede_dev *qdev = dev->data->dev_private; 918 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 919 unsigned int i, qid, stat_idx = 0; 920 921 if (xstats_names != NULL) { 922 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 923 snprintf(xstats_names[stat_idx].name, 924 sizeof(xstats_names[stat_idx].name), 925 "%s", 926 qede_xstats_strings[i].name); 927 stat_idx++; 928 } 929 930 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) { 931 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 932 snprintf(xstats_names[stat_idx].name, 933 sizeof(xstats_names[stat_idx].name), 934 "%.4s%d%s", 935 qede_rxq_xstats_strings[i].name, qid, 936 qede_rxq_xstats_strings[i].name + 4); 937 stat_idx++; 938 } 939 } 940 } 941 942 return stat_cnt; 943 } 944 945 static int 946 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 947 unsigned int n) 948 { 949 struct qede_dev *qdev = dev->data->dev_private; 950 struct ecore_dev *edev = &qdev->edev; 951 struct ecore_eth_stats stats; 952 const unsigned int num = qede_get_xstats_count(qdev); 953 unsigned int i, qid, stat_idx = 0; 954 955 if (n < num) 956 return num; 957 958 qdev->ops->get_vport_stats(edev, &stats); 959 960 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 961 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 962 qede_xstats_strings[i].offset); 963 stat_idx++; 964 } 965 966 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 967 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 968 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 969 xstats[stat_idx].value = *(uint64_t *)( 970 ((char *)(qdev->fp_array[(qid)].rxq)) + 971 qede_rxq_xstats_strings[i].offset); 972 stat_idx++; 973 } 974 } 975 } 976 977 return stat_idx; 978 } 979 980 static void 981 qede_reset_xstats(struct rte_eth_dev *dev) 982 { 983 struct qede_dev *qdev = dev->data->dev_private; 984 struct ecore_dev *edev = &qdev->edev; 985 986 ecore_reset_vport_stats(edev); 987 } 988 989 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 990 { 991 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 992 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 993 struct qed_link_params link_params; 994 int rc; 995 996 DP_INFO(edev, "setting link state %d\n", link_up); 997 memset(&link_params, 0, sizeof(link_params)); 998 link_params.link_up = link_up; 999 rc = qdev->ops->common->set_link(edev, &link_params); 1000 if (rc != ECORE_SUCCESS) 1001 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1002 1003 return rc; 1004 } 1005 1006 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1007 { 1008 return qede_dev_set_link_state(eth_dev, true); 1009 } 1010 1011 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1012 { 1013 return qede_dev_set_link_state(eth_dev, false); 1014 } 1015 1016 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1017 { 1018 struct qede_dev *qdev = eth_dev->data->dev_private; 1019 struct ecore_dev *edev = &qdev->edev; 1020 1021 ecore_reset_vport_stats(edev); 1022 } 1023 1024 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1025 { 1026 enum qed_filter_rx_mode_type type = 1027 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1028 1029 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1030 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1031 1032 qede_rx_mode_setting(eth_dev, type); 1033 } 1034 1035 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1036 { 1037 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1038 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_PROMISC); 1039 else 1040 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR); 1041 } 1042 1043 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1044 struct rte_eth_fc_conf *fc_conf) 1045 { 1046 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1047 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1048 struct qed_link_output current_link; 1049 struct qed_link_params params; 1050 1051 memset(¤t_link, 0, sizeof(current_link)); 1052 qdev->ops->common->get_link(edev, ¤t_link); 1053 1054 memset(¶ms, 0, sizeof(params)); 1055 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1056 if (fc_conf->autoneg) { 1057 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1058 DP_ERR(edev, "Autoneg not supported\n"); 1059 return -EINVAL; 1060 } 1061 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1062 } 1063 1064 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1065 if (fc_conf->mode == RTE_FC_FULL) 1066 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1067 QED_LINK_PAUSE_RX_ENABLE); 1068 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1069 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1070 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1071 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1072 1073 params.link_up = true; 1074 (void)qdev->ops->common->set_link(edev, ¶ms); 1075 1076 return 0; 1077 } 1078 1079 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1080 struct rte_eth_fc_conf *fc_conf) 1081 { 1082 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1083 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1084 struct qed_link_output current_link; 1085 1086 memset(¤t_link, 0, sizeof(current_link)); 1087 qdev->ops->common->get_link(edev, ¤t_link); 1088 1089 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1090 fc_conf->autoneg = true; 1091 1092 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1093 QED_LINK_PAUSE_TX_ENABLE)) 1094 fc_conf->mode = RTE_FC_FULL; 1095 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1096 fc_conf->mode = RTE_FC_RX_PAUSE; 1097 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1098 fc_conf->mode = RTE_FC_TX_PAUSE; 1099 else 1100 fc_conf->mode = RTE_FC_NONE; 1101 1102 return 0; 1103 } 1104 1105 static const uint32_t * 1106 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1107 { 1108 static const uint32_t ptypes[] = { 1109 RTE_PTYPE_L3_IPV4, 1110 RTE_PTYPE_L3_IPV6, 1111 RTE_PTYPE_UNKNOWN 1112 }; 1113 1114 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1115 return ptypes; 1116 1117 return NULL; 1118 } 1119 1120 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1121 { 1122 *rss_caps = 0; 1123 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1124 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1125 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1126 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1127 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1128 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1129 } 1130 1131 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1132 struct rte_eth_rss_conf *rss_conf) 1133 { 1134 struct qed_update_vport_params vport_update_params; 1135 struct qede_dev *qdev = eth_dev->data->dev_private; 1136 struct ecore_dev *edev = &qdev->edev; 1137 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1138 uint64_t hf = rss_conf->rss_hf; 1139 int i; 1140 1141 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1142 1143 if (hf != 0) { 1144 /* Enable RSS */ 1145 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf); 1146 memcpy(&vport_update_params.rss_params, &qdev->rss_params, 1147 sizeof(vport_update_params.rss_params)); 1148 if (key) 1149 memcpy(qdev->rss_params.rss_key, rss_conf->rss_key, 1150 rss_conf->rss_key_len); 1151 vport_update_params.update_rss_flg = 1; 1152 qdev->rss_enabled = 1; 1153 } else { 1154 /* Disable RSS */ 1155 qdev->rss_enabled = 0; 1156 } 1157 1158 /* If the mapping doesn't fit any supported, return */ 1159 if (qdev->rss_params.rss_caps == 0 && hf != 0) 1160 return -EINVAL; 1161 1162 DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ? 1163 "Enabling RSS" : "Disabling RSS"); 1164 1165 vport_update_params.vport_id = 0; 1166 1167 return qdev->ops->vport_update(edev, &vport_update_params); 1168 } 1169 1170 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1171 struct rte_eth_rss_conf *rss_conf) 1172 { 1173 struct qede_dev *qdev = eth_dev->data->dev_private; 1174 uint64_t hf; 1175 1176 if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key)) 1177 return -EINVAL; 1178 1179 if (rss_conf->rss_key) 1180 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key, 1181 sizeof(qdev->rss_params.rss_key)); 1182 1183 hf = 0; 1184 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4) ? 1185 ETH_RSS_IPV4 : 0; 1186 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? 1187 ETH_RSS_IPV6 : 0; 1188 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ? 1189 ETH_RSS_IPV6_EX : 0; 1190 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ? 1191 ETH_RSS_NONFRAG_IPV4_TCP : 0; 1192 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? 1193 ETH_RSS_NONFRAG_IPV6_TCP : 0; 1194 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ? 1195 ETH_RSS_IPV6_TCP_EX : 0; 1196 1197 rss_conf->rss_hf = hf; 1198 1199 return 0; 1200 } 1201 1202 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 1203 struct rte_eth_rss_reta_entry64 *reta_conf, 1204 uint16_t reta_size) 1205 { 1206 struct qed_update_vport_params vport_update_params; 1207 struct qede_dev *qdev = eth_dev->data->dev_private; 1208 struct ecore_dev *edev = &qdev->edev; 1209 uint16_t i, idx, shift; 1210 1211 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1212 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 1213 reta_size); 1214 return -EINVAL; 1215 } 1216 1217 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1218 memcpy(&vport_update_params.rss_params, &qdev->rss_params, 1219 sizeof(vport_update_params.rss_params)); 1220 1221 for (i = 0; i < reta_size; i++) { 1222 idx = i / RTE_RETA_GROUP_SIZE; 1223 shift = i % RTE_RETA_GROUP_SIZE; 1224 if (reta_conf[idx].mask & (1ULL << shift)) { 1225 uint8_t entry = reta_conf[idx].reta[shift]; 1226 qdev->rss_params.rss_ind_table[i] = entry; 1227 } 1228 } 1229 1230 vport_update_params.update_rss_flg = 1; 1231 vport_update_params.vport_id = 0; 1232 1233 return qdev->ops->vport_update(edev, &vport_update_params); 1234 } 1235 1236 int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 1237 struct rte_eth_rss_reta_entry64 *reta_conf, 1238 uint16_t reta_size) 1239 { 1240 struct qede_dev *qdev = eth_dev->data->dev_private; 1241 uint16_t i, idx, shift; 1242 1243 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1244 struct ecore_dev *edev = &qdev->edev; 1245 DP_ERR(edev, "reta_size %d is not supported\n", 1246 reta_size); 1247 } 1248 1249 for (i = 0; i < reta_size; i++) { 1250 idx = i / RTE_RETA_GROUP_SIZE; 1251 shift = i % RTE_RETA_GROUP_SIZE; 1252 if (reta_conf[idx].mask & (1ULL << shift)) { 1253 uint8_t entry = qdev->rss_params.rss_ind_table[i]; 1254 reta_conf[idx].reta[shift] = entry; 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1262 { 1263 uint32_t frame_size; 1264 struct qede_dev *qdev = dev->data->dev_private; 1265 struct rte_eth_dev_info dev_info = {0}; 1266 1267 qede_dev_info_get(dev, &dev_info); 1268 1269 /* VLAN_TAG = 4 */ 1270 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4; 1271 1272 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 1273 return -EINVAL; 1274 1275 if (!dev->data->scattered_rx && 1276 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 1277 return -EINVAL; 1278 1279 if (frame_size > ETHER_MAX_LEN) 1280 dev->data->dev_conf.rxmode.jumbo_frame = 1; 1281 else 1282 dev->data->dev_conf.rxmode.jumbo_frame = 0; 1283 1284 /* update max frame size */ 1285 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1286 qdev->mtu = mtu; 1287 qede_dev_stop(dev); 1288 qede_dev_start(dev); 1289 1290 return 0; 1291 } 1292 1293 static const struct eth_dev_ops qede_eth_dev_ops = { 1294 .dev_configure = qede_dev_configure, 1295 .dev_infos_get = qede_dev_info_get, 1296 .rx_queue_setup = qede_rx_queue_setup, 1297 .rx_queue_release = qede_rx_queue_release, 1298 .tx_queue_setup = qede_tx_queue_setup, 1299 .tx_queue_release = qede_tx_queue_release, 1300 .dev_start = qede_dev_start, 1301 .dev_set_link_up = qede_dev_set_link_up, 1302 .dev_set_link_down = qede_dev_set_link_down, 1303 .link_update = qede_link_update, 1304 .promiscuous_enable = qede_promiscuous_enable, 1305 .promiscuous_disable = qede_promiscuous_disable, 1306 .allmulticast_enable = qede_allmulticast_enable, 1307 .allmulticast_disable = qede_allmulticast_disable, 1308 .dev_stop = qede_dev_stop, 1309 .dev_close = qede_dev_close, 1310 .stats_get = qede_get_stats, 1311 .stats_reset = qede_reset_stats, 1312 .xstats_get = qede_get_xstats, 1313 .xstats_reset = qede_reset_xstats, 1314 .xstats_get_names = qede_get_xstats_names, 1315 .mac_addr_add = qede_mac_addr_add, 1316 .mac_addr_remove = qede_mac_addr_remove, 1317 .mac_addr_set = qede_mac_addr_set, 1318 .vlan_offload_set = qede_vlan_offload_set, 1319 .vlan_filter_set = qede_vlan_filter_set, 1320 .flow_ctrl_set = qede_flow_ctrl_set, 1321 .flow_ctrl_get = qede_flow_ctrl_get, 1322 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 1323 .rss_hash_update = qede_rss_hash_update, 1324 .rss_hash_conf_get = qede_rss_hash_conf_get, 1325 .reta_update = qede_rss_reta_update, 1326 .reta_query = qede_rss_reta_query, 1327 .mtu_set = qede_set_mtu, 1328 }; 1329 1330 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 1331 .dev_configure = qede_dev_configure, 1332 .dev_infos_get = qede_dev_info_get, 1333 .rx_queue_setup = qede_rx_queue_setup, 1334 .rx_queue_release = qede_rx_queue_release, 1335 .tx_queue_setup = qede_tx_queue_setup, 1336 .tx_queue_release = qede_tx_queue_release, 1337 .dev_start = qede_dev_start, 1338 .dev_set_link_up = qede_dev_set_link_up, 1339 .dev_set_link_down = qede_dev_set_link_down, 1340 .link_update = qede_link_update, 1341 .promiscuous_enable = qede_promiscuous_enable, 1342 .promiscuous_disable = qede_promiscuous_disable, 1343 .allmulticast_enable = qede_allmulticast_enable, 1344 .allmulticast_disable = qede_allmulticast_disable, 1345 .dev_stop = qede_dev_stop, 1346 .dev_close = qede_dev_close, 1347 .stats_get = qede_get_stats, 1348 .stats_reset = qede_reset_stats, 1349 .xstats_get = qede_get_xstats, 1350 .xstats_reset = qede_reset_xstats, 1351 .xstats_get_names = qede_get_xstats_names, 1352 .vlan_offload_set = qede_vlan_offload_set, 1353 .vlan_filter_set = qede_vlan_filter_set, 1354 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 1355 .rss_hash_update = qede_rss_hash_update, 1356 .rss_hash_conf_get = qede_rss_hash_conf_get, 1357 .reta_update = qede_rss_reta_update, 1358 .reta_query = qede_rss_reta_query, 1359 .mtu_set = qede_set_mtu, 1360 }; 1361 1362 static void qede_update_pf_params(struct ecore_dev *edev) 1363 { 1364 struct ecore_pf_params pf_params; 1365 /* 32 rx + 32 tx */ 1366 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 1367 pf_params.eth_pf_params.num_cons = 64; 1368 qed_ops->common->update_pf_params(edev, &pf_params); 1369 } 1370 1371 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 1372 { 1373 struct rte_pci_device *pci_dev; 1374 struct rte_pci_addr pci_addr; 1375 struct qede_dev *adapter; 1376 struct ecore_dev *edev; 1377 struct qed_dev_eth_info dev_info; 1378 struct qed_slowpath_params params; 1379 static bool do_once = true; 1380 uint8_t bulletin_change; 1381 uint8_t vf_mac[ETHER_ADDR_LEN]; 1382 uint8_t is_mac_forced; 1383 bool is_mac_exist; 1384 /* Fix up ecore debug level */ 1385 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 1386 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 1387 uint32_t max_mac_addrs; 1388 int rc; 1389 1390 /* Extract key data structures */ 1391 adapter = eth_dev->data->dev_private; 1392 edev = &adapter->edev; 1393 pci_addr = eth_dev->pci_dev->addr; 1394 1395 PMD_INIT_FUNC_TRACE(edev); 1396 1397 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 1398 pci_addr.bus, pci_addr.devid, pci_addr.function, 1399 eth_dev->data->port_id); 1400 1401 eth_dev->rx_pkt_burst = qede_recv_pkts; 1402 eth_dev->tx_pkt_burst = qede_xmit_pkts; 1403 1404 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1405 DP_NOTICE(edev, false, 1406 "Skipping device init from secondary process\n"); 1407 return 0; 1408 } 1409 1410 pci_dev = eth_dev->pci_dev; 1411 1412 rte_eth_copy_pci_info(eth_dev, pci_dev); 1413 1414 qed_ops = qed_get_eth_ops(); 1415 if (!qed_ops) { 1416 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 1417 return -EINVAL; 1418 } 1419 1420 DP_INFO(edev, "Starting qede probe\n"); 1421 1422 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH, 1423 dp_module, dp_level, is_vf); 1424 1425 if (rc != 0) { 1426 DP_ERR(edev, "qede probe failed rc %d\n", rc); 1427 return -ENODEV; 1428 } 1429 1430 qede_update_pf_params(edev); 1431 1432 rte_intr_callback_register(ð_dev->pci_dev->intr_handle, 1433 qede_interrupt_handler, (void *)eth_dev); 1434 1435 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) { 1436 DP_ERR(edev, "rte_intr_enable() failed\n"); 1437 return -ENODEV; 1438 } 1439 1440 /* Start the Slowpath-process */ 1441 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 1442 params.int_mode = ECORE_INT_MODE_MSIX; 1443 params.drv_major = QEDE_PMD_VERSION_MAJOR; 1444 params.drv_minor = QEDE_PMD_VERSION_MINOR; 1445 params.drv_rev = QEDE_PMD_VERSION_REVISION; 1446 params.drv_eng = QEDE_PMD_VERSION_PATCH; 1447 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 1448 QEDE_PMD_DRV_VER_STR_SIZE); 1449 1450 /* For CMT mode device do periodic polling for slowpath events. 1451 * This is required since uio device uses only one MSI-x 1452 * interrupt vector but we need one for each engine. 1453 */ 1454 if (edev->num_hwfns > 1 && IS_PF(edev)) { 1455 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1456 qede_poll_sp_sb_cb, 1457 (void *)eth_dev); 1458 if (rc != 0) { 1459 DP_ERR(edev, "Unable to start periodic" 1460 " timer rc %d\n", rc); 1461 return -EINVAL; 1462 } 1463 } 1464 1465 rc = qed_ops->common->slowpath_start(edev, ¶ms); 1466 if (rc) { 1467 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 1468 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1469 (void *)eth_dev); 1470 return -ENODEV; 1471 } 1472 1473 rc = qed_ops->fill_dev_info(edev, &dev_info); 1474 if (rc) { 1475 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 1476 qed_ops->common->slowpath_stop(edev); 1477 qed_ops->common->remove(edev); 1478 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1479 (void *)eth_dev); 1480 return -ENODEV; 1481 } 1482 1483 qede_alloc_etherdev(adapter, &dev_info); 1484 1485 adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION); 1486 1487 if (!is_vf) 1488 adapter->dev_info.num_mac_addrs = 1489 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 1490 ECORE_MAC); 1491 else 1492 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 1493 &adapter->dev_info.num_mac_addrs); 1494 1495 /* Allocate memory for storing MAC addr */ 1496 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 1497 (ETHER_ADDR_LEN * 1498 adapter->dev_info.num_mac_addrs), 1499 RTE_CACHE_LINE_SIZE); 1500 1501 if (eth_dev->data->mac_addrs == NULL) { 1502 DP_ERR(edev, "Failed to allocate MAC address\n"); 1503 qed_ops->common->slowpath_stop(edev); 1504 qed_ops->common->remove(edev); 1505 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 1506 (void *)eth_dev); 1507 return -ENOMEM; 1508 } 1509 1510 if (!is_vf) { 1511 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 1512 hw_info.hw_mac_addr, 1513 ð_dev->data->mac_addrs[0]); 1514 ether_addr_copy(ð_dev->data->mac_addrs[0], 1515 &adapter->primary_mac); 1516 } else { 1517 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 1518 &bulletin_change); 1519 if (bulletin_change) { 1520 is_mac_exist = 1521 ecore_vf_bulletin_get_forced_mac( 1522 ECORE_LEADING_HWFN(edev), 1523 vf_mac, 1524 &is_mac_forced); 1525 if (is_mac_exist && is_mac_forced) { 1526 DP_INFO(edev, "VF macaddr received from PF\n"); 1527 ether_addr_copy((struct ether_addr *)&vf_mac, 1528 ð_dev->data->mac_addrs[0]); 1529 ether_addr_copy(ð_dev->data->mac_addrs[0], 1530 &adapter->primary_mac); 1531 } else { 1532 DP_NOTICE(edev, false, 1533 "No VF macaddr assigned\n"); 1534 } 1535 } 1536 } 1537 1538 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 1539 1540 if (do_once) { 1541 qede_print_adapter_info(adapter); 1542 do_once = false; 1543 } 1544 1545 adapter->state = QEDE_DEV_INIT; 1546 1547 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 1548 adapter->primary_mac.addr_bytes[0], 1549 adapter->primary_mac.addr_bytes[1], 1550 adapter->primary_mac.addr_bytes[2], 1551 adapter->primary_mac.addr_bytes[3], 1552 adapter->primary_mac.addr_bytes[4], 1553 adapter->primary_mac.addr_bytes[5]); 1554 1555 return rc; 1556 } 1557 1558 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 1559 { 1560 return qede_common_dev_init(eth_dev, 1); 1561 } 1562 1563 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 1564 { 1565 return qede_common_dev_init(eth_dev, 0); 1566 } 1567 1568 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 1569 { 1570 /* only uninitialize in the primary process */ 1571 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1572 return 0; 1573 1574 /* safe to close dev here */ 1575 qede_dev_close(eth_dev); 1576 1577 eth_dev->dev_ops = NULL; 1578 eth_dev->rx_pkt_burst = NULL; 1579 eth_dev->tx_pkt_burst = NULL; 1580 1581 if (eth_dev->data->mac_addrs) 1582 rte_free(eth_dev->data->mac_addrs); 1583 1584 eth_dev->data->mac_addrs = NULL; 1585 1586 return 0; 1587 } 1588 1589 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 1590 { 1591 return qede_dev_common_uninit(eth_dev); 1592 } 1593 1594 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 1595 { 1596 return qede_dev_common_uninit(eth_dev); 1597 } 1598 1599 static struct rte_pci_id pci_id_qedevf_map[] = { 1600 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 1601 { 1602 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF) 1603 }, 1604 { 1605 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV) 1606 }, 1607 {.vendor_id = 0,} 1608 }; 1609 1610 static struct rte_pci_id pci_id_qede_map[] = { 1611 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 1612 { 1613 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E) 1614 }, 1615 { 1616 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S) 1617 }, 1618 { 1619 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40) 1620 }, 1621 { 1622 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25) 1623 }, 1624 { 1625 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100) 1626 }, 1627 {.vendor_id = 0,} 1628 }; 1629 1630 static struct eth_driver rte_qedevf_pmd = { 1631 .pci_drv = { 1632 .id_table = pci_id_qedevf_map, 1633 .drv_flags = 1634 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1635 .probe = rte_eth_dev_pci_probe, 1636 .remove = rte_eth_dev_pci_remove, 1637 }, 1638 .eth_dev_init = qedevf_eth_dev_init, 1639 .eth_dev_uninit = qedevf_eth_dev_uninit, 1640 .dev_private_size = sizeof(struct qede_dev), 1641 }; 1642 1643 static struct eth_driver rte_qede_pmd = { 1644 .pci_drv = { 1645 .id_table = pci_id_qede_map, 1646 .drv_flags = 1647 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1648 .probe = rte_eth_dev_pci_probe, 1649 .remove = rte_eth_dev_pci_remove, 1650 }, 1651 .eth_dev_init = qede_eth_dev_init, 1652 .eth_dev_uninit = qede_eth_dev_uninit, 1653 .dev_private_size = sizeof(struct qede_dev), 1654 }; 1655 1656 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv); 1657 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 1658 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv); 1659 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 1660