1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static int64_t timer_period = 1; 16 17 /* VXLAN tunnel classification mapping */ 18 const struct _qede_vxlan_tunn_types { 19 uint16_t rte_filter_type; 20 enum ecore_filter_ucast_type qede_type; 21 enum ecore_tunn_clss qede_tunn_clss; 22 const char *string; 23 } qede_tunn_types[] = { 24 { 25 ETH_TUNNEL_FILTER_OMAC, 26 ECORE_FILTER_MAC, 27 ECORE_TUNN_CLSS_MAC_VLAN, 28 "outer-mac" 29 }, 30 { 31 ETH_TUNNEL_FILTER_TENID, 32 ECORE_FILTER_VNI, 33 ECORE_TUNN_CLSS_MAC_VNI, 34 "vni" 35 }, 36 { 37 ETH_TUNNEL_FILTER_IMAC, 38 ECORE_FILTER_INNER_MAC, 39 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 40 "inner-mac" 41 }, 42 { 43 ETH_TUNNEL_FILTER_IVLAN, 44 ECORE_FILTER_INNER_VLAN, 45 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 46 "inner-vlan" 47 }, 48 { 49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 50 ECORE_FILTER_MAC_VNI_PAIR, 51 ECORE_TUNN_CLSS_MAC_VNI, 52 "outer-mac and vni" 53 }, 54 { 55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 56 ECORE_FILTER_UNUSED, 57 MAX_ECORE_TUNN_CLSS, 58 "outer-mac and inner-mac" 59 }, 60 { 61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 62 ECORE_FILTER_UNUSED, 63 MAX_ECORE_TUNN_CLSS, 64 "outer-mac and inner-vlan" 65 }, 66 { 67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 68 ECORE_FILTER_INNER_MAC_VNI_PAIR, 69 ECORE_TUNN_CLSS_INNER_MAC_VNI, 70 "vni and inner-mac", 71 }, 72 { 73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 74 ECORE_FILTER_UNUSED, 75 MAX_ECORE_TUNN_CLSS, 76 "vni and inner-vlan", 77 }, 78 { 79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 80 ECORE_FILTER_INNER_PAIR, 81 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 82 "inner-mac and inner-vlan", 83 }, 84 { 85 ETH_TUNNEL_FILTER_OIP, 86 ECORE_FILTER_UNUSED, 87 MAX_ECORE_TUNN_CLSS, 88 "outer-IP" 89 }, 90 { 91 ETH_TUNNEL_FILTER_IIP, 92 ECORE_FILTER_UNUSED, 93 MAX_ECORE_TUNN_CLSS, 94 "inner-IP" 95 }, 96 { 97 RTE_TUNNEL_FILTER_IMAC_IVLAN, 98 ECORE_FILTER_UNUSED, 99 MAX_ECORE_TUNN_CLSS, 100 "IMAC_IVLAN" 101 }, 102 { 103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 104 ECORE_FILTER_UNUSED, 105 MAX_ECORE_TUNN_CLSS, 106 "IMAC_IVLAN_TENID" 107 }, 108 { 109 RTE_TUNNEL_FILTER_IMAC_TENID, 110 ECORE_FILTER_UNUSED, 111 MAX_ECORE_TUNN_CLSS, 112 "IMAC_TENID" 113 }, 114 { 115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 116 ECORE_FILTER_UNUSED, 117 MAX_ECORE_TUNN_CLSS, 118 "OMAC_TENID_IMAC" 119 }, 120 }; 121 122 struct rte_qede_xstats_name_off { 123 char name[RTE_ETH_XSTATS_NAME_SIZE]; 124 uint64_t offset; 125 }; 126 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 128 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, 129 {"rx_multicast_bytes", 130 offsetof(struct ecore_eth_stats, rx_mcast_bytes)}, 131 {"rx_broadcast_bytes", 132 offsetof(struct ecore_eth_stats, rx_bcast_bytes)}, 133 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)}, 134 {"rx_multicast_packets", 135 offsetof(struct ecore_eth_stats, rx_mcast_pkts)}, 136 {"rx_broadcast_packets", 137 offsetof(struct ecore_eth_stats, rx_bcast_pkts)}, 138 139 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)}, 140 {"tx_multicast_bytes", 141 offsetof(struct ecore_eth_stats, tx_mcast_bytes)}, 142 {"tx_broadcast_bytes", 143 offsetof(struct ecore_eth_stats, tx_bcast_bytes)}, 144 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)}, 145 {"tx_multicast_packets", 146 offsetof(struct ecore_eth_stats, tx_mcast_pkts)}, 147 {"tx_broadcast_packets", 148 offsetof(struct ecore_eth_stats, tx_bcast_pkts)}, 149 150 {"rx_64_byte_packets", 151 offsetof(struct ecore_eth_stats, rx_64_byte_packets)}, 152 {"rx_65_to_127_byte_packets", 153 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)}, 154 {"rx_128_to_255_byte_packets", 155 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)}, 156 {"rx_256_to_511_byte_packets", 157 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)}, 158 {"rx_512_to_1023_byte_packets", 159 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)}, 160 {"rx_1024_to_1518_byte_packets", 161 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)}, 162 {"rx_1519_to_1522_byte_packets", 163 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)}, 164 {"rx_1519_to_2047_byte_packets", 165 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)}, 166 {"rx_2048_to_4095_byte_packets", 167 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)}, 168 {"rx_4096_to_9216_byte_packets", 169 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)}, 170 {"rx_9217_to_16383_byte_packets", 171 offsetof(struct ecore_eth_stats, 172 rx_9217_to_16383_byte_packets)}, 173 {"tx_64_byte_packets", 174 offsetof(struct ecore_eth_stats, tx_64_byte_packets)}, 175 {"tx_65_to_127_byte_packets", 176 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)}, 177 {"tx_128_to_255_byte_packets", 178 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)}, 179 {"tx_256_to_511_byte_packets", 180 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)}, 181 {"tx_512_to_1023_byte_packets", 182 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)}, 183 {"tx_1024_to_1518_byte_packets", 184 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)}, 185 {"trx_1519_to_1522_byte_packets", 186 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)}, 187 {"tx_2048_to_4095_byte_packets", 188 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)}, 189 {"tx_4096_to_9216_byte_packets", 190 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)}, 191 {"tx_9217_to_16383_byte_packets", 192 offsetof(struct ecore_eth_stats, 193 tx_9217_to_16383_byte_packets)}, 194 195 {"rx_mac_crtl_frames", 196 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)}, 197 {"tx_mac_control_frames", 198 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)}, 199 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)}, 200 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)}, 201 {"rx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats, rx_pfc_frames)}, 203 {"tx_priority_flow_control_frames", 204 offsetof(struct ecore_eth_stats, tx_pfc_frames)}, 205 206 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)}, 207 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)}, 208 {"rx_carrier_errors", 209 offsetof(struct ecore_eth_stats, rx_carrier_errors)}, 210 {"rx_oversize_packet_errors", 211 offsetof(struct ecore_eth_stats, rx_oversize_packets)}, 212 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)}, 213 {"rx_undersize_packet_errors", 214 offsetof(struct ecore_eth_stats, rx_undersize_packets)}, 215 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)}, 216 {"rx_host_buffer_not_available", 217 offsetof(struct ecore_eth_stats, no_buff_discards)}, 218 /* Number of packets discarded because they are bigger than MTU */ 219 {"rx_packet_too_big_discards", 220 offsetof(struct ecore_eth_stats, packet_too_big_discard)}, 221 {"rx_ttl_zero_discards", 222 offsetof(struct ecore_eth_stats, ttl0_discard)}, 223 {"rx_multi_function_tag_filter_discards", 224 offsetof(struct ecore_eth_stats, mftag_filter_discards)}, 225 {"rx_mac_filter_discards", 226 offsetof(struct ecore_eth_stats, mac_filter_discards)}, 227 {"rx_hw_buffer_truncates", 228 offsetof(struct ecore_eth_stats, brb_truncates)}, 229 {"rx_hw_buffer_discards", 230 offsetof(struct ecore_eth_stats, brb_discards)}, 231 {"tx_lpi_entry_count", 232 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)}, 233 {"tx_total_collisions", 234 offsetof(struct ecore_eth_stats, tx_total_collisions)}, 235 {"tx_error_drop_packets", 236 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)}, 237 238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)}, 239 {"rx_mac_unicast_packets", 240 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)}, 241 {"rx_mac_multicast_packets", 242 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)}, 243 {"rx_mac_broadcast_packets", 244 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)}, 245 {"rx_mac_frames_ok", 246 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)}, 247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)}, 248 {"tx_mac_unicast_packets", 249 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)}, 250 {"tx_mac_multicast_packets", 251 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)}, 252 {"tx_mac_broadcast_packets", 253 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)}, 254 255 {"lro_coalesced_packets", 256 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)}, 257 {"lro_coalesced_events", 258 offsetof(struct ecore_eth_stats, tpa_coalesced_events)}, 259 {"lro_aborts_num", 260 offsetof(struct ecore_eth_stats, tpa_aborts_num)}, 261 {"lro_not_coalesced_packets", 262 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)}, 263 {"lro_coalesced_bytes", 264 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)}, 265 }; 266 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 268 {"rx_q_segments", 269 offsetof(struct qede_rx_queue, rx_segs)}, 270 {"rx_q_hw_errors", 271 offsetof(struct qede_rx_queue, rx_hw_errors)}, 272 {"rx_q_allocation_errors", 273 offsetof(struct qede_rx_queue, rx_alloc_errors)} 274 }; 275 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 277 { 278 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 279 } 280 281 static void 282 qede_interrupt_handler(void *param) 283 { 284 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 285 struct qede_dev *qdev = eth_dev->data->dev_private; 286 struct ecore_dev *edev = &qdev->edev; 287 288 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 289 if (rte_intr_enable(eth_dev->intr_handle)) 290 DP_ERR(edev, "rte_intr_enable failed\n"); 291 } 292 293 static void 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 295 { 296 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 297 qdev->ops = qed_ops; 298 } 299 300 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 301 static void qede_print_adapter_info(struct qede_dev *qdev) 302 { 303 struct ecore_dev *edev = &qdev->edev; 304 struct qed_dev_info *info = &qdev->dev_info.common; 305 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 306 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 307 308 DP_INFO(edev, "*********************************\n"); 309 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 310 DP_INFO(edev, " Chip details : %s%d\n", 311 ECORE_IS_BB(edev) ? "BB" : "AH", 312 CHIP_REV_IS_A0(edev) ? 0 : 1); 313 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 314 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 315 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 316 ver_str, QEDE_PMD_VERSION); 317 DP_INFO(edev, " Driver version : %s\n", drv_ver); 318 DP_INFO(edev, " Firmware version : %s\n", ver_str); 319 320 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 321 "%d.%d.%d.%d", 322 (info->mfw_rev >> 24) & 0xff, 323 (info->mfw_rev >> 16) & 0xff, 324 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 325 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 326 DP_INFO(edev, " Firmware file : %s\n", fw_file); 327 DP_INFO(edev, "*********************************\n"); 328 } 329 #endif 330 331 static int 332 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 333 { 334 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 335 struct ecore_sp_vport_start_params params; 336 struct ecore_hwfn *p_hwfn; 337 int rc; 338 int i; 339 340 memset(¶ms, 0, sizeof(params)); 341 params.vport_id = 0; 342 params.mtu = mtu; 343 /* @DPDK - Disable FW placement */ 344 params.zero_placement_offset = 1; 345 for_each_hwfn(edev, i) { 346 p_hwfn = &edev->hwfns[i]; 347 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 348 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 349 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 350 if (rc != ECORE_SUCCESS) { 351 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 352 return rc; 353 } 354 } 355 ecore_reset_vport_stats(edev); 356 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 357 358 return 0; 359 } 360 361 static int 362 qede_stop_vport(struct ecore_dev *edev) 363 { 364 struct ecore_hwfn *p_hwfn; 365 uint8_t vport_id; 366 int rc; 367 int i; 368 369 vport_id = 0; 370 for_each_hwfn(edev, i) { 371 p_hwfn = &edev->hwfns[i]; 372 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 373 vport_id); 374 if (rc != ECORE_SUCCESS) { 375 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 376 return rc; 377 } 378 } 379 380 return 0; 381 } 382 383 /* Activate or deactivate vport via vport-update */ 384 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 385 { 386 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 387 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 388 struct ecore_sp_vport_update_params params; 389 struct ecore_hwfn *p_hwfn; 390 uint8_t i; 391 int rc = -1; 392 393 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 394 params.vport_id = 0; 395 params.update_vport_active_rx_flg = 1; 396 params.update_vport_active_tx_flg = 1; 397 params.vport_active_rx_flg = flg; 398 params.vport_active_tx_flg = flg; 399 for_each_hwfn(edev, i) { 400 p_hwfn = &edev->hwfns[i]; 401 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 402 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 403 ECORE_SPQ_MODE_EBLOCK, NULL); 404 if (rc != ECORE_SUCCESS) { 405 DP_ERR(edev, "Failed to update vport\n"); 406 break; 407 } 408 } 409 DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated"); 410 return rc; 411 } 412 413 static void 414 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 415 uint16_t mtu, bool enable) 416 { 417 /* Enable LRO in split mode */ 418 sge_tpa_params->tpa_ipv4_en_flg = enable; 419 sge_tpa_params->tpa_ipv6_en_flg = enable; 420 sge_tpa_params->tpa_ipv4_tunn_en_flg = false; 421 sge_tpa_params->tpa_ipv6_tunn_en_flg = false; 422 /* set if tpa enable changes */ 423 sge_tpa_params->update_tpa_en_flg = 1; 424 /* set if tpa parameters should be handled */ 425 sge_tpa_params->update_tpa_param_flg = enable; 426 427 sge_tpa_params->max_buffers_per_cqe = 20; 428 /* Enable TPA in split mode. In this mode each TPA segment 429 * starts on the new BD, so there is one BD per segment. 430 */ 431 sge_tpa_params->tpa_pkt_split_flg = 1; 432 sge_tpa_params->tpa_hdr_data_split_flg = 0; 433 sge_tpa_params->tpa_gro_consistent_flg = 0; 434 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 435 sge_tpa_params->tpa_max_size = 0x7FFF; 436 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 437 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 438 } 439 440 /* Enable/disable LRO via vport-update */ 441 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 442 { 443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 445 struct ecore_sp_vport_update_params params; 446 struct ecore_sge_tpa_params tpa_params; 447 struct ecore_hwfn *p_hwfn; 448 int rc; 449 int i; 450 451 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 452 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 453 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 454 params.vport_id = 0; 455 params.sge_tpa_params = &tpa_params; 456 for_each_hwfn(edev, i) { 457 p_hwfn = &edev->hwfns[i]; 458 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 459 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 460 ECORE_SPQ_MODE_EBLOCK, NULL); 461 if (rc != ECORE_SUCCESS) { 462 DP_ERR(edev, "Failed to update LRO\n"); 463 return -1; 464 } 465 } 466 467 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 468 469 return 0; 470 } 471 472 /* Update MTU via vport-update without doing port restart. 473 * The vport must be deactivated before calling this API. 474 */ 475 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 476 { 477 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 478 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 479 struct ecore_sp_vport_update_params params; 480 struct ecore_hwfn *p_hwfn; 481 int rc; 482 int i; 483 484 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 485 params.vport_id = 0; 486 params.mtu = mtu; 487 params.vport_id = 0; 488 for_each_hwfn(edev, i) { 489 p_hwfn = &edev->hwfns[i]; 490 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 491 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 492 ECORE_SPQ_MODE_EBLOCK, NULL); 493 if (rc != ECORE_SUCCESS) { 494 DP_ERR(edev, "Failed to update MTU\n"); 495 return -1; 496 } 497 } 498 DP_INFO(edev, "MTU updated to %u\n", mtu); 499 500 return 0; 501 } 502 503 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 504 { 505 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 506 ucast->is_rx_filter = true; 507 ucast->is_tx_filter = true; 508 /* ucast->assert_on_error = true; - For debug */ 509 } 510 511 static int 512 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 513 enum qed_filter_rx_mode_type type) 514 { 515 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 516 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 517 struct ecore_filter_accept_flags flags; 518 519 memset(&flags, 0, sizeof(flags)); 520 521 flags.update_rx_mode_config = 1; 522 flags.update_tx_mode_config = 1; 523 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 524 ECORE_ACCEPT_MCAST_MATCHED | 525 ECORE_ACCEPT_BCAST; 526 527 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 528 ECORE_ACCEPT_MCAST_MATCHED | 529 ECORE_ACCEPT_BCAST; 530 531 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 532 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 533 if (IS_VF(edev)) { 534 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 535 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n"); 536 } 537 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 538 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 539 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC | 540 QED_FILTER_RX_MODE_TYPE_PROMISC)) { 541 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED | 542 ECORE_ACCEPT_MCAST_UNMATCHED; 543 } 544 545 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 546 ECORE_SPQ_MODE_CB, NULL); 547 } 548 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn, 549 uint8_t clss, bool mode, bool mask) 550 { 551 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info)); 552 p_tunn->vxlan.b_update_mode = mode; 553 p_tunn->vxlan.b_mode_enabled = mask; 554 p_tunn->b_update_rx_cls = true; 555 p_tunn->b_update_tx_cls = true; 556 p_tunn->vxlan.tun_cls = clss; 557 } 558 559 static int 560 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 561 bool add) 562 { 563 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 564 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 565 struct qede_ucast_entry *tmp = NULL; 566 struct qede_ucast_entry *u; 567 struct ether_addr *mac_addr; 568 569 mac_addr = (struct ether_addr *)ucast->mac; 570 if (add) { 571 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 572 if ((memcmp(mac_addr, &tmp->mac, 573 ETHER_ADDR_LEN) == 0) && 574 ucast->vlan == tmp->vlan) { 575 DP_ERR(edev, "Unicast MAC is already added" 576 " with vlan = %u, vni = %u\n", 577 ucast->vlan, ucast->vni); 578 return -EEXIST; 579 } 580 } 581 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 582 RTE_CACHE_LINE_SIZE); 583 if (!u) { 584 DP_ERR(edev, "Did not allocate memory for ucast\n"); 585 return -ENOMEM; 586 } 587 ether_addr_copy(mac_addr, &u->mac); 588 u->vlan = ucast->vlan; 589 u->vni = ucast->vni; 590 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 591 qdev->num_uc_addr++; 592 } else { 593 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 594 if ((memcmp(mac_addr, &tmp->mac, 595 ETHER_ADDR_LEN) == 0) && 596 ucast->vlan == tmp->vlan && 597 ucast->vni == tmp->vni) 598 break; 599 } 600 if (tmp == NULL) { 601 DP_INFO(edev, "Unicast MAC is not found\n"); 602 return -EINVAL; 603 } 604 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 605 qdev->num_uc_addr--; 606 } 607 608 return 0; 609 } 610 611 static int 612 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast, 613 bool add) 614 { 615 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 616 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 617 struct ether_addr *mac_addr; 618 struct qede_mcast_entry *tmp = NULL; 619 struct qede_mcast_entry *m; 620 621 mac_addr = (struct ether_addr *)mcast->mac; 622 if (add) { 623 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 624 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) { 625 DP_ERR(edev, 626 "Multicast MAC is already added\n"); 627 return -EEXIST; 628 } 629 } 630 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 631 RTE_CACHE_LINE_SIZE); 632 if (!m) { 633 DP_ERR(edev, 634 "Did not allocate memory for mcast\n"); 635 return -ENOMEM; 636 } 637 ether_addr_copy(mac_addr, &m->mac); 638 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 639 qdev->num_mc_addr++; 640 } else { 641 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 642 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) 643 break; 644 } 645 if (tmp == NULL) { 646 DP_INFO(edev, "Multicast mac is not found\n"); 647 return -EINVAL; 648 } 649 SLIST_REMOVE(&qdev->mc_list_head, tmp, 650 qede_mcast_entry, list); 651 qdev->num_mc_addr--; 652 } 653 654 return 0; 655 } 656 657 static enum _ecore_status_t 658 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 659 bool add) 660 { 661 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 662 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 663 enum _ecore_status_t rc; 664 struct ecore_filter_mcast mcast; 665 struct qede_mcast_entry *tmp; 666 uint16_t j = 0; 667 668 /* Multicast */ 669 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) { 670 if (add) { 671 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) { 672 DP_ERR(edev, 673 "Mcast filter table limit exceeded, " 674 "Please enable mcast promisc mode\n"); 675 return -ECORE_INVAL; 676 } 677 } 678 rc = qede_mcast_filter(eth_dev, ucast, add); 679 if (rc == 0) { 680 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr); 681 memset(&mcast, 0, sizeof(mcast)); 682 mcast.num_mc_addrs = qdev->num_mc_addr; 683 mcast.opcode = ECORE_FILTER_ADD; 684 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 685 ether_addr_copy(&tmp->mac, 686 (struct ether_addr *)&mcast.mac[j]); 687 j++; 688 } 689 rc = ecore_filter_mcast_cmd(edev, &mcast, 690 ECORE_SPQ_MODE_CB, NULL); 691 } 692 if (rc != ECORE_SUCCESS) { 693 DP_ERR(edev, "Failed to add multicast filter" 694 " rc = %d, op = %d\n", rc, add); 695 } 696 } else { /* Unicast */ 697 if (add) { 698 if (qdev->num_uc_addr >= 699 qdev->dev_info.num_mac_filters) { 700 DP_ERR(edev, 701 "Ucast filter table limit exceeded," 702 " Please enable promisc mode\n"); 703 return -ECORE_INVAL; 704 } 705 } 706 rc = qede_ucast_filter(eth_dev, ucast, add); 707 if (rc == 0) 708 rc = ecore_filter_ucast_cmd(edev, ucast, 709 ECORE_SPQ_MODE_CB, NULL); 710 if (rc != ECORE_SUCCESS) { 711 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 712 rc, add); 713 } 714 } 715 716 return rc; 717 } 718 719 static int 720 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 721 __rte_unused uint32_t index, __rte_unused uint32_t pool) 722 { 723 struct ecore_filter_ucast ucast; 724 int re; 725 726 qede_set_ucast_cmn_params(&ucast); 727 ucast.type = ECORE_FILTER_MAC; 728 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 729 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 730 return re; 731 } 732 733 static void 734 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 735 { 736 struct qede_dev *qdev = eth_dev->data->dev_private; 737 struct ecore_dev *edev = &qdev->edev; 738 struct ecore_filter_ucast ucast; 739 740 PMD_INIT_FUNC_TRACE(edev); 741 742 if (index >= qdev->dev_info.num_mac_filters) { 743 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 744 index, qdev->dev_info.num_mac_filters); 745 return; 746 } 747 748 qede_set_ucast_cmn_params(&ucast); 749 ucast.opcode = ECORE_FILTER_REMOVE; 750 ucast.type = ECORE_FILTER_MAC; 751 752 /* Use the index maintained by rte */ 753 ether_addr_copy(ð_dev->data->mac_addrs[index], 754 (struct ether_addr *)&ucast.mac); 755 756 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 757 } 758 759 static void 760 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 761 { 762 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 763 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 764 765 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 766 mac_addr->addr_bytes)) { 767 DP_ERR(edev, "Setting MAC address is not allowed\n"); 768 ether_addr_copy(&qdev->primary_mac, 769 ð_dev->data->mac_addrs[0]); 770 return; 771 } 772 773 qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 774 } 775 776 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 777 { 778 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 779 struct ecore_sp_vport_update_params params; 780 struct ecore_hwfn *p_hwfn; 781 uint8_t i; 782 int rc; 783 784 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 785 params.vport_id = 0; 786 params.update_accept_any_vlan_flg = 1; 787 params.accept_any_vlan = flg; 788 for_each_hwfn(edev, i) { 789 p_hwfn = &edev->hwfns[i]; 790 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 791 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 792 ECORE_SPQ_MODE_EBLOCK, NULL); 793 if (rc != ECORE_SUCCESS) { 794 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 795 return; 796 } 797 } 798 799 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 800 } 801 802 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 803 { 804 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 805 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 806 struct ecore_sp_vport_update_params params; 807 struct ecore_hwfn *p_hwfn; 808 uint8_t i; 809 int rc; 810 811 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 812 params.vport_id = 0; 813 params.update_inner_vlan_removal_flg = 1; 814 params.inner_vlan_removal_flg = flg; 815 for_each_hwfn(edev, i) { 816 p_hwfn = &edev->hwfns[i]; 817 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 818 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 819 ECORE_SPQ_MODE_EBLOCK, NULL); 820 if (rc != ECORE_SUCCESS) { 821 DP_ERR(edev, "Failed to update vport\n"); 822 return -1; 823 } 824 } 825 826 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 827 return 0; 828 } 829 830 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 831 uint16_t vlan_id, int on) 832 { 833 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 834 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 835 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 836 struct qede_vlan_entry *tmp = NULL; 837 struct qede_vlan_entry *vlan; 838 struct ecore_filter_ucast ucast; 839 int rc; 840 841 if (on) { 842 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 843 DP_ERR(edev, "Reached max VLAN filter limit" 844 " enabling accept_any_vlan\n"); 845 qede_config_accept_any_vlan(qdev, true); 846 return 0; 847 } 848 849 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 850 if (tmp->vid == vlan_id) { 851 DP_ERR(edev, "VLAN %u already configured\n", 852 vlan_id); 853 return -EEXIST; 854 } 855 } 856 857 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 858 RTE_CACHE_LINE_SIZE); 859 860 if (!vlan) { 861 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 862 return -ENOMEM; 863 } 864 865 qede_set_ucast_cmn_params(&ucast); 866 ucast.opcode = ECORE_FILTER_ADD; 867 ucast.type = ECORE_FILTER_VLAN; 868 ucast.vlan = vlan_id; 869 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 870 NULL); 871 if (rc != 0) { 872 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 873 rc); 874 rte_free(vlan); 875 } else { 876 vlan->vid = vlan_id; 877 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 878 qdev->configured_vlans++; 879 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 880 vlan_id, qdev->configured_vlans); 881 } 882 } else { 883 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 884 if (tmp->vid == vlan_id) 885 break; 886 } 887 888 if (!tmp) { 889 if (qdev->configured_vlans == 0) { 890 DP_INFO(edev, 891 "No VLAN filters configured yet\n"); 892 return 0; 893 } 894 895 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 896 return -EINVAL; 897 } 898 899 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 900 901 qede_set_ucast_cmn_params(&ucast); 902 ucast.opcode = ECORE_FILTER_REMOVE; 903 ucast.type = ECORE_FILTER_VLAN; 904 ucast.vlan = vlan_id; 905 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 906 NULL); 907 if (rc != 0) { 908 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 909 vlan_id, rc); 910 } else { 911 qdev->configured_vlans--; 912 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 913 vlan_id, qdev->configured_vlans); 914 } 915 } 916 917 return rc; 918 } 919 920 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 921 { 922 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 923 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 924 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 925 926 if (mask & ETH_VLAN_STRIP_MASK) { 927 if (rxmode->hw_vlan_strip) 928 (void)qede_vlan_stripping(eth_dev, 1); 929 else 930 (void)qede_vlan_stripping(eth_dev, 0); 931 } 932 933 if (mask & ETH_VLAN_FILTER_MASK) { 934 /* VLAN filtering kicks in when a VLAN is added */ 935 if (rxmode->hw_vlan_filter) { 936 qede_vlan_filter_set(eth_dev, 0, 1); 937 } else { 938 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 939 DP_ERR(edev, 940 " Please remove existing VLAN filters" 941 " before disabling VLAN filtering\n"); 942 /* Signal app that VLAN filtering is still 943 * enabled 944 */ 945 rxmode->hw_vlan_filter = true; 946 } else { 947 qede_vlan_filter_set(eth_dev, 0, 0); 948 } 949 } 950 } 951 952 if (mask & ETH_VLAN_EXTEND_MASK) 953 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 954 " and classification is based on outer tag only\n"); 955 956 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 957 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 958 } 959 960 static void qede_prandom_bytes(uint32_t *buff) 961 { 962 uint8_t i; 963 964 srand((unsigned int)time(NULL)); 965 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 966 buff[i] = rand(); 967 } 968 969 int qede_config_rss(struct rte_eth_dev *eth_dev) 970 { 971 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 972 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 973 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 974 #endif 975 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 976 struct rte_eth_rss_reta_entry64 reta_conf[2]; 977 struct rte_eth_rss_conf rss_conf; 978 uint32_t i, id, pos, q; 979 980 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 981 if (!rss_conf.rss_key) { 982 DP_INFO(edev, "Applying driver default key\n"); 983 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 984 qede_prandom_bytes(&def_rss_key[0]); 985 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 986 } 987 988 /* Configure RSS hash */ 989 if (qede_rss_hash_update(eth_dev, &rss_conf)) 990 return -EINVAL; 991 992 /* Configure default RETA */ 993 memset(reta_conf, 0, sizeof(reta_conf)); 994 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 995 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 996 997 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 998 id = i / RTE_RETA_GROUP_SIZE; 999 pos = i % RTE_RETA_GROUP_SIZE; 1000 q = i % QEDE_RSS_COUNT(qdev); 1001 reta_conf[id].reta[pos] = q; 1002 } 1003 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1004 ECORE_RSS_IND_TABLE_SIZE)) 1005 return -EINVAL; 1006 1007 return 0; 1008 } 1009 1010 static void qede_fastpath_start(struct ecore_dev *edev) 1011 { 1012 struct ecore_hwfn *p_hwfn; 1013 int i; 1014 1015 for_each_hwfn(edev, i) { 1016 p_hwfn = &edev->hwfns[i]; 1017 ecore_hw_start_fastpath(p_hwfn); 1018 } 1019 } 1020 1021 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1022 { 1023 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1024 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1025 1026 PMD_INIT_FUNC_TRACE(edev); 1027 1028 /* Update MTU only if it has changed */ 1029 if (qdev->mtu != qdev->new_mtu) { 1030 if (qede_update_mtu(eth_dev, qdev->new_mtu)) 1031 goto err; 1032 qdev->mtu = qdev->new_mtu; 1033 /* If MTU has changed then update TPA too */ 1034 if (qdev->enable_lro) 1035 if (qede_enable_tpa(eth_dev, true)) 1036 goto err; 1037 } 1038 1039 /* Start queues */ 1040 if (qede_start_queues(eth_dev)) 1041 goto err; 1042 1043 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1044 * enabling RSS. Hence RSS configuration is deferred upto this point. 1045 * Also, we would like to retain similar behavior in PF case, so we 1046 * don't do PF/VF specific check here. 1047 */ 1048 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 1049 if (qede_config_rss(eth_dev)) 1050 goto err; 1051 1052 /* Enable vport*/ 1053 if (qede_activate_vport(eth_dev, true)) 1054 goto err; 1055 1056 /* Bring-up the link */ 1057 qede_dev_set_link_state(eth_dev, true); 1058 1059 /* Start/resume traffic */ 1060 qede_fastpath_start(edev); 1061 1062 DP_INFO(edev, "Device started\n"); 1063 1064 return 0; 1065 err: 1066 DP_ERR(edev, "Device start fails\n"); 1067 return -1; /* common error code is < 0 */ 1068 } 1069 1070 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1071 { 1072 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1073 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1074 1075 PMD_INIT_FUNC_TRACE(edev); 1076 1077 /* Disable vport */ 1078 if (qede_activate_vport(eth_dev, false)) 1079 return; 1080 1081 if (qdev->enable_lro) 1082 qede_enable_tpa(eth_dev, false); 1083 1084 /* TODO: Do we need disable LRO or RSS */ 1085 /* Stop queues */ 1086 qede_stop_queues(eth_dev); 1087 1088 /* Disable traffic */ 1089 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1090 1091 /* Bring the link down */ 1092 qede_dev_set_link_state(eth_dev, false); 1093 1094 DP_INFO(edev, "Device is stopped\n"); 1095 } 1096 1097 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1098 { 1099 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1100 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1101 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1102 1103 PMD_INIT_FUNC_TRACE(edev); 1104 1105 /* Check requirements for 100G mode */ 1106 if (edev->num_hwfns > 1) { 1107 if (eth_dev->data->nb_rx_queues < 2 || 1108 eth_dev->data->nb_tx_queues < 2) { 1109 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 1110 return -EINVAL; 1111 } 1112 1113 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 1114 (eth_dev->data->nb_tx_queues % 2 != 0)) { 1115 DP_ERR(edev, 1116 "100G mode needs even no. of RX/TX queues\n"); 1117 return -EINVAL; 1118 } 1119 } 1120 1121 /* Sanity checks and throw warnings */ 1122 if (rxmode->enable_scatter) 1123 eth_dev->data->scattered_rx = 1; 1124 if (!rxmode->hw_strip_crc) 1125 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 1126 if (!rxmode->hw_ip_checksum) 1127 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 1128 "in hw\n"); 1129 if (rxmode->header_split) 1130 DP_INFO(edev, "Header split enable is not supported\n"); 1131 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode == 1132 ETH_MQ_RX_RSS)) { 1133 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1134 return -ENOTSUP; 1135 } 1136 /* Flow director mode check */ 1137 if (qede_check_fdir_support(eth_dev)) 1138 return -ENOTSUP; 1139 1140 /* Deallocate resources if held previously. It is needed only if the 1141 * queue count has been changed from previous configuration. If its 1142 * going to change then it means RX/TX queue setup will be called 1143 * again and the fastpath pointers will be reinitialized there. 1144 */ 1145 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues || 1146 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) { 1147 qede_dealloc_fp_resc(eth_dev); 1148 /* Proceed with updated queue count */ 1149 qdev->num_tx_queues = eth_dev->data->nb_tx_queues; 1150 qdev->num_rx_queues = eth_dev->data->nb_rx_queues; 1151 if (qede_alloc_fp_resc(qdev)) 1152 return -ENOMEM; 1153 } 1154 1155 /* VF's MTU has to be set using vport-start where as 1156 * PF's MTU can be updated via vport-update. 1157 */ 1158 if (IS_VF(edev)) { 1159 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len)) 1160 return -1; 1161 } else { 1162 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len)) 1163 return -1; 1164 } 1165 1166 qdev->mtu = rxmode->max_rx_pkt_len; 1167 qdev->new_mtu = qdev->mtu; 1168 1169 /* Configure TPA parameters */ 1170 if (rxmode->enable_lro) { 1171 if (qede_enable_tpa(eth_dev, true)) 1172 return -EINVAL; 1173 /* Enable scatter mode for LRO */ 1174 if (!rxmode->enable_scatter) 1175 eth_dev->data->scattered_rx = 1; 1176 } 1177 qdev->enable_lro = rxmode->enable_lro; 1178 1179 /* Enable VLAN offloads by default */ 1180 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1181 ETH_VLAN_FILTER_MASK | 1182 ETH_VLAN_EXTEND_MASK); 1183 1184 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1185 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); 1186 1187 return 0; 1188 } 1189 1190 /* Info about HW descriptor ring limitations */ 1191 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1192 .nb_max = NUM_RX_BDS_MAX, 1193 .nb_min = 128, 1194 .nb_align = 128 /* lowest common multiple */ 1195 }; 1196 1197 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1198 .nb_max = NUM_TX_BDS_MAX, 1199 .nb_min = 256, 1200 .nb_align = 256, 1201 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1202 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1203 }; 1204 1205 static void 1206 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1207 struct rte_eth_dev_info *dev_info) 1208 { 1209 struct qede_dev *qdev = eth_dev->data->dev_private; 1210 struct ecore_dev *edev = &qdev->edev; 1211 struct qed_link_output link; 1212 uint32_t speed_cap = 0; 1213 1214 PMD_INIT_FUNC_TRACE(edev); 1215 1216 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1217 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1218 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1219 dev_info->rx_desc_lim = qede_rx_desc_lim; 1220 dev_info->tx_desc_lim = qede_tx_desc_lim; 1221 1222 if (IS_PF(edev)) 1223 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1224 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1225 else 1226 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1227 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1228 dev_info->max_tx_queues = dev_info->max_rx_queues; 1229 1230 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1231 dev_info->max_vfs = 0; 1232 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1233 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1234 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1235 1236 dev_info->default_txconf = (struct rte_eth_txconf) { 1237 .txq_flags = QEDE_TXQ_FLAGS, 1238 }; 1239 1240 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 1241 DEV_RX_OFFLOAD_IPV4_CKSUM | 1242 DEV_RX_OFFLOAD_UDP_CKSUM | 1243 DEV_RX_OFFLOAD_TCP_CKSUM | 1244 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1245 DEV_RX_OFFLOAD_TCP_LRO); 1246 1247 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1248 DEV_TX_OFFLOAD_IPV4_CKSUM | 1249 DEV_TX_OFFLOAD_UDP_CKSUM | 1250 DEV_TX_OFFLOAD_TCP_CKSUM | 1251 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1252 DEV_TX_OFFLOAD_TCP_TSO | 1253 DEV_TX_OFFLOAD_VXLAN_TNL_TSO); 1254 1255 memset(&link, 0, sizeof(struct qed_link_output)); 1256 qdev->ops->common->get_link(edev, &link); 1257 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1258 speed_cap |= ETH_LINK_SPEED_1G; 1259 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1260 speed_cap |= ETH_LINK_SPEED_10G; 1261 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1262 speed_cap |= ETH_LINK_SPEED_25G; 1263 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1264 speed_cap |= ETH_LINK_SPEED_40G; 1265 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1266 speed_cap |= ETH_LINK_SPEED_50G; 1267 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1268 speed_cap |= ETH_LINK_SPEED_100G; 1269 dev_info->speed_capa = speed_cap; 1270 } 1271 1272 /* return 0 means link status changed, -1 means not changed */ 1273 static int 1274 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1275 { 1276 struct qede_dev *qdev = eth_dev->data->dev_private; 1277 struct ecore_dev *edev = &qdev->edev; 1278 uint16_t link_duplex; 1279 struct qed_link_output link; 1280 struct rte_eth_link *curr = ð_dev->data->dev_link; 1281 1282 memset(&link, 0, sizeof(struct qed_link_output)); 1283 qdev->ops->common->get_link(edev, &link); 1284 1285 /* Link Speed */ 1286 curr->link_speed = link.speed; 1287 1288 /* Link Mode */ 1289 switch (link.duplex) { 1290 case QEDE_DUPLEX_HALF: 1291 link_duplex = ETH_LINK_HALF_DUPLEX; 1292 break; 1293 case QEDE_DUPLEX_FULL: 1294 link_duplex = ETH_LINK_FULL_DUPLEX; 1295 break; 1296 case QEDE_DUPLEX_UNKNOWN: 1297 default: 1298 link_duplex = -1; 1299 } 1300 curr->link_duplex = link_duplex; 1301 1302 /* Link Status */ 1303 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 1304 1305 /* AN */ 1306 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1307 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1308 1309 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1310 curr->link_speed, curr->link_duplex, 1311 curr->link_autoneg, curr->link_status); 1312 1313 /* return 0 means link status changed, -1 means not changed */ 1314 return ((curr->link_status == link.link_up) ? -1 : 0); 1315 } 1316 1317 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1318 { 1319 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1320 struct qede_dev *qdev = eth_dev->data->dev_private; 1321 struct ecore_dev *edev = &qdev->edev; 1322 1323 PMD_INIT_FUNC_TRACE(edev); 1324 #endif 1325 1326 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1327 1328 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1329 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1330 1331 qed_configure_filter_rx_mode(eth_dev, type); 1332 } 1333 1334 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1335 { 1336 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1337 struct qede_dev *qdev = eth_dev->data->dev_private; 1338 struct ecore_dev *edev = &qdev->edev; 1339 1340 PMD_INIT_FUNC_TRACE(edev); 1341 #endif 1342 1343 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1344 qed_configure_filter_rx_mode(eth_dev, 1345 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1346 else 1347 qed_configure_filter_rx_mode(eth_dev, 1348 QED_FILTER_RX_MODE_TYPE_REGULAR); 1349 } 1350 1351 static void qede_poll_sp_sb_cb(void *param) 1352 { 1353 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1354 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1355 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1356 int rc; 1357 1358 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1359 qede_interrupt_action(&edev->hwfns[1]); 1360 1361 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1362 qede_poll_sp_sb_cb, 1363 (void *)eth_dev); 1364 if (rc != 0) { 1365 DP_ERR(edev, "Unable to start periodic" 1366 " timer rc %d\n", rc); 1367 assert(false && "Unable to start periodic timer"); 1368 } 1369 } 1370 1371 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1372 { 1373 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1374 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1375 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1376 1377 PMD_INIT_FUNC_TRACE(edev); 1378 1379 /* dev_stop() shall cleanup fp resources in hw but without releasing 1380 * dma memories and sw structures so that dev_start() can be called 1381 * by the app without reconfiguration. However, in dev_close() we 1382 * can release all the resources and device can be brought up newly 1383 */ 1384 if (eth_dev->data->dev_started) 1385 qede_dev_stop(eth_dev); 1386 1387 qede_stop_vport(edev); 1388 qede_fdir_dealloc_resc(eth_dev); 1389 qede_dealloc_fp_resc(eth_dev); 1390 1391 eth_dev->data->nb_rx_queues = 0; 1392 eth_dev->data->nb_tx_queues = 0; 1393 1394 qdev->ops->common->slowpath_stop(edev); 1395 qdev->ops->common->remove(edev); 1396 rte_intr_disable(&pci_dev->intr_handle); 1397 rte_intr_callback_unregister(&pci_dev->intr_handle, 1398 qede_interrupt_handler, (void *)eth_dev); 1399 if (edev->num_hwfns > 1) 1400 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1401 } 1402 1403 static void 1404 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1405 { 1406 struct qede_dev *qdev = eth_dev->data->dev_private; 1407 struct ecore_dev *edev = &qdev->edev; 1408 struct ecore_eth_stats stats; 1409 unsigned int i = 0, j = 0, qid; 1410 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1411 struct qede_tx_queue *txq; 1412 1413 ecore_get_vport_stats(edev, &stats); 1414 1415 /* RX Stats */ 1416 eth_stats->ipackets = stats.rx_ucast_pkts + 1417 stats.rx_mcast_pkts + stats.rx_bcast_pkts; 1418 1419 eth_stats->ibytes = stats.rx_ucast_bytes + 1420 stats.rx_mcast_bytes + stats.rx_bcast_bytes; 1421 1422 eth_stats->ierrors = stats.rx_crc_errors + 1423 stats.rx_align_errors + 1424 stats.rx_carrier_errors + 1425 stats.rx_oversize_packets + 1426 stats.rx_jabbers + stats.rx_undersize_packets; 1427 1428 eth_stats->rx_nombuf = stats.no_buff_discards; 1429 1430 eth_stats->imissed = stats.mftag_filter_discards + 1431 stats.mac_filter_discards + 1432 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards; 1433 1434 /* TX stats */ 1435 eth_stats->opackets = stats.tx_ucast_pkts + 1436 stats.tx_mcast_pkts + stats.tx_bcast_pkts; 1437 1438 eth_stats->obytes = stats.tx_ucast_bytes + 1439 stats.tx_mcast_bytes + stats.tx_bcast_bytes; 1440 1441 eth_stats->oerrors = stats.tx_err_drop_pkts; 1442 1443 /* Queue stats */ 1444 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1445 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1446 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1447 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1448 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) || 1449 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev))) 1450 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1451 "Not all the queue stats will be displayed. Set" 1452 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1453 " appropriately and retry.\n"); 1454 1455 for_each_rss(qid) { 1456 eth_stats->q_ipackets[i] = 1457 *(uint64_t *)( 1458 ((char *)(qdev->fp_array[qid].rxq)) + 1459 offsetof(struct qede_rx_queue, 1460 rcv_pkts)); 1461 eth_stats->q_errors[i] = 1462 *(uint64_t *)( 1463 ((char *)(qdev->fp_array[qid].rxq)) + 1464 offsetof(struct qede_rx_queue, 1465 rx_hw_errors)) + 1466 *(uint64_t *)( 1467 ((char *)(qdev->fp_array[qid].rxq)) + 1468 offsetof(struct qede_rx_queue, 1469 rx_alloc_errors)); 1470 i++; 1471 if (i == rxq_stat_cntrs) 1472 break; 1473 } 1474 1475 for_each_tss(qid) { 1476 txq = qdev->fp_array[qid].txq; 1477 eth_stats->q_opackets[j] = 1478 *((uint64_t *)(uintptr_t) 1479 (((uint64_t)(uintptr_t)(txq)) + 1480 offsetof(struct qede_tx_queue, 1481 xmit_pkts))); 1482 j++; 1483 if (j == txq_stat_cntrs) 1484 break; 1485 } 1486 } 1487 1488 static unsigned 1489 qede_get_xstats_count(struct qede_dev *qdev) { 1490 return RTE_DIM(qede_xstats_strings) + 1491 (RTE_DIM(qede_rxq_xstats_strings) * 1492 RTE_MIN(QEDE_RSS_COUNT(qdev), 1493 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1494 } 1495 1496 static int 1497 qede_get_xstats_names(struct rte_eth_dev *dev, 1498 struct rte_eth_xstat_name *xstats_names, 1499 __rte_unused unsigned int limit) 1500 { 1501 struct qede_dev *qdev = dev->data->dev_private; 1502 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1503 unsigned int i, qid, stat_idx = 0; 1504 unsigned int rxq_stat_cntrs; 1505 1506 if (xstats_names != NULL) { 1507 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1508 snprintf(xstats_names[stat_idx].name, 1509 sizeof(xstats_names[stat_idx].name), 1510 "%s", 1511 qede_xstats_strings[i].name); 1512 stat_idx++; 1513 } 1514 1515 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1516 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1517 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1518 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1519 snprintf(xstats_names[stat_idx].name, 1520 sizeof(xstats_names[stat_idx].name), 1521 "%.4s%d%s", 1522 qede_rxq_xstats_strings[i].name, qid, 1523 qede_rxq_xstats_strings[i].name + 4); 1524 stat_idx++; 1525 } 1526 } 1527 } 1528 1529 return stat_cnt; 1530 } 1531 1532 static int 1533 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1534 unsigned int n) 1535 { 1536 struct qede_dev *qdev = dev->data->dev_private; 1537 struct ecore_dev *edev = &qdev->edev; 1538 struct ecore_eth_stats stats; 1539 const unsigned int num = qede_get_xstats_count(qdev); 1540 unsigned int i, qid, stat_idx = 0; 1541 unsigned int rxq_stat_cntrs; 1542 1543 if (n < num) 1544 return num; 1545 1546 ecore_get_vport_stats(edev, &stats); 1547 1548 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1549 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1550 qede_xstats_strings[i].offset); 1551 xstats[stat_idx].id = stat_idx; 1552 stat_idx++; 1553 } 1554 1555 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1556 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1557 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1558 for_each_rss(qid) { 1559 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1560 xstats[stat_idx].value = *(uint64_t *)( 1561 ((char *)(qdev->fp_array[qid].rxq)) + 1562 qede_rxq_xstats_strings[i].offset); 1563 xstats[stat_idx].id = stat_idx; 1564 stat_idx++; 1565 } 1566 } 1567 } 1568 1569 return stat_idx; 1570 } 1571 1572 static void 1573 qede_reset_xstats(struct rte_eth_dev *dev) 1574 { 1575 struct qede_dev *qdev = dev->data->dev_private; 1576 struct ecore_dev *edev = &qdev->edev; 1577 1578 ecore_reset_vport_stats(edev); 1579 } 1580 1581 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1582 { 1583 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1584 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1585 struct qed_link_params link_params; 1586 int rc; 1587 1588 DP_INFO(edev, "setting link state %d\n", link_up); 1589 memset(&link_params, 0, sizeof(link_params)); 1590 link_params.link_up = link_up; 1591 rc = qdev->ops->common->set_link(edev, &link_params); 1592 if (rc != ECORE_SUCCESS) 1593 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1594 1595 return rc; 1596 } 1597 1598 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1599 { 1600 return qede_dev_set_link_state(eth_dev, true); 1601 } 1602 1603 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1604 { 1605 return qede_dev_set_link_state(eth_dev, false); 1606 } 1607 1608 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1609 { 1610 struct qede_dev *qdev = eth_dev->data->dev_private; 1611 struct ecore_dev *edev = &qdev->edev; 1612 1613 ecore_reset_vport_stats(edev); 1614 } 1615 1616 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1617 { 1618 enum qed_filter_rx_mode_type type = 1619 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1620 1621 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1622 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1623 1624 qed_configure_filter_rx_mode(eth_dev, type); 1625 } 1626 1627 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1628 { 1629 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1630 qed_configure_filter_rx_mode(eth_dev, 1631 QED_FILTER_RX_MODE_TYPE_PROMISC); 1632 else 1633 qed_configure_filter_rx_mode(eth_dev, 1634 QED_FILTER_RX_MODE_TYPE_REGULAR); 1635 } 1636 1637 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1638 struct rte_eth_fc_conf *fc_conf) 1639 { 1640 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1641 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1642 struct qed_link_output current_link; 1643 struct qed_link_params params; 1644 1645 memset(¤t_link, 0, sizeof(current_link)); 1646 qdev->ops->common->get_link(edev, ¤t_link); 1647 1648 memset(¶ms, 0, sizeof(params)); 1649 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1650 if (fc_conf->autoneg) { 1651 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1652 DP_ERR(edev, "Autoneg not supported\n"); 1653 return -EINVAL; 1654 } 1655 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1656 } 1657 1658 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1659 if (fc_conf->mode == RTE_FC_FULL) 1660 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1661 QED_LINK_PAUSE_RX_ENABLE); 1662 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1663 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1664 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1665 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1666 1667 params.link_up = true; 1668 (void)qdev->ops->common->set_link(edev, ¶ms); 1669 1670 return 0; 1671 } 1672 1673 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1674 struct rte_eth_fc_conf *fc_conf) 1675 { 1676 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1677 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1678 struct qed_link_output current_link; 1679 1680 memset(¤t_link, 0, sizeof(current_link)); 1681 qdev->ops->common->get_link(edev, ¤t_link); 1682 1683 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1684 fc_conf->autoneg = true; 1685 1686 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1687 QED_LINK_PAUSE_TX_ENABLE)) 1688 fc_conf->mode = RTE_FC_FULL; 1689 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1690 fc_conf->mode = RTE_FC_RX_PAUSE; 1691 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1692 fc_conf->mode = RTE_FC_TX_PAUSE; 1693 else 1694 fc_conf->mode = RTE_FC_NONE; 1695 1696 return 0; 1697 } 1698 1699 static const uint32_t * 1700 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1701 { 1702 static const uint32_t ptypes[] = { 1703 RTE_PTYPE_L3_IPV4, 1704 RTE_PTYPE_L3_IPV6, 1705 RTE_PTYPE_UNKNOWN 1706 }; 1707 1708 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1709 return ptypes; 1710 1711 return NULL; 1712 } 1713 1714 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1715 { 1716 *rss_caps = 0; 1717 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1718 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1719 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1720 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1721 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1722 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1723 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 1724 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 1725 } 1726 1727 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1728 struct rte_eth_rss_conf *rss_conf) 1729 { 1730 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1731 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1732 struct ecore_sp_vport_update_params vport_update_params; 1733 struct ecore_rss_params rss_params; 1734 struct ecore_hwfn *p_hwfn; 1735 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1736 uint64_t hf = rss_conf->rss_hf; 1737 uint8_t len = rss_conf->rss_key_len; 1738 uint8_t idx; 1739 uint8_t i; 1740 int rc; 1741 1742 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1743 memset(&rss_params, 0, sizeof(rss_params)); 1744 1745 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 1746 (unsigned long)hf, len, key); 1747 1748 if (hf != 0) { 1749 /* Enabling RSS */ 1750 DP_INFO(edev, "Enabling rss\n"); 1751 1752 /* RSS caps */ 1753 qede_init_rss_caps(&rss_params.rss_caps, hf); 1754 rss_params.update_rss_capabilities = 1; 1755 1756 /* RSS hash key */ 1757 if (key) { 1758 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 1759 DP_ERR(edev, "RSS key length exceeds limit\n"); 1760 return -EINVAL; 1761 } 1762 DP_INFO(edev, "Applying user supplied hash key\n"); 1763 rss_params.update_rss_key = 1; 1764 memcpy(&rss_params.rss_key, key, len); 1765 } 1766 rss_params.rss_enable = 1; 1767 } 1768 1769 rss_params.update_rss_config = 1; 1770 /* tbl_size has to be set with capabilities */ 1771 rss_params.rss_table_size_log = 7; 1772 vport_update_params.vport_id = 0; 1773 /* pass the L2 handles instead of qids */ 1774 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 1775 idx = qdev->rss_ind_table[i]; 1776 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 1777 } 1778 vport_update_params.rss_params = &rss_params; 1779 1780 for_each_hwfn(edev, i) { 1781 p_hwfn = &edev->hwfns[i]; 1782 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1783 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1784 ECORE_SPQ_MODE_EBLOCK, NULL); 1785 if (rc) { 1786 DP_ERR(edev, "vport-update for RSS failed\n"); 1787 return rc; 1788 } 1789 } 1790 qdev->rss_enable = rss_params.rss_enable; 1791 1792 /* Update local structure for hash query */ 1793 qdev->rss_conf.rss_hf = hf; 1794 qdev->rss_conf.rss_key_len = len; 1795 if (qdev->rss_enable) { 1796 if (qdev->rss_conf.rss_key == NULL) { 1797 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 1798 if (qdev->rss_conf.rss_key == NULL) { 1799 DP_ERR(edev, "No memory to store RSS key\n"); 1800 return -ENOMEM; 1801 } 1802 } 1803 if (key && len) { 1804 DP_INFO(edev, "Storing RSS key\n"); 1805 memcpy(qdev->rss_conf.rss_key, key, len); 1806 } 1807 } else if (!qdev->rss_enable && len == 0) { 1808 if (qdev->rss_conf.rss_key) { 1809 free(qdev->rss_conf.rss_key); 1810 qdev->rss_conf.rss_key = NULL; 1811 DP_INFO(edev, "Free RSS key\n"); 1812 } 1813 } 1814 1815 return 0; 1816 } 1817 1818 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1819 struct rte_eth_rss_conf *rss_conf) 1820 { 1821 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1822 1823 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 1824 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 1825 1826 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 1827 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 1828 rss_conf->rss_key_len); 1829 return 0; 1830 } 1831 1832 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev, 1833 struct ecore_rss_params *rss) 1834 { 1835 int i, fn; 1836 bool rss_mode = 1; /* enable */ 1837 struct ecore_queue_cid *cid; 1838 struct ecore_rss_params *t_rss; 1839 1840 /* In regular scenario, we'd simply need to take input handlers. 1841 * But in CMT, we'd have to split the handlers according to the 1842 * engine they were configured on. We'd then have to understand 1843 * whether RSS is really required, since 2-queues on CMT doesn't 1844 * require RSS. 1845 */ 1846 1847 /* CMT should be round-robin */ 1848 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1849 cid = rss->rss_ind_table[i]; 1850 1851 if (cid->p_owner == ECORE_LEADING_HWFN(edev)) 1852 t_rss = &rss[0]; 1853 else 1854 t_rss = &rss[1]; 1855 1856 t_rss->rss_ind_table[i / edev->num_hwfns] = cid; 1857 } 1858 1859 t_rss = &rss[1]; 1860 t_rss->update_rss_ind_table = 1; 1861 t_rss->rss_table_size_log = 7; 1862 t_rss->update_rss_config = 1; 1863 1864 /* Make sure RSS is actually required */ 1865 for_each_hwfn(edev, fn) { 1866 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns; 1867 i++) { 1868 if (rss[fn].rss_ind_table[i] != 1869 rss[fn].rss_ind_table[0]) 1870 break; 1871 } 1872 1873 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) { 1874 DP_INFO(edev, 1875 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 1876 rss_mode = 0; 1877 goto out; 1878 } 1879 } 1880 1881 out: 1882 t_rss->rss_enable = rss_mode; 1883 1884 return rss_mode; 1885 } 1886 1887 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 1888 struct rte_eth_rss_reta_entry64 *reta_conf, 1889 uint16_t reta_size) 1890 { 1891 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1892 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1893 struct ecore_sp_vport_update_params vport_update_params; 1894 struct ecore_rss_params *params; 1895 struct ecore_hwfn *p_hwfn; 1896 uint16_t i, idx, shift; 1897 uint8_t entry; 1898 int rc = 0; 1899 1900 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1901 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 1902 reta_size); 1903 return -EINVAL; 1904 } 1905 1906 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1907 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns, 1908 RTE_CACHE_LINE_SIZE); 1909 1910 for (i = 0; i < reta_size; i++) { 1911 idx = i / RTE_RETA_GROUP_SIZE; 1912 shift = i % RTE_RETA_GROUP_SIZE; 1913 if (reta_conf[idx].mask & (1ULL << shift)) { 1914 entry = reta_conf[idx].reta[shift]; 1915 /* Pass rxq handles to ecore */ 1916 params->rss_ind_table[i] = 1917 qdev->fp_array[entry].rxq->handle; 1918 /* Update the local copy for RETA query command */ 1919 qdev->rss_ind_table[i] = entry; 1920 } 1921 } 1922 1923 params->update_rss_ind_table = 1; 1924 params->rss_table_size_log = 7; 1925 params->update_rss_config = 1; 1926 1927 /* Fix up RETA for CMT mode device */ 1928 if (edev->num_hwfns > 1) 1929 qdev->rss_enable = qede_update_rss_parm_cmt(edev, 1930 params); 1931 vport_update_params.vport_id = 0; 1932 /* Use the current value of rss_enable */ 1933 params->rss_enable = qdev->rss_enable; 1934 vport_update_params.rss_params = params; 1935 1936 for_each_hwfn(edev, i) { 1937 p_hwfn = &edev->hwfns[i]; 1938 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1939 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1940 ECORE_SPQ_MODE_EBLOCK, NULL); 1941 if (rc) { 1942 DP_ERR(edev, "vport-update for RSS failed\n"); 1943 goto out; 1944 } 1945 } 1946 1947 out: 1948 rte_free(params); 1949 return rc; 1950 } 1951 1952 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 1953 struct rte_eth_rss_reta_entry64 *reta_conf, 1954 uint16_t reta_size) 1955 { 1956 struct qede_dev *qdev = eth_dev->data->dev_private; 1957 struct ecore_dev *edev = &qdev->edev; 1958 uint16_t i, idx, shift; 1959 uint8_t entry; 1960 1961 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1962 DP_ERR(edev, "reta_size %d is not supported\n", 1963 reta_size); 1964 return -EINVAL; 1965 } 1966 1967 for (i = 0; i < reta_size; i++) { 1968 idx = i / RTE_RETA_GROUP_SIZE; 1969 shift = i % RTE_RETA_GROUP_SIZE; 1970 if (reta_conf[idx].mask & (1ULL << shift)) { 1971 entry = qdev->rss_ind_table[i]; 1972 reta_conf[idx].reta[shift] = entry; 1973 } 1974 } 1975 1976 return 0; 1977 } 1978 1979 1980 1981 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1982 { 1983 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 1984 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1985 struct rte_eth_dev_info dev_info = {0}; 1986 struct qede_fastpath *fp; 1987 uint32_t frame_size; 1988 uint16_t rx_buf_size; 1989 uint16_t bufsz; 1990 int i; 1991 1992 PMD_INIT_FUNC_TRACE(edev); 1993 qede_dev_info_get(dev, &dev_info); 1994 frame_size = mtu + QEDE_ETH_OVERHEAD; 1995 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { 1996 DP_ERR(edev, "MTU %u out of range\n", mtu); 1997 return -EINVAL; 1998 } 1999 if (!dev->data->scattered_rx && 2000 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2001 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2002 dev->data->min_rx_buf_size); 2003 return -EINVAL; 2004 } 2005 /* Temporarily replace I/O functions with dummy ones. It cannot 2006 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 2007 */ 2008 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 2009 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 2010 qede_dev_stop(dev); 2011 rte_delay_ms(1000); 2012 qdev->mtu = mtu; 2013 /* Fix up RX buf size for all queues of the port */ 2014 for_each_rss(i) { 2015 fp = &qdev->fp_array[i]; 2016 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2017 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2018 if (dev->data->scattered_rx) 2019 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD; 2020 else 2021 rx_buf_size = mtu + QEDE_ETH_OVERHEAD; 2022 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); 2023 fp->rxq->rx_buf_size = rx_buf_size; 2024 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size); 2025 } 2026 qede_dev_start(dev); 2027 if (frame_size > ETHER_MAX_LEN) 2028 dev->data->dev_conf.rxmode.jumbo_frame = 1; 2029 else 2030 dev->data->dev_conf.rxmode.jumbo_frame = 0; 2031 /* update max frame size */ 2032 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2033 /* Reassign back */ 2034 dev->rx_pkt_burst = qede_recv_pkts; 2035 dev->tx_pkt_burst = qede_xmit_pkts; 2036 2037 return 0; 2038 } 2039 2040 static int 2041 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev, 2042 struct rte_eth_udp_tunnel *tunnel_udp, 2043 bool add) 2044 { 2045 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2046 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2047 struct ecore_tunnel_info tunn; /* @DPDK */ 2048 struct ecore_hwfn *p_hwfn; 2049 int rc, i; 2050 2051 PMD_INIT_FUNC_TRACE(edev); 2052 2053 memset(&tunn, 0, sizeof(tunn)); 2054 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) { 2055 tunn.vxlan_port.b_update_port = true; 2056 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port : 2057 QEDE_VXLAN_DEF_PORT; 2058 for_each_hwfn(edev, i) { 2059 p_hwfn = &edev->hwfns[i]; 2060 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 2061 ECORE_SPQ_MODE_CB, NULL); 2062 if (rc != ECORE_SUCCESS) { 2063 DP_ERR(edev, "Unable to config UDP port %u\n", 2064 tunn.vxlan_port.port); 2065 return rc; 2066 } 2067 } 2068 } 2069 2070 return 0; 2071 } 2072 2073 static int 2074 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 2075 struct rte_eth_udp_tunnel *tunnel_udp) 2076 { 2077 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false); 2078 } 2079 2080 static int 2081 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 2082 struct rte_eth_udp_tunnel *tunnel_udp) 2083 { 2084 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true); 2085 } 2086 2087 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 2088 uint32_t *clss, char *str) 2089 { 2090 uint16_t j; 2091 *clss = MAX_ECORE_TUNN_CLSS; 2092 2093 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 2094 if (filter == qede_tunn_types[j].rte_filter_type) { 2095 *type = qede_tunn_types[j].qede_type; 2096 *clss = qede_tunn_types[j].qede_tunn_clss; 2097 strcpy(str, qede_tunn_types[j].string); 2098 return; 2099 } 2100 } 2101 } 2102 2103 static int 2104 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 2105 const struct rte_eth_tunnel_filter_conf *conf, 2106 uint32_t type) 2107 { 2108 /* Init commmon ucast params first */ 2109 qede_set_ucast_cmn_params(ucast); 2110 2111 /* Copy out the required fields based on classification type */ 2112 ucast->type = type; 2113 2114 switch (type) { 2115 case ECORE_FILTER_VNI: 2116 ucast->vni = conf->tenant_id; 2117 break; 2118 case ECORE_FILTER_INNER_VLAN: 2119 ucast->vlan = conf->inner_vlan; 2120 break; 2121 case ECORE_FILTER_MAC: 2122 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2123 ETHER_ADDR_LEN); 2124 break; 2125 case ECORE_FILTER_INNER_MAC: 2126 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2127 ETHER_ADDR_LEN); 2128 break; 2129 case ECORE_FILTER_MAC_VNI_PAIR: 2130 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2131 ETHER_ADDR_LEN); 2132 ucast->vni = conf->tenant_id; 2133 break; 2134 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 2135 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2136 ETHER_ADDR_LEN); 2137 ucast->vni = conf->tenant_id; 2138 break; 2139 case ECORE_FILTER_INNER_PAIR: 2140 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2141 ETHER_ADDR_LEN); 2142 ucast->vlan = conf->inner_vlan; 2143 break; 2144 default: 2145 return -EINVAL; 2146 } 2147 2148 return ECORE_SUCCESS; 2149 } 2150 2151 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, 2152 enum rte_filter_op filter_op, 2153 const struct rte_eth_tunnel_filter_conf *conf) 2154 { 2155 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2156 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2157 struct ecore_tunnel_info tunn; 2158 struct ecore_hwfn *p_hwfn; 2159 enum ecore_filter_ucast_type type; 2160 enum ecore_tunn_clss clss; 2161 struct ecore_filter_ucast ucast; 2162 char str[80]; 2163 uint16_t filter_type; 2164 int rc, i; 2165 2166 filter_type = conf->filter_type | qdev->vxlan_filter_type; 2167 /* First determine if the given filter classification is supported */ 2168 qede_get_ecore_tunn_params(filter_type, &type, &clss, str); 2169 if (clss == MAX_ECORE_TUNN_CLSS) { 2170 DP_ERR(edev, "Wrong filter type\n"); 2171 return -EINVAL; 2172 } 2173 /* Init tunnel ucast params */ 2174 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2175 if (rc != ECORE_SUCCESS) { 2176 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n", 2177 conf->filter_type); 2178 return rc; 2179 } 2180 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2181 str, filter_op, ucast.type); 2182 switch (filter_op) { 2183 case RTE_ETH_FILTER_ADD: 2184 ucast.opcode = ECORE_FILTER_ADD; 2185 2186 /* Skip MAC/VLAN if filter is based on VNI */ 2187 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2188 rc = qede_mac_int_ops(eth_dev, &ucast, 1); 2189 if (rc == 0) { 2190 /* Enable accept anyvlan */ 2191 qede_config_accept_any_vlan(qdev, true); 2192 } 2193 } else { 2194 rc = qede_ucast_filter(eth_dev, &ucast, 1); 2195 if (rc == 0) 2196 rc = ecore_filter_ucast_cmd(edev, &ucast, 2197 ECORE_SPQ_MODE_CB, NULL); 2198 } 2199 2200 if (rc != ECORE_SUCCESS) 2201 return rc; 2202 2203 qdev->vxlan_filter_type = filter_type; 2204 2205 DP_INFO(edev, "Enabling VXLAN tunneling\n"); 2206 qede_set_cmn_tunn_param(&tunn, clss, true, true); 2207 for_each_hwfn(edev, i) { 2208 p_hwfn = &edev->hwfns[i]; 2209 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, 2210 &tunn, ECORE_SPQ_MODE_CB, NULL); 2211 if (rc != ECORE_SUCCESS) { 2212 DP_ERR(edev, "Failed to update tunn_clss %u\n", 2213 tunn.vxlan.tun_cls); 2214 } 2215 } 2216 qdev->num_tunn_filters++; /* Filter added successfully */ 2217 break; 2218 case RTE_ETH_FILTER_DELETE: 2219 ucast.opcode = ECORE_FILTER_REMOVE; 2220 2221 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2222 rc = qede_mac_int_ops(eth_dev, &ucast, 0); 2223 } else { 2224 rc = qede_ucast_filter(eth_dev, &ucast, 0); 2225 if (rc == 0) 2226 rc = ecore_filter_ucast_cmd(edev, &ucast, 2227 ECORE_SPQ_MODE_CB, NULL); 2228 } 2229 if (rc != ECORE_SUCCESS) 2230 return rc; 2231 2232 qdev->vxlan_filter_type = filter_type; 2233 qdev->num_tunn_filters--; 2234 2235 /* Disable VXLAN if VXLAN filters become 0 */ 2236 if (qdev->num_tunn_filters == 0) { 2237 DP_INFO(edev, "Disabling VXLAN tunneling\n"); 2238 2239 /* Use 0 as tunnel mode */ 2240 qede_set_cmn_tunn_param(&tunn, clss, false, true); 2241 for_each_hwfn(edev, i) { 2242 p_hwfn = &edev->hwfns[i]; 2243 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 2244 ECORE_SPQ_MODE_CB, NULL); 2245 if (rc != ECORE_SUCCESS) { 2246 DP_ERR(edev, 2247 "Failed to update tunn_clss %u\n", 2248 tunn.vxlan.tun_cls); 2249 break; 2250 } 2251 } 2252 } 2253 break; 2254 default: 2255 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 2256 return -EINVAL; 2257 } 2258 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters); 2259 2260 return 0; 2261 } 2262 2263 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 2264 enum rte_filter_type filter_type, 2265 enum rte_filter_op filter_op, 2266 void *arg) 2267 { 2268 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2269 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2270 struct rte_eth_tunnel_filter_conf *filter_conf = 2271 (struct rte_eth_tunnel_filter_conf *)arg; 2272 2273 switch (filter_type) { 2274 case RTE_ETH_FILTER_TUNNEL: 2275 switch (filter_conf->tunnel_type) { 2276 case RTE_TUNNEL_TYPE_VXLAN: 2277 DP_INFO(edev, 2278 "Packet steering to the specified Rx queue" 2279 " is not supported with VXLAN tunneling"); 2280 return(qede_vxlan_tunn_config(eth_dev, filter_op, 2281 filter_conf)); 2282 /* Place holders for future tunneling support */ 2283 case RTE_TUNNEL_TYPE_GENEVE: 2284 case RTE_TUNNEL_TYPE_TEREDO: 2285 case RTE_TUNNEL_TYPE_NVGRE: 2286 case RTE_TUNNEL_TYPE_IP_IN_GRE: 2287 case RTE_L2_TUNNEL_TYPE_E_TAG: 2288 DP_ERR(edev, "Unsupported tunnel type %d\n", 2289 filter_conf->tunnel_type); 2290 return -EINVAL; 2291 case RTE_TUNNEL_TYPE_NONE: 2292 default: 2293 return 0; 2294 } 2295 break; 2296 case RTE_ETH_FILTER_FDIR: 2297 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 2298 case RTE_ETH_FILTER_NTUPLE: 2299 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 2300 case RTE_ETH_FILTER_MACVLAN: 2301 case RTE_ETH_FILTER_ETHERTYPE: 2302 case RTE_ETH_FILTER_FLEXIBLE: 2303 case RTE_ETH_FILTER_SYN: 2304 case RTE_ETH_FILTER_HASH: 2305 case RTE_ETH_FILTER_L2_TUNNEL: 2306 case RTE_ETH_FILTER_MAX: 2307 default: 2308 DP_ERR(edev, "Unsupported filter type %d\n", 2309 filter_type); 2310 return -EINVAL; 2311 } 2312 2313 return 0; 2314 } 2315 2316 static const struct eth_dev_ops qede_eth_dev_ops = { 2317 .dev_configure = qede_dev_configure, 2318 .dev_infos_get = qede_dev_info_get, 2319 .rx_queue_setup = qede_rx_queue_setup, 2320 .rx_queue_release = qede_rx_queue_release, 2321 .tx_queue_setup = qede_tx_queue_setup, 2322 .tx_queue_release = qede_tx_queue_release, 2323 .dev_start = qede_dev_start, 2324 .dev_set_link_up = qede_dev_set_link_up, 2325 .dev_set_link_down = qede_dev_set_link_down, 2326 .link_update = qede_link_update, 2327 .promiscuous_enable = qede_promiscuous_enable, 2328 .promiscuous_disable = qede_promiscuous_disable, 2329 .allmulticast_enable = qede_allmulticast_enable, 2330 .allmulticast_disable = qede_allmulticast_disable, 2331 .dev_stop = qede_dev_stop, 2332 .dev_close = qede_dev_close, 2333 .stats_get = qede_get_stats, 2334 .stats_reset = qede_reset_stats, 2335 .xstats_get = qede_get_xstats, 2336 .xstats_reset = qede_reset_xstats, 2337 .xstats_get_names = qede_get_xstats_names, 2338 .mac_addr_add = qede_mac_addr_add, 2339 .mac_addr_remove = qede_mac_addr_remove, 2340 .mac_addr_set = qede_mac_addr_set, 2341 .vlan_offload_set = qede_vlan_offload_set, 2342 .vlan_filter_set = qede_vlan_filter_set, 2343 .flow_ctrl_set = qede_flow_ctrl_set, 2344 .flow_ctrl_get = qede_flow_ctrl_get, 2345 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2346 .rss_hash_update = qede_rss_hash_update, 2347 .rss_hash_conf_get = qede_rss_hash_conf_get, 2348 .reta_update = qede_rss_reta_update, 2349 .reta_query = qede_rss_reta_query, 2350 .mtu_set = qede_set_mtu, 2351 .filter_ctrl = qede_dev_filter_ctrl, 2352 .udp_tunnel_port_add = qede_udp_dst_port_add, 2353 .udp_tunnel_port_del = qede_udp_dst_port_del, 2354 }; 2355 2356 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2357 .dev_configure = qede_dev_configure, 2358 .dev_infos_get = qede_dev_info_get, 2359 .rx_queue_setup = qede_rx_queue_setup, 2360 .rx_queue_release = qede_rx_queue_release, 2361 .tx_queue_setup = qede_tx_queue_setup, 2362 .tx_queue_release = qede_tx_queue_release, 2363 .dev_start = qede_dev_start, 2364 .dev_set_link_up = qede_dev_set_link_up, 2365 .dev_set_link_down = qede_dev_set_link_down, 2366 .link_update = qede_link_update, 2367 .promiscuous_enable = qede_promiscuous_enable, 2368 .promiscuous_disable = qede_promiscuous_disable, 2369 .allmulticast_enable = qede_allmulticast_enable, 2370 .allmulticast_disable = qede_allmulticast_disable, 2371 .dev_stop = qede_dev_stop, 2372 .dev_close = qede_dev_close, 2373 .stats_get = qede_get_stats, 2374 .stats_reset = qede_reset_stats, 2375 .xstats_get = qede_get_xstats, 2376 .xstats_reset = qede_reset_xstats, 2377 .xstats_get_names = qede_get_xstats_names, 2378 .vlan_offload_set = qede_vlan_offload_set, 2379 .vlan_filter_set = qede_vlan_filter_set, 2380 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2381 .rss_hash_update = qede_rss_hash_update, 2382 .rss_hash_conf_get = qede_rss_hash_conf_get, 2383 .reta_update = qede_rss_reta_update, 2384 .reta_query = qede_rss_reta_query, 2385 .mtu_set = qede_set_mtu, 2386 }; 2387 2388 static void qede_update_pf_params(struct ecore_dev *edev) 2389 { 2390 struct ecore_pf_params pf_params; 2391 2392 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2393 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2394 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 2395 qed_ops->common->update_pf_params(edev, &pf_params); 2396 } 2397 2398 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2399 { 2400 struct rte_pci_device *pci_dev; 2401 struct rte_pci_addr pci_addr; 2402 struct qede_dev *adapter; 2403 struct ecore_dev *edev; 2404 struct qed_dev_eth_info dev_info; 2405 struct qed_slowpath_params params; 2406 static bool do_once = true; 2407 uint8_t bulletin_change; 2408 uint8_t vf_mac[ETHER_ADDR_LEN]; 2409 uint8_t is_mac_forced; 2410 bool is_mac_exist; 2411 /* Fix up ecore debug level */ 2412 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2413 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2414 int rc; 2415 2416 /* Extract key data structures */ 2417 adapter = eth_dev->data->dev_private; 2418 edev = &adapter->edev; 2419 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2420 pci_addr = pci_dev->addr; 2421 2422 PMD_INIT_FUNC_TRACE(edev); 2423 2424 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2425 pci_addr.bus, pci_addr.devid, pci_addr.function, 2426 eth_dev->data->port_id); 2427 2428 eth_dev->rx_pkt_burst = qede_recv_pkts; 2429 eth_dev->tx_pkt_burst = qede_xmit_pkts; 2430 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 2431 2432 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2433 DP_NOTICE(edev, false, 2434 "Skipping device init from secondary process\n"); 2435 return 0; 2436 } 2437 2438 rte_eth_copy_pci_info(eth_dev, pci_dev); 2439 2440 /* @DPDK */ 2441 edev->vendor_id = pci_dev->id.vendor_id; 2442 edev->device_id = pci_dev->id.device_id; 2443 2444 qed_ops = qed_get_eth_ops(); 2445 if (!qed_ops) { 2446 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2447 return -EINVAL; 2448 } 2449 2450 DP_INFO(edev, "Starting qede probe\n"); 2451 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 2452 dp_level, is_vf); 2453 if (rc != 0) { 2454 DP_ERR(edev, "qede probe failed rc %d\n", rc); 2455 return -ENODEV; 2456 } 2457 qede_update_pf_params(edev); 2458 rte_intr_callback_register(&pci_dev->intr_handle, 2459 qede_interrupt_handler, (void *)eth_dev); 2460 if (rte_intr_enable(&pci_dev->intr_handle)) { 2461 DP_ERR(edev, "rte_intr_enable() failed\n"); 2462 return -ENODEV; 2463 } 2464 2465 /* Start the Slowpath-process */ 2466 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 2467 params.int_mode = ECORE_INT_MODE_MSIX; 2468 params.drv_major = QEDE_PMD_VERSION_MAJOR; 2469 params.drv_minor = QEDE_PMD_VERSION_MINOR; 2470 params.drv_rev = QEDE_PMD_VERSION_REVISION; 2471 params.drv_eng = QEDE_PMD_VERSION_PATCH; 2472 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 2473 QEDE_PMD_DRV_VER_STR_SIZE); 2474 2475 /* For CMT mode device do periodic polling for slowpath events. 2476 * This is required since uio device uses only one MSI-x 2477 * interrupt vector but we need one for each engine. 2478 */ 2479 if (edev->num_hwfns > 1 && IS_PF(edev)) { 2480 rc = rte_eal_alarm_set(timer_period * US_PER_S, 2481 qede_poll_sp_sb_cb, 2482 (void *)eth_dev); 2483 if (rc != 0) { 2484 DP_ERR(edev, "Unable to start periodic" 2485 " timer rc %d\n", rc); 2486 return -EINVAL; 2487 } 2488 } 2489 2490 rc = qed_ops->common->slowpath_start(edev, ¶ms); 2491 if (rc) { 2492 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 2493 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2494 (void *)eth_dev); 2495 return -ENODEV; 2496 } 2497 2498 rc = qed_ops->fill_dev_info(edev, &dev_info); 2499 if (rc) { 2500 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 2501 qed_ops->common->slowpath_stop(edev); 2502 qed_ops->common->remove(edev); 2503 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2504 (void *)eth_dev); 2505 return -ENODEV; 2506 } 2507 2508 qede_alloc_etherdev(adapter, &dev_info); 2509 2510 adapter->ops->common->set_name(edev, edev->name); 2511 2512 if (!is_vf) 2513 adapter->dev_info.num_mac_filters = 2514 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 2515 ECORE_MAC); 2516 else 2517 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 2518 (uint32_t *)&adapter->dev_info.num_mac_filters); 2519 2520 /* Allocate memory for storing MAC addr */ 2521 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 2522 (ETHER_ADDR_LEN * 2523 adapter->dev_info.num_mac_filters), 2524 RTE_CACHE_LINE_SIZE); 2525 2526 if (eth_dev->data->mac_addrs == NULL) { 2527 DP_ERR(edev, "Failed to allocate MAC address\n"); 2528 qed_ops->common->slowpath_stop(edev); 2529 qed_ops->common->remove(edev); 2530 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2531 (void *)eth_dev); 2532 return -ENOMEM; 2533 } 2534 2535 if (!is_vf) { 2536 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 2537 hw_info.hw_mac_addr, 2538 ð_dev->data->mac_addrs[0]); 2539 ether_addr_copy(ð_dev->data->mac_addrs[0], 2540 &adapter->primary_mac); 2541 } else { 2542 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 2543 &bulletin_change); 2544 if (bulletin_change) { 2545 is_mac_exist = 2546 ecore_vf_bulletin_get_forced_mac( 2547 ECORE_LEADING_HWFN(edev), 2548 vf_mac, 2549 &is_mac_forced); 2550 if (is_mac_exist && is_mac_forced) { 2551 DP_INFO(edev, "VF macaddr received from PF\n"); 2552 ether_addr_copy((struct ether_addr *)&vf_mac, 2553 ð_dev->data->mac_addrs[0]); 2554 ether_addr_copy(ð_dev->data->mac_addrs[0], 2555 &adapter->primary_mac); 2556 } else { 2557 DP_NOTICE(edev, false, 2558 "No VF macaddr assigned\n"); 2559 } 2560 } 2561 } 2562 2563 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 2564 2565 if (do_once) { 2566 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 2567 qede_print_adapter_info(adapter); 2568 #endif 2569 do_once = false; 2570 } 2571 2572 adapter->num_tx_queues = 0; 2573 adapter->num_rx_queues = 0; 2574 SLIST_INIT(&adapter->fdir_info.fdir_list_head); 2575 SLIST_INIT(&adapter->vlan_list_head); 2576 SLIST_INIT(&adapter->uc_list_head); 2577 adapter->mtu = ETHER_MTU; 2578 adapter->new_mtu = ETHER_MTU; 2579 if (!is_vf) 2580 if (qede_start_vport(adapter, adapter->mtu)) 2581 return -1; 2582 2583 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 2584 adapter->primary_mac.addr_bytes[0], 2585 adapter->primary_mac.addr_bytes[1], 2586 adapter->primary_mac.addr_bytes[2], 2587 adapter->primary_mac.addr_bytes[3], 2588 adapter->primary_mac.addr_bytes[4], 2589 adapter->primary_mac.addr_bytes[5]); 2590 2591 DP_INFO(edev, "Device initialized\n"); 2592 2593 return 0; 2594 } 2595 2596 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 2597 { 2598 return qede_common_dev_init(eth_dev, 1); 2599 } 2600 2601 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 2602 { 2603 return qede_common_dev_init(eth_dev, 0); 2604 } 2605 2606 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 2607 { 2608 /* only uninitialize in the primary process */ 2609 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2610 return 0; 2611 2612 /* safe to close dev here */ 2613 qede_dev_close(eth_dev); 2614 2615 eth_dev->dev_ops = NULL; 2616 eth_dev->rx_pkt_burst = NULL; 2617 eth_dev->tx_pkt_burst = NULL; 2618 2619 if (eth_dev->data->mac_addrs) 2620 rte_free(eth_dev->data->mac_addrs); 2621 2622 eth_dev->data->mac_addrs = NULL; 2623 2624 return 0; 2625 } 2626 2627 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2628 { 2629 return qede_dev_common_uninit(eth_dev); 2630 } 2631 2632 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2633 { 2634 return qede_dev_common_uninit(eth_dev); 2635 } 2636 2637 static const struct rte_pci_id pci_id_qedevf_map[] = { 2638 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2639 { 2640 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 2641 }, 2642 { 2643 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 2644 }, 2645 { 2646 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 2647 }, 2648 {.vendor_id = 0,} 2649 }; 2650 2651 static const struct rte_pci_id pci_id_qede_map[] = { 2652 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2653 { 2654 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 2655 }, 2656 { 2657 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 2658 }, 2659 { 2660 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 2661 }, 2662 { 2663 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 2664 }, 2665 { 2666 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 2667 }, 2668 { 2669 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 2670 }, 2671 { 2672 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 2673 }, 2674 { 2675 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 2676 }, 2677 { 2678 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 2679 }, 2680 { 2681 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 2682 }, 2683 {.vendor_id = 0,} 2684 }; 2685 2686 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2687 struct rte_pci_device *pci_dev) 2688 { 2689 return rte_eth_dev_pci_generic_probe(pci_dev, 2690 sizeof(struct qede_dev), qedevf_eth_dev_init); 2691 } 2692 2693 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2694 { 2695 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 2696 } 2697 2698 static struct rte_pci_driver rte_qedevf_pmd = { 2699 .id_table = pci_id_qedevf_map, 2700 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2701 .probe = qedevf_eth_dev_pci_probe, 2702 .remove = qedevf_eth_dev_pci_remove, 2703 }; 2704 2705 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2706 struct rte_pci_device *pci_dev) 2707 { 2708 return rte_eth_dev_pci_generic_probe(pci_dev, 2709 sizeof(struct qede_dev), qede_eth_dev_init); 2710 } 2711 2712 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2713 { 2714 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 2715 } 2716 2717 static struct rte_pci_driver rte_qede_pmd = { 2718 .id_table = pci_id_qede_map, 2719 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2720 .probe = qede_eth_dev_pci_probe, 2721 .remove = qede_eth_dev_pci_remove, 2722 }; 2723 2724 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 2725 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 2726 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 2727 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 2728 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 2729 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 2730