1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static int64_t timer_period = 1; 16 17 /* VXLAN tunnel classification mapping */ 18 const struct _qede_vxlan_tunn_types { 19 uint16_t rte_filter_type; 20 enum ecore_filter_ucast_type qede_type; 21 enum ecore_tunn_clss qede_tunn_clss; 22 const char *string; 23 } qede_tunn_types[] = { 24 { 25 ETH_TUNNEL_FILTER_OMAC, 26 ECORE_FILTER_MAC, 27 ECORE_TUNN_CLSS_MAC_VLAN, 28 "outer-mac" 29 }, 30 { 31 ETH_TUNNEL_FILTER_TENID, 32 ECORE_FILTER_VNI, 33 ECORE_TUNN_CLSS_MAC_VNI, 34 "vni" 35 }, 36 { 37 ETH_TUNNEL_FILTER_IMAC, 38 ECORE_FILTER_INNER_MAC, 39 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 40 "inner-mac" 41 }, 42 { 43 ETH_TUNNEL_FILTER_IVLAN, 44 ECORE_FILTER_INNER_VLAN, 45 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 46 "inner-vlan" 47 }, 48 { 49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 50 ECORE_FILTER_MAC_VNI_PAIR, 51 ECORE_TUNN_CLSS_MAC_VNI, 52 "outer-mac and vni" 53 }, 54 { 55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 56 ECORE_FILTER_UNUSED, 57 MAX_ECORE_TUNN_CLSS, 58 "outer-mac and inner-mac" 59 }, 60 { 61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 62 ECORE_FILTER_UNUSED, 63 MAX_ECORE_TUNN_CLSS, 64 "outer-mac and inner-vlan" 65 }, 66 { 67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 68 ECORE_FILTER_INNER_MAC_VNI_PAIR, 69 ECORE_TUNN_CLSS_INNER_MAC_VNI, 70 "vni and inner-mac", 71 }, 72 { 73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 74 ECORE_FILTER_UNUSED, 75 MAX_ECORE_TUNN_CLSS, 76 "vni and inner-vlan", 77 }, 78 { 79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 80 ECORE_FILTER_INNER_PAIR, 81 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 82 "inner-mac and inner-vlan", 83 }, 84 { 85 ETH_TUNNEL_FILTER_OIP, 86 ECORE_FILTER_UNUSED, 87 MAX_ECORE_TUNN_CLSS, 88 "outer-IP" 89 }, 90 { 91 ETH_TUNNEL_FILTER_IIP, 92 ECORE_FILTER_UNUSED, 93 MAX_ECORE_TUNN_CLSS, 94 "inner-IP" 95 }, 96 { 97 RTE_TUNNEL_FILTER_IMAC_IVLAN, 98 ECORE_FILTER_UNUSED, 99 MAX_ECORE_TUNN_CLSS, 100 "IMAC_IVLAN" 101 }, 102 { 103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 104 ECORE_FILTER_UNUSED, 105 MAX_ECORE_TUNN_CLSS, 106 "IMAC_IVLAN_TENID" 107 }, 108 { 109 RTE_TUNNEL_FILTER_IMAC_TENID, 110 ECORE_FILTER_UNUSED, 111 MAX_ECORE_TUNN_CLSS, 112 "IMAC_TENID" 113 }, 114 { 115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 116 ECORE_FILTER_UNUSED, 117 MAX_ECORE_TUNN_CLSS, 118 "OMAC_TENID_IMAC" 119 }, 120 }; 121 122 struct rte_qede_xstats_name_off { 123 char name[RTE_ETH_XSTATS_NAME_SIZE]; 124 uint64_t offset; 125 }; 126 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 128 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, 129 {"rx_multicast_bytes", 130 offsetof(struct ecore_eth_stats, rx_mcast_bytes)}, 131 {"rx_broadcast_bytes", 132 offsetof(struct ecore_eth_stats, rx_bcast_bytes)}, 133 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)}, 134 {"rx_multicast_packets", 135 offsetof(struct ecore_eth_stats, rx_mcast_pkts)}, 136 {"rx_broadcast_packets", 137 offsetof(struct ecore_eth_stats, rx_bcast_pkts)}, 138 139 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)}, 140 {"tx_multicast_bytes", 141 offsetof(struct ecore_eth_stats, tx_mcast_bytes)}, 142 {"tx_broadcast_bytes", 143 offsetof(struct ecore_eth_stats, tx_bcast_bytes)}, 144 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)}, 145 {"tx_multicast_packets", 146 offsetof(struct ecore_eth_stats, tx_mcast_pkts)}, 147 {"tx_broadcast_packets", 148 offsetof(struct ecore_eth_stats, tx_bcast_pkts)}, 149 150 {"rx_64_byte_packets", 151 offsetof(struct ecore_eth_stats, rx_64_byte_packets)}, 152 {"rx_65_to_127_byte_packets", 153 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)}, 154 {"rx_128_to_255_byte_packets", 155 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)}, 156 {"rx_256_to_511_byte_packets", 157 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)}, 158 {"rx_512_to_1023_byte_packets", 159 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)}, 160 {"rx_1024_to_1518_byte_packets", 161 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)}, 162 {"rx_1519_to_1522_byte_packets", 163 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)}, 164 {"rx_1519_to_2047_byte_packets", 165 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)}, 166 {"rx_2048_to_4095_byte_packets", 167 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)}, 168 {"rx_4096_to_9216_byte_packets", 169 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)}, 170 {"rx_9217_to_16383_byte_packets", 171 offsetof(struct ecore_eth_stats, 172 rx_9217_to_16383_byte_packets)}, 173 {"tx_64_byte_packets", 174 offsetof(struct ecore_eth_stats, tx_64_byte_packets)}, 175 {"tx_65_to_127_byte_packets", 176 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)}, 177 {"tx_128_to_255_byte_packets", 178 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)}, 179 {"tx_256_to_511_byte_packets", 180 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)}, 181 {"tx_512_to_1023_byte_packets", 182 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)}, 183 {"tx_1024_to_1518_byte_packets", 184 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)}, 185 {"trx_1519_to_1522_byte_packets", 186 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)}, 187 {"tx_2048_to_4095_byte_packets", 188 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)}, 189 {"tx_4096_to_9216_byte_packets", 190 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)}, 191 {"tx_9217_to_16383_byte_packets", 192 offsetof(struct ecore_eth_stats, 193 tx_9217_to_16383_byte_packets)}, 194 195 {"rx_mac_crtl_frames", 196 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)}, 197 {"tx_mac_control_frames", 198 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)}, 199 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)}, 200 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)}, 201 {"rx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats, rx_pfc_frames)}, 203 {"tx_priority_flow_control_frames", 204 offsetof(struct ecore_eth_stats, tx_pfc_frames)}, 205 206 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)}, 207 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)}, 208 {"rx_carrier_errors", 209 offsetof(struct ecore_eth_stats, rx_carrier_errors)}, 210 {"rx_oversize_packet_errors", 211 offsetof(struct ecore_eth_stats, rx_oversize_packets)}, 212 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)}, 213 {"rx_undersize_packet_errors", 214 offsetof(struct ecore_eth_stats, rx_undersize_packets)}, 215 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)}, 216 {"rx_host_buffer_not_available", 217 offsetof(struct ecore_eth_stats, no_buff_discards)}, 218 /* Number of packets discarded because they are bigger than MTU */ 219 {"rx_packet_too_big_discards", 220 offsetof(struct ecore_eth_stats, packet_too_big_discard)}, 221 {"rx_ttl_zero_discards", 222 offsetof(struct ecore_eth_stats, ttl0_discard)}, 223 {"rx_multi_function_tag_filter_discards", 224 offsetof(struct ecore_eth_stats, mftag_filter_discards)}, 225 {"rx_mac_filter_discards", 226 offsetof(struct ecore_eth_stats, mac_filter_discards)}, 227 {"rx_hw_buffer_truncates", 228 offsetof(struct ecore_eth_stats, brb_truncates)}, 229 {"rx_hw_buffer_discards", 230 offsetof(struct ecore_eth_stats, brb_discards)}, 231 {"tx_lpi_entry_count", 232 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)}, 233 {"tx_total_collisions", 234 offsetof(struct ecore_eth_stats, tx_total_collisions)}, 235 {"tx_error_drop_packets", 236 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)}, 237 238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)}, 239 {"rx_mac_unicast_packets", 240 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)}, 241 {"rx_mac_multicast_packets", 242 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)}, 243 {"rx_mac_broadcast_packets", 244 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)}, 245 {"rx_mac_frames_ok", 246 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)}, 247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)}, 248 {"tx_mac_unicast_packets", 249 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)}, 250 {"tx_mac_multicast_packets", 251 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)}, 252 {"tx_mac_broadcast_packets", 253 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)}, 254 255 {"lro_coalesced_packets", 256 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)}, 257 {"lro_coalesced_events", 258 offsetof(struct ecore_eth_stats, tpa_coalesced_events)}, 259 {"lro_aborts_num", 260 offsetof(struct ecore_eth_stats, tpa_aborts_num)}, 261 {"lro_not_coalesced_packets", 262 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)}, 263 {"lro_coalesced_bytes", 264 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)}, 265 }; 266 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 268 {"rx_q_segments", 269 offsetof(struct qede_rx_queue, rx_segs)}, 270 {"rx_q_hw_errors", 271 offsetof(struct qede_rx_queue, rx_hw_errors)}, 272 {"rx_q_allocation_errors", 273 offsetof(struct qede_rx_queue, rx_alloc_errors)} 274 }; 275 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 277 { 278 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 279 } 280 281 static void 282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param) 283 { 284 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 285 struct qede_dev *qdev = eth_dev->data->dev_private; 286 struct ecore_dev *edev = &qdev->edev; 287 288 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 289 if (rte_intr_enable(handle)) 290 DP_ERR(edev, "rte_intr_enable failed\n"); 291 } 292 293 static void 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 295 { 296 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 297 qdev->num_tc = qdev->dev_info.num_tc; 298 qdev->ops = qed_ops; 299 } 300 301 static void qede_print_adapter_info(struct qede_dev *qdev) 302 { 303 struct ecore_dev *edev = &qdev->edev; 304 struct qed_dev_info *info = &qdev->dev_info.common; 305 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 306 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 307 308 DP_INFO(edev, "*********************************\n"); 309 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 310 DP_INFO(edev, " Chip details : %s%d\n", 311 ECORE_IS_BB(edev) ? "BB" : "AH", 312 CHIP_REV_IS_A0(edev) ? 0 : 1); 313 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 314 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 315 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 316 ver_str, QEDE_PMD_VERSION); 317 DP_INFO(edev, " Driver version : %s\n", drv_ver); 318 DP_INFO(edev, " Firmware version : %s\n", ver_str); 319 320 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 321 "%d.%d.%d.%d", 322 (info->mfw_rev >> 24) & 0xff, 323 (info->mfw_rev >> 16) & 0xff, 324 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 325 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 326 DP_INFO(edev, " Firmware file : %s\n", fw_file); 327 DP_INFO(edev, "*********************************\n"); 328 } 329 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 331 { 332 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 333 ucast->is_rx_filter = true; 334 ucast->is_tx_filter = true; 335 /* ucast->assert_on_error = true; - For debug */ 336 } 337 338 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn, 339 uint8_t clss, bool mode, bool mask) 340 { 341 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info)); 342 p_tunn->vxlan.b_update_mode = mode; 343 p_tunn->vxlan.b_mode_enabled = mask; 344 p_tunn->b_update_rx_cls = true; 345 p_tunn->b_update_tx_cls = true; 346 p_tunn->vxlan.tun_cls = clss; 347 } 348 349 static int 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 351 bool add) 352 { 353 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 354 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 355 struct qede_ucast_entry *tmp = NULL; 356 struct qede_ucast_entry *u; 357 struct ether_addr *mac_addr; 358 359 mac_addr = (struct ether_addr *)ucast->mac; 360 if (add) { 361 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 362 if ((memcmp(mac_addr, &tmp->mac, 363 ETHER_ADDR_LEN) == 0) && 364 ucast->vlan == tmp->vlan) { 365 DP_ERR(edev, "Unicast MAC is already added" 366 " with vlan = %u, vni = %u\n", 367 ucast->vlan, ucast->vni); 368 return -EEXIST; 369 } 370 } 371 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 372 RTE_CACHE_LINE_SIZE); 373 if (!u) { 374 DP_ERR(edev, "Did not allocate memory for ucast\n"); 375 return -ENOMEM; 376 } 377 ether_addr_copy(mac_addr, &u->mac); 378 u->vlan = ucast->vlan; 379 u->vni = ucast->vni; 380 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 381 qdev->num_uc_addr++; 382 } else { 383 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 384 if ((memcmp(mac_addr, &tmp->mac, 385 ETHER_ADDR_LEN) == 0) && 386 ucast->vlan == tmp->vlan && 387 ucast->vni == tmp->vni) 388 break; 389 } 390 if (tmp == NULL) { 391 DP_INFO(edev, "Unicast MAC is not found\n"); 392 return -EINVAL; 393 } 394 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 395 qdev->num_uc_addr--; 396 } 397 398 return 0; 399 } 400 401 static int 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast, 403 bool add) 404 { 405 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 406 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 407 struct ether_addr *mac_addr; 408 struct qede_mcast_entry *tmp = NULL; 409 struct qede_mcast_entry *m; 410 411 mac_addr = (struct ether_addr *)mcast->mac; 412 if (add) { 413 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 414 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) { 415 DP_ERR(edev, 416 "Multicast MAC is already added\n"); 417 return -EEXIST; 418 } 419 } 420 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 421 RTE_CACHE_LINE_SIZE); 422 if (!m) { 423 DP_ERR(edev, 424 "Did not allocate memory for mcast\n"); 425 return -ENOMEM; 426 } 427 ether_addr_copy(mac_addr, &m->mac); 428 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 429 qdev->num_mc_addr++; 430 } else { 431 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 432 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) 433 break; 434 } 435 if (tmp == NULL) { 436 DP_INFO(edev, "Multicast mac is not found\n"); 437 return -EINVAL; 438 } 439 SLIST_REMOVE(&qdev->mc_list_head, tmp, 440 qede_mcast_entry, list); 441 qdev->num_mc_addr--; 442 } 443 444 return 0; 445 } 446 447 static enum _ecore_status_t 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 449 bool add) 450 { 451 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 452 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 453 enum _ecore_status_t rc; 454 struct ecore_filter_mcast mcast; 455 struct qede_mcast_entry *tmp; 456 uint16_t j = 0; 457 458 /* Multicast */ 459 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) { 460 if (add) { 461 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) { 462 DP_ERR(edev, 463 "Mcast filter table limit exceeded, " 464 "Please enable mcast promisc mode\n"); 465 return -ECORE_INVAL; 466 } 467 } 468 rc = qede_mcast_filter(eth_dev, ucast, add); 469 if (rc == 0) { 470 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr); 471 memset(&mcast, 0, sizeof(mcast)); 472 mcast.num_mc_addrs = qdev->num_mc_addr; 473 mcast.opcode = ECORE_FILTER_ADD; 474 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 475 ether_addr_copy(&tmp->mac, 476 (struct ether_addr *)&mcast.mac[j]); 477 j++; 478 } 479 rc = ecore_filter_mcast_cmd(edev, &mcast, 480 ECORE_SPQ_MODE_CB, NULL); 481 } 482 if (rc != ECORE_SUCCESS) { 483 DP_ERR(edev, "Failed to add multicast filter" 484 " rc = %d, op = %d\n", rc, add); 485 } 486 } else { /* Unicast */ 487 if (add) { 488 if (qdev->num_uc_addr >= 489 qdev->dev_info.num_mac_filters) { 490 DP_ERR(edev, 491 "Ucast filter table limit exceeded," 492 " Please enable promisc mode\n"); 493 return -ECORE_INVAL; 494 } 495 } 496 rc = qede_ucast_filter(eth_dev, ucast, add); 497 if (rc == 0) 498 rc = ecore_filter_ucast_cmd(edev, ucast, 499 ECORE_SPQ_MODE_CB, NULL); 500 if (rc != ECORE_SUCCESS) { 501 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 502 rc, add); 503 } 504 } 505 506 return rc; 507 } 508 509 static void 510 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 511 uint32_t index, __rte_unused uint32_t pool) 512 { 513 struct ecore_filter_ucast ucast; 514 515 qede_set_ucast_cmn_params(&ucast); 516 ucast.type = ECORE_FILTER_MAC; 517 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 518 (void)qede_mac_int_ops(eth_dev, &ucast, 1); 519 } 520 521 static void 522 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 523 { 524 struct qede_dev *qdev = eth_dev->data->dev_private; 525 struct ecore_dev *edev = &qdev->edev; 526 struct ether_addr mac_addr; 527 struct ecore_filter_ucast ucast; 528 int rc; 529 530 PMD_INIT_FUNC_TRACE(edev); 531 532 if (index >= qdev->dev_info.num_mac_filters) { 533 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 534 index, qdev->dev_info.num_mac_filters); 535 return; 536 } 537 538 qede_set_ucast_cmn_params(&ucast); 539 ucast.opcode = ECORE_FILTER_REMOVE; 540 ucast.type = ECORE_FILTER_MAC; 541 542 /* Use the index maintained by rte */ 543 ether_addr_copy(ð_dev->data->mac_addrs[index], 544 (struct ether_addr *)&ucast.mac); 545 546 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 547 } 548 549 static void 550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 551 { 552 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 553 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 554 struct ecore_filter_ucast ucast; 555 int rc; 556 557 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 558 mac_addr->addr_bytes)) { 559 DP_ERR(edev, "Setting MAC address is not allowed\n"); 560 ether_addr_copy(&qdev->primary_mac, 561 ð_dev->data->mac_addrs[0]); 562 return; 563 } 564 565 /* First remove the primary mac */ 566 qede_set_ucast_cmn_params(&ucast); 567 ucast.opcode = ECORE_FILTER_REMOVE; 568 ucast.type = ECORE_FILTER_MAC; 569 ether_addr_copy(&qdev->primary_mac, 570 (struct ether_addr *)&ucast.mac); 571 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 572 if (rc != 0) { 573 DP_ERR(edev, "Unable to remove current macaddr" 574 " Reverting to previous default mac\n"); 575 ether_addr_copy(&qdev->primary_mac, 576 ð_dev->data->mac_addrs[0]); 577 return; 578 } 579 580 /* Add new MAC */ 581 ucast.opcode = ECORE_FILTER_ADD; 582 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 583 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 584 if (rc != 0) 585 DP_ERR(edev, "Unable to add new default mac\n"); 586 else 587 ether_addr_copy(mac_addr, &qdev->primary_mac); 588 } 589 590 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action) 591 { 592 struct ecore_dev *edev = &qdev->edev; 593 struct qed_update_vport_params params = { 594 .vport_id = 0, 595 .accept_any_vlan = action, 596 .update_accept_any_vlan_flg = 1, 597 }; 598 int rc; 599 600 /* Proceed only if action actually needs to be performed */ 601 if (qdev->accept_any_vlan == action) 602 return; 603 604 rc = qdev->ops->vport_update(edev, ¶ms); 605 if (rc) { 606 DP_ERR(edev, "Failed to %s accept-any-vlan\n", 607 action ? "enable" : "disable"); 608 } else { 609 DP_INFO(edev, "%s accept-any-vlan\n", 610 action ? "enabled" : "disabled"); 611 qdev->accept_any_vlan = action; 612 } 613 } 614 615 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping) 616 { 617 struct qed_update_vport_params vport_update_params; 618 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 619 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 620 int rc; 621 622 memset(&vport_update_params, 0, sizeof(vport_update_params)); 623 vport_update_params.vport_id = 0; 624 vport_update_params.update_inner_vlan_removal_flg = 1; 625 vport_update_params.inner_vlan_removal_flg = set_stripping; 626 rc = qdev->ops->vport_update(edev, &vport_update_params); 627 if (rc) { 628 DP_ERR(edev, "Update V-PORT failed %d\n", rc); 629 return rc; 630 } 631 632 return 0; 633 } 634 635 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 636 { 637 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 638 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 639 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 640 641 if (mask & ETH_VLAN_STRIP_MASK) { 642 if (rxmode->hw_vlan_strip) 643 (void)qede_vlan_stripping(eth_dev, 1); 644 else 645 (void)qede_vlan_stripping(eth_dev, 0); 646 } 647 648 if (mask & ETH_VLAN_FILTER_MASK) { 649 /* VLAN filtering kicks in when a VLAN is added */ 650 if (rxmode->hw_vlan_filter) { 651 qede_vlan_filter_set(eth_dev, 0, 1); 652 } else { 653 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 654 DP_ERR(edev, 655 " Please remove existing VLAN filters" 656 " before disabling VLAN filtering\n"); 657 /* Signal app that VLAN filtering is still 658 * enabled 659 */ 660 rxmode->hw_vlan_filter = true; 661 } else { 662 qede_vlan_filter_set(eth_dev, 0, 0); 663 } 664 } 665 } 666 667 if (mask & ETH_VLAN_EXTEND_MASK) 668 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 669 " and classification is based on outer tag only\n"); 670 671 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 672 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 673 } 674 675 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 676 uint16_t vlan_id, int on) 677 { 678 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 679 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 680 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 681 struct qede_vlan_entry *tmp = NULL; 682 struct qede_vlan_entry *vlan; 683 struct ecore_filter_ucast ucast; 684 int rc; 685 686 if (on) { 687 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 688 DP_ERR(edev, "Reached max VLAN filter limit" 689 " enabling accept_any_vlan\n"); 690 qede_config_accept_any_vlan(qdev, true); 691 return 0; 692 } 693 694 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 695 if (tmp->vid == vlan_id) { 696 DP_ERR(edev, "VLAN %u already configured\n", 697 vlan_id); 698 return -EEXIST; 699 } 700 } 701 702 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 703 RTE_CACHE_LINE_SIZE); 704 705 if (!vlan) { 706 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 707 return -ENOMEM; 708 } 709 710 qede_set_ucast_cmn_params(&ucast); 711 ucast.opcode = ECORE_FILTER_ADD; 712 ucast.type = ECORE_FILTER_VLAN; 713 ucast.vlan = vlan_id; 714 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 715 NULL); 716 if (rc != 0) { 717 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 718 rc); 719 rte_free(vlan); 720 } else { 721 vlan->vid = vlan_id; 722 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 723 qdev->configured_vlans++; 724 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 725 vlan_id, qdev->configured_vlans); 726 } 727 } else { 728 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 729 if (tmp->vid == vlan_id) 730 break; 731 } 732 733 if (!tmp) { 734 if (qdev->configured_vlans == 0) { 735 DP_INFO(edev, 736 "No VLAN filters configured yet\n"); 737 return 0; 738 } 739 740 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 741 return -EINVAL; 742 } 743 744 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 745 746 qede_set_ucast_cmn_params(&ucast); 747 ucast.opcode = ECORE_FILTER_REMOVE; 748 ucast.type = ECORE_FILTER_VLAN; 749 ucast.vlan = vlan_id; 750 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 751 NULL); 752 if (rc != 0) { 753 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 754 vlan_id, rc); 755 } else { 756 qdev->configured_vlans--; 757 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 758 vlan_id, qdev->configured_vlans); 759 } 760 } 761 762 return rc; 763 } 764 765 static int qede_init_vport(struct qede_dev *qdev) 766 { 767 struct ecore_dev *edev = &qdev->edev; 768 struct qed_start_vport_params start = {0}; 769 int rc; 770 771 start.remove_inner_vlan = 1; 772 start.enable_lro = qdev->enable_lro; 773 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD; 774 start.vport_id = 0; 775 start.drop_ttl0 = false; 776 start.clear_stats = 1; 777 start.handle_ptp_pkts = 0; 778 779 rc = qdev->ops->vport_start(edev, &start); 780 if (rc) { 781 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 782 return rc; 783 } 784 785 DP_INFO(edev, 786 "Start vport ramrod passed, vport_id = %d, MTU = %u\n", 787 start.vport_id, ETHER_MTU); 788 789 return 0; 790 } 791 792 static void qede_prandom_bytes(uint32_t *buff) 793 { 794 uint8_t i; 795 796 srand((unsigned int)time(NULL)); 797 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 798 buff[i] = rand(); 799 } 800 801 static int qede_config_rss(struct rte_eth_dev *eth_dev) 802 { 803 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 804 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 805 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 806 struct rte_eth_rss_reta_entry64 reta_conf[2]; 807 struct rte_eth_rss_conf rss_conf; 808 uint32_t i, id, pos, q; 809 810 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 811 if (!rss_conf.rss_key) { 812 DP_INFO(edev, "Applying driver default key\n"); 813 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 814 qede_prandom_bytes(&def_rss_key[0]); 815 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 816 } 817 818 /* Configure RSS hash */ 819 if (qede_rss_hash_update(eth_dev, &rss_conf)) 820 return -EINVAL; 821 822 /* Configure default RETA */ 823 memset(reta_conf, 0, sizeof(reta_conf)); 824 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 825 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 826 827 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 828 id = i / RTE_RETA_GROUP_SIZE; 829 pos = i % RTE_RETA_GROUP_SIZE; 830 q = i % QEDE_RSS_COUNT(qdev); 831 reta_conf[id].reta[pos] = q; 832 } 833 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 834 ECORE_RSS_IND_TABLE_SIZE)) 835 return -EINVAL; 836 837 return 0; 838 } 839 840 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 841 { 842 struct qede_dev *qdev = eth_dev->data->dev_private; 843 struct ecore_dev *edev = &qdev->edev; 844 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 845 int rc, i, j; 846 847 PMD_INIT_FUNC_TRACE(edev); 848 849 /* Check requirements for 100G mode */ 850 if (edev->num_hwfns > 1) { 851 if (eth_dev->data->nb_rx_queues < 2 || 852 eth_dev->data->nb_tx_queues < 2) { 853 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 854 return -EINVAL; 855 } 856 857 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 858 (eth_dev->data->nb_tx_queues % 2 != 0)) { 859 DP_ERR(edev, 860 "100G mode needs even no. of RX/TX queues\n"); 861 return -EINVAL; 862 } 863 } 864 865 /* Sanity checks and throw warnings */ 866 if (rxmode->enable_scatter == 1) 867 eth_dev->data->scattered_rx = 1; 868 869 if (!rxmode->hw_strip_crc) 870 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 871 872 if (!rxmode->hw_ip_checksum) 873 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 874 "in hw\n"); 875 876 if (rxmode->enable_lro) { 877 qdev->enable_lro = true; 878 /* Enable scatter mode for LRO */ 879 if (!rxmode->enable_scatter) 880 eth_dev->data->scattered_rx = 1; 881 } 882 883 /* Check for the port restart case */ 884 if (qdev->state != QEDE_DEV_INIT) { 885 rc = qdev->ops->vport_stop(edev, 0); 886 if (rc != 0) 887 return rc; 888 qede_dealloc_fp_resc(eth_dev); 889 } 890 891 qdev->fp_num_tx = eth_dev->data->nb_tx_queues; 892 qdev->fp_num_rx = eth_dev->data->nb_rx_queues; 893 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx; 894 895 /* Fastpath status block should be initialized before sending 896 * VPORT-START in the case of VF. Anyway, do it for both VF/PF. 897 */ 898 rc = qede_alloc_fp_resc(qdev); 899 if (rc != 0) 900 return rc; 901 902 /* Issue VPORT-START with default config values to allow 903 * other port configurations early on. 904 */ 905 rc = qede_init_vport(qdev); 906 if (rc != 0) 907 return rc; 908 909 /* Do RSS configuration after vport-start */ 910 switch (rxmode->mq_mode) { 911 case ETH_MQ_RX_RSS: 912 rc = qede_config_rss(eth_dev); 913 if (rc != 0) { 914 qdev->ops->vport_stop(edev, 0); 915 qede_dealloc_fp_resc(eth_dev); 916 return -EINVAL; 917 } 918 break; 919 case ETH_MQ_RX_NONE: 920 DP_INFO(edev, "RSS is disabled\n"); 921 break; 922 default: 923 DP_ERR(edev, "Unsupported RSS mode\n"); 924 qdev->ops->vport_stop(edev, 0); 925 qede_dealloc_fp_resc(eth_dev); 926 return -EINVAL; 927 } 928 929 /* Flow director mode check */ 930 rc = qede_check_fdir_support(eth_dev); 931 if (rc) { 932 qdev->ops->vport_stop(edev, 0); 933 qede_dealloc_fp_resc(eth_dev); 934 return -EINVAL; 935 } 936 SLIST_INIT(&qdev->fdir_info.fdir_list_head); 937 938 SLIST_INIT(&qdev->vlan_list_head); 939 940 /* Add primary mac for PF */ 941 if (IS_PF(edev)) 942 qede_mac_addr_set(eth_dev, &qdev->primary_mac); 943 944 /* Enable VLAN offloads by default */ 945 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 946 ETH_VLAN_FILTER_MASK | 947 ETH_VLAN_EXTEND_MASK); 948 949 qdev->state = QEDE_DEV_CONFIG; 950 951 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n", 952 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev), 953 qdev->num_tc); 954 955 return 0; 956 } 957 958 /* Info about HW descriptor ring limitations */ 959 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 960 .nb_max = NUM_RX_BDS_MAX, 961 .nb_min = 128, 962 .nb_align = 128 /* lowest common multiple */ 963 }; 964 965 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 966 .nb_max = NUM_TX_BDS_MAX, 967 .nb_min = 256, 968 .nb_align = 256, 969 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 970 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 971 }; 972 973 static void 974 qede_dev_info_get(struct rte_eth_dev *eth_dev, 975 struct rte_eth_dev_info *dev_info) 976 { 977 struct qede_dev *qdev = eth_dev->data->dev_private; 978 struct ecore_dev *edev = &qdev->edev; 979 struct qed_link_output link; 980 uint32_t speed_cap = 0; 981 982 PMD_INIT_FUNC_TRACE(edev); 983 984 dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 985 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 986 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 987 dev_info->rx_desc_lim = qede_rx_desc_lim; 988 dev_info->tx_desc_lim = qede_tx_desc_lim; 989 990 if (IS_PF(edev)) 991 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 992 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 993 else 994 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 995 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 996 dev_info->max_tx_queues = dev_info->max_rx_queues; 997 998 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 999 dev_info->max_vfs = 0; 1000 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1001 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1002 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1003 1004 dev_info->default_txconf = (struct rte_eth_txconf) { 1005 .txq_flags = QEDE_TXQ_FLAGS, 1006 }; 1007 1008 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 1009 DEV_RX_OFFLOAD_IPV4_CKSUM | 1010 DEV_RX_OFFLOAD_UDP_CKSUM | 1011 DEV_RX_OFFLOAD_TCP_CKSUM | 1012 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1013 DEV_RX_OFFLOAD_TCP_LRO); 1014 1015 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1016 DEV_TX_OFFLOAD_IPV4_CKSUM | 1017 DEV_TX_OFFLOAD_UDP_CKSUM | 1018 DEV_TX_OFFLOAD_TCP_CKSUM | 1019 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1020 DEV_TX_OFFLOAD_TCP_TSO | 1021 DEV_TX_OFFLOAD_VXLAN_TNL_TSO); 1022 1023 memset(&link, 0, sizeof(struct qed_link_output)); 1024 qdev->ops->common->get_link(edev, &link); 1025 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1026 speed_cap |= ETH_LINK_SPEED_1G; 1027 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1028 speed_cap |= ETH_LINK_SPEED_10G; 1029 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1030 speed_cap |= ETH_LINK_SPEED_25G; 1031 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1032 speed_cap |= ETH_LINK_SPEED_40G; 1033 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1034 speed_cap |= ETH_LINK_SPEED_50G; 1035 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1036 speed_cap |= ETH_LINK_SPEED_100G; 1037 dev_info->speed_capa = speed_cap; 1038 } 1039 1040 /* return 0 means link status changed, -1 means not changed */ 1041 static int 1042 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1043 { 1044 struct qede_dev *qdev = eth_dev->data->dev_private; 1045 struct ecore_dev *edev = &qdev->edev; 1046 uint16_t link_duplex; 1047 struct qed_link_output link; 1048 struct rte_eth_link *curr = ð_dev->data->dev_link; 1049 1050 memset(&link, 0, sizeof(struct qed_link_output)); 1051 qdev->ops->common->get_link(edev, &link); 1052 1053 /* Link Speed */ 1054 curr->link_speed = link.speed; 1055 1056 /* Link Mode */ 1057 switch (link.duplex) { 1058 case QEDE_DUPLEX_HALF: 1059 link_duplex = ETH_LINK_HALF_DUPLEX; 1060 break; 1061 case QEDE_DUPLEX_FULL: 1062 link_duplex = ETH_LINK_FULL_DUPLEX; 1063 break; 1064 case QEDE_DUPLEX_UNKNOWN: 1065 default: 1066 link_duplex = -1; 1067 } 1068 curr->link_duplex = link_duplex; 1069 1070 /* Link Status */ 1071 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 1072 1073 /* AN */ 1074 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1075 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1076 1077 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1078 curr->link_speed, curr->link_duplex, 1079 curr->link_autoneg, curr->link_status); 1080 1081 /* return 0 means link status changed, -1 means not changed */ 1082 return ((curr->link_status == link.link_up) ? -1 : 0); 1083 } 1084 1085 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1086 { 1087 struct qede_dev *qdev = eth_dev->data->dev_private; 1088 struct ecore_dev *edev = &qdev->edev; 1089 1090 PMD_INIT_FUNC_TRACE(edev); 1091 1092 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1093 1094 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1095 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1096 1097 qed_configure_filter_rx_mode(eth_dev, type); 1098 } 1099 1100 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1101 { 1102 struct qede_dev *qdev = eth_dev->data->dev_private; 1103 struct ecore_dev *edev = &qdev->edev; 1104 1105 PMD_INIT_FUNC_TRACE(edev); 1106 1107 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1108 qed_configure_filter_rx_mode(eth_dev, 1109 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1110 else 1111 qed_configure_filter_rx_mode(eth_dev, 1112 QED_FILTER_RX_MODE_TYPE_REGULAR); 1113 } 1114 1115 static void qede_poll_sp_sb_cb(void *param) 1116 { 1117 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1118 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1119 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1120 int rc; 1121 1122 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1123 qede_interrupt_action(&edev->hwfns[1]); 1124 1125 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1126 qede_poll_sp_sb_cb, 1127 (void *)eth_dev); 1128 if (rc != 0) { 1129 DP_ERR(edev, "Unable to start periodic" 1130 " timer rc %d\n", rc); 1131 assert(false && "Unable to start periodic timer"); 1132 } 1133 } 1134 1135 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1136 { 1137 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1138 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1139 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1140 int rc; 1141 1142 PMD_INIT_FUNC_TRACE(edev); 1143 1144 qede_fdir_dealloc_resc(eth_dev); 1145 1146 /* dev_stop() shall cleanup fp resources in hw but without releasing 1147 * dma memories and sw structures so that dev_start() can be called 1148 * by the app without reconfiguration. However, in dev_close() we 1149 * can release all the resources and device can be brought up newly 1150 */ 1151 if (qdev->state != QEDE_DEV_STOP) 1152 qede_dev_stop(eth_dev); 1153 else 1154 DP_INFO(edev, "Device is already stopped\n"); 1155 1156 rc = qdev->ops->vport_stop(edev, 0); 1157 if (rc != 0) 1158 DP_ERR(edev, "Failed to stop VPORT\n"); 1159 1160 qede_dealloc_fp_resc(eth_dev); 1161 1162 qdev->ops->common->slowpath_stop(edev); 1163 1164 qdev->ops->common->remove(edev); 1165 1166 rte_intr_disable(&pci_dev->intr_handle); 1167 1168 rte_intr_callback_unregister(&pci_dev->intr_handle, 1169 qede_interrupt_handler, (void *)eth_dev); 1170 1171 if (edev->num_hwfns > 1) 1172 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1173 1174 qdev->state = QEDE_DEV_INIT; /* Go back to init state */ 1175 } 1176 1177 static void 1178 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1179 { 1180 struct qede_dev *qdev = eth_dev->data->dev_private; 1181 struct ecore_dev *edev = &qdev->edev; 1182 struct ecore_eth_stats stats; 1183 unsigned int i = 0, j = 0, qid; 1184 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1185 struct qede_tx_queue *txq; 1186 1187 qdev->ops->get_vport_stats(edev, &stats); 1188 1189 /* RX Stats */ 1190 eth_stats->ipackets = stats.rx_ucast_pkts + 1191 stats.rx_mcast_pkts + stats.rx_bcast_pkts; 1192 1193 eth_stats->ibytes = stats.rx_ucast_bytes + 1194 stats.rx_mcast_bytes + stats.rx_bcast_bytes; 1195 1196 eth_stats->ierrors = stats.rx_crc_errors + 1197 stats.rx_align_errors + 1198 stats.rx_carrier_errors + 1199 stats.rx_oversize_packets + 1200 stats.rx_jabbers + stats.rx_undersize_packets; 1201 1202 eth_stats->rx_nombuf = stats.no_buff_discards; 1203 1204 eth_stats->imissed = stats.mftag_filter_discards + 1205 stats.mac_filter_discards + 1206 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards; 1207 1208 /* TX stats */ 1209 eth_stats->opackets = stats.tx_ucast_pkts + 1210 stats.tx_mcast_pkts + stats.tx_bcast_pkts; 1211 1212 eth_stats->obytes = stats.tx_ucast_bytes + 1213 stats.tx_mcast_bytes + stats.tx_bcast_bytes; 1214 1215 eth_stats->oerrors = stats.tx_err_drop_pkts; 1216 1217 /* Queue stats */ 1218 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1219 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1220 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1221 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1222 if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) || 1223 (txq_stat_cntrs != QEDE_TSS_COUNT(qdev))) 1224 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1225 "Not all the queue stats will be displayed. Set" 1226 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1227 " appropriately and retry.\n"); 1228 1229 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 1230 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 1231 eth_stats->q_ipackets[i] = 1232 *(uint64_t *)( 1233 ((char *)(qdev->fp_array[(qid)].rxq)) + 1234 offsetof(struct qede_rx_queue, 1235 rcv_pkts)); 1236 eth_stats->q_errors[i] = 1237 *(uint64_t *)( 1238 ((char *)(qdev->fp_array[(qid)].rxq)) + 1239 offsetof(struct qede_rx_queue, 1240 rx_hw_errors)) + 1241 *(uint64_t *)( 1242 ((char *)(qdev->fp_array[(qid)].rxq)) + 1243 offsetof(struct qede_rx_queue, 1244 rx_alloc_errors)); 1245 i++; 1246 } 1247 if (i == rxq_stat_cntrs) 1248 break; 1249 } 1250 1251 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 1252 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) { 1253 txq = qdev->fp_array[(qid)].txqs[0]; 1254 eth_stats->q_opackets[j] = 1255 *((uint64_t *)(uintptr_t) 1256 (((uint64_t)(uintptr_t)(txq)) + 1257 offsetof(struct qede_tx_queue, 1258 xmit_pkts))); 1259 j++; 1260 } 1261 if (j == txq_stat_cntrs) 1262 break; 1263 } 1264 } 1265 1266 static unsigned 1267 qede_get_xstats_count(struct qede_dev *qdev) { 1268 return RTE_DIM(qede_xstats_strings) + 1269 (RTE_DIM(qede_rxq_xstats_strings) * 1270 RTE_MIN(QEDE_RSS_COUNT(qdev), 1271 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1272 } 1273 1274 static int 1275 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, 1276 struct rte_eth_xstat_name *xstats_names, unsigned limit) 1277 { 1278 struct qede_dev *qdev = dev->data->dev_private; 1279 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1280 unsigned int i, qid, stat_idx = 0; 1281 unsigned int rxq_stat_cntrs; 1282 1283 if (xstats_names != NULL) { 1284 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1285 snprintf(xstats_names[stat_idx].name, 1286 sizeof(xstats_names[stat_idx].name), 1287 "%s", 1288 qede_xstats_strings[i].name); 1289 stat_idx++; 1290 } 1291 1292 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1293 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1294 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1295 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1296 snprintf(xstats_names[stat_idx].name, 1297 sizeof(xstats_names[stat_idx].name), 1298 "%.4s%d%s", 1299 qede_rxq_xstats_strings[i].name, qid, 1300 qede_rxq_xstats_strings[i].name + 4); 1301 stat_idx++; 1302 } 1303 } 1304 } 1305 1306 return stat_cnt; 1307 } 1308 1309 static int 1310 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1311 unsigned int n) 1312 { 1313 struct qede_dev *qdev = dev->data->dev_private; 1314 struct ecore_dev *edev = &qdev->edev; 1315 struct ecore_eth_stats stats; 1316 const unsigned int num = qede_get_xstats_count(qdev); 1317 unsigned int i, qid, stat_idx = 0; 1318 unsigned int rxq_stat_cntrs; 1319 1320 if (n < num) 1321 return num; 1322 1323 qdev->ops->get_vport_stats(edev, &stats); 1324 1325 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1326 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1327 qede_xstats_strings[i].offset); 1328 xstats[stat_idx].id = stat_idx; 1329 stat_idx++; 1330 } 1331 1332 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1333 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1334 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1335 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 1336 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1337 xstats[stat_idx].value = *(uint64_t *)( 1338 ((char *)(qdev->fp_array[(qid)].rxq)) + 1339 qede_rxq_xstats_strings[i].offset); 1340 xstats[stat_idx].id = stat_idx; 1341 stat_idx++; 1342 } 1343 } 1344 } 1345 1346 return stat_idx; 1347 } 1348 1349 static void 1350 qede_reset_xstats(struct rte_eth_dev *dev) 1351 { 1352 struct qede_dev *qdev = dev->data->dev_private; 1353 struct ecore_dev *edev = &qdev->edev; 1354 1355 ecore_reset_vport_stats(edev); 1356 } 1357 1358 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1359 { 1360 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1361 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1362 struct qed_link_params link_params; 1363 int rc; 1364 1365 DP_INFO(edev, "setting link state %d\n", link_up); 1366 memset(&link_params, 0, sizeof(link_params)); 1367 link_params.link_up = link_up; 1368 rc = qdev->ops->common->set_link(edev, &link_params); 1369 if (rc != ECORE_SUCCESS) 1370 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1371 1372 return rc; 1373 } 1374 1375 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1376 { 1377 return qede_dev_set_link_state(eth_dev, true); 1378 } 1379 1380 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1381 { 1382 return qede_dev_set_link_state(eth_dev, false); 1383 } 1384 1385 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1386 { 1387 struct qede_dev *qdev = eth_dev->data->dev_private; 1388 struct ecore_dev *edev = &qdev->edev; 1389 1390 ecore_reset_vport_stats(edev); 1391 } 1392 1393 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1394 { 1395 enum qed_filter_rx_mode_type type = 1396 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1397 1398 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1399 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1400 1401 qed_configure_filter_rx_mode(eth_dev, type); 1402 } 1403 1404 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1405 { 1406 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1407 qed_configure_filter_rx_mode(eth_dev, 1408 QED_FILTER_RX_MODE_TYPE_PROMISC); 1409 else 1410 qed_configure_filter_rx_mode(eth_dev, 1411 QED_FILTER_RX_MODE_TYPE_REGULAR); 1412 } 1413 1414 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1415 struct rte_eth_fc_conf *fc_conf) 1416 { 1417 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1418 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1419 struct qed_link_output current_link; 1420 struct qed_link_params params; 1421 1422 memset(¤t_link, 0, sizeof(current_link)); 1423 qdev->ops->common->get_link(edev, ¤t_link); 1424 1425 memset(¶ms, 0, sizeof(params)); 1426 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1427 if (fc_conf->autoneg) { 1428 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1429 DP_ERR(edev, "Autoneg not supported\n"); 1430 return -EINVAL; 1431 } 1432 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1433 } 1434 1435 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1436 if (fc_conf->mode == RTE_FC_FULL) 1437 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1438 QED_LINK_PAUSE_RX_ENABLE); 1439 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1440 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1441 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1442 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1443 1444 params.link_up = true; 1445 (void)qdev->ops->common->set_link(edev, ¶ms); 1446 1447 return 0; 1448 } 1449 1450 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1451 struct rte_eth_fc_conf *fc_conf) 1452 { 1453 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1454 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1455 struct qed_link_output current_link; 1456 1457 memset(¤t_link, 0, sizeof(current_link)); 1458 qdev->ops->common->get_link(edev, ¤t_link); 1459 1460 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1461 fc_conf->autoneg = true; 1462 1463 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1464 QED_LINK_PAUSE_TX_ENABLE)) 1465 fc_conf->mode = RTE_FC_FULL; 1466 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1467 fc_conf->mode = RTE_FC_RX_PAUSE; 1468 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1469 fc_conf->mode = RTE_FC_TX_PAUSE; 1470 else 1471 fc_conf->mode = RTE_FC_NONE; 1472 1473 return 0; 1474 } 1475 1476 static const uint32_t * 1477 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1478 { 1479 static const uint32_t ptypes[] = { 1480 RTE_PTYPE_L3_IPV4, 1481 RTE_PTYPE_L3_IPV6, 1482 RTE_PTYPE_UNKNOWN 1483 }; 1484 1485 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1486 return ptypes; 1487 1488 return NULL; 1489 } 1490 1491 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1492 { 1493 *rss_caps = 0; 1494 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1495 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1496 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1497 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1498 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1499 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1500 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 1501 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 1502 } 1503 1504 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1505 struct rte_eth_rss_conf *rss_conf) 1506 { 1507 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1508 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1509 struct ecore_sp_vport_update_params vport_update_params; 1510 struct ecore_rss_params rss_params; 1511 struct ecore_hwfn *p_hwfn; 1512 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1513 uint64_t hf = rss_conf->rss_hf; 1514 uint8_t len = rss_conf->rss_key_len; 1515 uint8_t idx; 1516 uint8_t i; 1517 int rc; 1518 1519 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1520 memset(&rss_params, 0, sizeof(rss_params)); 1521 1522 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 1523 (unsigned long)hf, len, key); 1524 1525 if (hf != 0) { 1526 /* Enabling RSS */ 1527 DP_INFO(edev, "Enabling rss\n"); 1528 1529 /* RSS caps */ 1530 qede_init_rss_caps(&rss_params.rss_caps, hf); 1531 rss_params.update_rss_capabilities = 1; 1532 1533 /* RSS hash key */ 1534 if (key) { 1535 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 1536 DP_ERR(edev, "RSS key length exceeds limit\n"); 1537 return -EINVAL; 1538 } 1539 DP_INFO(edev, "Applying user supplied hash key\n"); 1540 rss_params.update_rss_key = 1; 1541 memcpy(&rss_params.rss_key, key, len); 1542 } 1543 rss_params.rss_enable = 1; 1544 } 1545 1546 rss_params.update_rss_config = 1; 1547 /* tbl_size has to be set with capabilities */ 1548 rss_params.rss_table_size_log = 7; 1549 vport_update_params.vport_id = 0; 1550 /* pass the L2 handles instead of qids */ 1551 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 1552 idx = qdev->rss_ind_table[i]; 1553 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 1554 } 1555 vport_update_params.rss_params = &rss_params; 1556 1557 for_each_hwfn(edev, i) { 1558 p_hwfn = &edev->hwfns[i]; 1559 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1560 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1561 ECORE_SPQ_MODE_EBLOCK, NULL); 1562 if (rc) { 1563 DP_ERR(edev, "vport-update for RSS failed\n"); 1564 return rc; 1565 } 1566 } 1567 qdev->rss_enable = rss_params.rss_enable; 1568 1569 /* Update local structure for hash query */ 1570 qdev->rss_conf.rss_hf = hf; 1571 qdev->rss_conf.rss_key_len = len; 1572 if (qdev->rss_enable) { 1573 if (qdev->rss_conf.rss_key == NULL) { 1574 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 1575 if (qdev->rss_conf.rss_key == NULL) { 1576 DP_ERR(edev, "No memory to store RSS key\n"); 1577 return -ENOMEM; 1578 } 1579 } 1580 if (key && len) { 1581 DP_INFO(edev, "Storing RSS key\n"); 1582 memcpy(qdev->rss_conf.rss_key, key, len); 1583 } 1584 } else if (!qdev->rss_enable && len == 0) { 1585 if (qdev->rss_conf.rss_key) { 1586 free(qdev->rss_conf.rss_key); 1587 qdev->rss_conf.rss_key = NULL; 1588 DP_INFO(edev, "Free RSS key\n"); 1589 } 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1596 struct rte_eth_rss_conf *rss_conf) 1597 { 1598 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1599 1600 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 1601 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 1602 1603 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 1604 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 1605 rss_conf->rss_key_len); 1606 return 0; 1607 } 1608 1609 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 1610 struct rte_eth_rss_reta_entry64 *reta_conf, 1611 uint16_t reta_size) 1612 { 1613 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1614 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1615 struct ecore_sp_vport_update_params vport_update_params; 1616 struct ecore_rss_params params; 1617 struct ecore_hwfn *p_hwfn; 1618 uint16_t i, idx, shift; 1619 uint8_t entry; 1620 int rc; 1621 1622 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1623 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 1624 reta_size); 1625 return -EINVAL; 1626 } 1627 1628 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1629 memset(¶ms, 0, sizeof(params)); 1630 1631 for (i = 0; i < reta_size; i++) { 1632 idx = i / RTE_RETA_GROUP_SIZE; 1633 shift = i % RTE_RETA_GROUP_SIZE; 1634 if (reta_conf[idx].mask & (1ULL << shift)) { 1635 entry = reta_conf[idx].reta[shift]; 1636 /* Pass rxq handles to ecore */ 1637 params.rss_ind_table[i] = 1638 qdev->fp_array[entry].rxq->handle; 1639 /* Update the local copy for RETA query command */ 1640 qdev->rss_ind_table[i] = entry; 1641 } 1642 } 1643 1644 /* Fix up RETA for CMT mode device */ 1645 if (edev->num_hwfns > 1) 1646 qdev->rss_enable = qed_update_rss_parm_cmt(edev, 1647 params.rss_ind_table[0]); 1648 params.update_rss_ind_table = 1; 1649 params.rss_table_size_log = 7; 1650 params.update_rss_config = 1; 1651 vport_update_params.vport_id = 0; 1652 /* Use the current value of rss_enable */ 1653 params.rss_enable = qdev->rss_enable; 1654 vport_update_params.rss_params = ¶ms; 1655 1656 for_each_hwfn(edev, i) { 1657 p_hwfn = &edev->hwfns[i]; 1658 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1659 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1660 ECORE_SPQ_MODE_EBLOCK, NULL); 1661 if (rc) { 1662 DP_ERR(edev, "vport-update for RSS failed\n"); 1663 return rc; 1664 } 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 1671 struct rte_eth_rss_reta_entry64 *reta_conf, 1672 uint16_t reta_size) 1673 { 1674 struct qede_dev *qdev = eth_dev->data->dev_private; 1675 struct ecore_dev *edev = &qdev->edev; 1676 uint16_t i, idx, shift; 1677 uint8_t entry; 1678 1679 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1680 DP_ERR(edev, "reta_size %d is not supported\n", 1681 reta_size); 1682 return -EINVAL; 1683 } 1684 1685 for (i = 0; i < reta_size; i++) { 1686 idx = i / RTE_RETA_GROUP_SIZE; 1687 shift = i % RTE_RETA_GROUP_SIZE; 1688 if (reta_conf[idx].mask & (1ULL << shift)) { 1689 entry = qdev->rss_ind_table[i]; 1690 reta_conf[idx].reta[shift] = entry; 1691 } 1692 } 1693 1694 return 0; 1695 } 1696 1697 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1698 { 1699 uint32_t frame_size; 1700 struct qede_dev *qdev = dev->data->dev_private; 1701 struct rte_eth_dev_info dev_info = {0}; 1702 1703 qede_dev_info_get(dev, &dev_info); 1704 1705 /* VLAN_TAG = 4 */ 1706 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4; 1707 1708 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 1709 return -EINVAL; 1710 1711 if (!dev->data->scattered_rx && 1712 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 1713 return -EINVAL; 1714 1715 if (frame_size > ETHER_MAX_LEN) 1716 dev->data->dev_conf.rxmode.jumbo_frame = 1; 1717 else 1718 dev->data->dev_conf.rxmode.jumbo_frame = 0; 1719 1720 /* update max frame size */ 1721 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1722 qdev->mtu = mtu; 1723 qede_dev_stop(dev); 1724 qede_dev_start(dev); 1725 1726 return 0; 1727 } 1728 1729 static int 1730 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev, 1731 struct rte_eth_udp_tunnel *tunnel_udp, 1732 bool add) 1733 { 1734 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1735 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1736 struct ecore_tunnel_info tunn; /* @DPDK */ 1737 struct ecore_hwfn *p_hwfn; 1738 int rc, i; 1739 1740 PMD_INIT_FUNC_TRACE(edev); 1741 1742 memset(&tunn, 0, sizeof(tunn)); 1743 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) { 1744 tunn.vxlan_port.b_update_port = true; 1745 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port : 1746 QEDE_VXLAN_DEF_PORT; 1747 for_each_hwfn(edev, i) { 1748 p_hwfn = &edev->hwfns[i]; 1749 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 1750 ECORE_SPQ_MODE_CB, NULL); 1751 if (rc != ECORE_SUCCESS) { 1752 DP_ERR(edev, "Unable to config UDP port %u\n", 1753 tunn.vxlan_port.port); 1754 return rc; 1755 } 1756 } 1757 } 1758 1759 return 0; 1760 } 1761 1762 int 1763 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 1764 struct rte_eth_udp_tunnel *tunnel_udp) 1765 { 1766 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false); 1767 } 1768 1769 int 1770 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 1771 struct rte_eth_udp_tunnel *tunnel_udp) 1772 { 1773 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true); 1774 } 1775 1776 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 1777 uint32_t *clss, char *str) 1778 { 1779 uint16_t j; 1780 *clss = MAX_ECORE_TUNN_CLSS; 1781 1782 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 1783 if (filter == qede_tunn_types[j].rte_filter_type) { 1784 *type = qede_tunn_types[j].qede_type; 1785 *clss = qede_tunn_types[j].qede_tunn_clss; 1786 strcpy(str, qede_tunn_types[j].string); 1787 return; 1788 } 1789 } 1790 } 1791 1792 static int 1793 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 1794 const struct rte_eth_tunnel_filter_conf *conf, 1795 uint32_t type) 1796 { 1797 /* Init commmon ucast params first */ 1798 qede_set_ucast_cmn_params(ucast); 1799 1800 /* Copy out the required fields based on classification type */ 1801 ucast->type = type; 1802 1803 switch (type) { 1804 case ECORE_FILTER_VNI: 1805 ucast->vni = conf->tenant_id; 1806 break; 1807 case ECORE_FILTER_INNER_VLAN: 1808 ucast->vlan = conf->inner_vlan; 1809 break; 1810 case ECORE_FILTER_MAC: 1811 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 1812 ETHER_ADDR_LEN); 1813 break; 1814 case ECORE_FILTER_INNER_MAC: 1815 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1816 ETHER_ADDR_LEN); 1817 break; 1818 case ECORE_FILTER_MAC_VNI_PAIR: 1819 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 1820 ETHER_ADDR_LEN); 1821 ucast->vni = conf->tenant_id; 1822 break; 1823 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 1824 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1825 ETHER_ADDR_LEN); 1826 ucast->vni = conf->tenant_id; 1827 break; 1828 case ECORE_FILTER_INNER_PAIR: 1829 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1830 ETHER_ADDR_LEN); 1831 ucast->vlan = conf->inner_vlan; 1832 break; 1833 default: 1834 return -EINVAL; 1835 } 1836 1837 return ECORE_SUCCESS; 1838 } 1839 1840 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, 1841 enum rte_filter_op filter_op, 1842 const struct rte_eth_tunnel_filter_conf *conf) 1843 { 1844 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1845 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1846 struct ecore_tunnel_info tunn; 1847 struct ecore_hwfn *p_hwfn; 1848 enum ecore_filter_ucast_type type; 1849 enum ecore_tunn_clss clss; 1850 struct ecore_filter_ucast ucast; 1851 char str[80]; 1852 uint16_t filter_type; 1853 int rc, i; 1854 1855 filter_type = conf->filter_type | qdev->vxlan_filter_type; 1856 /* First determine if the given filter classification is supported */ 1857 qede_get_ecore_tunn_params(filter_type, &type, &clss, str); 1858 if (clss == MAX_ECORE_TUNN_CLSS) { 1859 DP_ERR(edev, "Wrong filter type\n"); 1860 return -EINVAL; 1861 } 1862 /* Init tunnel ucast params */ 1863 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 1864 if (rc != ECORE_SUCCESS) { 1865 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n", 1866 conf->filter_type); 1867 return rc; 1868 } 1869 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 1870 str, filter_op, ucast.type); 1871 switch (filter_op) { 1872 case RTE_ETH_FILTER_ADD: 1873 ucast.opcode = ECORE_FILTER_ADD; 1874 1875 /* Skip MAC/VLAN if filter is based on VNI */ 1876 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 1877 rc = qede_mac_int_ops(eth_dev, &ucast, 1); 1878 if (rc == 0) { 1879 /* Enable accept anyvlan */ 1880 qede_config_accept_any_vlan(qdev, true); 1881 } 1882 } else { 1883 rc = qede_ucast_filter(eth_dev, &ucast, 1); 1884 if (rc == 0) 1885 rc = ecore_filter_ucast_cmd(edev, &ucast, 1886 ECORE_SPQ_MODE_CB, NULL); 1887 } 1888 1889 if (rc != ECORE_SUCCESS) 1890 return rc; 1891 1892 qdev->vxlan_filter_type = filter_type; 1893 1894 DP_INFO(edev, "Enabling VXLAN tunneling\n"); 1895 qede_set_cmn_tunn_param(&tunn, clss, true, true); 1896 for_each_hwfn(edev, i) { 1897 p_hwfn = &edev->hwfns[i]; 1898 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, 1899 &tunn, ECORE_SPQ_MODE_CB, NULL); 1900 if (rc != ECORE_SUCCESS) { 1901 DP_ERR(edev, "Failed to update tunn_clss %u\n", 1902 tunn.vxlan.tun_cls); 1903 } 1904 } 1905 qdev->num_tunn_filters++; /* Filter added successfully */ 1906 break; 1907 case RTE_ETH_FILTER_DELETE: 1908 ucast.opcode = ECORE_FILTER_REMOVE; 1909 1910 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 1911 rc = qede_mac_int_ops(eth_dev, &ucast, 0); 1912 } else { 1913 rc = qede_ucast_filter(eth_dev, &ucast, 0); 1914 if (rc == 0) 1915 rc = ecore_filter_ucast_cmd(edev, &ucast, 1916 ECORE_SPQ_MODE_CB, NULL); 1917 } 1918 if (rc != ECORE_SUCCESS) 1919 return rc; 1920 1921 qdev->vxlan_filter_type = filter_type; 1922 qdev->num_tunn_filters--; 1923 1924 /* Disable VXLAN if VXLAN filters become 0 */ 1925 if (qdev->num_tunn_filters == 0) { 1926 DP_INFO(edev, "Disabling VXLAN tunneling\n"); 1927 1928 /* Use 0 as tunnel mode */ 1929 qede_set_cmn_tunn_param(&tunn, clss, false, true); 1930 for_each_hwfn(edev, i) { 1931 p_hwfn = &edev->hwfns[i]; 1932 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 1933 ECORE_SPQ_MODE_CB, NULL); 1934 if (rc != ECORE_SUCCESS) { 1935 DP_ERR(edev, 1936 "Failed to update tunn_clss %u\n", 1937 tunn.vxlan.tun_cls); 1938 break; 1939 } 1940 } 1941 } 1942 break; 1943 default: 1944 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 1945 return -EINVAL; 1946 } 1947 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters); 1948 1949 return 0; 1950 } 1951 1952 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 1953 enum rte_filter_type filter_type, 1954 enum rte_filter_op filter_op, 1955 void *arg) 1956 { 1957 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1958 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1959 struct rte_eth_tunnel_filter_conf *filter_conf = 1960 (struct rte_eth_tunnel_filter_conf *)arg; 1961 1962 switch (filter_type) { 1963 case RTE_ETH_FILTER_TUNNEL: 1964 switch (filter_conf->tunnel_type) { 1965 case RTE_TUNNEL_TYPE_VXLAN: 1966 DP_INFO(edev, 1967 "Packet steering to the specified Rx queue" 1968 " is not supported with VXLAN tunneling"); 1969 return(qede_vxlan_tunn_config(eth_dev, filter_op, 1970 filter_conf)); 1971 /* Place holders for future tunneling support */ 1972 case RTE_TUNNEL_TYPE_GENEVE: 1973 case RTE_TUNNEL_TYPE_TEREDO: 1974 case RTE_TUNNEL_TYPE_NVGRE: 1975 case RTE_TUNNEL_TYPE_IP_IN_GRE: 1976 case RTE_L2_TUNNEL_TYPE_E_TAG: 1977 DP_ERR(edev, "Unsupported tunnel type %d\n", 1978 filter_conf->tunnel_type); 1979 return -EINVAL; 1980 case RTE_TUNNEL_TYPE_NONE: 1981 default: 1982 return 0; 1983 } 1984 break; 1985 case RTE_ETH_FILTER_FDIR: 1986 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 1987 case RTE_ETH_FILTER_NTUPLE: 1988 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 1989 case RTE_ETH_FILTER_MACVLAN: 1990 case RTE_ETH_FILTER_ETHERTYPE: 1991 case RTE_ETH_FILTER_FLEXIBLE: 1992 case RTE_ETH_FILTER_SYN: 1993 case RTE_ETH_FILTER_HASH: 1994 case RTE_ETH_FILTER_L2_TUNNEL: 1995 case RTE_ETH_FILTER_MAX: 1996 default: 1997 DP_ERR(edev, "Unsupported filter type %d\n", 1998 filter_type); 1999 return -EINVAL; 2000 } 2001 2002 return 0; 2003 } 2004 2005 static const struct eth_dev_ops qede_eth_dev_ops = { 2006 .dev_configure = qede_dev_configure, 2007 .dev_infos_get = qede_dev_info_get, 2008 .rx_queue_setup = qede_rx_queue_setup, 2009 .rx_queue_release = qede_rx_queue_release, 2010 .tx_queue_setup = qede_tx_queue_setup, 2011 .tx_queue_release = qede_tx_queue_release, 2012 .dev_start = qede_dev_start, 2013 .dev_set_link_up = qede_dev_set_link_up, 2014 .dev_set_link_down = qede_dev_set_link_down, 2015 .link_update = qede_link_update, 2016 .promiscuous_enable = qede_promiscuous_enable, 2017 .promiscuous_disable = qede_promiscuous_disable, 2018 .allmulticast_enable = qede_allmulticast_enable, 2019 .allmulticast_disable = qede_allmulticast_disable, 2020 .dev_stop = qede_dev_stop, 2021 .dev_close = qede_dev_close, 2022 .stats_get = qede_get_stats, 2023 .stats_reset = qede_reset_stats, 2024 .xstats_get = qede_get_xstats, 2025 .xstats_reset = qede_reset_xstats, 2026 .xstats_get_names = qede_get_xstats_names, 2027 .mac_addr_add = qede_mac_addr_add, 2028 .mac_addr_remove = qede_mac_addr_remove, 2029 .mac_addr_set = qede_mac_addr_set, 2030 .vlan_offload_set = qede_vlan_offload_set, 2031 .vlan_filter_set = qede_vlan_filter_set, 2032 .flow_ctrl_set = qede_flow_ctrl_set, 2033 .flow_ctrl_get = qede_flow_ctrl_get, 2034 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2035 .rss_hash_update = qede_rss_hash_update, 2036 .rss_hash_conf_get = qede_rss_hash_conf_get, 2037 .reta_update = qede_rss_reta_update, 2038 .reta_query = qede_rss_reta_query, 2039 .mtu_set = qede_set_mtu, 2040 .filter_ctrl = qede_dev_filter_ctrl, 2041 .udp_tunnel_port_add = qede_udp_dst_port_add, 2042 .udp_tunnel_port_del = qede_udp_dst_port_del, 2043 }; 2044 2045 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2046 .dev_configure = qede_dev_configure, 2047 .dev_infos_get = qede_dev_info_get, 2048 .rx_queue_setup = qede_rx_queue_setup, 2049 .rx_queue_release = qede_rx_queue_release, 2050 .tx_queue_setup = qede_tx_queue_setup, 2051 .tx_queue_release = qede_tx_queue_release, 2052 .dev_start = qede_dev_start, 2053 .dev_set_link_up = qede_dev_set_link_up, 2054 .dev_set_link_down = qede_dev_set_link_down, 2055 .link_update = qede_link_update, 2056 .promiscuous_enable = qede_promiscuous_enable, 2057 .promiscuous_disable = qede_promiscuous_disable, 2058 .allmulticast_enable = qede_allmulticast_enable, 2059 .allmulticast_disable = qede_allmulticast_disable, 2060 .dev_stop = qede_dev_stop, 2061 .dev_close = qede_dev_close, 2062 .stats_get = qede_get_stats, 2063 .stats_reset = qede_reset_stats, 2064 .xstats_get = qede_get_xstats, 2065 .xstats_reset = qede_reset_xstats, 2066 .xstats_get_names = qede_get_xstats_names, 2067 .vlan_offload_set = qede_vlan_offload_set, 2068 .vlan_filter_set = qede_vlan_filter_set, 2069 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2070 .rss_hash_update = qede_rss_hash_update, 2071 .rss_hash_conf_get = qede_rss_hash_conf_get, 2072 .reta_update = qede_rss_reta_update, 2073 .reta_query = qede_rss_reta_query, 2074 .mtu_set = qede_set_mtu, 2075 }; 2076 2077 static void qede_update_pf_params(struct ecore_dev *edev) 2078 { 2079 struct ecore_pf_params pf_params; 2080 2081 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2082 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2083 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 2084 qed_ops->common->update_pf_params(edev, &pf_params); 2085 } 2086 2087 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2088 { 2089 struct rte_pci_device *pci_dev; 2090 struct rte_pci_addr pci_addr; 2091 struct qede_dev *adapter; 2092 struct ecore_dev *edev; 2093 struct qed_dev_eth_info dev_info; 2094 struct qed_slowpath_params params; 2095 static bool do_once = true; 2096 uint8_t bulletin_change; 2097 uint8_t vf_mac[ETHER_ADDR_LEN]; 2098 uint8_t is_mac_forced; 2099 bool is_mac_exist; 2100 /* Fix up ecore debug level */ 2101 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2102 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2103 uint32_t max_mac_addrs; 2104 int rc; 2105 2106 /* Extract key data structures */ 2107 adapter = eth_dev->data->dev_private; 2108 edev = &adapter->edev; 2109 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2110 pci_addr = pci_dev->addr; 2111 2112 PMD_INIT_FUNC_TRACE(edev); 2113 2114 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2115 pci_addr.bus, pci_addr.devid, pci_addr.function, 2116 eth_dev->data->port_id); 2117 2118 eth_dev->rx_pkt_burst = qede_recv_pkts; 2119 eth_dev->tx_pkt_burst = qede_xmit_pkts; 2120 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 2121 2122 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2123 DP_NOTICE(edev, false, 2124 "Skipping device init from secondary process\n"); 2125 return 0; 2126 } 2127 2128 rte_eth_copy_pci_info(eth_dev, pci_dev); 2129 2130 /* @DPDK */ 2131 edev->vendor_id = pci_dev->id.vendor_id; 2132 edev->device_id = pci_dev->id.device_id; 2133 2134 qed_ops = qed_get_eth_ops(); 2135 if (!qed_ops) { 2136 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2137 return -EINVAL; 2138 } 2139 2140 DP_INFO(edev, "Starting qede probe\n"); 2141 2142 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH, 2143 dp_module, dp_level, is_vf); 2144 2145 if (rc != 0) { 2146 DP_ERR(edev, "qede probe failed rc %d\n", rc); 2147 return -ENODEV; 2148 } 2149 2150 qede_update_pf_params(edev); 2151 2152 rte_intr_callback_register(&pci_dev->intr_handle, 2153 qede_interrupt_handler, (void *)eth_dev); 2154 2155 if (rte_intr_enable(&pci_dev->intr_handle)) { 2156 DP_ERR(edev, "rte_intr_enable() failed\n"); 2157 return -ENODEV; 2158 } 2159 2160 /* Start the Slowpath-process */ 2161 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 2162 params.int_mode = ECORE_INT_MODE_MSIX; 2163 params.drv_major = QEDE_PMD_VERSION_MAJOR; 2164 params.drv_minor = QEDE_PMD_VERSION_MINOR; 2165 params.drv_rev = QEDE_PMD_VERSION_REVISION; 2166 params.drv_eng = QEDE_PMD_VERSION_PATCH; 2167 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 2168 QEDE_PMD_DRV_VER_STR_SIZE); 2169 2170 /* For CMT mode device do periodic polling for slowpath events. 2171 * This is required since uio device uses only one MSI-x 2172 * interrupt vector but we need one for each engine. 2173 */ 2174 if (edev->num_hwfns > 1 && IS_PF(edev)) { 2175 rc = rte_eal_alarm_set(timer_period * US_PER_S, 2176 qede_poll_sp_sb_cb, 2177 (void *)eth_dev); 2178 if (rc != 0) { 2179 DP_ERR(edev, "Unable to start periodic" 2180 " timer rc %d\n", rc); 2181 return -EINVAL; 2182 } 2183 } 2184 2185 rc = qed_ops->common->slowpath_start(edev, ¶ms); 2186 if (rc) { 2187 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 2188 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2189 (void *)eth_dev); 2190 return -ENODEV; 2191 } 2192 2193 rc = qed_ops->fill_dev_info(edev, &dev_info); 2194 if (rc) { 2195 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 2196 qed_ops->common->slowpath_stop(edev); 2197 qed_ops->common->remove(edev); 2198 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2199 (void *)eth_dev); 2200 return -ENODEV; 2201 } 2202 2203 qede_alloc_etherdev(adapter, &dev_info); 2204 2205 adapter->ops->common->set_name(edev, edev->name); 2206 2207 if (!is_vf) 2208 adapter->dev_info.num_mac_filters = 2209 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 2210 ECORE_MAC); 2211 else 2212 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 2213 (uint32_t *)&adapter->dev_info.num_mac_filters); 2214 2215 /* Allocate memory for storing MAC addr */ 2216 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 2217 (ETHER_ADDR_LEN * 2218 adapter->dev_info.num_mac_filters), 2219 RTE_CACHE_LINE_SIZE); 2220 2221 if (eth_dev->data->mac_addrs == NULL) { 2222 DP_ERR(edev, "Failed to allocate MAC address\n"); 2223 qed_ops->common->slowpath_stop(edev); 2224 qed_ops->common->remove(edev); 2225 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2226 (void *)eth_dev); 2227 return -ENOMEM; 2228 } 2229 2230 if (!is_vf) { 2231 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 2232 hw_info.hw_mac_addr, 2233 ð_dev->data->mac_addrs[0]); 2234 ether_addr_copy(ð_dev->data->mac_addrs[0], 2235 &adapter->primary_mac); 2236 } else { 2237 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 2238 &bulletin_change); 2239 if (bulletin_change) { 2240 is_mac_exist = 2241 ecore_vf_bulletin_get_forced_mac( 2242 ECORE_LEADING_HWFN(edev), 2243 vf_mac, 2244 &is_mac_forced); 2245 if (is_mac_exist && is_mac_forced) { 2246 DP_INFO(edev, "VF macaddr received from PF\n"); 2247 ether_addr_copy((struct ether_addr *)&vf_mac, 2248 ð_dev->data->mac_addrs[0]); 2249 ether_addr_copy(ð_dev->data->mac_addrs[0], 2250 &adapter->primary_mac); 2251 } else { 2252 DP_NOTICE(edev, false, 2253 "No VF macaddr assigned\n"); 2254 } 2255 } 2256 } 2257 2258 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 2259 2260 if (do_once) { 2261 qede_print_adapter_info(adapter); 2262 do_once = false; 2263 } 2264 2265 adapter->state = QEDE_DEV_INIT; 2266 2267 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 2268 adapter->primary_mac.addr_bytes[0], 2269 adapter->primary_mac.addr_bytes[1], 2270 adapter->primary_mac.addr_bytes[2], 2271 adapter->primary_mac.addr_bytes[3], 2272 adapter->primary_mac.addr_bytes[4], 2273 adapter->primary_mac.addr_bytes[5]); 2274 2275 return rc; 2276 } 2277 2278 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 2279 { 2280 return qede_common_dev_init(eth_dev, 1); 2281 } 2282 2283 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 2284 { 2285 return qede_common_dev_init(eth_dev, 0); 2286 } 2287 2288 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 2289 { 2290 /* only uninitialize in the primary process */ 2291 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2292 return 0; 2293 2294 /* safe to close dev here */ 2295 qede_dev_close(eth_dev); 2296 2297 eth_dev->dev_ops = NULL; 2298 eth_dev->rx_pkt_burst = NULL; 2299 eth_dev->tx_pkt_burst = NULL; 2300 2301 if (eth_dev->data->mac_addrs) 2302 rte_free(eth_dev->data->mac_addrs); 2303 2304 eth_dev->data->mac_addrs = NULL; 2305 2306 return 0; 2307 } 2308 2309 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2310 { 2311 return qede_dev_common_uninit(eth_dev); 2312 } 2313 2314 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2315 { 2316 return qede_dev_common_uninit(eth_dev); 2317 } 2318 2319 static const struct rte_pci_id pci_id_qedevf_map[] = { 2320 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2321 { 2322 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 2323 }, 2324 { 2325 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 2326 }, 2327 { 2328 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 2329 }, 2330 {.vendor_id = 0,} 2331 }; 2332 2333 static const struct rte_pci_id pci_id_qede_map[] = { 2334 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2335 { 2336 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 2337 }, 2338 { 2339 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 2340 }, 2341 { 2342 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 2343 }, 2344 { 2345 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 2346 }, 2347 { 2348 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 2349 }, 2350 { 2351 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 2352 }, 2353 { 2354 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 2355 }, 2356 { 2357 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 2358 }, 2359 { 2360 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 2361 }, 2362 { 2363 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 2364 }, 2365 {.vendor_id = 0,} 2366 }; 2367 2368 static struct eth_driver rte_qedevf_pmd = { 2369 .pci_drv = { 2370 .id_table = pci_id_qedevf_map, 2371 .drv_flags = 2372 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2373 .probe = rte_eth_dev_pci_probe, 2374 .remove = rte_eth_dev_pci_remove, 2375 }, 2376 .eth_dev_init = qedevf_eth_dev_init, 2377 .eth_dev_uninit = qedevf_eth_dev_uninit, 2378 .dev_private_size = sizeof(struct qede_dev), 2379 }; 2380 2381 static struct eth_driver rte_qede_pmd = { 2382 .pci_drv = { 2383 .id_table = pci_id_qede_map, 2384 .drv_flags = 2385 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2386 .probe = rte_eth_dev_pci_probe, 2387 .remove = rte_eth_dev_pci_remove, 2388 }, 2389 .eth_dev_init = qede_eth_dev_init, 2390 .eth_dev_uninit = qede_eth_dev_uninit, 2391 .dev_private_size = sizeof(struct qede_dev), 2392 }; 2393 2394 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv); 2395 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 2396 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio"); 2397 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv); 2398 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 2399 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio"); 2400