1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static int64_t timer_period = 1; 16 17 /* VXLAN tunnel classification mapping */ 18 const struct _qede_vxlan_tunn_types { 19 uint16_t rte_filter_type; 20 enum ecore_filter_ucast_type qede_type; 21 enum ecore_tunn_clss qede_tunn_clss; 22 const char *string; 23 } qede_tunn_types[] = { 24 { 25 ETH_TUNNEL_FILTER_OMAC, 26 ECORE_FILTER_MAC, 27 ECORE_TUNN_CLSS_MAC_VLAN, 28 "outer-mac" 29 }, 30 { 31 ETH_TUNNEL_FILTER_TENID, 32 ECORE_FILTER_VNI, 33 ECORE_TUNN_CLSS_MAC_VNI, 34 "vni" 35 }, 36 { 37 ETH_TUNNEL_FILTER_IMAC, 38 ECORE_FILTER_INNER_MAC, 39 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 40 "inner-mac" 41 }, 42 { 43 ETH_TUNNEL_FILTER_IVLAN, 44 ECORE_FILTER_INNER_VLAN, 45 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 46 "inner-vlan" 47 }, 48 { 49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 50 ECORE_FILTER_MAC_VNI_PAIR, 51 ECORE_TUNN_CLSS_MAC_VNI, 52 "outer-mac and vni" 53 }, 54 { 55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 56 ECORE_FILTER_UNUSED, 57 MAX_ECORE_TUNN_CLSS, 58 "outer-mac and inner-mac" 59 }, 60 { 61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 62 ECORE_FILTER_UNUSED, 63 MAX_ECORE_TUNN_CLSS, 64 "outer-mac and inner-vlan" 65 }, 66 { 67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 68 ECORE_FILTER_INNER_MAC_VNI_PAIR, 69 ECORE_TUNN_CLSS_INNER_MAC_VNI, 70 "vni and inner-mac", 71 }, 72 { 73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 74 ECORE_FILTER_UNUSED, 75 MAX_ECORE_TUNN_CLSS, 76 "vni and inner-vlan", 77 }, 78 { 79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 80 ECORE_FILTER_INNER_PAIR, 81 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 82 "inner-mac and inner-vlan", 83 }, 84 { 85 ETH_TUNNEL_FILTER_OIP, 86 ECORE_FILTER_UNUSED, 87 MAX_ECORE_TUNN_CLSS, 88 "outer-IP" 89 }, 90 { 91 ETH_TUNNEL_FILTER_IIP, 92 ECORE_FILTER_UNUSED, 93 MAX_ECORE_TUNN_CLSS, 94 "inner-IP" 95 }, 96 { 97 RTE_TUNNEL_FILTER_IMAC_IVLAN, 98 ECORE_FILTER_UNUSED, 99 MAX_ECORE_TUNN_CLSS, 100 "IMAC_IVLAN" 101 }, 102 { 103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 104 ECORE_FILTER_UNUSED, 105 MAX_ECORE_TUNN_CLSS, 106 "IMAC_IVLAN_TENID" 107 }, 108 { 109 RTE_TUNNEL_FILTER_IMAC_TENID, 110 ECORE_FILTER_UNUSED, 111 MAX_ECORE_TUNN_CLSS, 112 "IMAC_TENID" 113 }, 114 { 115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 116 ECORE_FILTER_UNUSED, 117 MAX_ECORE_TUNN_CLSS, 118 "OMAC_TENID_IMAC" 119 }, 120 }; 121 122 struct rte_qede_xstats_name_off { 123 char name[RTE_ETH_XSTATS_NAME_SIZE]; 124 uint64_t offset; 125 }; 126 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 128 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)}, 129 {"rx_multicast_bytes", 130 offsetof(struct ecore_eth_stats, rx_mcast_bytes)}, 131 {"rx_broadcast_bytes", 132 offsetof(struct ecore_eth_stats, rx_bcast_bytes)}, 133 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)}, 134 {"rx_multicast_packets", 135 offsetof(struct ecore_eth_stats, rx_mcast_pkts)}, 136 {"rx_broadcast_packets", 137 offsetof(struct ecore_eth_stats, rx_bcast_pkts)}, 138 139 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)}, 140 {"tx_multicast_bytes", 141 offsetof(struct ecore_eth_stats, tx_mcast_bytes)}, 142 {"tx_broadcast_bytes", 143 offsetof(struct ecore_eth_stats, tx_bcast_bytes)}, 144 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)}, 145 {"tx_multicast_packets", 146 offsetof(struct ecore_eth_stats, tx_mcast_pkts)}, 147 {"tx_broadcast_packets", 148 offsetof(struct ecore_eth_stats, tx_bcast_pkts)}, 149 150 {"rx_64_byte_packets", 151 offsetof(struct ecore_eth_stats, rx_64_byte_packets)}, 152 {"rx_65_to_127_byte_packets", 153 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)}, 154 {"rx_128_to_255_byte_packets", 155 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)}, 156 {"rx_256_to_511_byte_packets", 157 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)}, 158 {"rx_512_to_1023_byte_packets", 159 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)}, 160 {"rx_1024_to_1518_byte_packets", 161 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)}, 162 {"rx_1519_to_1522_byte_packets", 163 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)}, 164 {"rx_1519_to_2047_byte_packets", 165 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)}, 166 {"rx_2048_to_4095_byte_packets", 167 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)}, 168 {"rx_4096_to_9216_byte_packets", 169 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)}, 170 {"rx_9217_to_16383_byte_packets", 171 offsetof(struct ecore_eth_stats, 172 rx_9217_to_16383_byte_packets)}, 173 {"tx_64_byte_packets", 174 offsetof(struct ecore_eth_stats, tx_64_byte_packets)}, 175 {"tx_65_to_127_byte_packets", 176 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)}, 177 {"tx_128_to_255_byte_packets", 178 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)}, 179 {"tx_256_to_511_byte_packets", 180 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)}, 181 {"tx_512_to_1023_byte_packets", 182 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)}, 183 {"tx_1024_to_1518_byte_packets", 184 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)}, 185 {"trx_1519_to_1522_byte_packets", 186 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)}, 187 {"tx_2048_to_4095_byte_packets", 188 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)}, 189 {"tx_4096_to_9216_byte_packets", 190 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)}, 191 {"tx_9217_to_16383_byte_packets", 192 offsetof(struct ecore_eth_stats, 193 tx_9217_to_16383_byte_packets)}, 194 195 {"rx_mac_crtl_frames", 196 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)}, 197 {"tx_mac_control_frames", 198 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)}, 199 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)}, 200 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)}, 201 {"rx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats, rx_pfc_frames)}, 203 {"tx_priority_flow_control_frames", 204 offsetof(struct ecore_eth_stats, tx_pfc_frames)}, 205 206 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)}, 207 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)}, 208 {"rx_carrier_errors", 209 offsetof(struct ecore_eth_stats, rx_carrier_errors)}, 210 {"rx_oversize_packet_errors", 211 offsetof(struct ecore_eth_stats, rx_oversize_packets)}, 212 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)}, 213 {"rx_undersize_packet_errors", 214 offsetof(struct ecore_eth_stats, rx_undersize_packets)}, 215 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)}, 216 {"rx_host_buffer_not_available", 217 offsetof(struct ecore_eth_stats, no_buff_discards)}, 218 /* Number of packets discarded because they are bigger than MTU */ 219 {"rx_packet_too_big_discards", 220 offsetof(struct ecore_eth_stats, packet_too_big_discard)}, 221 {"rx_ttl_zero_discards", 222 offsetof(struct ecore_eth_stats, ttl0_discard)}, 223 {"rx_multi_function_tag_filter_discards", 224 offsetof(struct ecore_eth_stats, mftag_filter_discards)}, 225 {"rx_mac_filter_discards", 226 offsetof(struct ecore_eth_stats, mac_filter_discards)}, 227 {"rx_hw_buffer_truncates", 228 offsetof(struct ecore_eth_stats, brb_truncates)}, 229 {"rx_hw_buffer_discards", 230 offsetof(struct ecore_eth_stats, brb_discards)}, 231 {"tx_lpi_entry_count", 232 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)}, 233 {"tx_total_collisions", 234 offsetof(struct ecore_eth_stats, tx_total_collisions)}, 235 {"tx_error_drop_packets", 236 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)}, 237 238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)}, 239 {"rx_mac_unicast_packets", 240 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)}, 241 {"rx_mac_multicast_packets", 242 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)}, 243 {"rx_mac_broadcast_packets", 244 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)}, 245 {"rx_mac_frames_ok", 246 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)}, 247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)}, 248 {"tx_mac_unicast_packets", 249 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)}, 250 {"tx_mac_multicast_packets", 251 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)}, 252 {"tx_mac_broadcast_packets", 253 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)}, 254 255 {"lro_coalesced_packets", 256 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)}, 257 {"lro_coalesced_events", 258 offsetof(struct ecore_eth_stats, tpa_coalesced_events)}, 259 {"lro_aborts_num", 260 offsetof(struct ecore_eth_stats, tpa_aborts_num)}, 261 {"lro_not_coalesced_packets", 262 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)}, 263 {"lro_coalesced_bytes", 264 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)}, 265 }; 266 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 268 {"rx_q_segments", 269 offsetof(struct qede_rx_queue, rx_segs)}, 270 {"rx_q_hw_errors", 271 offsetof(struct qede_rx_queue, rx_hw_errors)}, 272 {"rx_q_allocation_errors", 273 offsetof(struct qede_rx_queue, rx_alloc_errors)} 274 }; 275 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 277 { 278 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 279 } 280 281 static void 282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param) 283 { 284 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 285 struct qede_dev *qdev = eth_dev->data->dev_private; 286 struct ecore_dev *edev = &qdev->edev; 287 288 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 289 if (rte_intr_enable(handle)) 290 DP_ERR(edev, "rte_intr_enable failed\n"); 291 } 292 293 static void 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 295 { 296 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 297 qdev->num_tc = qdev->dev_info.num_tc; 298 qdev->ops = qed_ops; 299 } 300 301 static void qede_print_adapter_info(struct qede_dev *qdev) 302 { 303 struct ecore_dev *edev = &qdev->edev; 304 struct qed_dev_info *info = &qdev->dev_info.common; 305 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 306 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 307 308 DP_INFO(edev, "*********************************\n"); 309 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 310 DP_INFO(edev, " Chip details : %s%d\n", 311 ECORE_IS_BB(edev) ? "BB" : "AH", 312 CHIP_REV_IS_A0(edev) ? 0 : 1); 313 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 314 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 315 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 316 ver_str, QEDE_PMD_VERSION); 317 DP_INFO(edev, " Driver version : %s\n", drv_ver); 318 DP_INFO(edev, " Firmware version : %s\n", ver_str); 319 320 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 321 "%d.%d.%d.%d", 322 (info->mfw_rev >> 24) & 0xff, 323 (info->mfw_rev >> 16) & 0xff, 324 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 325 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 326 DP_INFO(edev, " Firmware file : %s\n", fw_file); 327 DP_INFO(edev, "*********************************\n"); 328 } 329 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 331 { 332 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 333 ucast->is_rx_filter = true; 334 ucast->is_tx_filter = true; 335 /* ucast->assert_on_error = true; - For debug */ 336 } 337 338 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn, 339 uint8_t clss, bool mode, bool mask) 340 { 341 memset(p_tunn, 0, sizeof(struct ecore_tunnel_info)); 342 p_tunn->vxlan.b_update_mode = mode; 343 p_tunn->vxlan.b_mode_enabled = mask; 344 p_tunn->b_update_rx_cls = true; 345 p_tunn->b_update_tx_cls = true; 346 p_tunn->vxlan.tun_cls = clss; 347 } 348 349 static int 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 351 bool add) 352 { 353 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 354 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 355 struct qede_ucast_entry *tmp = NULL; 356 struct qede_ucast_entry *u; 357 struct ether_addr *mac_addr; 358 359 mac_addr = (struct ether_addr *)ucast->mac; 360 if (add) { 361 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 362 if ((memcmp(mac_addr, &tmp->mac, 363 ETHER_ADDR_LEN) == 0) && 364 ucast->vlan == tmp->vlan) { 365 DP_ERR(edev, "Unicast MAC is already added" 366 " with vlan = %u, vni = %u\n", 367 ucast->vlan, ucast->vni); 368 return -EEXIST; 369 } 370 } 371 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 372 RTE_CACHE_LINE_SIZE); 373 if (!u) { 374 DP_ERR(edev, "Did not allocate memory for ucast\n"); 375 return -ENOMEM; 376 } 377 ether_addr_copy(mac_addr, &u->mac); 378 u->vlan = ucast->vlan; 379 u->vni = ucast->vni; 380 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 381 qdev->num_uc_addr++; 382 } else { 383 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 384 if ((memcmp(mac_addr, &tmp->mac, 385 ETHER_ADDR_LEN) == 0) && 386 ucast->vlan == tmp->vlan && 387 ucast->vni == tmp->vni) 388 break; 389 } 390 if (tmp == NULL) { 391 DP_INFO(edev, "Unicast MAC is not found\n"); 392 return -EINVAL; 393 } 394 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 395 qdev->num_uc_addr--; 396 } 397 398 return 0; 399 } 400 401 static int 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast, 403 bool add) 404 { 405 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 406 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 407 struct ether_addr *mac_addr; 408 struct qede_mcast_entry *tmp = NULL; 409 struct qede_mcast_entry *m; 410 411 mac_addr = (struct ether_addr *)mcast->mac; 412 if (add) { 413 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 414 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) { 415 DP_ERR(edev, 416 "Multicast MAC is already added\n"); 417 return -EEXIST; 418 } 419 } 420 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 421 RTE_CACHE_LINE_SIZE); 422 if (!m) { 423 DP_ERR(edev, 424 "Did not allocate memory for mcast\n"); 425 return -ENOMEM; 426 } 427 ether_addr_copy(mac_addr, &m->mac); 428 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 429 qdev->num_mc_addr++; 430 } else { 431 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 432 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) 433 break; 434 } 435 if (tmp == NULL) { 436 DP_INFO(edev, "Multicast mac is not found\n"); 437 return -EINVAL; 438 } 439 SLIST_REMOVE(&qdev->mc_list_head, tmp, 440 qede_mcast_entry, list); 441 qdev->num_mc_addr--; 442 } 443 444 return 0; 445 } 446 447 static enum _ecore_status_t 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 449 bool add) 450 { 451 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 452 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 453 enum _ecore_status_t rc; 454 struct ecore_filter_mcast mcast; 455 struct qede_mcast_entry *tmp; 456 uint16_t j = 0; 457 458 /* Multicast */ 459 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) { 460 if (add) { 461 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) { 462 DP_ERR(edev, 463 "Mcast filter table limit exceeded, " 464 "Please enable mcast promisc mode\n"); 465 return -ECORE_INVAL; 466 } 467 } 468 rc = qede_mcast_filter(eth_dev, ucast, add); 469 if (rc == 0) { 470 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr); 471 memset(&mcast, 0, sizeof(mcast)); 472 mcast.num_mc_addrs = qdev->num_mc_addr; 473 mcast.opcode = ECORE_FILTER_ADD; 474 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 475 ether_addr_copy(&tmp->mac, 476 (struct ether_addr *)&mcast.mac[j]); 477 j++; 478 } 479 rc = ecore_filter_mcast_cmd(edev, &mcast, 480 ECORE_SPQ_MODE_CB, NULL); 481 } 482 if (rc != ECORE_SUCCESS) { 483 DP_ERR(edev, "Failed to add multicast filter" 484 " rc = %d, op = %d\n", rc, add); 485 } 486 } else { /* Unicast */ 487 if (add) { 488 if (qdev->num_uc_addr >= 489 qdev->dev_info.num_mac_filters) { 490 DP_ERR(edev, 491 "Ucast filter table limit exceeded," 492 " Please enable promisc mode\n"); 493 return -ECORE_INVAL; 494 } 495 } 496 rc = qede_ucast_filter(eth_dev, ucast, add); 497 if (rc == 0) 498 rc = ecore_filter_ucast_cmd(edev, ucast, 499 ECORE_SPQ_MODE_CB, NULL); 500 if (rc != ECORE_SUCCESS) { 501 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 502 rc, add); 503 } 504 } 505 506 return rc; 507 } 508 509 static void 510 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 511 uint32_t index, __rte_unused uint32_t pool) 512 { 513 struct ecore_filter_ucast ucast; 514 515 qede_set_ucast_cmn_params(&ucast); 516 ucast.type = ECORE_FILTER_MAC; 517 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 518 (void)qede_mac_int_ops(eth_dev, &ucast, 1); 519 } 520 521 static void 522 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 523 { 524 struct qede_dev *qdev = eth_dev->data->dev_private; 525 struct ecore_dev *edev = &qdev->edev; 526 struct ether_addr mac_addr; 527 struct ecore_filter_ucast ucast; 528 int rc; 529 530 PMD_INIT_FUNC_TRACE(edev); 531 532 if (index >= qdev->dev_info.num_mac_filters) { 533 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 534 index, qdev->dev_info.num_mac_filters); 535 return; 536 } 537 538 qede_set_ucast_cmn_params(&ucast); 539 ucast.opcode = ECORE_FILTER_REMOVE; 540 ucast.type = ECORE_FILTER_MAC; 541 542 /* Use the index maintained by rte */ 543 ether_addr_copy(ð_dev->data->mac_addrs[index], 544 (struct ether_addr *)&ucast.mac); 545 546 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 547 } 548 549 static void 550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 551 { 552 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 553 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 554 struct ecore_filter_ucast ucast; 555 int rc; 556 557 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 558 mac_addr->addr_bytes)) { 559 DP_ERR(edev, "Setting MAC address is not allowed\n"); 560 ether_addr_copy(&qdev->primary_mac, 561 ð_dev->data->mac_addrs[0]); 562 return; 563 } 564 565 /* First remove the primary mac */ 566 qede_set_ucast_cmn_params(&ucast); 567 ucast.opcode = ECORE_FILTER_REMOVE; 568 ucast.type = ECORE_FILTER_MAC; 569 ether_addr_copy(&qdev->primary_mac, 570 (struct ether_addr *)&ucast.mac); 571 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 572 if (rc != 0) { 573 DP_ERR(edev, "Unable to remove current macaddr" 574 " Reverting to previous default mac\n"); 575 ether_addr_copy(&qdev->primary_mac, 576 ð_dev->data->mac_addrs[0]); 577 return; 578 } 579 580 /* Add new MAC */ 581 ucast.opcode = ECORE_FILTER_ADD; 582 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 583 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 584 if (rc != 0) 585 DP_ERR(edev, "Unable to add new default mac\n"); 586 else 587 ether_addr_copy(mac_addr, &qdev->primary_mac); 588 } 589 590 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action) 591 { 592 struct ecore_dev *edev = &qdev->edev; 593 struct qed_update_vport_params params = { 594 .vport_id = 0, 595 .accept_any_vlan = action, 596 .update_accept_any_vlan_flg = 1, 597 }; 598 int rc; 599 600 /* Proceed only if action actually needs to be performed */ 601 if (qdev->accept_any_vlan == action) 602 return; 603 604 rc = qdev->ops->vport_update(edev, ¶ms); 605 if (rc) { 606 DP_ERR(edev, "Failed to %s accept-any-vlan\n", 607 action ? "enable" : "disable"); 608 } else { 609 DP_INFO(edev, "%s accept-any-vlan\n", 610 action ? "enabled" : "disabled"); 611 qdev->accept_any_vlan = action; 612 } 613 } 614 615 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping) 616 { 617 struct qed_update_vport_params vport_update_params; 618 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 619 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 620 int rc; 621 622 memset(&vport_update_params, 0, sizeof(vport_update_params)); 623 vport_update_params.vport_id = 0; 624 vport_update_params.update_inner_vlan_removal_flg = 1; 625 vport_update_params.inner_vlan_removal_flg = set_stripping; 626 rc = qdev->ops->vport_update(edev, &vport_update_params); 627 if (rc) { 628 DP_ERR(edev, "Update V-PORT failed %d\n", rc); 629 return rc; 630 } 631 632 return 0; 633 } 634 635 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 636 { 637 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 638 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 639 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 640 641 if (mask & ETH_VLAN_STRIP_MASK) { 642 if (rxmode->hw_vlan_strip) 643 (void)qede_vlan_stripping(eth_dev, 1); 644 else 645 (void)qede_vlan_stripping(eth_dev, 0); 646 } 647 648 if (mask & ETH_VLAN_FILTER_MASK) { 649 /* VLAN filtering kicks in when a VLAN is added */ 650 if (rxmode->hw_vlan_filter) { 651 qede_vlan_filter_set(eth_dev, 0, 1); 652 } else { 653 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 654 DP_ERR(edev, 655 " Please remove existing VLAN filters" 656 " before disabling VLAN filtering\n"); 657 /* Signal app that VLAN filtering is still 658 * enabled 659 */ 660 rxmode->hw_vlan_filter = true; 661 } else { 662 qede_vlan_filter_set(eth_dev, 0, 0); 663 } 664 } 665 } 666 667 if (mask & ETH_VLAN_EXTEND_MASK) 668 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 669 " and classification is based on outer tag only\n"); 670 671 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 672 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 673 } 674 675 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 676 uint16_t vlan_id, int on) 677 { 678 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 679 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 680 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 681 struct qede_vlan_entry *tmp = NULL; 682 struct qede_vlan_entry *vlan; 683 struct ecore_filter_ucast ucast; 684 int rc; 685 686 if (on) { 687 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 688 DP_ERR(edev, "Reached max VLAN filter limit" 689 " enabling accept_any_vlan\n"); 690 qede_config_accept_any_vlan(qdev, true); 691 return 0; 692 } 693 694 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 695 if (tmp->vid == vlan_id) { 696 DP_ERR(edev, "VLAN %u already configured\n", 697 vlan_id); 698 return -EEXIST; 699 } 700 } 701 702 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 703 RTE_CACHE_LINE_SIZE); 704 705 if (!vlan) { 706 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 707 return -ENOMEM; 708 } 709 710 qede_set_ucast_cmn_params(&ucast); 711 ucast.opcode = ECORE_FILTER_ADD; 712 ucast.type = ECORE_FILTER_VLAN; 713 ucast.vlan = vlan_id; 714 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 715 NULL); 716 if (rc != 0) { 717 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 718 rc); 719 rte_free(vlan); 720 } else { 721 vlan->vid = vlan_id; 722 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 723 qdev->configured_vlans++; 724 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 725 vlan_id, qdev->configured_vlans); 726 } 727 } else { 728 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 729 if (tmp->vid == vlan_id) 730 break; 731 } 732 733 if (!tmp) { 734 if (qdev->configured_vlans == 0) { 735 DP_INFO(edev, 736 "No VLAN filters configured yet\n"); 737 return 0; 738 } 739 740 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 741 return -EINVAL; 742 } 743 744 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 745 746 qede_set_ucast_cmn_params(&ucast); 747 ucast.opcode = ECORE_FILTER_REMOVE; 748 ucast.type = ECORE_FILTER_VLAN; 749 ucast.vlan = vlan_id; 750 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 751 NULL); 752 if (rc != 0) { 753 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 754 vlan_id, rc); 755 } else { 756 qdev->configured_vlans--; 757 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 758 vlan_id, qdev->configured_vlans); 759 } 760 } 761 762 return rc; 763 } 764 765 static int qede_init_vport(struct qede_dev *qdev) 766 { 767 struct ecore_dev *edev = &qdev->edev; 768 struct qed_start_vport_params start = {0}; 769 int rc; 770 771 start.remove_inner_vlan = 1; 772 start.gro_enable = 0; 773 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD; 774 start.vport_id = 0; 775 start.drop_ttl0 = false; 776 start.clear_stats = 1; 777 start.handle_ptp_pkts = 0; 778 779 rc = qdev->ops->vport_start(edev, &start); 780 if (rc) { 781 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 782 return rc; 783 } 784 785 DP_INFO(edev, 786 "Start vport ramrod passed, vport_id = %d, MTU = %u\n", 787 start.vport_id, ETHER_MTU); 788 789 return 0; 790 } 791 792 static void qede_prandom_bytes(uint32_t *buff) 793 { 794 uint8_t i; 795 796 srand((unsigned int)time(NULL)); 797 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 798 buff[i] = rand(); 799 } 800 801 static int qede_config_rss(struct rte_eth_dev *eth_dev) 802 { 803 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 804 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 805 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 806 struct rte_eth_rss_reta_entry64 reta_conf[2]; 807 struct rte_eth_rss_conf rss_conf; 808 uint32_t i, id, pos, q; 809 810 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 811 if (!rss_conf.rss_key) { 812 DP_INFO(edev, "Applying driver default key\n"); 813 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 814 qede_prandom_bytes(&def_rss_key[0]); 815 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 816 } 817 818 /* Configure RSS hash */ 819 if (qede_rss_hash_update(eth_dev, &rss_conf)) 820 return -EINVAL; 821 822 /* Configure default RETA */ 823 memset(reta_conf, 0, sizeof(reta_conf)); 824 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 825 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 826 827 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 828 id = i / RTE_RETA_GROUP_SIZE; 829 pos = i % RTE_RETA_GROUP_SIZE; 830 q = i % QEDE_RSS_COUNT(qdev); 831 reta_conf[id].reta[pos] = q; 832 } 833 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 834 ECORE_RSS_IND_TABLE_SIZE)) 835 return -EINVAL; 836 837 return 0; 838 } 839 840 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 841 { 842 struct qede_dev *qdev = eth_dev->data->dev_private; 843 struct ecore_dev *edev = &qdev->edev; 844 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 845 int rc, i, j; 846 847 PMD_INIT_FUNC_TRACE(edev); 848 849 /* Check requirements for 100G mode */ 850 if (edev->num_hwfns > 1) { 851 if (eth_dev->data->nb_rx_queues < 2 || 852 eth_dev->data->nb_tx_queues < 2) { 853 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 854 return -EINVAL; 855 } 856 857 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 858 (eth_dev->data->nb_tx_queues % 2 != 0)) { 859 DP_ERR(edev, 860 "100G mode needs even no. of RX/TX queues\n"); 861 return -EINVAL; 862 } 863 } 864 865 /* Sanity checks and throw warnings */ 866 if (rxmode->enable_scatter == 1) 867 eth_dev->data->scattered_rx = 1; 868 869 if (rxmode->enable_lro == 1) { 870 DP_ERR(edev, "LRO is not supported\n"); 871 return -EINVAL; 872 } 873 874 if (!rxmode->hw_strip_crc) 875 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 876 877 if (!rxmode->hw_ip_checksum) 878 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 879 "in hw\n"); 880 881 /* Check for the port restart case */ 882 if (qdev->state != QEDE_DEV_INIT) { 883 rc = qdev->ops->vport_stop(edev, 0); 884 if (rc != 0) 885 return rc; 886 qede_dealloc_fp_resc(eth_dev); 887 } 888 889 qdev->fp_num_tx = eth_dev->data->nb_tx_queues; 890 qdev->fp_num_rx = eth_dev->data->nb_rx_queues; 891 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx; 892 893 /* Fastpath status block should be initialized before sending 894 * VPORT-START in the case of VF. Anyway, do it for both VF/PF. 895 */ 896 rc = qede_alloc_fp_resc(qdev); 897 if (rc != 0) 898 return rc; 899 900 /* Issue VPORT-START with default config values to allow 901 * other port configurations early on. 902 */ 903 rc = qede_init_vport(qdev); 904 if (rc != 0) 905 return rc; 906 907 /* Do RSS configuration after vport-start */ 908 switch (rxmode->mq_mode) { 909 case ETH_MQ_RX_RSS: 910 rc = qede_config_rss(eth_dev); 911 if (rc != 0) { 912 qdev->ops->vport_stop(edev, 0); 913 qede_dealloc_fp_resc(eth_dev); 914 return -EINVAL; 915 } 916 break; 917 case ETH_MQ_RX_NONE: 918 DP_INFO(edev, "RSS is disabled\n"); 919 break; 920 default: 921 DP_ERR(edev, "Unsupported RSS mode\n"); 922 qdev->ops->vport_stop(edev, 0); 923 qede_dealloc_fp_resc(eth_dev); 924 return -EINVAL; 925 } 926 927 SLIST_INIT(&qdev->vlan_list_head); 928 929 /* Add primary mac for PF */ 930 if (IS_PF(edev)) 931 qede_mac_addr_set(eth_dev, &qdev->primary_mac); 932 933 /* Enable VLAN offloads by default */ 934 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 935 ETH_VLAN_FILTER_MASK | 936 ETH_VLAN_EXTEND_MASK); 937 938 qdev->state = QEDE_DEV_CONFIG; 939 940 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n", 941 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev), 942 qdev->num_tc); 943 944 return 0; 945 } 946 947 /* Info about HW descriptor ring limitations */ 948 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 949 .nb_max = NUM_RX_BDS_MAX, 950 .nb_min = 128, 951 .nb_align = 128 /* lowest common multiple */ 952 }; 953 954 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 955 .nb_max = NUM_TX_BDS_MAX, 956 .nb_min = 256, 957 .nb_align = 256 958 }; 959 960 static void 961 qede_dev_info_get(struct rte_eth_dev *eth_dev, 962 struct rte_eth_dev_info *dev_info) 963 { 964 struct qede_dev *qdev = eth_dev->data->dev_private; 965 struct ecore_dev *edev = &qdev->edev; 966 struct qed_link_output link; 967 uint32_t speed_cap = 0; 968 969 PMD_INIT_FUNC_TRACE(edev); 970 971 dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 972 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 973 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 974 dev_info->rx_desc_lim = qede_rx_desc_lim; 975 dev_info->tx_desc_lim = qede_tx_desc_lim; 976 977 if (IS_PF(edev)) 978 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 979 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 980 else 981 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 982 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 983 dev_info->max_tx_queues = dev_info->max_rx_queues; 984 985 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 986 dev_info->max_vfs = 0; 987 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 988 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 989 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 990 991 dev_info->default_txconf = (struct rte_eth_txconf) { 992 .txq_flags = QEDE_TXQ_FLAGS, 993 }; 994 995 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 996 DEV_RX_OFFLOAD_IPV4_CKSUM | 997 DEV_RX_OFFLOAD_UDP_CKSUM | 998 DEV_RX_OFFLOAD_TCP_CKSUM | 999 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM); 1000 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1001 DEV_TX_OFFLOAD_IPV4_CKSUM | 1002 DEV_TX_OFFLOAD_UDP_CKSUM | 1003 DEV_TX_OFFLOAD_TCP_CKSUM | 1004 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM); 1005 1006 memset(&link, 0, sizeof(struct qed_link_output)); 1007 qdev->ops->common->get_link(edev, &link); 1008 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1009 speed_cap |= ETH_LINK_SPEED_1G; 1010 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1011 speed_cap |= ETH_LINK_SPEED_10G; 1012 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1013 speed_cap |= ETH_LINK_SPEED_25G; 1014 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1015 speed_cap |= ETH_LINK_SPEED_40G; 1016 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1017 speed_cap |= ETH_LINK_SPEED_50G; 1018 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1019 speed_cap |= ETH_LINK_SPEED_100G; 1020 dev_info->speed_capa = speed_cap; 1021 } 1022 1023 /* return 0 means link status changed, -1 means not changed */ 1024 static int 1025 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1026 { 1027 struct qede_dev *qdev = eth_dev->data->dev_private; 1028 struct ecore_dev *edev = &qdev->edev; 1029 uint16_t link_duplex; 1030 struct qed_link_output link; 1031 struct rte_eth_link *curr = ð_dev->data->dev_link; 1032 1033 memset(&link, 0, sizeof(struct qed_link_output)); 1034 qdev->ops->common->get_link(edev, &link); 1035 1036 /* Link Speed */ 1037 curr->link_speed = link.speed; 1038 1039 /* Link Mode */ 1040 switch (link.duplex) { 1041 case QEDE_DUPLEX_HALF: 1042 link_duplex = ETH_LINK_HALF_DUPLEX; 1043 break; 1044 case QEDE_DUPLEX_FULL: 1045 link_duplex = ETH_LINK_FULL_DUPLEX; 1046 break; 1047 case QEDE_DUPLEX_UNKNOWN: 1048 default: 1049 link_duplex = -1; 1050 } 1051 curr->link_duplex = link_duplex; 1052 1053 /* Link Status */ 1054 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 1055 1056 /* AN */ 1057 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1058 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1059 1060 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1061 curr->link_speed, curr->link_duplex, 1062 curr->link_autoneg, curr->link_status); 1063 1064 /* return 0 means link status changed, -1 means not changed */ 1065 return ((curr->link_status == link.link_up) ? -1 : 0); 1066 } 1067 1068 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1069 { 1070 struct qede_dev *qdev = eth_dev->data->dev_private; 1071 struct ecore_dev *edev = &qdev->edev; 1072 1073 PMD_INIT_FUNC_TRACE(edev); 1074 1075 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1076 1077 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1078 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1079 1080 qed_configure_filter_rx_mode(eth_dev, type); 1081 } 1082 1083 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1084 { 1085 struct qede_dev *qdev = eth_dev->data->dev_private; 1086 struct ecore_dev *edev = &qdev->edev; 1087 1088 PMD_INIT_FUNC_TRACE(edev); 1089 1090 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1091 qed_configure_filter_rx_mode(eth_dev, 1092 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1093 else 1094 qed_configure_filter_rx_mode(eth_dev, 1095 QED_FILTER_RX_MODE_TYPE_REGULAR); 1096 } 1097 1098 static void qede_poll_sp_sb_cb(void *param) 1099 { 1100 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1101 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1102 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1103 int rc; 1104 1105 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1106 qede_interrupt_action(&edev->hwfns[1]); 1107 1108 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1109 qede_poll_sp_sb_cb, 1110 (void *)eth_dev); 1111 if (rc != 0) { 1112 DP_ERR(edev, "Unable to start periodic" 1113 " timer rc %d\n", rc); 1114 assert(false && "Unable to start periodic timer"); 1115 } 1116 } 1117 1118 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1119 { 1120 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1121 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1122 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1123 int rc; 1124 1125 PMD_INIT_FUNC_TRACE(edev); 1126 1127 /* dev_stop() shall cleanup fp resources in hw but without releasing 1128 * dma memories and sw structures so that dev_start() can be called 1129 * by the app without reconfiguration. However, in dev_close() we 1130 * can release all the resources and device can be brought up newly 1131 */ 1132 if (qdev->state != QEDE_DEV_STOP) 1133 qede_dev_stop(eth_dev); 1134 else 1135 DP_INFO(edev, "Device is already stopped\n"); 1136 1137 rc = qdev->ops->vport_stop(edev, 0); 1138 if (rc != 0) 1139 DP_ERR(edev, "Failed to stop VPORT\n"); 1140 1141 qede_dealloc_fp_resc(eth_dev); 1142 1143 qdev->ops->common->slowpath_stop(edev); 1144 1145 qdev->ops->common->remove(edev); 1146 1147 rte_intr_disable(&pci_dev->intr_handle); 1148 1149 rte_intr_callback_unregister(&pci_dev->intr_handle, 1150 qede_interrupt_handler, (void *)eth_dev); 1151 1152 if (edev->num_hwfns > 1) 1153 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1154 1155 qdev->state = QEDE_DEV_INIT; /* Go back to init state */ 1156 } 1157 1158 static void 1159 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1160 { 1161 struct qede_dev *qdev = eth_dev->data->dev_private; 1162 struct ecore_dev *edev = &qdev->edev; 1163 struct ecore_eth_stats stats; 1164 unsigned int i = 0, j = 0, qid; 1165 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1166 struct qede_tx_queue *txq; 1167 1168 qdev->ops->get_vport_stats(edev, &stats); 1169 1170 /* RX Stats */ 1171 eth_stats->ipackets = stats.rx_ucast_pkts + 1172 stats.rx_mcast_pkts + stats.rx_bcast_pkts; 1173 1174 eth_stats->ibytes = stats.rx_ucast_bytes + 1175 stats.rx_mcast_bytes + stats.rx_bcast_bytes; 1176 1177 eth_stats->ierrors = stats.rx_crc_errors + 1178 stats.rx_align_errors + 1179 stats.rx_carrier_errors + 1180 stats.rx_oversize_packets + 1181 stats.rx_jabbers + stats.rx_undersize_packets; 1182 1183 eth_stats->rx_nombuf = stats.no_buff_discards; 1184 1185 eth_stats->imissed = stats.mftag_filter_discards + 1186 stats.mac_filter_discards + 1187 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards; 1188 1189 /* TX stats */ 1190 eth_stats->opackets = stats.tx_ucast_pkts + 1191 stats.tx_mcast_pkts + stats.tx_bcast_pkts; 1192 1193 eth_stats->obytes = stats.tx_ucast_bytes + 1194 stats.tx_mcast_bytes + stats.tx_bcast_bytes; 1195 1196 eth_stats->oerrors = stats.tx_err_drop_pkts; 1197 1198 /* Queue stats */ 1199 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1200 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1201 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1202 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1203 if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) || 1204 (txq_stat_cntrs != QEDE_TSS_COUNT(qdev))) 1205 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1206 "Not all the queue stats will be displayed. Set" 1207 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1208 " appropriately and retry.\n"); 1209 1210 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 1211 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 1212 eth_stats->q_ipackets[i] = 1213 *(uint64_t *)( 1214 ((char *)(qdev->fp_array[(qid)].rxq)) + 1215 offsetof(struct qede_rx_queue, 1216 rcv_pkts)); 1217 eth_stats->q_errors[i] = 1218 *(uint64_t *)( 1219 ((char *)(qdev->fp_array[(qid)].rxq)) + 1220 offsetof(struct qede_rx_queue, 1221 rx_hw_errors)) + 1222 *(uint64_t *)( 1223 ((char *)(qdev->fp_array[(qid)].rxq)) + 1224 offsetof(struct qede_rx_queue, 1225 rx_alloc_errors)); 1226 i++; 1227 } 1228 if (i == rxq_stat_cntrs) 1229 break; 1230 } 1231 1232 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) { 1233 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) { 1234 txq = qdev->fp_array[(qid)].txqs[0]; 1235 eth_stats->q_opackets[j] = 1236 *((uint64_t *)(uintptr_t) 1237 (((uint64_t)(uintptr_t)(txq)) + 1238 offsetof(struct qede_tx_queue, 1239 xmit_pkts))); 1240 j++; 1241 } 1242 if (j == txq_stat_cntrs) 1243 break; 1244 } 1245 } 1246 1247 static unsigned 1248 qede_get_xstats_count(struct qede_dev *qdev) { 1249 return RTE_DIM(qede_xstats_strings) + 1250 (RTE_DIM(qede_rxq_xstats_strings) * 1251 RTE_MIN(QEDE_RSS_COUNT(qdev), 1252 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1253 } 1254 1255 static int 1256 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev, 1257 struct rte_eth_xstat_name *xstats_names, unsigned limit) 1258 { 1259 struct qede_dev *qdev = dev->data->dev_private; 1260 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1261 unsigned int i, qid, stat_idx = 0; 1262 unsigned int rxq_stat_cntrs; 1263 1264 if (xstats_names != NULL) { 1265 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1266 snprintf(xstats_names[stat_idx].name, 1267 sizeof(xstats_names[stat_idx].name), 1268 "%s", 1269 qede_xstats_strings[i].name); 1270 stat_idx++; 1271 } 1272 1273 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1274 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1275 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1276 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1277 snprintf(xstats_names[stat_idx].name, 1278 sizeof(xstats_names[stat_idx].name), 1279 "%.4s%d%s", 1280 qede_rxq_xstats_strings[i].name, qid, 1281 qede_rxq_xstats_strings[i].name + 4); 1282 stat_idx++; 1283 } 1284 } 1285 } 1286 1287 return stat_cnt; 1288 } 1289 1290 static int 1291 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1292 unsigned int n) 1293 { 1294 struct qede_dev *qdev = dev->data->dev_private; 1295 struct ecore_dev *edev = &qdev->edev; 1296 struct ecore_eth_stats stats; 1297 const unsigned int num = qede_get_xstats_count(qdev); 1298 unsigned int i, qid, stat_idx = 0; 1299 unsigned int rxq_stat_cntrs; 1300 1301 if (n < num) 1302 return num; 1303 1304 qdev->ops->get_vport_stats(edev, &stats); 1305 1306 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1307 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1308 qede_xstats_strings[i].offset); 1309 xstats[stat_idx].id = stat_idx; 1310 stat_idx++; 1311 } 1312 1313 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1314 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1315 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1316 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) { 1317 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1318 xstats[stat_idx].value = *(uint64_t *)( 1319 ((char *)(qdev->fp_array[(qid)].rxq)) + 1320 qede_rxq_xstats_strings[i].offset); 1321 xstats[stat_idx].id = stat_idx; 1322 stat_idx++; 1323 } 1324 } 1325 } 1326 1327 return stat_idx; 1328 } 1329 1330 static void 1331 qede_reset_xstats(struct rte_eth_dev *dev) 1332 { 1333 struct qede_dev *qdev = dev->data->dev_private; 1334 struct ecore_dev *edev = &qdev->edev; 1335 1336 ecore_reset_vport_stats(edev); 1337 } 1338 1339 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1340 { 1341 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1342 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1343 struct qed_link_params link_params; 1344 int rc; 1345 1346 DP_INFO(edev, "setting link state %d\n", link_up); 1347 memset(&link_params, 0, sizeof(link_params)); 1348 link_params.link_up = link_up; 1349 rc = qdev->ops->common->set_link(edev, &link_params); 1350 if (rc != ECORE_SUCCESS) 1351 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1352 1353 return rc; 1354 } 1355 1356 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1357 { 1358 return qede_dev_set_link_state(eth_dev, true); 1359 } 1360 1361 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1362 { 1363 return qede_dev_set_link_state(eth_dev, false); 1364 } 1365 1366 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1367 { 1368 struct qede_dev *qdev = eth_dev->data->dev_private; 1369 struct ecore_dev *edev = &qdev->edev; 1370 1371 ecore_reset_vport_stats(edev); 1372 } 1373 1374 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1375 { 1376 enum qed_filter_rx_mode_type type = 1377 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1378 1379 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1380 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1381 1382 qed_configure_filter_rx_mode(eth_dev, type); 1383 } 1384 1385 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1386 { 1387 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1388 qed_configure_filter_rx_mode(eth_dev, 1389 QED_FILTER_RX_MODE_TYPE_PROMISC); 1390 else 1391 qed_configure_filter_rx_mode(eth_dev, 1392 QED_FILTER_RX_MODE_TYPE_REGULAR); 1393 } 1394 1395 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1396 struct rte_eth_fc_conf *fc_conf) 1397 { 1398 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1399 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1400 struct qed_link_output current_link; 1401 struct qed_link_params params; 1402 1403 memset(¤t_link, 0, sizeof(current_link)); 1404 qdev->ops->common->get_link(edev, ¤t_link); 1405 1406 memset(¶ms, 0, sizeof(params)); 1407 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1408 if (fc_conf->autoneg) { 1409 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1410 DP_ERR(edev, "Autoneg not supported\n"); 1411 return -EINVAL; 1412 } 1413 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1414 } 1415 1416 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1417 if (fc_conf->mode == RTE_FC_FULL) 1418 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1419 QED_LINK_PAUSE_RX_ENABLE); 1420 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1421 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1422 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1423 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1424 1425 params.link_up = true; 1426 (void)qdev->ops->common->set_link(edev, ¶ms); 1427 1428 return 0; 1429 } 1430 1431 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1432 struct rte_eth_fc_conf *fc_conf) 1433 { 1434 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1435 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1436 struct qed_link_output current_link; 1437 1438 memset(¤t_link, 0, sizeof(current_link)); 1439 qdev->ops->common->get_link(edev, ¤t_link); 1440 1441 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1442 fc_conf->autoneg = true; 1443 1444 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1445 QED_LINK_PAUSE_TX_ENABLE)) 1446 fc_conf->mode = RTE_FC_FULL; 1447 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1448 fc_conf->mode = RTE_FC_RX_PAUSE; 1449 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1450 fc_conf->mode = RTE_FC_TX_PAUSE; 1451 else 1452 fc_conf->mode = RTE_FC_NONE; 1453 1454 return 0; 1455 } 1456 1457 static const uint32_t * 1458 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1459 { 1460 static const uint32_t ptypes[] = { 1461 RTE_PTYPE_L3_IPV4, 1462 RTE_PTYPE_L3_IPV6, 1463 RTE_PTYPE_UNKNOWN 1464 }; 1465 1466 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1467 return ptypes; 1468 1469 return NULL; 1470 } 1471 1472 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1473 { 1474 *rss_caps = 0; 1475 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1476 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1477 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1478 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1479 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1480 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1481 } 1482 1483 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1484 struct rte_eth_rss_conf *rss_conf) 1485 { 1486 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1487 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1488 struct ecore_sp_vport_update_params vport_update_params; 1489 struct ecore_rss_params rss_params; 1490 struct ecore_hwfn *p_hwfn; 1491 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1492 uint64_t hf = rss_conf->rss_hf; 1493 uint8_t len = rss_conf->rss_key_len; 1494 uint8_t idx; 1495 uint8_t i; 1496 int rc; 1497 1498 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1499 memset(&rss_params, 0, sizeof(rss_params)); 1500 1501 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 1502 (unsigned long)hf, len, key); 1503 1504 if (hf != 0) { 1505 /* Enabling RSS */ 1506 DP_INFO(edev, "Enabling rss\n"); 1507 1508 /* RSS caps */ 1509 qede_init_rss_caps(&rss_params.rss_caps, hf); 1510 rss_params.update_rss_capabilities = 1; 1511 1512 /* RSS hash key */ 1513 if (key) { 1514 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 1515 DP_ERR(edev, "RSS key length exceeds limit\n"); 1516 return -EINVAL; 1517 } 1518 DP_INFO(edev, "Applying user supplied hash key\n"); 1519 rss_params.update_rss_key = 1; 1520 memcpy(&rss_params.rss_key, key, len); 1521 } 1522 rss_params.rss_enable = 1; 1523 } 1524 1525 rss_params.update_rss_config = 1; 1526 /* tbl_size has to be set with capabilities */ 1527 rss_params.rss_table_size_log = 7; 1528 vport_update_params.vport_id = 0; 1529 /* pass the L2 handles instead of qids */ 1530 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 1531 idx = qdev->rss_ind_table[i]; 1532 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 1533 } 1534 vport_update_params.rss_params = &rss_params; 1535 1536 for_each_hwfn(edev, i) { 1537 p_hwfn = &edev->hwfns[i]; 1538 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1539 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1540 ECORE_SPQ_MODE_EBLOCK, NULL); 1541 if (rc) { 1542 DP_ERR(edev, "vport-update for RSS failed\n"); 1543 return rc; 1544 } 1545 } 1546 qdev->rss_enable = rss_params.rss_enable; 1547 1548 /* Update local structure for hash query */ 1549 qdev->rss_conf.rss_hf = hf; 1550 qdev->rss_conf.rss_key_len = len; 1551 if (qdev->rss_enable) { 1552 if (qdev->rss_conf.rss_key == NULL) { 1553 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 1554 if (qdev->rss_conf.rss_key == NULL) { 1555 DP_ERR(edev, "No memory to store RSS key\n"); 1556 return -ENOMEM; 1557 } 1558 } 1559 if (key && len) { 1560 DP_INFO(edev, "Storing RSS key\n"); 1561 memcpy(qdev->rss_conf.rss_key, key, len); 1562 } 1563 } else if (!qdev->rss_enable && len == 0) { 1564 if (qdev->rss_conf.rss_key) { 1565 free(qdev->rss_conf.rss_key); 1566 qdev->rss_conf.rss_key = NULL; 1567 DP_INFO(edev, "Free RSS key\n"); 1568 } 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1575 struct rte_eth_rss_conf *rss_conf) 1576 { 1577 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1578 1579 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 1580 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 1581 1582 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 1583 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 1584 rss_conf->rss_key_len); 1585 return 0; 1586 } 1587 1588 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 1589 struct rte_eth_rss_reta_entry64 *reta_conf, 1590 uint16_t reta_size) 1591 { 1592 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1593 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1594 struct ecore_sp_vport_update_params vport_update_params; 1595 struct ecore_rss_params params; 1596 struct ecore_hwfn *p_hwfn; 1597 uint16_t i, idx, shift; 1598 uint8_t entry; 1599 int rc; 1600 1601 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1602 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 1603 reta_size); 1604 return -EINVAL; 1605 } 1606 1607 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1608 memset(¶ms, 0, sizeof(params)); 1609 1610 for (i = 0; i < reta_size; i++) { 1611 idx = i / RTE_RETA_GROUP_SIZE; 1612 shift = i % RTE_RETA_GROUP_SIZE; 1613 if (reta_conf[idx].mask & (1ULL << shift)) { 1614 entry = reta_conf[idx].reta[shift]; 1615 /* Pass rxq handles to ecore */ 1616 params.rss_ind_table[i] = 1617 qdev->fp_array[entry].rxq->handle; 1618 /* Update the local copy for RETA query command */ 1619 qdev->rss_ind_table[i] = entry; 1620 } 1621 } 1622 1623 /* Fix up RETA for CMT mode device */ 1624 if (edev->num_hwfns > 1) 1625 qdev->rss_enable = qed_update_rss_parm_cmt(edev, 1626 params.rss_ind_table[0]); 1627 params.update_rss_ind_table = 1; 1628 params.rss_table_size_log = 7; 1629 params.update_rss_config = 1; 1630 vport_update_params.vport_id = 0; 1631 /* Use the current value of rss_enable */ 1632 params.rss_enable = qdev->rss_enable; 1633 vport_update_params.rss_params = ¶ms; 1634 1635 for_each_hwfn(edev, i) { 1636 p_hwfn = &edev->hwfns[i]; 1637 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1638 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1639 ECORE_SPQ_MODE_EBLOCK, NULL); 1640 if (rc) { 1641 DP_ERR(edev, "vport-update for RSS failed\n"); 1642 return rc; 1643 } 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 1650 struct rte_eth_rss_reta_entry64 *reta_conf, 1651 uint16_t reta_size) 1652 { 1653 struct qede_dev *qdev = eth_dev->data->dev_private; 1654 struct ecore_dev *edev = &qdev->edev; 1655 uint16_t i, idx, shift; 1656 uint8_t entry; 1657 1658 if (reta_size > ETH_RSS_RETA_SIZE_128) { 1659 DP_ERR(edev, "reta_size %d is not supported\n", 1660 reta_size); 1661 return -EINVAL; 1662 } 1663 1664 for (i = 0; i < reta_size; i++) { 1665 idx = i / RTE_RETA_GROUP_SIZE; 1666 shift = i % RTE_RETA_GROUP_SIZE; 1667 if (reta_conf[idx].mask & (1ULL << shift)) { 1668 entry = qdev->rss_ind_table[i]; 1669 reta_conf[idx].reta[shift] = entry; 1670 } 1671 } 1672 1673 return 0; 1674 } 1675 1676 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1677 { 1678 uint32_t frame_size; 1679 struct qede_dev *qdev = dev->data->dev_private; 1680 struct rte_eth_dev_info dev_info = {0}; 1681 1682 qede_dev_info_get(dev, &dev_info); 1683 1684 /* VLAN_TAG = 4 */ 1685 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4; 1686 1687 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 1688 return -EINVAL; 1689 1690 if (!dev->data->scattered_rx && 1691 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) 1692 return -EINVAL; 1693 1694 if (frame_size > ETHER_MAX_LEN) 1695 dev->data->dev_conf.rxmode.jumbo_frame = 1; 1696 else 1697 dev->data->dev_conf.rxmode.jumbo_frame = 0; 1698 1699 /* update max frame size */ 1700 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1701 qdev->mtu = mtu; 1702 qede_dev_stop(dev); 1703 qede_dev_start(dev); 1704 1705 return 0; 1706 } 1707 1708 static int 1709 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev, 1710 struct rte_eth_udp_tunnel *tunnel_udp, 1711 bool add) 1712 { 1713 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1714 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1715 struct ecore_tunnel_info tunn; /* @DPDK */ 1716 struct ecore_hwfn *p_hwfn; 1717 int rc, i; 1718 1719 PMD_INIT_FUNC_TRACE(edev); 1720 1721 memset(&tunn, 0, sizeof(tunn)); 1722 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) { 1723 tunn.vxlan_port.b_update_port = true; 1724 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port : 1725 QEDE_VXLAN_DEF_PORT; 1726 for_each_hwfn(edev, i) { 1727 p_hwfn = &edev->hwfns[i]; 1728 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 1729 ECORE_SPQ_MODE_CB, NULL); 1730 if (rc != ECORE_SUCCESS) { 1731 DP_ERR(edev, "Unable to config UDP port %u\n", 1732 tunn.vxlan_port.port); 1733 return rc; 1734 } 1735 } 1736 } 1737 1738 return 0; 1739 } 1740 1741 int 1742 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 1743 struct rte_eth_udp_tunnel *tunnel_udp) 1744 { 1745 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false); 1746 } 1747 1748 int 1749 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 1750 struct rte_eth_udp_tunnel *tunnel_udp) 1751 { 1752 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true); 1753 } 1754 1755 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 1756 uint32_t *clss, char *str) 1757 { 1758 uint16_t j; 1759 *clss = MAX_ECORE_TUNN_CLSS; 1760 1761 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 1762 if (filter == qede_tunn_types[j].rte_filter_type) { 1763 *type = qede_tunn_types[j].qede_type; 1764 *clss = qede_tunn_types[j].qede_tunn_clss; 1765 strcpy(str, qede_tunn_types[j].string); 1766 return; 1767 } 1768 } 1769 } 1770 1771 static int 1772 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 1773 const struct rte_eth_tunnel_filter_conf *conf, 1774 uint32_t type) 1775 { 1776 /* Init commmon ucast params first */ 1777 qede_set_ucast_cmn_params(ucast); 1778 1779 /* Copy out the required fields based on classification type */ 1780 ucast->type = type; 1781 1782 switch (type) { 1783 case ECORE_FILTER_VNI: 1784 ucast->vni = conf->tenant_id; 1785 break; 1786 case ECORE_FILTER_INNER_VLAN: 1787 ucast->vlan = conf->inner_vlan; 1788 break; 1789 case ECORE_FILTER_MAC: 1790 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 1791 ETHER_ADDR_LEN); 1792 break; 1793 case ECORE_FILTER_INNER_MAC: 1794 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1795 ETHER_ADDR_LEN); 1796 break; 1797 case ECORE_FILTER_MAC_VNI_PAIR: 1798 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 1799 ETHER_ADDR_LEN); 1800 ucast->vni = conf->tenant_id; 1801 break; 1802 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 1803 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1804 ETHER_ADDR_LEN); 1805 ucast->vni = conf->tenant_id; 1806 break; 1807 case ECORE_FILTER_INNER_PAIR: 1808 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 1809 ETHER_ADDR_LEN); 1810 ucast->vlan = conf->inner_vlan; 1811 break; 1812 default: 1813 return -EINVAL; 1814 } 1815 1816 return ECORE_SUCCESS; 1817 } 1818 1819 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, 1820 enum rte_filter_op filter_op, 1821 const struct rte_eth_tunnel_filter_conf *conf) 1822 { 1823 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1824 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1825 struct ecore_tunnel_info tunn; 1826 struct ecore_hwfn *p_hwfn; 1827 enum ecore_filter_ucast_type type; 1828 enum ecore_tunn_clss clss; 1829 struct ecore_filter_ucast ucast; 1830 char str[80]; 1831 uint16_t filter_type; 1832 int rc, i; 1833 1834 filter_type = conf->filter_type | qdev->vxlan_filter_type; 1835 /* First determine if the given filter classification is supported */ 1836 qede_get_ecore_tunn_params(filter_type, &type, &clss, str); 1837 if (clss == MAX_ECORE_TUNN_CLSS) { 1838 DP_ERR(edev, "Wrong filter type\n"); 1839 return -EINVAL; 1840 } 1841 /* Init tunnel ucast params */ 1842 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 1843 if (rc != ECORE_SUCCESS) { 1844 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n", 1845 conf->filter_type); 1846 return rc; 1847 } 1848 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 1849 str, filter_op, ucast.type); 1850 switch (filter_op) { 1851 case RTE_ETH_FILTER_ADD: 1852 ucast.opcode = ECORE_FILTER_ADD; 1853 1854 /* Skip MAC/VLAN if filter is based on VNI */ 1855 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 1856 rc = qede_mac_int_ops(eth_dev, &ucast, 1); 1857 if (rc == 0) { 1858 /* Enable accept anyvlan */ 1859 qede_config_accept_any_vlan(qdev, true); 1860 } 1861 } else { 1862 rc = qede_ucast_filter(eth_dev, &ucast, 1); 1863 if (rc == 0) 1864 rc = ecore_filter_ucast_cmd(edev, &ucast, 1865 ECORE_SPQ_MODE_CB, NULL); 1866 } 1867 1868 if (rc != ECORE_SUCCESS) 1869 return rc; 1870 1871 qdev->vxlan_filter_type = filter_type; 1872 1873 DP_INFO(edev, "Enabling VXLAN tunneling\n"); 1874 qede_set_cmn_tunn_param(&tunn, clss, true, true); 1875 for_each_hwfn(edev, i) { 1876 p_hwfn = &edev->hwfns[i]; 1877 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, 1878 &tunn, ECORE_SPQ_MODE_CB, NULL); 1879 if (rc != ECORE_SUCCESS) { 1880 DP_ERR(edev, "Failed to update tunn_clss %u\n", 1881 tunn.vxlan.tun_cls); 1882 } 1883 } 1884 qdev->num_tunn_filters++; /* Filter added successfully */ 1885 break; 1886 case RTE_ETH_FILTER_DELETE: 1887 ucast.opcode = ECORE_FILTER_REMOVE; 1888 1889 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 1890 rc = qede_mac_int_ops(eth_dev, &ucast, 0); 1891 } else { 1892 rc = qede_ucast_filter(eth_dev, &ucast, 0); 1893 if (rc == 0) 1894 rc = ecore_filter_ucast_cmd(edev, &ucast, 1895 ECORE_SPQ_MODE_CB, NULL); 1896 } 1897 if (rc != ECORE_SUCCESS) 1898 return rc; 1899 1900 qdev->vxlan_filter_type = filter_type; 1901 qdev->num_tunn_filters--; 1902 1903 /* Disable VXLAN if VXLAN filters become 0 */ 1904 if (qdev->num_tunn_filters == 0) { 1905 DP_INFO(edev, "Disabling VXLAN tunneling\n"); 1906 1907 /* Use 0 as tunnel mode */ 1908 qede_set_cmn_tunn_param(&tunn, clss, false, true); 1909 for_each_hwfn(edev, i) { 1910 p_hwfn = &edev->hwfns[i]; 1911 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn, 1912 ECORE_SPQ_MODE_CB, NULL); 1913 if (rc != ECORE_SUCCESS) { 1914 DP_ERR(edev, 1915 "Failed to update tunn_clss %u\n", 1916 tunn.vxlan.tun_cls); 1917 break; 1918 } 1919 } 1920 } 1921 break; 1922 default: 1923 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 1924 return -EINVAL; 1925 } 1926 DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters); 1927 1928 return 0; 1929 } 1930 1931 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 1932 enum rte_filter_type filter_type, 1933 enum rte_filter_op filter_op, 1934 void *arg) 1935 { 1936 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1937 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1938 struct rte_eth_tunnel_filter_conf *filter_conf = 1939 (struct rte_eth_tunnel_filter_conf *)arg; 1940 1941 switch (filter_type) { 1942 case RTE_ETH_FILTER_TUNNEL: 1943 switch (filter_conf->tunnel_type) { 1944 case RTE_TUNNEL_TYPE_VXLAN: 1945 DP_INFO(edev, 1946 "Packet steering to the specified Rx queue" 1947 " is not supported with VXLAN tunneling"); 1948 return(qede_vxlan_tunn_config(eth_dev, filter_op, 1949 filter_conf)); 1950 /* Place holders for future tunneling support */ 1951 case RTE_TUNNEL_TYPE_GENEVE: 1952 case RTE_TUNNEL_TYPE_TEREDO: 1953 case RTE_TUNNEL_TYPE_NVGRE: 1954 case RTE_TUNNEL_TYPE_IP_IN_GRE: 1955 case RTE_L2_TUNNEL_TYPE_E_TAG: 1956 DP_ERR(edev, "Unsupported tunnel type %d\n", 1957 filter_conf->tunnel_type); 1958 return -EINVAL; 1959 case RTE_TUNNEL_TYPE_NONE: 1960 default: 1961 return 0; 1962 } 1963 break; 1964 case RTE_ETH_FILTER_FDIR: 1965 case RTE_ETH_FILTER_MACVLAN: 1966 case RTE_ETH_FILTER_ETHERTYPE: 1967 case RTE_ETH_FILTER_FLEXIBLE: 1968 case RTE_ETH_FILTER_SYN: 1969 case RTE_ETH_FILTER_NTUPLE: 1970 case RTE_ETH_FILTER_HASH: 1971 case RTE_ETH_FILTER_L2_TUNNEL: 1972 case RTE_ETH_FILTER_MAX: 1973 default: 1974 DP_ERR(edev, "Unsupported filter type %d\n", 1975 filter_type); 1976 return -EINVAL; 1977 } 1978 1979 return 0; 1980 } 1981 1982 static const struct eth_dev_ops qede_eth_dev_ops = { 1983 .dev_configure = qede_dev_configure, 1984 .dev_infos_get = qede_dev_info_get, 1985 .rx_queue_setup = qede_rx_queue_setup, 1986 .rx_queue_release = qede_rx_queue_release, 1987 .tx_queue_setup = qede_tx_queue_setup, 1988 .tx_queue_release = qede_tx_queue_release, 1989 .dev_start = qede_dev_start, 1990 .dev_set_link_up = qede_dev_set_link_up, 1991 .dev_set_link_down = qede_dev_set_link_down, 1992 .link_update = qede_link_update, 1993 .promiscuous_enable = qede_promiscuous_enable, 1994 .promiscuous_disable = qede_promiscuous_disable, 1995 .allmulticast_enable = qede_allmulticast_enable, 1996 .allmulticast_disable = qede_allmulticast_disable, 1997 .dev_stop = qede_dev_stop, 1998 .dev_close = qede_dev_close, 1999 .stats_get = qede_get_stats, 2000 .stats_reset = qede_reset_stats, 2001 .xstats_get = qede_get_xstats, 2002 .xstats_reset = qede_reset_xstats, 2003 .xstats_get_names = qede_get_xstats_names, 2004 .mac_addr_add = qede_mac_addr_add, 2005 .mac_addr_remove = qede_mac_addr_remove, 2006 .mac_addr_set = qede_mac_addr_set, 2007 .vlan_offload_set = qede_vlan_offload_set, 2008 .vlan_filter_set = qede_vlan_filter_set, 2009 .flow_ctrl_set = qede_flow_ctrl_set, 2010 .flow_ctrl_get = qede_flow_ctrl_get, 2011 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2012 .rss_hash_update = qede_rss_hash_update, 2013 .rss_hash_conf_get = qede_rss_hash_conf_get, 2014 .reta_update = qede_rss_reta_update, 2015 .reta_query = qede_rss_reta_query, 2016 .mtu_set = qede_set_mtu, 2017 .filter_ctrl = qede_dev_filter_ctrl, 2018 .udp_tunnel_port_add = qede_udp_dst_port_add, 2019 .udp_tunnel_port_del = qede_udp_dst_port_del, 2020 }; 2021 2022 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2023 .dev_configure = qede_dev_configure, 2024 .dev_infos_get = qede_dev_info_get, 2025 .rx_queue_setup = qede_rx_queue_setup, 2026 .rx_queue_release = qede_rx_queue_release, 2027 .tx_queue_setup = qede_tx_queue_setup, 2028 .tx_queue_release = qede_tx_queue_release, 2029 .dev_start = qede_dev_start, 2030 .dev_set_link_up = qede_dev_set_link_up, 2031 .dev_set_link_down = qede_dev_set_link_down, 2032 .link_update = qede_link_update, 2033 .promiscuous_enable = qede_promiscuous_enable, 2034 .promiscuous_disable = qede_promiscuous_disable, 2035 .allmulticast_enable = qede_allmulticast_enable, 2036 .allmulticast_disable = qede_allmulticast_disable, 2037 .dev_stop = qede_dev_stop, 2038 .dev_close = qede_dev_close, 2039 .stats_get = qede_get_stats, 2040 .stats_reset = qede_reset_stats, 2041 .xstats_get = qede_get_xstats, 2042 .xstats_reset = qede_reset_xstats, 2043 .xstats_get_names = qede_get_xstats_names, 2044 .vlan_offload_set = qede_vlan_offload_set, 2045 .vlan_filter_set = qede_vlan_filter_set, 2046 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2047 .rss_hash_update = qede_rss_hash_update, 2048 .rss_hash_conf_get = qede_rss_hash_conf_get, 2049 .reta_update = qede_rss_reta_update, 2050 .reta_query = qede_rss_reta_query, 2051 .mtu_set = qede_set_mtu, 2052 }; 2053 2054 static void qede_update_pf_params(struct ecore_dev *edev) 2055 { 2056 struct ecore_pf_params pf_params; 2057 2058 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2059 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2060 qed_ops->common->update_pf_params(edev, &pf_params); 2061 } 2062 2063 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2064 { 2065 struct rte_pci_device *pci_dev; 2066 struct rte_pci_addr pci_addr; 2067 struct qede_dev *adapter; 2068 struct ecore_dev *edev; 2069 struct qed_dev_eth_info dev_info; 2070 struct qed_slowpath_params params; 2071 static bool do_once = true; 2072 uint8_t bulletin_change; 2073 uint8_t vf_mac[ETHER_ADDR_LEN]; 2074 uint8_t is_mac_forced; 2075 bool is_mac_exist; 2076 /* Fix up ecore debug level */ 2077 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2078 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2079 uint32_t max_mac_addrs; 2080 int rc; 2081 2082 /* Extract key data structures */ 2083 adapter = eth_dev->data->dev_private; 2084 edev = &adapter->edev; 2085 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2086 pci_addr = pci_dev->addr; 2087 2088 PMD_INIT_FUNC_TRACE(edev); 2089 2090 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2091 pci_addr.bus, pci_addr.devid, pci_addr.function, 2092 eth_dev->data->port_id); 2093 2094 eth_dev->rx_pkt_burst = qede_recv_pkts; 2095 eth_dev->tx_pkt_burst = qede_xmit_pkts; 2096 2097 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2098 DP_NOTICE(edev, false, 2099 "Skipping device init from secondary process\n"); 2100 return 0; 2101 } 2102 2103 rte_eth_copy_pci_info(eth_dev, pci_dev); 2104 2105 /* @DPDK */ 2106 edev->vendor_id = pci_dev->id.vendor_id; 2107 edev->device_id = pci_dev->id.device_id; 2108 2109 qed_ops = qed_get_eth_ops(); 2110 if (!qed_ops) { 2111 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2112 return -EINVAL; 2113 } 2114 2115 DP_INFO(edev, "Starting qede probe\n"); 2116 2117 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH, 2118 dp_module, dp_level, is_vf); 2119 2120 if (rc != 0) { 2121 DP_ERR(edev, "qede probe failed rc %d\n", rc); 2122 return -ENODEV; 2123 } 2124 2125 qede_update_pf_params(edev); 2126 2127 rte_intr_callback_register(&pci_dev->intr_handle, 2128 qede_interrupt_handler, (void *)eth_dev); 2129 2130 if (rte_intr_enable(&pci_dev->intr_handle)) { 2131 DP_ERR(edev, "rte_intr_enable() failed\n"); 2132 return -ENODEV; 2133 } 2134 2135 /* Start the Slowpath-process */ 2136 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 2137 params.int_mode = ECORE_INT_MODE_MSIX; 2138 params.drv_major = QEDE_PMD_VERSION_MAJOR; 2139 params.drv_minor = QEDE_PMD_VERSION_MINOR; 2140 params.drv_rev = QEDE_PMD_VERSION_REVISION; 2141 params.drv_eng = QEDE_PMD_VERSION_PATCH; 2142 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 2143 QEDE_PMD_DRV_VER_STR_SIZE); 2144 2145 /* For CMT mode device do periodic polling for slowpath events. 2146 * This is required since uio device uses only one MSI-x 2147 * interrupt vector but we need one for each engine. 2148 */ 2149 if (edev->num_hwfns > 1 && IS_PF(edev)) { 2150 rc = rte_eal_alarm_set(timer_period * US_PER_S, 2151 qede_poll_sp_sb_cb, 2152 (void *)eth_dev); 2153 if (rc != 0) { 2154 DP_ERR(edev, "Unable to start periodic" 2155 " timer rc %d\n", rc); 2156 return -EINVAL; 2157 } 2158 } 2159 2160 rc = qed_ops->common->slowpath_start(edev, ¶ms); 2161 if (rc) { 2162 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 2163 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2164 (void *)eth_dev); 2165 return -ENODEV; 2166 } 2167 2168 rc = qed_ops->fill_dev_info(edev, &dev_info); 2169 if (rc) { 2170 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 2171 qed_ops->common->slowpath_stop(edev); 2172 qed_ops->common->remove(edev); 2173 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2174 (void *)eth_dev); 2175 return -ENODEV; 2176 } 2177 2178 qede_alloc_etherdev(adapter, &dev_info); 2179 2180 adapter->ops->common->set_name(edev, edev->name); 2181 2182 if (!is_vf) 2183 adapter->dev_info.num_mac_filters = 2184 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 2185 ECORE_MAC); 2186 else 2187 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 2188 (uint32_t *)&adapter->dev_info.num_mac_filters); 2189 2190 /* Allocate memory for storing MAC addr */ 2191 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 2192 (ETHER_ADDR_LEN * 2193 adapter->dev_info.num_mac_filters), 2194 RTE_CACHE_LINE_SIZE); 2195 2196 if (eth_dev->data->mac_addrs == NULL) { 2197 DP_ERR(edev, "Failed to allocate MAC address\n"); 2198 qed_ops->common->slowpath_stop(edev); 2199 qed_ops->common->remove(edev); 2200 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2201 (void *)eth_dev); 2202 return -ENOMEM; 2203 } 2204 2205 if (!is_vf) { 2206 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 2207 hw_info.hw_mac_addr, 2208 ð_dev->data->mac_addrs[0]); 2209 ether_addr_copy(ð_dev->data->mac_addrs[0], 2210 &adapter->primary_mac); 2211 } else { 2212 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 2213 &bulletin_change); 2214 if (bulletin_change) { 2215 is_mac_exist = 2216 ecore_vf_bulletin_get_forced_mac( 2217 ECORE_LEADING_HWFN(edev), 2218 vf_mac, 2219 &is_mac_forced); 2220 if (is_mac_exist && is_mac_forced) { 2221 DP_INFO(edev, "VF macaddr received from PF\n"); 2222 ether_addr_copy((struct ether_addr *)&vf_mac, 2223 ð_dev->data->mac_addrs[0]); 2224 ether_addr_copy(ð_dev->data->mac_addrs[0], 2225 &adapter->primary_mac); 2226 } else { 2227 DP_NOTICE(edev, false, 2228 "No VF macaddr assigned\n"); 2229 } 2230 } 2231 } 2232 2233 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 2234 2235 if (do_once) { 2236 qede_print_adapter_info(adapter); 2237 do_once = false; 2238 } 2239 2240 adapter->state = QEDE_DEV_INIT; 2241 2242 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 2243 adapter->primary_mac.addr_bytes[0], 2244 adapter->primary_mac.addr_bytes[1], 2245 adapter->primary_mac.addr_bytes[2], 2246 adapter->primary_mac.addr_bytes[3], 2247 adapter->primary_mac.addr_bytes[4], 2248 adapter->primary_mac.addr_bytes[5]); 2249 2250 return rc; 2251 } 2252 2253 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 2254 { 2255 return qede_common_dev_init(eth_dev, 1); 2256 } 2257 2258 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 2259 { 2260 return qede_common_dev_init(eth_dev, 0); 2261 } 2262 2263 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 2264 { 2265 /* only uninitialize in the primary process */ 2266 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2267 return 0; 2268 2269 /* safe to close dev here */ 2270 qede_dev_close(eth_dev); 2271 2272 eth_dev->dev_ops = NULL; 2273 eth_dev->rx_pkt_burst = NULL; 2274 eth_dev->tx_pkt_burst = NULL; 2275 2276 if (eth_dev->data->mac_addrs) 2277 rte_free(eth_dev->data->mac_addrs); 2278 2279 eth_dev->data->mac_addrs = NULL; 2280 2281 return 0; 2282 } 2283 2284 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2285 { 2286 return qede_dev_common_uninit(eth_dev); 2287 } 2288 2289 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2290 { 2291 return qede_dev_common_uninit(eth_dev); 2292 } 2293 2294 static const struct rte_pci_id pci_id_qedevf_map[] = { 2295 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2296 { 2297 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 2298 }, 2299 { 2300 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 2301 }, 2302 { 2303 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 2304 }, 2305 {.vendor_id = 0,} 2306 }; 2307 2308 static const struct rte_pci_id pci_id_qede_map[] = { 2309 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2310 { 2311 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 2312 }, 2313 { 2314 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 2315 }, 2316 { 2317 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 2318 }, 2319 { 2320 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 2321 }, 2322 { 2323 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 2324 }, 2325 { 2326 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 2327 }, 2328 { 2329 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 2330 }, 2331 { 2332 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 2333 }, 2334 { 2335 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 2336 }, 2337 { 2338 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 2339 }, 2340 {.vendor_id = 0,} 2341 }; 2342 2343 static struct eth_driver rte_qedevf_pmd = { 2344 .pci_drv = { 2345 .id_table = pci_id_qedevf_map, 2346 .drv_flags = 2347 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2348 .probe = rte_eth_dev_pci_probe, 2349 .remove = rte_eth_dev_pci_remove, 2350 }, 2351 .eth_dev_init = qedevf_eth_dev_init, 2352 .eth_dev_uninit = qedevf_eth_dev_uninit, 2353 .dev_private_size = sizeof(struct qede_dev), 2354 }; 2355 2356 static struct eth_driver rte_qede_pmd = { 2357 .pci_drv = { 2358 .id_table = pci_id_qede_map, 2359 .drv_flags = 2360 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2361 .probe = rte_eth_dev_pci_probe, 2362 .remove = rte_eth_dev_pci_remove, 2363 }, 2364 .eth_dev_init = qede_eth_dev_init, 2365 .eth_dev_uninit = qede_eth_dev_uninit, 2366 .dev_private_size = sizeof(struct qede_dev), 2367 }; 2368 2369 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv); 2370 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 2371 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio"); 2372 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv); 2373 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 2374 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio"); 2375