1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 #include <rte_kvargs.h> 13 14 /* Globals */ 15 int qede_logtype_init; 16 int qede_logtype_driver; 17 18 static const struct qed_eth_ops *qed_ops; 19 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */ 20 21 /* VXLAN tunnel classification mapping */ 22 const struct _qede_udp_tunn_types { 23 uint16_t rte_filter_type; 24 enum ecore_filter_ucast_type qede_type; 25 enum ecore_tunn_clss qede_tunn_clss; 26 const char *string; 27 } qede_tunn_types[] = { 28 { 29 ETH_TUNNEL_FILTER_OMAC, 30 ECORE_FILTER_MAC, 31 ECORE_TUNN_CLSS_MAC_VLAN, 32 "outer-mac" 33 }, 34 { 35 ETH_TUNNEL_FILTER_TENID, 36 ECORE_FILTER_VNI, 37 ECORE_TUNN_CLSS_MAC_VNI, 38 "vni" 39 }, 40 { 41 ETH_TUNNEL_FILTER_IMAC, 42 ECORE_FILTER_INNER_MAC, 43 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 44 "inner-mac" 45 }, 46 { 47 ETH_TUNNEL_FILTER_IVLAN, 48 ECORE_FILTER_INNER_VLAN, 49 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 50 "inner-vlan" 51 }, 52 { 53 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 54 ECORE_FILTER_MAC_VNI_PAIR, 55 ECORE_TUNN_CLSS_MAC_VNI, 56 "outer-mac and vni" 57 }, 58 { 59 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 60 ECORE_FILTER_UNUSED, 61 MAX_ECORE_TUNN_CLSS, 62 "outer-mac and inner-mac" 63 }, 64 { 65 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 66 ECORE_FILTER_UNUSED, 67 MAX_ECORE_TUNN_CLSS, 68 "outer-mac and inner-vlan" 69 }, 70 { 71 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 72 ECORE_FILTER_INNER_MAC_VNI_PAIR, 73 ECORE_TUNN_CLSS_INNER_MAC_VNI, 74 "vni and inner-mac", 75 }, 76 { 77 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 78 ECORE_FILTER_UNUSED, 79 MAX_ECORE_TUNN_CLSS, 80 "vni and inner-vlan", 81 }, 82 { 83 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 84 ECORE_FILTER_INNER_PAIR, 85 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 86 "inner-mac and inner-vlan", 87 }, 88 { 89 ETH_TUNNEL_FILTER_OIP, 90 ECORE_FILTER_UNUSED, 91 MAX_ECORE_TUNN_CLSS, 92 "outer-IP" 93 }, 94 { 95 ETH_TUNNEL_FILTER_IIP, 96 ECORE_FILTER_UNUSED, 97 MAX_ECORE_TUNN_CLSS, 98 "inner-IP" 99 }, 100 { 101 RTE_TUNNEL_FILTER_IMAC_IVLAN, 102 ECORE_FILTER_UNUSED, 103 MAX_ECORE_TUNN_CLSS, 104 "IMAC_IVLAN" 105 }, 106 { 107 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 108 ECORE_FILTER_UNUSED, 109 MAX_ECORE_TUNN_CLSS, 110 "IMAC_IVLAN_TENID" 111 }, 112 { 113 RTE_TUNNEL_FILTER_IMAC_TENID, 114 ECORE_FILTER_UNUSED, 115 MAX_ECORE_TUNN_CLSS, 116 "IMAC_TENID" 117 }, 118 { 119 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 120 ECORE_FILTER_UNUSED, 121 MAX_ECORE_TUNN_CLSS, 122 "OMAC_TENID_IMAC" 123 }, 124 }; 125 126 struct rte_qede_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 uint64_t offset; 129 }; 130 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 132 {"rx_unicast_bytes", 133 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)}, 134 {"rx_multicast_bytes", 135 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)}, 136 {"rx_broadcast_bytes", 137 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)}, 138 {"rx_unicast_packets", 139 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)}, 140 {"rx_multicast_packets", 141 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)}, 142 {"rx_broadcast_packets", 143 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)}, 144 145 {"tx_unicast_bytes", 146 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)}, 147 {"tx_multicast_bytes", 148 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)}, 149 {"tx_broadcast_bytes", 150 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)}, 151 {"tx_unicast_packets", 152 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)}, 153 {"tx_multicast_packets", 154 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)}, 155 {"tx_broadcast_packets", 156 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)}, 157 158 {"rx_64_byte_packets", 159 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)}, 160 {"rx_65_to_127_byte_packets", 161 offsetof(struct ecore_eth_stats_common, 162 rx_65_to_127_byte_packets)}, 163 {"rx_128_to_255_byte_packets", 164 offsetof(struct ecore_eth_stats_common, 165 rx_128_to_255_byte_packets)}, 166 {"rx_256_to_511_byte_packets", 167 offsetof(struct ecore_eth_stats_common, 168 rx_256_to_511_byte_packets)}, 169 {"rx_512_to_1023_byte_packets", 170 offsetof(struct ecore_eth_stats_common, 171 rx_512_to_1023_byte_packets)}, 172 {"rx_1024_to_1518_byte_packets", 173 offsetof(struct ecore_eth_stats_common, 174 rx_1024_to_1518_byte_packets)}, 175 {"tx_64_byte_packets", 176 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)}, 177 {"tx_65_to_127_byte_packets", 178 offsetof(struct ecore_eth_stats_common, 179 tx_65_to_127_byte_packets)}, 180 {"tx_128_to_255_byte_packets", 181 offsetof(struct ecore_eth_stats_common, 182 tx_128_to_255_byte_packets)}, 183 {"tx_256_to_511_byte_packets", 184 offsetof(struct ecore_eth_stats_common, 185 tx_256_to_511_byte_packets)}, 186 {"tx_512_to_1023_byte_packets", 187 offsetof(struct ecore_eth_stats_common, 188 tx_512_to_1023_byte_packets)}, 189 {"tx_1024_to_1518_byte_packets", 190 offsetof(struct ecore_eth_stats_common, 191 tx_1024_to_1518_byte_packets)}, 192 193 {"rx_mac_crtl_frames", 194 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)}, 195 {"tx_mac_control_frames", 196 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)}, 197 {"rx_pause_frames", 198 offsetof(struct ecore_eth_stats_common, rx_pause_frames)}, 199 {"tx_pause_frames", 200 offsetof(struct ecore_eth_stats_common, tx_pause_frames)}, 201 {"rx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)}, 203 {"tx_priority_flow_control_frames", 204 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)}, 205 206 {"rx_crc_errors", 207 offsetof(struct ecore_eth_stats_common, rx_crc_errors)}, 208 {"rx_align_errors", 209 offsetof(struct ecore_eth_stats_common, rx_align_errors)}, 210 {"rx_carrier_errors", 211 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)}, 212 {"rx_oversize_packet_errors", 213 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)}, 214 {"rx_jabber_errors", 215 offsetof(struct ecore_eth_stats_common, rx_jabbers)}, 216 {"rx_undersize_packet_errors", 217 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)}, 218 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)}, 219 {"rx_host_buffer_not_available", 220 offsetof(struct ecore_eth_stats_common, no_buff_discards)}, 221 /* Number of packets discarded because they are bigger than MTU */ 222 {"rx_packet_too_big_discards", 223 offsetof(struct ecore_eth_stats_common, 224 packet_too_big_discard)}, 225 {"rx_ttl_zero_discards", 226 offsetof(struct ecore_eth_stats_common, ttl0_discard)}, 227 {"rx_multi_function_tag_filter_discards", 228 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)}, 229 {"rx_mac_filter_discards", 230 offsetof(struct ecore_eth_stats_common, mac_filter_discards)}, 231 {"rx_hw_buffer_truncates", 232 offsetof(struct ecore_eth_stats_common, brb_truncates)}, 233 {"rx_hw_buffer_discards", 234 offsetof(struct ecore_eth_stats_common, brb_discards)}, 235 {"tx_error_drop_packets", 236 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)}, 237 238 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)}, 239 {"rx_mac_unicast_packets", 240 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)}, 241 {"rx_mac_multicast_packets", 242 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)}, 243 {"rx_mac_broadcast_packets", 244 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)}, 245 {"rx_mac_frames_ok", 246 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)}, 247 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)}, 248 {"tx_mac_unicast_packets", 249 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)}, 250 {"tx_mac_multicast_packets", 251 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)}, 252 {"tx_mac_broadcast_packets", 253 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)}, 254 255 {"lro_coalesced_packets", 256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)}, 257 {"lro_coalesced_events", 258 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)}, 259 {"lro_aborts_num", 260 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)}, 261 {"lro_not_coalesced_packets", 262 offsetof(struct ecore_eth_stats_common, 263 tpa_not_coalesced_pkts)}, 264 {"lro_coalesced_bytes", 265 offsetof(struct ecore_eth_stats_common, 266 tpa_coalesced_bytes)}, 267 }; 268 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = { 270 {"rx_1519_to_1522_byte_packets", 271 offsetof(struct ecore_eth_stats, bb) + 272 offsetof(struct ecore_eth_stats_bb, 273 rx_1519_to_1522_byte_packets)}, 274 {"rx_1519_to_2047_byte_packets", 275 offsetof(struct ecore_eth_stats, bb) + 276 offsetof(struct ecore_eth_stats_bb, 277 rx_1519_to_2047_byte_packets)}, 278 {"rx_2048_to_4095_byte_packets", 279 offsetof(struct ecore_eth_stats, bb) + 280 offsetof(struct ecore_eth_stats_bb, 281 rx_2048_to_4095_byte_packets)}, 282 {"rx_4096_to_9216_byte_packets", 283 offsetof(struct ecore_eth_stats, bb) + 284 offsetof(struct ecore_eth_stats_bb, 285 rx_4096_to_9216_byte_packets)}, 286 {"rx_9217_to_16383_byte_packets", 287 offsetof(struct ecore_eth_stats, bb) + 288 offsetof(struct ecore_eth_stats_bb, 289 rx_9217_to_16383_byte_packets)}, 290 291 {"tx_1519_to_2047_byte_packets", 292 offsetof(struct ecore_eth_stats, bb) + 293 offsetof(struct ecore_eth_stats_bb, 294 tx_1519_to_2047_byte_packets)}, 295 {"tx_2048_to_4095_byte_packets", 296 offsetof(struct ecore_eth_stats, bb) + 297 offsetof(struct ecore_eth_stats_bb, 298 tx_2048_to_4095_byte_packets)}, 299 {"tx_4096_to_9216_byte_packets", 300 offsetof(struct ecore_eth_stats, bb) + 301 offsetof(struct ecore_eth_stats_bb, 302 tx_4096_to_9216_byte_packets)}, 303 {"tx_9217_to_16383_byte_packets", 304 offsetof(struct ecore_eth_stats, bb) + 305 offsetof(struct ecore_eth_stats_bb, 306 tx_9217_to_16383_byte_packets)}, 307 308 {"tx_lpi_entry_count", 309 offsetof(struct ecore_eth_stats, bb) + 310 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)}, 311 {"tx_total_collisions", 312 offsetof(struct ecore_eth_stats, bb) + 313 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)}, 314 }; 315 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = { 317 {"rx_1519_to_max_byte_packets", 318 offsetof(struct ecore_eth_stats, ah) + 319 offsetof(struct ecore_eth_stats_ah, 320 rx_1519_to_max_byte_packets)}, 321 {"tx_1519_to_max_byte_packets", 322 offsetof(struct ecore_eth_stats, ah) + 323 offsetof(struct ecore_eth_stats_ah, 324 tx_1519_to_max_byte_packets)}, 325 }; 326 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 328 {"rx_q_segments", 329 offsetof(struct qede_rx_queue, rx_segs)}, 330 {"rx_q_hw_errors", 331 offsetof(struct qede_rx_queue, rx_hw_errors)}, 332 {"rx_q_allocation_errors", 333 offsetof(struct qede_rx_queue, rx_alloc_errors)} 334 }; 335 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 337 { 338 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 339 } 340 341 static void 342 qede_interrupt_handler(void *param) 343 { 344 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 345 struct qede_dev *qdev = eth_dev->data->dev_private; 346 struct ecore_dev *edev = &qdev->edev; 347 348 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 349 if (rte_intr_enable(eth_dev->intr_handle)) 350 DP_ERR(edev, "rte_intr_enable failed\n"); 351 } 352 353 static void 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 355 { 356 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 357 qdev->ops = qed_ops; 358 } 359 360 static void qede_print_adapter_info(struct qede_dev *qdev) 361 { 362 struct ecore_dev *edev = &qdev->edev; 363 struct qed_dev_info *info = &qdev->dev_info.common; 364 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 365 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 366 367 DP_INFO(edev, "*********************************\n"); 368 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 369 DP_INFO(edev, " Chip details : %s %c%d\n", 370 ECORE_IS_BB(edev) ? "BB" : "AH", 371 'A' + edev->chip_rev, 372 (int)edev->chip_metal); 373 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 374 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 375 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 376 ver_str, QEDE_PMD_VERSION); 377 DP_INFO(edev, " Driver version : %s\n", drv_ver); 378 DP_INFO(edev, " Firmware version : %s\n", ver_str); 379 380 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 381 "%d.%d.%d.%d", 382 (info->mfw_rev >> 24) & 0xff, 383 (info->mfw_rev >> 16) & 0xff, 384 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 385 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 386 DP_INFO(edev, " Firmware file : %s\n", fw_file); 387 DP_INFO(edev, "*********************************\n"); 388 } 389 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats) 391 { 392 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 393 unsigned int i = 0, j = 0, qid; 394 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 395 struct qede_tx_queue *txq; 396 397 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n"); 398 399 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 400 RTE_ETHDEV_QUEUE_STAT_CNTRS); 401 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 402 RTE_ETHDEV_QUEUE_STAT_CNTRS); 403 404 for_each_rss(qid) { 405 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 406 offsetof(struct qede_rx_queue, rcv_pkts), 0, 407 sizeof(uint64_t)); 408 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 409 offsetof(struct qede_rx_queue, rx_hw_errors), 0, 410 sizeof(uint64_t)); 411 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 412 offsetof(struct qede_rx_queue, rx_alloc_errors), 0, 413 sizeof(uint64_t)); 414 415 if (xstats) 416 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++) 417 OSAL_MEMSET((((char *) 418 (qdev->fp_array[qid].rxq)) + 419 qede_rxq_xstats_strings[j].offset), 420 0, 421 sizeof(uint64_t)); 422 423 i++; 424 if (i == rxq_stat_cntrs) 425 break; 426 } 427 428 i = 0; 429 430 for_each_tss(qid) { 431 txq = qdev->fp_array[qid].txq; 432 433 OSAL_MEMSET((uint64_t *)(uintptr_t) 434 (((uint64_t)(uintptr_t)(txq)) + 435 offsetof(struct qede_tx_queue, xmit_pkts)), 0, 436 sizeof(uint64_t)); 437 438 i++; 439 if (i == txq_stat_cntrs) 440 break; 441 } 442 } 443 444 static int 445 qede_stop_vport(struct ecore_dev *edev) 446 { 447 struct ecore_hwfn *p_hwfn; 448 uint8_t vport_id; 449 int rc; 450 int i; 451 452 vport_id = 0; 453 for_each_hwfn(edev, i) { 454 p_hwfn = &edev->hwfns[i]; 455 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 456 vport_id); 457 if (rc != ECORE_SUCCESS) { 458 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 459 return rc; 460 } 461 } 462 463 DP_INFO(edev, "vport stopped\n"); 464 465 return 0; 466 } 467 468 static int 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 470 { 471 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 472 struct ecore_sp_vport_start_params params; 473 struct ecore_hwfn *p_hwfn; 474 int rc; 475 int i; 476 477 if (qdev->vport_started) 478 qede_stop_vport(edev); 479 480 memset(¶ms, 0, sizeof(params)); 481 params.vport_id = 0; 482 params.mtu = mtu; 483 /* @DPDK - Disable FW placement */ 484 params.zero_placement_offset = 1; 485 for_each_hwfn(edev, i) { 486 p_hwfn = &edev->hwfns[i]; 487 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 488 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 489 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 490 if (rc != ECORE_SUCCESS) { 491 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 492 return rc; 493 } 494 } 495 ecore_reset_vport_stats(edev); 496 qdev->vport_started = true; 497 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 498 499 return 0; 500 } 501 502 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching" 503 #define QEDE_VF_TX_SWITCHING "vf_tx_switching" 504 505 /* Activate or deactivate vport via vport-update */ 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 507 { 508 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 509 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 510 struct ecore_sp_vport_update_params params; 511 struct ecore_hwfn *p_hwfn; 512 uint8_t i; 513 int rc = -1; 514 515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 516 params.vport_id = 0; 517 params.update_vport_active_rx_flg = 1; 518 params.update_vport_active_tx_flg = 1; 519 params.vport_active_rx_flg = flg; 520 params.vport_active_tx_flg = flg; 521 if (~qdev->enable_tx_switching & flg) { 522 params.update_tx_switching_flg = 1; 523 params.tx_switching_flg = !flg; 524 } 525 for_each_hwfn(edev, i) { 526 p_hwfn = &edev->hwfns[i]; 527 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 528 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 529 ECORE_SPQ_MODE_EBLOCK, NULL); 530 if (rc != ECORE_SUCCESS) { 531 DP_ERR(edev, "Failed to update vport\n"); 532 break; 533 } 534 } 535 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated"); 536 537 return rc; 538 } 539 540 static void 541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 542 uint16_t mtu, bool enable) 543 { 544 /* Enable LRO in split mode */ 545 sge_tpa_params->tpa_ipv4_en_flg = enable; 546 sge_tpa_params->tpa_ipv6_en_flg = enable; 547 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable; 548 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable; 549 /* set if tpa enable changes */ 550 sge_tpa_params->update_tpa_en_flg = 1; 551 /* set if tpa parameters should be handled */ 552 sge_tpa_params->update_tpa_param_flg = enable; 553 554 sge_tpa_params->max_buffers_per_cqe = 20; 555 /* Enable TPA in split mode. In this mode each TPA segment 556 * starts on the new BD, so there is one BD per segment. 557 */ 558 sge_tpa_params->tpa_pkt_split_flg = 1; 559 sge_tpa_params->tpa_hdr_data_split_flg = 0; 560 sge_tpa_params->tpa_gro_consistent_flg = 0; 561 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 562 sge_tpa_params->tpa_max_size = 0x7FFF; 563 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 564 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 565 } 566 567 /* Enable/disable LRO via vport-update */ 568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 569 { 570 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 572 struct ecore_sp_vport_update_params params; 573 struct ecore_sge_tpa_params tpa_params; 574 struct ecore_hwfn *p_hwfn; 575 int rc; 576 int i; 577 578 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 579 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 580 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 581 params.vport_id = 0; 582 params.sge_tpa_params = &tpa_params; 583 for_each_hwfn(edev, i) { 584 p_hwfn = &edev->hwfns[i]; 585 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 586 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 587 ECORE_SPQ_MODE_EBLOCK, NULL); 588 if (rc != ECORE_SUCCESS) { 589 DP_ERR(edev, "Failed to update LRO\n"); 590 return -1; 591 } 592 } 593 qdev->enable_lro = flg; 594 eth_dev->data->lro = flg; 595 596 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 597 598 return 0; 599 } 600 601 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 602 { 603 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 604 ucast->is_rx_filter = true; 605 ucast->is_tx_filter = true; 606 /* ucast->assert_on_error = true; - For debug */ 607 } 608 609 static int 610 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 611 enum qed_filter_rx_mode_type type) 612 { 613 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 614 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 615 struct ecore_filter_accept_flags flags; 616 617 memset(&flags, 0, sizeof(flags)); 618 619 flags.update_rx_mode_config = 1; 620 flags.update_tx_mode_config = 1; 621 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 622 ECORE_ACCEPT_MCAST_MATCHED | 623 ECORE_ACCEPT_BCAST; 624 625 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 626 ECORE_ACCEPT_MCAST_MATCHED | 627 ECORE_ACCEPT_BCAST; 628 629 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 630 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 631 if (IS_VF(edev)) { 632 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 633 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n"); 634 } 635 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 636 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 637 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC | 638 QED_FILTER_RX_MODE_TYPE_PROMISC)) { 639 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED | 640 ECORE_ACCEPT_MCAST_UNMATCHED; 641 } 642 643 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 644 ECORE_SPQ_MODE_CB, NULL); 645 } 646 647 static int 648 qede_tunnel_update(struct qede_dev *qdev, 649 struct ecore_tunnel_info *tunn_info) 650 { 651 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 652 enum _ecore_status_t rc = ECORE_INVAL; 653 struct ecore_hwfn *p_hwfn; 654 struct ecore_ptt *p_ptt; 655 int i; 656 657 for_each_hwfn(edev, i) { 658 p_hwfn = &edev->hwfns[i]; 659 if (IS_PF(edev)) { 660 p_ptt = ecore_ptt_acquire(p_hwfn); 661 if (!p_ptt) { 662 DP_ERR(p_hwfn, "Can't acquire PTT\n"); 663 return -EAGAIN; 664 } 665 } else { 666 p_ptt = NULL; 667 } 668 669 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, 670 tunn_info, ECORE_SPQ_MODE_CB, NULL); 671 if (IS_PF(edev)) 672 ecore_ptt_release(p_hwfn, p_ptt); 673 674 if (rc != ECORE_SUCCESS) 675 break; 676 } 677 678 return rc; 679 } 680 681 static int 682 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 683 bool enable) 684 { 685 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 686 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 687 enum _ecore_status_t rc = ECORE_INVAL; 688 struct ecore_tunnel_info tunn; 689 690 if (qdev->vxlan.enable == enable) 691 return ECORE_SUCCESS; 692 693 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 694 tunn.vxlan.b_update_mode = true; 695 tunn.vxlan.b_mode_enabled = enable; 696 tunn.b_update_rx_cls = true; 697 tunn.b_update_tx_cls = true; 698 tunn.vxlan.tun_cls = clss; 699 700 tunn.vxlan_port.b_update_port = true; 701 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0; 702 703 rc = qede_tunnel_update(qdev, &tunn); 704 if (rc == ECORE_SUCCESS) { 705 qdev->vxlan.enable = enable; 706 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0; 707 DP_INFO(edev, "vxlan is %s, UDP port = %d\n", 708 enable ? "enabled" : "disabled", qdev->vxlan.udp_port); 709 } else { 710 DP_ERR(edev, "Failed to update tunn_clss %u\n", 711 tunn.vxlan.tun_cls); 712 } 713 714 return rc; 715 } 716 717 static int 718 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 719 bool enable) 720 { 721 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 722 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 723 enum _ecore_status_t rc = ECORE_INVAL; 724 struct ecore_tunnel_info tunn; 725 726 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 727 tunn.l2_geneve.b_update_mode = true; 728 tunn.l2_geneve.b_mode_enabled = enable; 729 tunn.ip_geneve.b_update_mode = true; 730 tunn.ip_geneve.b_mode_enabled = enable; 731 tunn.l2_geneve.tun_cls = clss; 732 tunn.ip_geneve.tun_cls = clss; 733 tunn.b_update_rx_cls = true; 734 tunn.b_update_tx_cls = true; 735 736 tunn.geneve_port.b_update_port = true; 737 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0; 738 739 rc = qede_tunnel_update(qdev, &tunn); 740 if (rc == ECORE_SUCCESS) { 741 qdev->geneve.enable = enable; 742 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0; 743 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n", 744 enable ? "enabled" : "disabled", qdev->geneve.udp_port); 745 } else { 746 DP_ERR(edev, "Failed to update tunn_clss %u\n", 747 clss); 748 } 749 750 return rc; 751 } 752 753 static int 754 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 755 bool enable) 756 { 757 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 758 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 759 enum _ecore_status_t rc = ECORE_INVAL; 760 struct ecore_tunnel_info tunn; 761 762 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 763 tunn.ip_gre.b_update_mode = true; 764 tunn.ip_gre.b_mode_enabled = enable; 765 tunn.ip_gre.tun_cls = clss; 766 tunn.ip_gre.tun_cls = clss; 767 tunn.b_update_rx_cls = true; 768 tunn.b_update_tx_cls = true; 769 770 rc = qede_tunnel_update(qdev, &tunn); 771 if (rc == ECORE_SUCCESS) { 772 qdev->ipgre.enable = enable; 773 DP_INFO(edev, "IPGRE is %s\n", 774 enable ? "enabled" : "disabled"); 775 } else { 776 DP_ERR(edev, "Failed to update tunn_clss %u\n", 777 clss); 778 } 779 780 return rc; 781 } 782 783 static int 784 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 785 enum rte_eth_tunnel_type tunn_type, bool enable) 786 { 787 int rc = -EINVAL; 788 789 switch (tunn_type) { 790 case RTE_TUNNEL_TYPE_VXLAN: 791 rc = qede_vxlan_enable(eth_dev, clss, enable); 792 break; 793 case RTE_TUNNEL_TYPE_GENEVE: 794 rc = qede_geneve_enable(eth_dev, clss, enable); 795 break; 796 case RTE_TUNNEL_TYPE_IP_IN_GRE: 797 rc = qede_ipgre_enable(eth_dev, clss, enable); 798 break; 799 default: 800 rc = -EINVAL; 801 break; 802 } 803 804 return rc; 805 } 806 807 static int 808 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 809 bool add) 810 { 811 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 812 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 813 struct qede_ucast_entry *tmp = NULL; 814 struct qede_ucast_entry *u; 815 struct ether_addr *mac_addr; 816 817 mac_addr = (struct ether_addr *)ucast->mac; 818 if (add) { 819 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 820 if ((memcmp(mac_addr, &tmp->mac, 821 ETHER_ADDR_LEN) == 0) && 822 ucast->vni == tmp->vni && 823 ucast->vlan == tmp->vlan) { 824 DP_INFO(edev, "Unicast MAC is already added" 825 " with vlan = %u, vni = %u\n", 826 ucast->vlan, ucast->vni); 827 return 0; 828 } 829 } 830 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 831 RTE_CACHE_LINE_SIZE); 832 if (!u) { 833 DP_ERR(edev, "Did not allocate memory for ucast\n"); 834 return -ENOMEM; 835 } 836 ether_addr_copy(mac_addr, &u->mac); 837 u->vlan = ucast->vlan; 838 u->vni = ucast->vni; 839 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 840 qdev->num_uc_addr++; 841 } else { 842 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 843 if ((memcmp(mac_addr, &tmp->mac, 844 ETHER_ADDR_LEN) == 0) && 845 ucast->vlan == tmp->vlan && 846 ucast->vni == tmp->vni) 847 break; 848 } 849 if (tmp == NULL) { 850 DP_INFO(edev, "Unicast MAC is not found\n"); 851 return -EINVAL; 852 } 853 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 854 qdev->num_uc_addr--; 855 } 856 857 return 0; 858 } 859 860 static int 861 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs, 862 uint32_t mc_addrs_num) 863 { 864 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 865 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 866 struct ecore_filter_mcast mcast; 867 struct qede_mcast_entry *m = NULL; 868 uint8_t i; 869 int rc; 870 871 for (i = 0; i < mc_addrs_num; i++) { 872 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 873 RTE_CACHE_LINE_SIZE); 874 if (!m) { 875 DP_ERR(edev, "Did not allocate memory for mcast\n"); 876 return -ENOMEM; 877 } 878 ether_addr_copy(&mc_addrs[i], &m->mac); 879 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 880 } 881 memset(&mcast, 0, sizeof(mcast)); 882 mcast.num_mc_addrs = mc_addrs_num; 883 mcast.opcode = ECORE_FILTER_ADD; 884 for (i = 0; i < mc_addrs_num; i++) 885 ether_addr_copy(&mc_addrs[i], (struct ether_addr *) 886 &mcast.mac[i]); 887 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 888 if (rc != ECORE_SUCCESS) { 889 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc); 890 return -1; 891 } 892 893 return 0; 894 } 895 896 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev) 897 { 898 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 899 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 900 struct qede_mcast_entry *tmp = NULL; 901 struct ecore_filter_mcast mcast; 902 int j; 903 int rc; 904 905 memset(&mcast, 0, sizeof(mcast)); 906 mcast.num_mc_addrs = qdev->num_mc_addr; 907 mcast.opcode = ECORE_FILTER_REMOVE; 908 j = 0; 909 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 910 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]); 911 j++; 912 } 913 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 914 if (rc != ECORE_SUCCESS) { 915 DP_ERR(edev, "Failed to delete multicast filter\n"); 916 return -1; 917 } 918 /* Init the list */ 919 while (!SLIST_EMPTY(&qdev->mc_list_head)) { 920 tmp = SLIST_FIRST(&qdev->mc_list_head); 921 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list); 922 } 923 SLIST_INIT(&qdev->mc_list_head); 924 925 return 0; 926 } 927 928 static enum _ecore_status_t 929 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 930 bool add) 931 { 932 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 933 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 934 enum _ecore_status_t rc = ECORE_INVAL; 935 936 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) { 937 DP_ERR(edev, "Ucast filter table limit exceeded," 938 " Please enable promisc mode\n"); 939 return ECORE_INVAL; 940 } 941 942 rc = qede_ucast_filter(eth_dev, ucast, add); 943 if (rc == 0) 944 rc = ecore_filter_ucast_cmd(edev, ucast, 945 ECORE_SPQ_MODE_CB, NULL); 946 if (rc != ECORE_SUCCESS) 947 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 948 rc, add); 949 950 return rc; 951 } 952 953 static int 954 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 955 __rte_unused uint32_t index, __rte_unused uint32_t pool) 956 { 957 struct ecore_filter_ucast ucast; 958 int re; 959 960 qede_set_ucast_cmn_params(&ucast); 961 ucast.type = ECORE_FILTER_MAC; 962 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 963 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 964 return re; 965 } 966 967 static void 968 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 969 { 970 struct qede_dev *qdev = eth_dev->data->dev_private; 971 struct ecore_dev *edev = &qdev->edev; 972 struct ecore_filter_ucast ucast; 973 974 PMD_INIT_FUNC_TRACE(edev); 975 976 if (index >= qdev->dev_info.num_mac_filters) { 977 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 978 index, qdev->dev_info.num_mac_filters); 979 return; 980 } 981 982 qede_set_ucast_cmn_params(&ucast); 983 ucast.opcode = ECORE_FILTER_REMOVE; 984 ucast.type = ECORE_FILTER_MAC; 985 986 /* Use the index maintained by rte */ 987 ether_addr_copy(ð_dev->data->mac_addrs[index], 988 (struct ether_addr *)&ucast.mac); 989 990 qede_mac_int_ops(eth_dev, &ucast, false); 991 } 992 993 static int 994 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 995 { 996 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 997 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 998 999 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 1000 mac_addr->addr_bytes)) { 1001 DP_ERR(edev, "Setting MAC address is not allowed\n"); 1002 return -EPERM; 1003 } 1004 1005 qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 1006 return 0; 1007 } 1008 1009 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 1010 { 1011 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1012 struct ecore_sp_vport_update_params params; 1013 struct ecore_hwfn *p_hwfn; 1014 uint8_t i; 1015 int rc; 1016 1017 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1018 params.vport_id = 0; 1019 params.update_accept_any_vlan_flg = 1; 1020 params.accept_any_vlan = flg; 1021 for_each_hwfn(edev, i) { 1022 p_hwfn = &edev->hwfns[i]; 1023 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1024 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1025 ECORE_SPQ_MODE_EBLOCK, NULL); 1026 if (rc != ECORE_SUCCESS) { 1027 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 1028 return; 1029 } 1030 } 1031 1032 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 1033 } 1034 1035 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 1036 { 1037 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1038 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1039 struct ecore_sp_vport_update_params params; 1040 struct ecore_hwfn *p_hwfn; 1041 uint8_t i; 1042 int rc; 1043 1044 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1045 params.vport_id = 0; 1046 params.update_inner_vlan_removal_flg = 1; 1047 params.inner_vlan_removal_flg = flg; 1048 for_each_hwfn(edev, i) { 1049 p_hwfn = &edev->hwfns[i]; 1050 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1051 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1052 ECORE_SPQ_MODE_EBLOCK, NULL); 1053 if (rc != ECORE_SUCCESS) { 1054 DP_ERR(edev, "Failed to update vport\n"); 1055 return -1; 1056 } 1057 } 1058 1059 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 1060 return 0; 1061 } 1062 1063 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 1064 uint16_t vlan_id, int on) 1065 { 1066 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1067 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1068 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 1069 struct qede_vlan_entry *tmp = NULL; 1070 struct qede_vlan_entry *vlan; 1071 struct ecore_filter_ucast ucast; 1072 int rc; 1073 1074 if (on) { 1075 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 1076 DP_ERR(edev, "Reached max VLAN filter limit" 1077 " enabling accept_any_vlan\n"); 1078 qede_config_accept_any_vlan(qdev, true); 1079 return 0; 1080 } 1081 1082 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1083 if (tmp->vid == vlan_id) { 1084 DP_INFO(edev, "VLAN %u already configured\n", 1085 vlan_id); 1086 return 0; 1087 } 1088 } 1089 1090 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 1091 RTE_CACHE_LINE_SIZE); 1092 1093 if (!vlan) { 1094 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 1095 return -ENOMEM; 1096 } 1097 1098 qede_set_ucast_cmn_params(&ucast); 1099 ucast.opcode = ECORE_FILTER_ADD; 1100 ucast.type = ECORE_FILTER_VLAN; 1101 ucast.vlan = vlan_id; 1102 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1103 NULL); 1104 if (rc != 0) { 1105 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 1106 rc); 1107 rte_free(vlan); 1108 } else { 1109 vlan->vid = vlan_id; 1110 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 1111 qdev->configured_vlans++; 1112 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 1113 vlan_id, qdev->configured_vlans); 1114 } 1115 } else { 1116 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1117 if (tmp->vid == vlan_id) 1118 break; 1119 } 1120 1121 if (!tmp) { 1122 if (qdev->configured_vlans == 0) { 1123 DP_INFO(edev, 1124 "No VLAN filters configured yet\n"); 1125 return 0; 1126 } 1127 1128 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 1129 return -EINVAL; 1130 } 1131 1132 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 1133 1134 qede_set_ucast_cmn_params(&ucast); 1135 ucast.opcode = ECORE_FILTER_REMOVE; 1136 ucast.type = ECORE_FILTER_VLAN; 1137 ucast.vlan = vlan_id; 1138 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1139 NULL); 1140 if (rc != 0) { 1141 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 1142 vlan_id, rc); 1143 } else { 1144 qdev->configured_vlans--; 1145 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 1146 vlan_id, qdev->configured_vlans); 1147 } 1148 } 1149 1150 return rc; 1151 } 1152 1153 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 1154 { 1155 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1156 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1157 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1158 1159 if (mask & ETH_VLAN_STRIP_MASK) { 1160 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1161 (void)qede_vlan_stripping(eth_dev, 1); 1162 else 1163 (void)qede_vlan_stripping(eth_dev, 0); 1164 } 1165 1166 if (mask & ETH_VLAN_FILTER_MASK) { 1167 /* VLAN filtering kicks in when a VLAN is added */ 1168 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 1169 qede_vlan_filter_set(eth_dev, 0, 1); 1170 } else { 1171 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 1172 DP_ERR(edev, 1173 " Please remove existing VLAN filters" 1174 " before disabling VLAN filtering\n"); 1175 /* Signal app that VLAN filtering is still 1176 * enabled 1177 */ 1178 eth_dev->data->dev_conf.rxmode.offloads |= 1179 DEV_RX_OFFLOAD_VLAN_FILTER; 1180 } else { 1181 qede_vlan_filter_set(eth_dev, 0, 0); 1182 } 1183 } 1184 } 1185 1186 if (mask & ETH_VLAN_EXTEND_MASK) 1187 DP_ERR(edev, "Extend VLAN not supported\n"); 1188 1189 qdev->vlan_offload_mask = mask; 1190 1191 DP_INFO(edev, "VLAN offload mask %d\n", mask); 1192 1193 return 0; 1194 } 1195 1196 static void qede_prandom_bytes(uint32_t *buff) 1197 { 1198 uint8_t i; 1199 1200 srand((unsigned int)time(NULL)); 1201 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 1202 buff[i] = rand(); 1203 } 1204 1205 int qede_config_rss(struct rte_eth_dev *eth_dev) 1206 { 1207 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1208 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1209 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 1210 struct rte_eth_rss_reta_entry64 reta_conf[2]; 1211 struct rte_eth_rss_conf rss_conf; 1212 uint32_t i, id, pos, q; 1213 1214 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 1215 if (!rss_conf.rss_key) { 1216 DP_INFO(edev, "Applying driver default key\n"); 1217 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1218 qede_prandom_bytes(&def_rss_key[0]); 1219 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 1220 } 1221 1222 /* Configure RSS hash */ 1223 if (qede_rss_hash_update(eth_dev, &rss_conf)) 1224 return -EINVAL; 1225 1226 /* Configure default RETA */ 1227 memset(reta_conf, 0, sizeof(reta_conf)); 1228 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 1229 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 1230 1231 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1232 id = i / RTE_RETA_GROUP_SIZE; 1233 pos = i % RTE_RETA_GROUP_SIZE; 1234 q = i % QEDE_RSS_COUNT(qdev); 1235 reta_conf[id].reta[pos] = q; 1236 } 1237 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1238 ECORE_RSS_IND_TABLE_SIZE)) 1239 return -EINVAL; 1240 1241 return 0; 1242 } 1243 1244 static void qede_fastpath_start(struct ecore_dev *edev) 1245 { 1246 struct ecore_hwfn *p_hwfn; 1247 int i; 1248 1249 for_each_hwfn(edev, i) { 1250 p_hwfn = &edev->hwfns[i]; 1251 ecore_hw_start_fastpath(p_hwfn); 1252 } 1253 } 1254 1255 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1256 { 1257 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1258 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1259 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1260 1261 PMD_INIT_FUNC_TRACE(edev); 1262 1263 /* Update MTU only if it has changed */ 1264 if (eth_dev->data->mtu != qdev->mtu) { 1265 if (qede_update_mtu(eth_dev, qdev->mtu)) 1266 goto err; 1267 } 1268 1269 /* Configure TPA parameters */ 1270 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1271 if (qede_enable_tpa(eth_dev, true)) 1272 return -EINVAL; 1273 /* Enable scatter mode for LRO */ 1274 if (!eth_dev->data->scattered_rx) 1275 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER; 1276 } 1277 1278 /* Start queues */ 1279 if (qede_start_queues(eth_dev)) 1280 goto err; 1281 1282 if (IS_PF(edev)) 1283 qede_reset_queue_stats(qdev, true); 1284 1285 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1286 * enabling RSS. Hence RSS configuration is deferred upto this point. 1287 * Also, we would like to retain similar behavior in PF case, so we 1288 * don't do PF/VF specific check here. 1289 */ 1290 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 1291 if (qede_config_rss(eth_dev)) 1292 goto err; 1293 1294 /* Enable vport*/ 1295 if (qede_activate_vport(eth_dev, true)) 1296 goto err; 1297 1298 /* Update link status */ 1299 qede_link_update(eth_dev, 0); 1300 1301 /* Start/resume traffic */ 1302 qede_fastpath_start(edev); 1303 1304 DP_INFO(edev, "Device started\n"); 1305 1306 return 0; 1307 err: 1308 DP_ERR(edev, "Device start fails\n"); 1309 return -1; /* common error code is < 0 */ 1310 } 1311 1312 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1313 { 1314 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1315 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1316 1317 PMD_INIT_FUNC_TRACE(edev); 1318 1319 /* Disable vport */ 1320 if (qede_activate_vport(eth_dev, false)) 1321 return; 1322 1323 if (qdev->enable_lro) 1324 qede_enable_tpa(eth_dev, false); 1325 1326 /* Stop queues */ 1327 qede_stop_queues(eth_dev); 1328 1329 /* Disable traffic */ 1330 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1331 1332 if (IS_PF(edev)) 1333 qede_mac_addr_remove(eth_dev, 0); 1334 1335 DP_INFO(edev, "Device is stopped\n"); 1336 } 1337 1338 const char *valid_args[] = { 1339 QEDE_NPAR_TX_SWITCHING, 1340 QEDE_VF_TX_SWITCHING, 1341 NULL, 1342 }; 1343 1344 static int qede_args_check(const char *key, const char *val, void *opaque) 1345 { 1346 unsigned long tmp; 1347 int ret = 0; 1348 struct rte_eth_dev *eth_dev = opaque; 1349 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1350 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1351 1352 errno = 0; 1353 tmp = strtoul(val, NULL, 0); 1354 if (errno) { 1355 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val); 1356 return errno; 1357 } 1358 1359 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) || 1360 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) { 1361 qdev->enable_tx_switching = !!tmp; 1362 DP_INFO(edev, "Disabling %s tx-switching\n", 1363 strcmp(QEDE_NPAR_TX_SWITCHING, key) ? 1364 "VF" : "NPAR"); 1365 } 1366 1367 return ret; 1368 } 1369 1370 static int qede_args(struct rte_eth_dev *eth_dev) 1371 { 1372 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1373 struct rte_kvargs *kvlist; 1374 struct rte_devargs *devargs; 1375 int ret; 1376 int i; 1377 1378 devargs = pci_dev->device.devargs; 1379 if (!devargs) 1380 return 0; /* return success */ 1381 1382 kvlist = rte_kvargs_parse(devargs->args, valid_args); 1383 if (kvlist == NULL) 1384 return -EINVAL; 1385 1386 /* Process parameters. */ 1387 for (i = 0; (valid_args[i] != NULL); ++i) { 1388 if (rte_kvargs_count(kvlist, valid_args[i])) { 1389 ret = rte_kvargs_process(kvlist, valid_args[i], 1390 qede_args_check, eth_dev); 1391 if (ret != ECORE_SUCCESS) { 1392 rte_kvargs_free(kvlist); 1393 return ret; 1394 } 1395 } 1396 } 1397 rte_kvargs_free(kvlist); 1398 1399 return 0; 1400 } 1401 1402 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1403 { 1404 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1405 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1406 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1407 int ret; 1408 1409 PMD_INIT_FUNC_TRACE(edev); 1410 1411 /* Check requirements for 100G mode */ 1412 if (ECORE_IS_CMT(edev)) { 1413 if (eth_dev->data->nb_rx_queues < 2 || 1414 eth_dev->data->nb_tx_queues < 2) { 1415 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 1416 return -EINVAL; 1417 } 1418 1419 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 1420 (eth_dev->data->nb_tx_queues % 2 != 0)) { 1421 DP_ERR(edev, 1422 "100G mode needs even no. of RX/TX queues\n"); 1423 return -EINVAL; 1424 } 1425 } 1426 1427 /* We need to have min 1 RX queue.There is no min check in 1428 * rte_eth_dev_configure(), so we are checking it here. 1429 */ 1430 if (eth_dev->data->nb_rx_queues == 0) { 1431 DP_ERR(edev, "Minimum one RX queue is required\n"); 1432 return -EINVAL; 1433 } 1434 1435 /* Enable Tx switching by default */ 1436 qdev->enable_tx_switching = 1; 1437 1438 /* Parse devargs and fix up rxmode */ 1439 if (qede_args(eth_dev)) 1440 DP_NOTICE(edev, false, 1441 "Invalid devargs supplied, requested change will not take effect\n"); 1442 1443 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || 1444 rxmode->mq_mode == ETH_MQ_RX_RSS)) { 1445 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1446 return -ENOTSUP; 1447 } 1448 /* Flow director mode check */ 1449 if (qede_check_fdir_support(eth_dev)) 1450 return -ENOTSUP; 1451 1452 qede_dealloc_fp_resc(eth_dev); 1453 qdev->num_tx_queues = eth_dev->data->nb_tx_queues; 1454 qdev->num_rx_queues = eth_dev->data->nb_rx_queues; 1455 if (qede_alloc_fp_resc(qdev)) 1456 return -ENOMEM; 1457 1458 /* If jumbo enabled adjust MTU */ 1459 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 1460 eth_dev->data->mtu = 1461 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1462 ETHER_HDR_LEN - ETHER_CRC_LEN; 1463 1464 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) 1465 eth_dev->data->scattered_rx = 1; 1466 1467 if (qede_start_vport(qdev, eth_dev->data->mtu)) 1468 return -1; 1469 1470 qdev->mtu = eth_dev->data->mtu; 1471 1472 /* Enable VLAN offloads by default */ 1473 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1474 ETH_VLAN_FILTER_MASK | 1475 ETH_VLAN_EXTEND_MASK); 1476 if (ret) 1477 return ret; 1478 1479 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1480 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); 1481 1482 return 0; 1483 } 1484 1485 /* Info about HW descriptor ring limitations */ 1486 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1487 .nb_max = 0x8000, /* 32K */ 1488 .nb_min = 128, 1489 .nb_align = 128 /* lowest common multiple */ 1490 }; 1491 1492 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1493 .nb_max = 0x8000, /* 32K */ 1494 .nb_min = 256, 1495 .nb_align = 256, 1496 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1497 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1498 }; 1499 1500 static void 1501 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1502 struct rte_eth_dev_info *dev_info) 1503 { 1504 struct qede_dev *qdev = eth_dev->data->dev_private; 1505 struct ecore_dev *edev = &qdev->edev; 1506 struct qed_link_output link; 1507 uint32_t speed_cap = 0; 1508 1509 PMD_INIT_FUNC_TRACE(edev); 1510 1511 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1512 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1513 dev_info->rx_desc_lim = qede_rx_desc_lim; 1514 dev_info->tx_desc_lim = qede_tx_desc_lim; 1515 1516 if (IS_PF(edev)) 1517 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1518 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1519 else 1520 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1521 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1522 dev_info->max_tx_queues = dev_info->max_rx_queues; 1523 1524 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1525 dev_info->max_vfs = 0; 1526 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1527 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1528 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1529 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 1530 DEV_RX_OFFLOAD_UDP_CKSUM | 1531 DEV_RX_OFFLOAD_TCP_CKSUM | 1532 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1533 DEV_RX_OFFLOAD_TCP_LRO | 1534 DEV_RX_OFFLOAD_CRC_STRIP | 1535 DEV_RX_OFFLOAD_SCATTER | 1536 DEV_RX_OFFLOAD_JUMBO_FRAME | 1537 DEV_RX_OFFLOAD_VLAN_FILTER | 1538 DEV_RX_OFFLOAD_VLAN_STRIP); 1539 dev_info->rx_queue_offload_capa = 0; 1540 1541 /* TX offloads are on a per-packet basis, so it is applicable 1542 * to both at port and queue levels. 1543 */ 1544 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1545 DEV_TX_OFFLOAD_IPV4_CKSUM | 1546 DEV_TX_OFFLOAD_UDP_CKSUM | 1547 DEV_TX_OFFLOAD_TCP_CKSUM | 1548 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1549 DEV_TX_OFFLOAD_QINQ_INSERT | 1550 DEV_TX_OFFLOAD_MULTI_SEGS | 1551 DEV_TX_OFFLOAD_TCP_TSO | 1552 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 1553 DEV_TX_OFFLOAD_GENEVE_TNL_TSO); 1554 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa; 1555 1556 dev_info->default_txconf = (struct rte_eth_txconf) { 1557 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS, 1558 }; 1559 1560 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1561 /* Packets are always dropped if no descriptors are available */ 1562 .rx_drop_en = 1, 1563 /* The below RX offloads are always enabled */ 1564 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP | 1565 DEV_RX_OFFLOAD_IPV4_CKSUM | 1566 DEV_RX_OFFLOAD_TCP_CKSUM | 1567 DEV_RX_OFFLOAD_UDP_CKSUM), 1568 }; 1569 1570 memset(&link, 0, sizeof(struct qed_link_output)); 1571 qdev->ops->common->get_link(edev, &link); 1572 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1573 speed_cap |= ETH_LINK_SPEED_1G; 1574 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1575 speed_cap |= ETH_LINK_SPEED_10G; 1576 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1577 speed_cap |= ETH_LINK_SPEED_25G; 1578 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1579 speed_cap |= ETH_LINK_SPEED_40G; 1580 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1581 speed_cap |= ETH_LINK_SPEED_50G; 1582 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1583 speed_cap |= ETH_LINK_SPEED_100G; 1584 dev_info->speed_capa = speed_cap; 1585 } 1586 1587 /* return 0 means link status changed, -1 means not changed */ 1588 int 1589 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1590 { 1591 struct qede_dev *qdev = eth_dev->data->dev_private; 1592 struct ecore_dev *edev = &qdev->edev; 1593 struct qed_link_output q_link; 1594 struct rte_eth_link link; 1595 uint16_t link_duplex; 1596 1597 memset(&q_link, 0, sizeof(q_link)); 1598 memset(&link, 0, sizeof(link)); 1599 1600 qdev->ops->common->get_link(edev, &q_link); 1601 1602 /* Link Speed */ 1603 link.link_speed = q_link.speed; 1604 1605 /* Link Mode */ 1606 switch (q_link.duplex) { 1607 case QEDE_DUPLEX_HALF: 1608 link_duplex = ETH_LINK_HALF_DUPLEX; 1609 break; 1610 case QEDE_DUPLEX_FULL: 1611 link_duplex = ETH_LINK_FULL_DUPLEX; 1612 break; 1613 case QEDE_DUPLEX_UNKNOWN: 1614 default: 1615 link_duplex = -1; 1616 } 1617 link.link_duplex = link_duplex; 1618 1619 /* Link Status */ 1620 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 1621 1622 /* AN */ 1623 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1624 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1625 1626 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1627 link.link_speed, link.link_duplex, 1628 link.link_autoneg, link.link_status); 1629 1630 return rte_eth_linkstatus_set(eth_dev, &link); 1631 } 1632 1633 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1634 { 1635 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1636 struct qede_dev *qdev = eth_dev->data->dev_private; 1637 struct ecore_dev *edev = &qdev->edev; 1638 1639 PMD_INIT_FUNC_TRACE(edev); 1640 #endif 1641 1642 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1643 1644 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1645 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1646 1647 qed_configure_filter_rx_mode(eth_dev, type); 1648 } 1649 1650 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1651 { 1652 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1653 struct qede_dev *qdev = eth_dev->data->dev_private; 1654 struct ecore_dev *edev = &qdev->edev; 1655 1656 PMD_INIT_FUNC_TRACE(edev); 1657 #endif 1658 1659 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1660 qed_configure_filter_rx_mode(eth_dev, 1661 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1662 else 1663 qed_configure_filter_rx_mode(eth_dev, 1664 QED_FILTER_RX_MODE_TYPE_REGULAR); 1665 } 1666 1667 static void qede_poll_sp_sb_cb(void *param) 1668 { 1669 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1670 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1671 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1672 int rc; 1673 1674 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1675 qede_interrupt_action(&edev->hwfns[1]); 1676 1677 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 1678 qede_poll_sp_sb_cb, 1679 (void *)eth_dev); 1680 if (rc != 0) { 1681 DP_ERR(edev, "Unable to start periodic" 1682 " timer rc %d\n", rc); 1683 assert(false && "Unable to start periodic timer"); 1684 } 1685 } 1686 1687 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1688 { 1689 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1690 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1691 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1692 1693 PMD_INIT_FUNC_TRACE(edev); 1694 1695 /* dev_stop() shall cleanup fp resources in hw but without releasing 1696 * dma memories and sw structures so that dev_start() can be called 1697 * by the app without reconfiguration. However, in dev_close() we 1698 * can release all the resources and device can be brought up newly 1699 */ 1700 if (eth_dev->data->dev_started) 1701 qede_dev_stop(eth_dev); 1702 1703 qede_stop_vport(edev); 1704 qdev->vport_started = false; 1705 qede_fdir_dealloc_resc(eth_dev); 1706 qede_dealloc_fp_resc(eth_dev); 1707 1708 eth_dev->data->nb_rx_queues = 0; 1709 eth_dev->data->nb_tx_queues = 0; 1710 1711 /* Bring the link down */ 1712 qede_dev_set_link_state(eth_dev, false); 1713 qdev->ops->common->slowpath_stop(edev); 1714 qdev->ops->common->remove(edev); 1715 rte_intr_disable(&pci_dev->intr_handle); 1716 rte_intr_callback_unregister(&pci_dev->intr_handle, 1717 qede_interrupt_handler, (void *)eth_dev); 1718 if (ECORE_IS_CMT(edev)) 1719 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1720 } 1721 1722 static int 1723 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1724 { 1725 struct qede_dev *qdev = eth_dev->data->dev_private; 1726 struct ecore_dev *edev = &qdev->edev; 1727 struct ecore_eth_stats stats; 1728 unsigned int i = 0, j = 0, qid; 1729 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1730 struct qede_tx_queue *txq; 1731 1732 ecore_get_vport_stats(edev, &stats); 1733 1734 /* RX Stats */ 1735 eth_stats->ipackets = stats.common.rx_ucast_pkts + 1736 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts; 1737 1738 eth_stats->ibytes = stats.common.rx_ucast_bytes + 1739 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes; 1740 1741 eth_stats->ierrors = stats.common.rx_crc_errors + 1742 stats.common.rx_align_errors + 1743 stats.common.rx_carrier_errors + 1744 stats.common.rx_oversize_packets + 1745 stats.common.rx_jabbers + stats.common.rx_undersize_packets; 1746 1747 eth_stats->rx_nombuf = stats.common.no_buff_discards; 1748 1749 eth_stats->imissed = stats.common.mftag_filter_discards + 1750 stats.common.mac_filter_discards + 1751 stats.common.no_buff_discards + 1752 stats.common.brb_truncates + stats.common.brb_discards; 1753 1754 /* TX stats */ 1755 eth_stats->opackets = stats.common.tx_ucast_pkts + 1756 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts; 1757 1758 eth_stats->obytes = stats.common.tx_ucast_bytes + 1759 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes; 1760 1761 eth_stats->oerrors = stats.common.tx_err_drop_pkts; 1762 1763 /* Queue stats */ 1764 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1765 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1766 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1767 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1768 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) || 1769 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev))) 1770 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1771 "Not all the queue stats will be displayed. Set" 1772 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1773 " appropriately and retry.\n"); 1774 1775 for_each_rss(qid) { 1776 eth_stats->q_ipackets[i] = 1777 *(uint64_t *)( 1778 ((char *)(qdev->fp_array[qid].rxq)) + 1779 offsetof(struct qede_rx_queue, 1780 rcv_pkts)); 1781 eth_stats->q_errors[i] = 1782 *(uint64_t *)( 1783 ((char *)(qdev->fp_array[qid].rxq)) + 1784 offsetof(struct qede_rx_queue, 1785 rx_hw_errors)) + 1786 *(uint64_t *)( 1787 ((char *)(qdev->fp_array[qid].rxq)) + 1788 offsetof(struct qede_rx_queue, 1789 rx_alloc_errors)); 1790 i++; 1791 if (i == rxq_stat_cntrs) 1792 break; 1793 } 1794 1795 for_each_tss(qid) { 1796 txq = qdev->fp_array[qid].txq; 1797 eth_stats->q_opackets[j] = 1798 *((uint64_t *)(uintptr_t) 1799 (((uint64_t)(uintptr_t)(txq)) + 1800 offsetof(struct qede_tx_queue, 1801 xmit_pkts))); 1802 j++; 1803 if (j == txq_stat_cntrs) 1804 break; 1805 } 1806 1807 return 0; 1808 } 1809 1810 static unsigned 1811 qede_get_xstats_count(struct qede_dev *qdev) { 1812 if (ECORE_IS_BB(&qdev->edev)) 1813 return RTE_DIM(qede_xstats_strings) + 1814 RTE_DIM(qede_bb_xstats_strings) + 1815 (RTE_DIM(qede_rxq_xstats_strings) * 1816 RTE_MIN(QEDE_RSS_COUNT(qdev), 1817 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1818 else 1819 return RTE_DIM(qede_xstats_strings) + 1820 RTE_DIM(qede_ah_xstats_strings) + 1821 (RTE_DIM(qede_rxq_xstats_strings) * 1822 RTE_MIN(QEDE_RSS_COUNT(qdev), 1823 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1824 } 1825 1826 static int 1827 qede_get_xstats_names(struct rte_eth_dev *dev, 1828 struct rte_eth_xstat_name *xstats_names, 1829 __rte_unused unsigned int limit) 1830 { 1831 struct qede_dev *qdev = dev->data->dev_private; 1832 struct ecore_dev *edev = &qdev->edev; 1833 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1834 unsigned int i, qid, stat_idx = 0; 1835 unsigned int rxq_stat_cntrs; 1836 1837 if (xstats_names != NULL) { 1838 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1839 snprintf(xstats_names[stat_idx].name, 1840 sizeof(xstats_names[stat_idx].name), 1841 "%s", 1842 qede_xstats_strings[i].name); 1843 stat_idx++; 1844 } 1845 1846 if (ECORE_IS_BB(edev)) { 1847 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1848 snprintf(xstats_names[stat_idx].name, 1849 sizeof(xstats_names[stat_idx].name), 1850 "%s", 1851 qede_bb_xstats_strings[i].name); 1852 stat_idx++; 1853 } 1854 } else { 1855 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1856 snprintf(xstats_names[stat_idx].name, 1857 sizeof(xstats_names[stat_idx].name), 1858 "%s", 1859 qede_ah_xstats_strings[i].name); 1860 stat_idx++; 1861 } 1862 } 1863 1864 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1865 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1866 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1867 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1868 snprintf(xstats_names[stat_idx].name, 1869 sizeof(xstats_names[stat_idx].name), 1870 "%.4s%d%s", 1871 qede_rxq_xstats_strings[i].name, qid, 1872 qede_rxq_xstats_strings[i].name + 4); 1873 stat_idx++; 1874 } 1875 } 1876 } 1877 1878 return stat_cnt; 1879 } 1880 1881 static int 1882 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1883 unsigned int n) 1884 { 1885 struct qede_dev *qdev = dev->data->dev_private; 1886 struct ecore_dev *edev = &qdev->edev; 1887 struct ecore_eth_stats stats; 1888 const unsigned int num = qede_get_xstats_count(qdev); 1889 unsigned int i, qid, stat_idx = 0; 1890 unsigned int rxq_stat_cntrs; 1891 1892 if (n < num) 1893 return num; 1894 1895 ecore_get_vport_stats(edev, &stats); 1896 1897 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1898 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1899 qede_xstats_strings[i].offset); 1900 xstats[stat_idx].id = stat_idx; 1901 stat_idx++; 1902 } 1903 1904 if (ECORE_IS_BB(edev)) { 1905 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1906 xstats[stat_idx].value = 1907 *(uint64_t *)(((char *)&stats) + 1908 qede_bb_xstats_strings[i].offset); 1909 xstats[stat_idx].id = stat_idx; 1910 stat_idx++; 1911 } 1912 } else { 1913 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1914 xstats[stat_idx].value = 1915 *(uint64_t *)(((char *)&stats) + 1916 qede_ah_xstats_strings[i].offset); 1917 xstats[stat_idx].id = stat_idx; 1918 stat_idx++; 1919 } 1920 } 1921 1922 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1923 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1924 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1925 for_each_rss(qid) { 1926 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1927 xstats[stat_idx].value = *(uint64_t *)( 1928 ((char *)(qdev->fp_array[qid].rxq)) + 1929 qede_rxq_xstats_strings[i].offset); 1930 xstats[stat_idx].id = stat_idx; 1931 stat_idx++; 1932 } 1933 } 1934 } 1935 1936 return stat_idx; 1937 } 1938 1939 static void 1940 qede_reset_xstats(struct rte_eth_dev *dev) 1941 { 1942 struct qede_dev *qdev = dev->data->dev_private; 1943 struct ecore_dev *edev = &qdev->edev; 1944 1945 ecore_reset_vport_stats(edev); 1946 qede_reset_queue_stats(qdev, true); 1947 } 1948 1949 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1950 { 1951 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1952 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1953 struct qed_link_params link_params; 1954 int rc; 1955 1956 DP_INFO(edev, "setting link state %d\n", link_up); 1957 memset(&link_params, 0, sizeof(link_params)); 1958 link_params.link_up = link_up; 1959 rc = qdev->ops->common->set_link(edev, &link_params); 1960 if (rc != ECORE_SUCCESS) 1961 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1962 1963 return rc; 1964 } 1965 1966 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1967 { 1968 return qede_dev_set_link_state(eth_dev, true); 1969 } 1970 1971 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1972 { 1973 return qede_dev_set_link_state(eth_dev, false); 1974 } 1975 1976 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1977 { 1978 struct qede_dev *qdev = eth_dev->data->dev_private; 1979 struct ecore_dev *edev = &qdev->edev; 1980 1981 ecore_reset_vport_stats(edev); 1982 qede_reset_queue_stats(qdev, false); 1983 } 1984 1985 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1986 { 1987 enum qed_filter_rx_mode_type type = 1988 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1989 1990 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1991 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1992 1993 qed_configure_filter_rx_mode(eth_dev, type); 1994 } 1995 1996 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1997 { 1998 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1999 qed_configure_filter_rx_mode(eth_dev, 2000 QED_FILTER_RX_MODE_TYPE_PROMISC); 2001 else 2002 qed_configure_filter_rx_mode(eth_dev, 2003 QED_FILTER_RX_MODE_TYPE_REGULAR); 2004 } 2005 2006 static int 2007 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs, 2008 uint32_t mc_addrs_num) 2009 { 2010 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2011 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2012 uint8_t i; 2013 2014 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) { 2015 DP_ERR(edev, "Reached max multicast filters limit," 2016 "Please enable multicast promisc mode\n"); 2017 return -ENOSPC; 2018 } 2019 2020 for (i = 0; i < mc_addrs_num; i++) { 2021 if (!is_multicast_ether_addr(&mc_addrs[i])) { 2022 DP_ERR(edev, "Not a valid multicast MAC\n"); 2023 return -EINVAL; 2024 } 2025 } 2026 2027 /* Flush all existing entries */ 2028 if (qede_del_mcast_filters(eth_dev)) 2029 return -1; 2030 2031 /* Set new mcast list */ 2032 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num); 2033 } 2034 2035 /* Update MTU via vport-update without doing port restart. 2036 * The vport must be deactivated before calling this API. 2037 */ 2038 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 2039 { 2040 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2041 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2042 struct ecore_hwfn *p_hwfn; 2043 int rc; 2044 int i; 2045 2046 if (IS_PF(edev)) { 2047 struct ecore_sp_vport_update_params params; 2048 2049 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 2050 params.vport_id = 0; 2051 params.mtu = mtu; 2052 params.vport_id = 0; 2053 for_each_hwfn(edev, i) { 2054 p_hwfn = &edev->hwfns[i]; 2055 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2056 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 2057 ECORE_SPQ_MODE_EBLOCK, NULL); 2058 if (rc != ECORE_SUCCESS) 2059 goto err; 2060 } 2061 } else { 2062 for_each_hwfn(edev, i) { 2063 p_hwfn = &edev->hwfns[i]; 2064 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu); 2065 if (rc == ECORE_INVAL) { 2066 DP_INFO(edev, "VF MTU Update TLV not supported\n"); 2067 /* Recreate vport */ 2068 rc = qede_start_vport(qdev, mtu); 2069 if (rc != ECORE_SUCCESS) 2070 goto err; 2071 2072 /* Restore config lost due to vport stop */ 2073 qede_mac_addr_set(eth_dev, &qdev->primary_mac); 2074 2075 if (eth_dev->data->promiscuous) 2076 qede_promiscuous_enable(eth_dev); 2077 else 2078 qede_promiscuous_disable(eth_dev); 2079 2080 if (eth_dev->data->all_multicast) 2081 qede_allmulticast_enable(eth_dev); 2082 else 2083 qede_allmulticast_disable(eth_dev); 2084 2085 qede_vlan_offload_set(eth_dev, 2086 qdev->vlan_offload_mask); 2087 } else if (rc != ECORE_SUCCESS) { 2088 goto err; 2089 } 2090 } 2091 } 2092 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu); 2093 2094 return 0; 2095 2096 err: 2097 DP_ERR(edev, "Failed to update MTU\n"); 2098 return -1; 2099 } 2100 2101 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 2102 struct rte_eth_fc_conf *fc_conf) 2103 { 2104 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2105 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2106 struct qed_link_output current_link; 2107 struct qed_link_params params; 2108 2109 memset(¤t_link, 0, sizeof(current_link)); 2110 qdev->ops->common->get_link(edev, ¤t_link); 2111 2112 memset(¶ms, 0, sizeof(params)); 2113 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 2114 if (fc_conf->autoneg) { 2115 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 2116 DP_ERR(edev, "Autoneg not supported\n"); 2117 return -EINVAL; 2118 } 2119 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 2120 } 2121 2122 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 2123 if (fc_conf->mode == RTE_FC_FULL) 2124 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 2125 QED_LINK_PAUSE_RX_ENABLE); 2126 if (fc_conf->mode == RTE_FC_TX_PAUSE) 2127 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 2128 if (fc_conf->mode == RTE_FC_RX_PAUSE) 2129 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 2130 2131 params.link_up = true; 2132 (void)qdev->ops->common->set_link(edev, ¶ms); 2133 2134 return 0; 2135 } 2136 2137 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 2138 struct rte_eth_fc_conf *fc_conf) 2139 { 2140 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2141 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2142 struct qed_link_output current_link; 2143 2144 memset(¤t_link, 0, sizeof(current_link)); 2145 qdev->ops->common->get_link(edev, ¤t_link); 2146 2147 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 2148 fc_conf->autoneg = true; 2149 2150 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 2151 QED_LINK_PAUSE_TX_ENABLE)) 2152 fc_conf->mode = RTE_FC_FULL; 2153 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 2154 fc_conf->mode = RTE_FC_RX_PAUSE; 2155 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 2156 fc_conf->mode = RTE_FC_TX_PAUSE; 2157 else 2158 fc_conf->mode = RTE_FC_NONE; 2159 2160 return 0; 2161 } 2162 2163 static const uint32_t * 2164 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 2165 { 2166 static const uint32_t ptypes[] = { 2167 RTE_PTYPE_L2_ETHER, 2168 RTE_PTYPE_L2_ETHER_VLAN, 2169 RTE_PTYPE_L3_IPV4, 2170 RTE_PTYPE_L3_IPV6, 2171 RTE_PTYPE_L4_TCP, 2172 RTE_PTYPE_L4_UDP, 2173 RTE_PTYPE_TUNNEL_VXLAN, 2174 RTE_PTYPE_L4_FRAG, 2175 RTE_PTYPE_TUNNEL_GENEVE, 2176 RTE_PTYPE_TUNNEL_GRE, 2177 /* Inner */ 2178 RTE_PTYPE_INNER_L2_ETHER, 2179 RTE_PTYPE_INNER_L2_ETHER_VLAN, 2180 RTE_PTYPE_INNER_L3_IPV4, 2181 RTE_PTYPE_INNER_L3_IPV6, 2182 RTE_PTYPE_INNER_L4_TCP, 2183 RTE_PTYPE_INNER_L4_UDP, 2184 RTE_PTYPE_INNER_L4_FRAG, 2185 RTE_PTYPE_UNKNOWN 2186 }; 2187 2188 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 2189 return ptypes; 2190 2191 return NULL; 2192 } 2193 2194 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 2195 { 2196 *rss_caps = 0; 2197 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 2198 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 2199 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 2200 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 2201 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 2202 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 2203 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 2204 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 2205 } 2206 2207 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 2208 struct rte_eth_rss_conf *rss_conf) 2209 { 2210 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2211 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2212 struct ecore_sp_vport_update_params vport_update_params; 2213 struct ecore_rss_params rss_params; 2214 struct ecore_hwfn *p_hwfn; 2215 uint32_t *key = (uint32_t *)rss_conf->rss_key; 2216 uint64_t hf = rss_conf->rss_hf; 2217 uint8_t len = rss_conf->rss_key_len; 2218 uint8_t idx; 2219 uint8_t i; 2220 int rc; 2221 2222 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2223 memset(&rss_params, 0, sizeof(rss_params)); 2224 2225 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 2226 (unsigned long)hf, len, key); 2227 2228 if (hf != 0) { 2229 /* Enabling RSS */ 2230 DP_INFO(edev, "Enabling rss\n"); 2231 2232 /* RSS caps */ 2233 qede_init_rss_caps(&rss_params.rss_caps, hf); 2234 rss_params.update_rss_capabilities = 1; 2235 2236 /* RSS hash key */ 2237 if (key) { 2238 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 2239 DP_ERR(edev, "RSS key length exceeds limit\n"); 2240 return -EINVAL; 2241 } 2242 DP_INFO(edev, "Applying user supplied hash key\n"); 2243 rss_params.update_rss_key = 1; 2244 memcpy(&rss_params.rss_key, key, len); 2245 } 2246 rss_params.rss_enable = 1; 2247 } 2248 2249 rss_params.update_rss_config = 1; 2250 /* tbl_size has to be set with capabilities */ 2251 rss_params.rss_table_size_log = 7; 2252 vport_update_params.vport_id = 0; 2253 /* pass the L2 handles instead of qids */ 2254 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 2255 idx = i % QEDE_RSS_COUNT(qdev); 2256 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 2257 } 2258 vport_update_params.rss_params = &rss_params; 2259 2260 for_each_hwfn(edev, i) { 2261 p_hwfn = &edev->hwfns[i]; 2262 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2263 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2264 ECORE_SPQ_MODE_EBLOCK, NULL); 2265 if (rc) { 2266 DP_ERR(edev, "vport-update for RSS failed\n"); 2267 return rc; 2268 } 2269 } 2270 qdev->rss_enable = rss_params.rss_enable; 2271 2272 /* Update local structure for hash query */ 2273 qdev->rss_conf.rss_hf = hf; 2274 qdev->rss_conf.rss_key_len = len; 2275 if (qdev->rss_enable) { 2276 if (qdev->rss_conf.rss_key == NULL) { 2277 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 2278 if (qdev->rss_conf.rss_key == NULL) { 2279 DP_ERR(edev, "No memory to store RSS key\n"); 2280 return -ENOMEM; 2281 } 2282 } 2283 if (key && len) { 2284 DP_INFO(edev, "Storing RSS key\n"); 2285 memcpy(qdev->rss_conf.rss_key, key, len); 2286 } 2287 } else if (!qdev->rss_enable && len == 0) { 2288 if (qdev->rss_conf.rss_key) { 2289 free(qdev->rss_conf.rss_key); 2290 qdev->rss_conf.rss_key = NULL; 2291 DP_INFO(edev, "Free RSS key\n"); 2292 } 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 2299 struct rte_eth_rss_conf *rss_conf) 2300 { 2301 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2302 2303 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 2304 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 2305 2306 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 2307 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 2308 rss_conf->rss_key_len); 2309 return 0; 2310 } 2311 2312 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev, 2313 struct ecore_rss_params *rss) 2314 { 2315 int i, fn; 2316 bool rss_mode = 1; /* enable */ 2317 struct ecore_queue_cid *cid; 2318 struct ecore_rss_params *t_rss; 2319 2320 /* In regular scenario, we'd simply need to take input handlers. 2321 * But in CMT, we'd have to split the handlers according to the 2322 * engine they were configured on. We'd then have to understand 2323 * whether RSS is really required, since 2-queues on CMT doesn't 2324 * require RSS. 2325 */ 2326 2327 /* CMT should be round-robin */ 2328 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 2329 cid = rss->rss_ind_table[i]; 2330 2331 if (cid->p_owner == ECORE_LEADING_HWFN(edev)) 2332 t_rss = &rss[0]; 2333 else 2334 t_rss = &rss[1]; 2335 2336 t_rss->rss_ind_table[i / edev->num_hwfns] = cid; 2337 } 2338 2339 t_rss = &rss[1]; 2340 t_rss->update_rss_ind_table = 1; 2341 t_rss->rss_table_size_log = 7; 2342 t_rss->update_rss_config = 1; 2343 2344 /* Make sure RSS is actually required */ 2345 for_each_hwfn(edev, fn) { 2346 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns; 2347 i++) { 2348 if (rss[fn].rss_ind_table[i] != 2349 rss[fn].rss_ind_table[0]) 2350 break; 2351 } 2352 2353 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) { 2354 DP_INFO(edev, 2355 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2356 rss_mode = 0; 2357 goto out; 2358 } 2359 } 2360 2361 out: 2362 t_rss->rss_enable = rss_mode; 2363 2364 return rss_mode; 2365 } 2366 2367 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 2368 struct rte_eth_rss_reta_entry64 *reta_conf, 2369 uint16_t reta_size) 2370 { 2371 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2372 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2373 struct ecore_sp_vport_update_params vport_update_params; 2374 struct ecore_rss_params *params; 2375 struct ecore_hwfn *p_hwfn; 2376 uint16_t i, idx, shift; 2377 uint8_t entry; 2378 int rc = 0; 2379 2380 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2381 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 2382 reta_size); 2383 return -EINVAL; 2384 } 2385 2386 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2387 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns, 2388 RTE_CACHE_LINE_SIZE); 2389 if (params == NULL) { 2390 DP_ERR(edev, "failed to allocate memory\n"); 2391 return -ENOMEM; 2392 } 2393 2394 for (i = 0; i < reta_size; i++) { 2395 idx = i / RTE_RETA_GROUP_SIZE; 2396 shift = i % RTE_RETA_GROUP_SIZE; 2397 if (reta_conf[idx].mask & (1ULL << shift)) { 2398 entry = reta_conf[idx].reta[shift]; 2399 /* Pass rxq handles to ecore */ 2400 params->rss_ind_table[i] = 2401 qdev->fp_array[entry].rxq->handle; 2402 /* Update the local copy for RETA query command */ 2403 qdev->rss_ind_table[i] = entry; 2404 } 2405 } 2406 2407 params->update_rss_ind_table = 1; 2408 params->rss_table_size_log = 7; 2409 params->update_rss_config = 1; 2410 2411 /* Fix up RETA for CMT mode device */ 2412 if (ECORE_IS_CMT(edev)) 2413 qdev->rss_enable = qede_update_rss_parm_cmt(edev, 2414 params); 2415 vport_update_params.vport_id = 0; 2416 /* Use the current value of rss_enable */ 2417 params->rss_enable = qdev->rss_enable; 2418 vport_update_params.rss_params = params; 2419 2420 for_each_hwfn(edev, i) { 2421 p_hwfn = &edev->hwfns[i]; 2422 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2423 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2424 ECORE_SPQ_MODE_EBLOCK, NULL); 2425 if (rc) { 2426 DP_ERR(edev, "vport-update for RSS failed\n"); 2427 goto out; 2428 } 2429 } 2430 2431 out: 2432 rte_free(params); 2433 return rc; 2434 } 2435 2436 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 2437 struct rte_eth_rss_reta_entry64 *reta_conf, 2438 uint16_t reta_size) 2439 { 2440 struct qede_dev *qdev = eth_dev->data->dev_private; 2441 struct ecore_dev *edev = &qdev->edev; 2442 uint16_t i, idx, shift; 2443 uint8_t entry; 2444 2445 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2446 DP_ERR(edev, "reta_size %d is not supported\n", 2447 reta_size); 2448 return -EINVAL; 2449 } 2450 2451 for (i = 0; i < reta_size; i++) { 2452 idx = i / RTE_RETA_GROUP_SIZE; 2453 shift = i % RTE_RETA_GROUP_SIZE; 2454 if (reta_conf[idx].mask & (1ULL << shift)) { 2455 entry = qdev->rss_ind_table[i]; 2456 reta_conf[idx].reta[shift] = entry; 2457 } 2458 } 2459 2460 return 0; 2461 } 2462 2463 2464 2465 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 2466 { 2467 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 2468 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2469 struct rte_eth_dev_info dev_info = {0}; 2470 struct qede_fastpath *fp; 2471 uint32_t max_rx_pkt_len; 2472 uint32_t frame_size; 2473 uint16_t rx_buf_size; 2474 uint16_t bufsz; 2475 bool restart = false; 2476 int i; 2477 2478 PMD_INIT_FUNC_TRACE(edev); 2479 qede_dev_info_get(dev, &dev_info); 2480 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2481 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD; 2482 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { 2483 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n", 2484 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN - 2485 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD); 2486 return -EINVAL; 2487 } 2488 if (!dev->data->scattered_rx && 2489 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2490 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2491 dev->data->min_rx_buf_size); 2492 return -EINVAL; 2493 } 2494 /* Temporarily replace I/O functions with dummy ones. It cannot 2495 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 2496 */ 2497 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 2498 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 2499 if (dev->data->dev_started) { 2500 dev->data->dev_started = 0; 2501 qede_dev_stop(dev); 2502 restart = true; 2503 } else { 2504 if (IS_PF(edev)) 2505 qede_mac_addr_remove(dev, 0); 2506 } 2507 rte_delay_ms(1000); 2508 qdev->mtu = mtu; 2509 2510 /* Fix up RX buf size for all queues of the port */ 2511 for_each_rss(i) { 2512 fp = &qdev->fp_array[i]; 2513 if (fp->rxq != NULL) { 2514 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2515 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2516 if (dev->data->scattered_rx) 2517 rx_buf_size = bufsz + ETHER_HDR_LEN + 2518 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD; 2519 else 2520 rx_buf_size = frame_size; 2521 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); 2522 fp->rxq->rx_buf_size = rx_buf_size; 2523 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size); 2524 } 2525 } 2526 if (max_rx_pkt_len > ETHER_MAX_LEN) 2527 dev->data->dev_conf.rxmode.jumbo_frame = 1; 2528 else 2529 dev->data->dev_conf.rxmode.jumbo_frame = 0; 2530 2531 if (!dev->data->dev_started && restart) { 2532 qede_dev_start(dev); 2533 dev->data->dev_started = 1; 2534 } 2535 2536 /* update max frame size */ 2537 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len; 2538 /* Reassign back */ 2539 dev->rx_pkt_burst = qede_recv_pkts; 2540 dev->tx_pkt_burst = qede_xmit_pkts; 2541 2542 return 0; 2543 } 2544 2545 static int 2546 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 2547 struct rte_eth_udp_tunnel *tunnel_udp) 2548 { 2549 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2550 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2551 struct ecore_tunnel_info tunn; /* @DPDK */ 2552 uint16_t udp_port; 2553 int rc; 2554 2555 PMD_INIT_FUNC_TRACE(edev); 2556 2557 memset(&tunn, 0, sizeof(tunn)); 2558 2559 switch (tunnel_udp->prot_type) { 2560 case RTE_TUNNEL_TYPE_VXLAN: 2561 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) { 2562 DP_ERR(edev, "UDP port %u doesn't exist\n", 2563 tunnel_udp->udp_port); 2564 return ECORE_INVAL; 2565 } 2566 udp_port = 0; 2567 2568 tunn.vxlan_port.b_update_port = true; 2569 tunn.vxlan_port.port = udp_port; 2570 2571 rc = qede_tunnel_update(qdev, &tunn); 2572 if (rc != ECORE_SUCCESS) { 2573 DP_ERR(edev, "Unable to config UDP port %u\n", 2574 tunn.vxlan_port.port); 2575 return rc; 2576 } 2577 2578 qdev->vxlan.udp_port = udp_port; 2579 /* If the request is to delete UDP port and if the number of 2580 * VXLAN filters have reached 0 then VxLAN offload can be be 2581 * disabled. 2582 */ 2583 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0) 2584 return qede_vxlan_enable(eth_dev, 2585 ECORE_TUNN_CLSS_MAC_VLAN, false); 2586 2587 break; 2588 case RTE_TUNNEL_TYPE_GENEVE: 2589 if (qdev->geneve.udp_port != tunnel_udp->udp_port) { 2590 DP_ERR(edev, "UDP port %u doesn't exist\n", 2591 tunnel_udp->udp_port); 2592 return ECORE_INVAL; 2593 } 2594 2595 udp_port = 0; 2596 2597 tunn.geneve_port.b_update_port = true; 2598 tunn.geneve_port.port = udp_port; 2599 2600 rc = qede_tunnel_update(qdev, &tunn); 2601 if (rc != ECORE_SUCCESS) { 2602 DP_ERR(edev, "Unable to config UDP port %u\n", 2603 tunn.vxlan_port.port); 2604 return rc; 2605 } 2606 2607 qdev->vxlan.udp_port = udp_port; 2608 /* If the request is to delete UDP port and if the number of 2609 * GENEVE filters have reached 0 then GENEVE offload can be be 2610 * disabled. 2611 */ 2612 if (qdev->geneve.enable && qdev->geneve.num_filters == 0) 2613 return qede_geneve_enable(eth_dev, 2614 ECORE_TUNN_CLSS_MAC_VLAN, false); 2615 2616 break; 2617 2618 default: 2619 return ECORE_INVAL; 2620 } 2621 2622 return 0; 2623 2624 } 2625 static int 2626 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 2627 struct rte_eth_udp_tunnel *tunnel_udp) 2628 { 2629 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2630 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2631 struct ecore_tunnel_info tunn; /* @DPDK */ 2632 uint16_t udp_port; 2633 int rc; 2634 2635 PMD_INIT_FUNC_TRACE(edev); 2636 2637 memset(&tunn, 0, sizeof(tunn)); 2638 2639 switch (tunnel_udp->prot_type) { 2640 case RTE_TUNNEL_TYPE_VXLAN: 2641 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) { 2642 DP_INFO(edev, 2643 "UDP port %u for VXLAN was already configured\n", 2644 tunnel_udp->udp_port); 2645 return ECORE_SUCCESS; 2646 } 2647 2648 /* Enable VxLAN tunnel with default MAC/VLAN classification if 2649 * it was not enabled while adding VXLAN filter before UDP port 2650 * update. 2651 */ 2652 if (!qdev->vxlan.enable) { 2653 rc = qede_vxlan_enable(eth_dev, 2654 ECORE_TUNN_CLSS_MAC_VLAN, true); 2655 if (rc != ECORE_SUCCESS) { 2656 DP_ERR(edev, "Failed to enable VXLAN " 2657 "prior to updating UDP port\n"); 2658 return rc; 2659 } 2660 } 2661 udp_port = tunnel_udp->udp_port; 2662 2663 tunn.vxlan_port.b_update_port = true; 2664 tunn.vxlan_port.port = udp_port; 2665 2666 rc = qede_tunnel_update(qdev, &tunn); 2667 if (rc != ECORE_SUCCESS) { 2668 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n", 2669 udp_port); 2670 return rc; 2671 } 2672 2673 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port); 2674 2675 qdev->vxlan.udp_port = udp_port; 2676 break; 2677 case RTE_TUNNEL_TYPE_GENEVE: 2678 if (qdev->geneve.udp_port == tunnel_udp->udp_port) { 2679 DP_INFO(edev, 2680 "UDP port %u for GENEVE was already configured\n", 2681 tunnel_udp->udp_port); 2682 return ECORE_SUCCESS; 2683 } 2684 2685 /* Enable GENEVE tunnel with default MAC/VLAN classification if 2686 * it was not enabled while adding GENEVE filter before UDP port 2687 * update. 2688 */ 2689 if (!qdev->geneve.enable) { 2690 rc = qede_geneve_enable(eth_dev, 2691 ECORE_TUNN_CLSS_MAC_VLAN, true); 2692 if (rc != ECORE_SUCCESS) { 2693 DP_ERR(edev, "Failed to enable GENEVE " 2694 "prior to updating UDP port\n"); 2695 return rc; 2696 } 2697 } 2698 udp_port = tunnel_udp->udp_port; 2699 2700 tunn.geneve_port.b_update_port = true; 2701 tunn.geneve_port.port = udp_port; 2702 2703 rc = qede_tunnel_update(qdev, &tunn); 2704 if (rc != ECORE_SUCCESS) { 2705 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n", 2706 udp_port); 2707 return rc; 2708 } 2709 2710 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port); 2711 2712 qdev->geneve.udp_port = udp_port; 2713 break; 2714 default: 2715 return ECORE_INVAL; 2716 } 2717 2718 return 0; 2719 } 2720 2721 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 2722 uint32_t *clss, char *str) 2723 { 2724 uint16_t j; 2725 *clss = MAX_ECORE_TUNN_CLSS; 2726 2727 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 2728 if (filter == qede_tunn_types[j].rte_filter_type) { 2729 *type = qede_tunn_types[j].qede_type; 2730 *clss = qede_tunn_types[j].qede_tunn_clss; 2731 strcpy(str, qede_tunn_types[j].string); 2732 return; 2733 } 2734 } 2735 } 2736 2737 static int 2738 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 2739 const struct rte_eth_tunnel_filter_conf *conf, 2740 uint32_t type) 2741 { 2742 /* Init commmon ucast params first */ 2743 qede_set_ucast_cmn_params(ucast); 2744 2745 /* Copy out the required fields based on classification type */ 2746 ucast->type = type; 2747 2748 switch (type) { 2749 case ECORE_FILTER_VNI: 2750 ucast->vni = conf->tenant_id; 2751 break; 2752 case ECORE_FILTER_INNER_VLAN: 2753 ucast->vlan = conf->inner_vlan; 2754 break; 2755 case ECORE_FILTER_MAC: 2756 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2757 ETHER_ADDR_LEN); 2758 break; 2759 case ECORE_FILTER_INNER_MAC: 2760 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2761 ETHER_ADDR_LEN); 2762 break; 2763 case ECORE_FILTER_MAC_VNI_PAIR: 2764 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2765 ETHER_ADDR_LEN); 2766 ucast->vni = conf->tenant_id; 2767 break; 2768 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 2769 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2770 ETHER_ADDR_LEN); 2771 ucast->vni = conf->tenant_id; 2772 break; 2773 case ECORE_FILTER_INNER_PAIR: 2774 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2775 ETHER_ADDR_LEN); 2776 ucast->vlan = conf->inner_vlan; 2777 break; 2778 default: 2779 return -EINVAL; 2780 } 2781 2782 return ECORE_SUCCESS; 2783 } 2784 2785 static int 2786 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2787 const struct rte_eth_tunnel_filter_conf *conf, 2788 __attribute__((unused)) enum rte_filter_op filter_op, 2789 enum ecore_tunn_clss *clss, 2790 bool add) 2791 { 2792 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2793 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2794 struct ecore_filter_ucast ucast = {0}; 2795 enum ecore_filter_ucast_type type; 2796 uint16_t filter_type = 0; 2797 char str[80]; 2798 int rc; 2799 2800 filter_type = conf->filter_type; 2801 /* Determine if the given filter classification is supported */ 2802 qede_get_ecore_tunn_params(filter_type, &type, clss, str); 2803 if (*clss == MAX_ECORE_TUNN_CLSS) { 2804 DP_ERR(edev, "Unsupported filter type\n"); 2805 return -EINVAL; 2806 } 2807 /* Init tunnel ucast params */ 2808 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2809 if (rc != ECORE_SUCCESS) { 2810 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n", 2811 conf->filter_type); 2812 return rc; 2813 } 2814 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2815 str, filter_op, ucast.type); 2816 2817 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE; 2818 2819 /* Skip MAC/VLAN if filter is based on VNI */ 2820 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2821 rc = qede_mac_int_ops(eth_dev, &ucast, add); 2822 if ((rc == 0) && add) { 2823 /* Enable accept anyvlan */ 2824 qede_config_accept_any_vlan(qdev, true); 2825 } 2826 } else { 2827 rc = qede_ucast_filter(eth_dev, &ucast, add); 2828 if (rc == 0) 2829 rc = ecore_filter_ucast_cmd(edev, &ucast, 2830 ECORE_SPQ_MODE_CB, NULL); 2831 } 2832 2833 return rc; 2834 } 2835 2836 static int 2837 qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2838 enum rte_filter_op filter_op, 2839 const struct rte_eth_tunnel_filter_conf *conf) 2840 { 2841 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2842 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2843 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS; 2844 bool add; 2845 int rc; 2846 2847 PMD_INIT_FUNC_TRACE(edev); 2848 2849 switch (filter_op) { 2850 case RTE_ETH_FILTER_ADD: 2851 add = true; 2852 break; 2853 case RTE_ETH_FILTER_DELETE: 2854 add = false; 2855 break; 2856 default: 2857 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 2858 return -EINVAL; 2859 } 2860 2861 if (IS_VF(edev)) 2862 return qede_tunn_enable(eth_dev, 2863 ECORE_TUNN_CLSS_MAC_VLAN, 2864 conf->tunnel_type, add); 2865 2866 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add); 2867 if (rc != ECORE_SUCCESS) 2868 return rc; 2869 2870 if (add) { 2871 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) { 2872 qdev->vxlan.num_filters++; 2873 qdev->vxlan.filter_type = conf->filter_type; 2874 } else { /* GENEVE */ 2875 qdev->geneve.num_filters++; 2876 qdev->geneve.filter_type = conf->filter_type; 2877 } 2878 2879 if (!qdev->vxlan.enable || !qdev->geneve.enable || 2880 !qdev->ipgre.enable) 2881 return qede_tunn_enable(eth_dev, clss, 2882 conf->tunnel_type, 2883 true); 2884 } else { 2885 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) 2886 qdev->vxlan.num_filters--; 2887 else /*GENEVE*/ 2888 qdev->geneve.num_filters--; 2889 2890 /* Disable VXLAN if VXLAN filters become 0 */ 2891 if ((qdev->vxlan.num_filters == 0) || 2892 (qdev->geneve.num_filters == 0)) 2893 return qede_tunn_enable(eth_dev, clss, 2894 conf->tunnel_type, 2895 false); 2896 } 2897 2898 return 0; 2899 } 2900 2901 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 2902 enum rte_filter_type filter_type, 2903 enum rte_filter_op filter_op, 2904 void *arg) 2905 { 2906 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2907 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2908 struct rte_eth_tunnel_filter_conf *filter_conf = 2909 (struct rte_eth_tunnel_filter_conf *)arg; 2910 2911 switch (filter_type) { 2912 case RTE_ETH_FILTER_TUNNEL: 2913 switch (filter_conf->tunnel_type) { 2914 case RTE_TUNNEL_TYPE_VXLAN: 2915 case RTE_TUNNEL_TYPE_GENEVE: 2916 case RTE_TUNNEL_TYPE_IP_IN_GRE: 2917 DP_INFO(edev, 2918 "Packet steering to the specified Rx queue" 2919 " is not supported with UDP tunneling"); 2920 return(qede_tunn_filter_config(eth_dev, filter_op, 2921 filter_conf)); 2922 case RTE_TUNNEL_TYPE_TEREDO: 2923 case RTE_TUNNEL_TYPE_NVGRE: 2924 case RTE_L2_TUNNEL_TYPE_E_TAG: 2925 DP_ERR(edev, "Unsupported tunnel type %d\n", 2926 filter_conf->tunnel_type); 2927 return -EINVAL; 2928 case RTE_TUNNEL_TYPE_NONE: 2929 default: 2930 return 0; 2931 } 2932 break; 2933 case RTE_ETH_FILTER_FDIR: 2934 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 2935 case RTE_ETH_FILTER_NTUPLE: 2936 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 2937 case RTE_ETH_FILTER_MACVLAN: 2938 case RTE_ETH_FILTER_ETHERTYPE: 2939 case RTE_ETH_FILTER_FLEXIBLE: 2940 case RTE_ETH_FILTER_SYN: 2941 case RTE_ETH_FILTER_HASH: 2942 case RTE_ETH_FILTER_L2_TUNNEL: 2943 case RTE_ETH_FILTER_MAX: 2944 default: 2945 DP_ERR(edev, "Unsupported filter type %d\n", 2946 filter_type); 2947 return -EINVAL; 2948 } 2949 2950 return 0; 2951 } 2952 2953 static const struct eth_dev_ops qede_eth_dev_ops = { 2954 .dev_configure = qede_dev_configure, 2955 .dev_infos_get = qede_dev_info_get, 2956 .rx_queue_setup = qede_rx_queue_setup, 2957 .rx_queue_release = qede_rx_queue_release, 2958 .tx_queue_setup = qede_tx_queue_setup, 2959 .tx_queue_release = qede_tx_queue_release, 2960 .dev_start = qede_dev_start, 2961 .dev_set_link_up = qede_dev_set_link_up, 2962 .dev_set_link_down = qede_dev_set_link_down, 2963 .link_update = qede_link_update, 2964 .promiscuous_enable = qede_promiscuous_enable, 2965 .promiscuous_disable = qede_promiscuous_disable, 2966 .allmulticast_enable = qede_allmulticast_enable, 2967 .allmulticast_disable = qede_allmulticast_disable, 2968 .set_mc_addr_list = qede_set_mc_addr_list, 2969 .dev_stop = qede_dev_stop, 2970 .dev_close = qede_dev_close, 2971 .stats_get = qede_get_stats, 2972 .stats_reset = qede_reset_stats, 2973 .xstats_get = qede_get_xstats, 2974 .xstats_reset = qede_reset_xstats, 2975 .xstats_get_names = qede_get_xstats_names, 2976 .mac_addr_add = qede_mac_addr_add, 2977 .mac_addr_remove = qede_mac_addr_remove, 2978 .mac_addr_set = qede_mac_addr_set, 2979 .vlan_offload_set = qede_vlan_offload_set, 2980 .vlan_filter_set = qede_vlan_filter_set, 2981 .flow_ctrl_set = qede_flow_ctrl_set, 2982 .flow_ctrl_get = qede_flow_ctrl_get, 2983 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2984 .rss_hash_update = qede_rss_hash_update, 2985 .rss_hash_conf_get = qede_rss_hash_conf_get, 2986 .reta_update = qede_rss_reta_update, 2987 .reta_query = qede_rss_reta_query, 2988 .mtu_set = qede_set_mtu, 2989 .filter_ctrl = qede_dev_filter_ctrl, 2990 .udp_tunnel_port_add = qede_udp_dst_port_add, 2991 .udp_tunnel_port_del = qede_udp_dst_port_del, 2992 }; 2993 2994 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2995 .dev_configure = qede_dev_configure, 2996 .dev_infos_get = qede_dev_info_get, 2997 .rx_queue_setup = qede_rx_queue_setup, 2998 .rx_queue_release = qede_rx_queue_release, 2999 .tx_queue_setup = qede_tx_queue_setup, 3000 .tx_queue_release = qede_tx_queue_release, 3001 .dev_start = qede_dev_start, 3002 .dev_set_link_up = qede_dev_set_link_up, 3003 .dev_set_link_down = qede_dev_set_link_down, 3004 .link_update = qede_link_update, 3005 .promiscuous_enable = qede_promiscuous_enable, 3006 .promiscuous_disable = qede_promiscuous_disable, 3007 .allmulticast_enable = qede_allmulticast_enable, 3008 .allmulticast_disable = qede_allmulticast_disable, 3009 .set_mc_addr_list = qede_set_mc_addr_list, 3010 .dev_stop = qede_dev_stop, 3011 .dev_close = qede_dev_close, 3012 .stats_get = qede_get_stats, 3013 .stats_reset = qede_reset_stats, 3014 .xstats_get = qede_get_xstats, 3015 .xstats_reset = qede_reset_xstats, 3016 .xstats_get_names = qede_get_xstats_names, 3017 .vlan_offload_set = qede_vlan_offload_set, 3018 .vlan_filter_set = qede_vlan_filter_set, 3019 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 3020 .rss_hash_update = qede_rss_hash_update, 3021 .rss_hash_conf_get = qede_rss_hash_conf_get, 3022 .reta_update = qede_rss_reta_update, 3023 .reta_query = qede_rss_reta_query, 3024 .mtu_set = qede_set_mtu, 3025 .udp_tunnel_port_add = qede_udp_dst_port_add, 3026 .udp_tunnel_port_del = qede_udp_dst_port_del, 3027 }; 3028 3029 static void qede_update_pf_params(struct ecore_dev *edev) 3030 { 3031 struct ecore_pf_params pf_params; 3032 3033 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 3034 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 3035 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 3036 qed_ops->common->update_pf_params(edev, &pf_params); 3037 } 3038 3039 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 3040 { 3041 struct rte_pci_device *pci_dev; 3042 struct rte_pci_addr pci_addr; 3043 struct qede_dev *adapter; 3044 struct ecore_dev *edev; 3045 struct qed_dev_eth_info dev_info; 3046 struct qed_slowpath_params params; 3047 static bool do_once = true; 3048 uint8_t bulletin_change; 3049 uint8_t vf_mac[ETHER_ADDR_LEN]; 3050 uint8_t is_mac_forced; 3051 bool is_mac_exist; 3052 /* Fix up ecore debug level */ 3053 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 3054 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 3055 int rc; 3056 3057 /* Extract key data structures */ 3058 adapter = eth_dev->data->dev_private; 3059 adapter->ethdev = eth_dev; 3060 edev = &adapter->edev; 3061 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3062 pci_addr = pci_dev->addr; 3063 3064 PMD_INIT_FUNC_TRACE(edev); 3065 3066 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 3067 pci_addr.bus, pci_addr.devid, pci_addr.function, 3068 eth_dev->data->port_id); 3069 3070 eth_dev->rx_pkt_burst = qede_recv_pkts; 3071 eth_dev->tx_pkt_burst = qede_xmit_pkts; 3072 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 3073 3074 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3075 DP_ERR(edev, "Skipping device init from secondary process\n"); 3076 return 0; 3077 } 3078 3079 rte_eth_copy_pci_info(eth_dev, pci_dev); 3080 3081 /* @DPDK */ 3082 edev->vendor_id = pci_dev->id.vendor_id; 3083 edev->device_id = pci_dev->id.device_id; 3084 3085 qed_ops = qed_get_eth_ops(); 3086 if (!qed_ops) { 3087 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 3088 return -EINVAL; 3089 } 3090 3091 DP_INFO(edev, "Starting qede probe\n"); 3092 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 3093 dp_level, is_vf); 3094 if (rc != 0) { 3095 DP_ERR(edev, "qede probe failed rc %d\n", rc); 3096 return -ENODEV; 3097 } 3098 qede_update_pf_params(edev); 3099 rte_intr_callback_register(&pci_dev->intr_handle, 3100 qede_interrupt_handler, (void *)eth_dev); 3101 if (rte_intr_enable(&pci_dev->intr_handle)) { 3102 DP_ERR(edev, "rte_intr_enable() failed\n"); 3103 return -ENODEV; 3104 } 3105 3106 /* Start the Slowpath-process */ 3107 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 3108 params.int_mode = ECORE_INT_MODE_MSIX; 3109 params.drv_major = QEDE_PMD_VERSION_MAJOR; 3110 params.drv_minor = QEDE_PMD_VERSION_MINOR; 3111 params.drv_rev = QEDE_PMD_VERSION_REVISION; 3112 params.drv_eng = QEDE_PMD_VERSION_PATCH; 3113 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 3114 QEDE_PMD_DRV_VER_STR_SIZE); 3115 3116 /* For CMT mode device do periodic polling for slowpath events. 3117 * This is required since uio device uses only one MSI-x 3118 * interrupt vector but we need one for each engine. 3119 */ 3120 if (ECORE_IS_CMT(edev) && IS_PF(edev)) { 3121 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 3122 qede_poll_sp_sb_cb, 3123 (void *)eth_dev); 3124 if (rc != 0) { 3125 DP_ERR(edev, "Unable to start periodic" 3126 " timer rc %d\n", rc); 3127 return -EINVAL; 3128 } 3129 } 3130 3131 rc = qed_ops->common->slowpath_start(edev, ¶ms); 3132 if (rc) { 3133 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 3134 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3135 (void *)eth_dev); 3136 return -ENODEV; 3137 } 3138 3139 rc = qed_ops->fill_dev_info(edev, &dev_info); 3140 if (rc) { 3141 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 3142 qed_ops->common->slowpath_stop(edev); 3143 qed_ops->common->remove(edev); 3144 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3145 (void *)eth_dev); 3146 return -ENODEV; 3147 } 3148 3149 qede_alloc_etherdev(adapter, &dev_info); 3150 3151 adapter->ops->common->set_name(edev, edev->name); 3152 3153 if (!is_vf) 3154 adapter->dev_info.num_mac_filters = 3155 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 3156 ECORE_MAC); 3157 else 3158 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 3159 (uint32_t *)&adapter->dev_info.num_mac_filters); 3160 3161 /* Allocate memory for storing MAC addr */ 3162 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 3163 (ETHER_ADDR_LEN * 3164 adapter->dev_info.num_mac_filters), 3165 RTE_CACHE_LINE_SIZE); 3166 3167 if (eth_dev->data->mac_addrs == NULL) { 3168 DP_ERR(edev, "Failed to allocate MAC address\n"); 3169 qed_ops->common->slowpath_stop(edev); 3170 qed_ops->common->remove(edev); 3171 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3172 (void *)eth_dev); 3173 return -ENOMEM; 3174 } 3175 3176 if (!is_vf) { 3177 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 3178 hw_info.hw_mac_addr, 3179 ð_dev->data->mac_addrs[0]); 3180 ether_addr_copy(ð_dev->data->mac_addrs[0], 3181 &adapter->primary_mac); 3182 } else { 3183 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 3184 &bulletin_change); 3185 if (bulletin_change) { 3186 is_mac_exist = 3187 ecore_vf_bulletin_get_forced_mac( 3188 ECORE_LEADING_HWFN(edev), 3189 vf_mac, 3190 &is_mac_forced); 3191 if (is_mac_exist && is_mac_forced) { 3192 DP_INFO(edev, "VF macaddr received from PF\n"); 3193 ether_addr_copy((struct ether_addr *)&vf_mac, 3194 ð_dev->data->mac_addrs[0]); 3195 ether_addr_copy(ð_dev->data->mac_addrs[0], 3196 &adapter->primary_mac); 3197 } else { 3198 DP_ERR(edev, "No VF macaddr assigned\n"); 3199 } 3200 } 3201 } 3202 3203 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 3204 3205 if (do_once) { 3206 qede_print_adapter_info(adapter); 3207 do_once = false; 3208 } 3209 3210 /* Bring-up the link */ 3211 qede_dev_set_link_state(eth_dev, true); 3212 3213 adapter->num_tx_queues = 0; 3214 adapter->num_rx_queues = 0; 3215 SLIST_INIT(&adapter->fdir_info.fdir_list_head); 3216 SLIST_INIT(&adapter->vlan_list_head); 3217 SLIST_INIT(&adapter->uc_list_head); 3218 SLIST_INIT(&adapter->mc_list_head); 3219 adapter->mtu = ETHER_MTU; 3220 adapter->vport_started = false; 3221 3222 /* VF tunnel offloads is enabled by default in PF driver */ 3223 adapter->vxlan.num_filters = 0; 3224 adapter->geneve.num_filters = 0; 3225 adapter->ipgre.num_filters = 0; 3226 if (is_vf) { 3227 adapter->vxlan.enable = true; 3228 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC | 3229 ETH_TUNNEL_FILTER_IVLAN; 3230 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT; 3231 adapter->geneve.enable = true; 3232 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC | 3233 ETH_TUNNEL_FILTER_IVLAN; 3234 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT; 3235 adapter->ipgre.enable = true; 3236 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC | 3237 ETH_TUNNEL_FILTER_IVLAN; 3238 } else { 3239 adapter->vxlan.enable = false; 3240 adapter->geneve.enable = false; 3241 adapter->ipgre.enable = false; 3242 } 3243 3244 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 3245 adapter->primary_mac.addr_bytes[0], 3246 adapter->primary_mac.addr_bytes[1], 3247 adapter->primary_mac.addr_bytes[2], 3248 adapter->primary_mac.addr_bytes[3], 3249 adapter->primary_mac.addr_bytes[4], 3250 adapter->primary_mac.addr_bytes[5]); 3251 3252 DP_INFO(edev, "Device initialized\n"); 3253 3254 return 0; 3255 } 3256 3257 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 3258 { 3259 return qede_common_dev_init(eth_dev, 1); 3260 } 3261 3262 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 3263 { 3264 return qede_common_dev_init(eth_dev, 0); 3265 } 3266 3267 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 3268 { 3269 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 3270 struct qede_dev *qdev = eth_dev->data->dev_private; 3271 struct ecore_dev *edev = &qdev->edev; 3272 3273 PMD_INIT_FUNC_TRACE(edev); 3274 #endif 3275 3276 /* only uninitialize in the primary process */ 3277 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3278 return 0; 3279 3280 /* safe to close dev here */ 3281 qede_dev_close(eth_dev); 3282 3283 eth_dev->dev_ops = NULL; 3284 eth_dev->rx_pkt_burst = NULL; 3285 eth_dev->tx_pkt_burst = NULL; 3286 3287 if (eth_dev->data->mac_addrs) 3288 rte_free(eth_dev->data->mac_addrs); 3289 3290 eth_dev->data->mac_addrs = NULL; 3291 3292 return 0; 3293 } 3294 3295 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3296 { 3297 return qede_dev_common_uninit(eth_dev); 3298 } 3299 3300 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3301 { 3302 return qede_dev_common_uninit(eth_dev); 3303 } 3304 3305 static const struct rte_pci_id pci_id_qedevf_map[] = { 3306 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3307 { 3308 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 3309 }, 3310 { 3311 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 3312 }, 3313 { 3314 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 3315 }, 3316 {.vendor_id = 0,} 3317 }; 3318 3319 static const struct rte_pci_id pci_id_qede_map[] = { 3320 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3321 { 3322 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 3323 }, 3324 { 3325 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 3326 }, 3327 { 3328 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 3329 }, 3330 { 3331 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 3332 }, 3333 { 3334 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 3335 }, 3336 { 3337 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 3338 }, 3339 { 3340 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 3341 }, 3342 { 3343 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 3344 }, 3345 { 3346 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 3347 }, 3348 { 3349 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 3350 }, 3351 {.vendor_id = 0,} 3352 }; 3353 3354 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3355 struct rte_pci_device *pci_dev) 3356 { 3357 return rte_eth_dev_pci_generic_probe(pci_dev, 3358 sizeof(struct qede_dev), qedevf_eth_dev_init); 3359 } 3360 3361 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3362 { 3363 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 3364 } 3365 3366 static struct rte_pci_driver rte_qedevf_pmd = { 3367 .id_table = pci_id_qedevf_map, 3368 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3369 .probe = qedevf_eth_dev_pci_probe, 3370 .remove = qedevf_eth_dev_pci_remove, 3371 }; 3372 3373 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3374 struct rte_pci_device *pci_dev) 3375 { 3376 return rte_eth_dev_pci_generic_probe(pci_dev, 3377 sizeof(struct qede_dev), qede_eth_dev_init); 3378 } 3379 3380 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3381 { 3382 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 3383 } 3384 3385 static struct rte_pci_driver rte_qede_pmd = { 3386 .id_table = pci_id_qede_map, 3387 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3388 .probe = qede_eth_dev_pci_probe, 3389 .remove = qede_eth_dev_pci_remove, 3390 }; 3391 3392 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 3393 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 3394 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 3395 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 3396 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 3397 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 3398 3399 RTE_INIT(qede_init_log); 3400 static void 3401 qede_init_log(void) 3402 { 3403 qede_logtype_init = rte_log_register("pmd.net.qede.init"); 3404 if (qede_logtype_init >= 0) 3405 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE); 3406 qede_logtype_driver = rte_log_register("pmd.net.qede.driver"); 3407 if (qede_logtype_driver >= 0) 3408 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE); 3409 } 3410