1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "qede_ethdev.h" 10 #include <rte_alarm.h> 11 #include <rte_version.h> 12 13 /* Globals */ 14 static const struct qed_eth_ops *qed_ops; 15 static int64_t timer_period = 1; 16 17 /* VXLAN tunnel classification mapping */ 18 const struct _qede_vxlan_tunn_types { 19 uint16_t rte_filter_type; 20 enum ecore_filter_ucast_type qede_type; 21 enum ecore_tunn_clss qede_tunn_clss; 22 const char *string; 23 } qede_tunn_types[] = { 24 { 25 ETH_TUNNEL_FILTER_OMAC, 26 ECORE_FILTER_MAC, 27 ECORE_TUNN_CLSS_MAC_VLAN, 28 "outer-mac" 29 }, 30 { 31 ETH_TUNNEL_FILTER_TENID, 32 ECORE_FILTER_VNI, 33 ECORE_TUNN_CLSS_MAC_VNI, 34 "vni" 35 }, 36 { 37 ETH_TUNNEL_FILTER_IMAC, 38 ECORE_FILTER_INNER_MAC, 39 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 40 "inner-mac" 41 }, 42 { 43 ETH_TUNNEL_FILTER_IVLAN, 44 ECORE_FILTER_INNER_VLAN, 45 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 46 "inner-vlan" 47 }, 48 { 49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 50 ECORE_FILTER_MAC_VNI_PAIR, 51 ECORE_TUNN_CLSS_MAC_VNI, 52 "outer-mac and vni" 53 }, 54 { 55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 56 ECORE_FILTER_UNUSED, 57 MAX_ECORE_TUNN_CLSS, 58 "outer-mac and inner-mac" 59 }, 60 { 61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 62 ECORE_FILTER_UNUSED, 63 MAX_ECORE_TUNN_CLSS, 64 "outer-mac and inner-vlan" 65 }, 66 { 67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 68 ECORE_FILTER_INNER_MAC_VNI_PAIR, 69 ECORE_TUNN_CLSS_INNER_MAC_VNI, 70 "vni and inner-mac", 71 }, 72 { 73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 74 ECORE_FILTER_UNUSED, 75 MAX_ECORE_TUNN_CLSS, 76 "vni and inner-vlan", 77 }, 78 { 79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 80 ECORE_FILTER_INNER_PAIR, 81 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 82 "inner-mac and inner-vlan", 83 }, 84 { 85 ETH_TUNNEL_FILTER_OIP, 86 ECORE_FILTER_UNUSED, 87 MAX_ECORE_TUNN_CLSS, 88 "outer-IP" 89 }, 90 { 91 ETH_TUNNEL_FILTER_IIP, 92 ECORE_FILTER_UNUSED, 93 MAX_ECORE_TUNN_CLSS, 94 "inner-IP" 95 }, 96 { 97 RTE_TUNNEL_FILTER_IMAC_IVLAN, 98 ECORE_FILTER_UNUSED, 99 MAX_ECORE_TUNN_CLSS, 100 "IMAC_IVLAN" 101 }, 102 { 103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 104 ECORE_FILTER_UNUSED, 105 MAX_ECORE_TUNN_CLSS, 106 "IMAC_IVLAN_TENID" 107 }, 108 { 109 RTE_TUNNEL_FILTER_IMAC_TENID, 110 ECORE_FILTER_UNUSED, 111 MAX_ECORE_TUNN_CLSS, 112 "IMAC_TENID" 113 }, 114 { 115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 116 ECORE_FILTER_UNUSED, 117 MAX_ECORE_TUNN_CLSS, 118 "OMAC_TENID_IMAC" 119 }, 120 }; 121 122 struct rte_qede_xstats_name_off { 123 char name[RTE_ETH_XSTATS_NAME_SIZE]; 124 uint64_t offset; 125 }; 126 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 128 {"rx_unicast_bytes", 129 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)}, 130 {"rx_multicast_bytes", 131 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)}, 132 {"rx_broadcast_bytes", 133 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)}, 134 {"rx_unicast_packets", 135 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)}, 136 {"rx_multicast_packets", 137 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)}, 138 {"rx_broadcast_packets", 139 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)}, 140 141 {"tx_unicast_bytes", 142 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)}, 143 {"tx_multicast_bytes", 144 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)}, 145 {"tx_broadcast_bytes", 146 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)}, 147 {"tx_unicast_packets", 148 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)}, 149 {"tx_multicast_packets", 150 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)}, 151 {"tx_broadcast_packets", 152 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)}, 153 154 {"rx_64_byte_packets", 155 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)}, 156 {"rx_65_to_127_byte_packets", 157 offsetof(struct ecore_eth_stats_common, 158 rx_65_to_127_byte_packets)}, 159 {"rx_128_to_255_byte_packets", 160 offsetof(struct ecore_eth_stats_common, 161 rx_128_to_255_byte_packets)}, 162 {"rx_256_to_511_byte_packets", 163 offsetof(struct ecore_eth_stats_common, 164 rx_256_to_511_byte_packets)}, 165 {"rx_512_to_1023_byte_packets", 166 offsetof(struct ecore_eth_stats_common, 167 rx_512_to_1023_byte_packets)}, 168 {"rx_1024_to_1518_byte_packets", 169 offsetof(struct ecore_eth_stats_common, 170 rx_1024_to_1518_byte_packets)}, 171 {"tx_64_byte_packets", 172 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)}, 173 {"tx_65_to_127_byte_packets", 174 offsetof(struct ecore_eth_stats_common, 175 tx_65_to_127_byte_packets)}, 176 {"tx_128_to_255_byte_packets", 177 offsetof(struct ecore_eth_stats_common, 178 tx_128_to_255_byte_packets)}, 179 {"tx_256_to_511_byte_packets", 180 offsetof(struct ecore_eth_stats_common, 181 tx_256_to_511_byte_packets)}, 182 {"tx_512_to_1023_byte_packets", 183 offsetof(struct ecore_eth_stats_common, 184 tx_512_to_1023_byte_packets)}, 185 {"tx_1024_to_1518_byte_packets", 186 offsetof(struct ecore_eth_stats_common, 187 tx_1024_to_1518_byte_packets)}, 188 189 {"rx_mac_crtl_frames", 190 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)}, 191 {"tx_mac_control_frames", 192 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)}, 193 {"rx_pause_frames", 194 offsetof(struct ecore_eth_stats_common, rx_pause_frames)}, 195 {"tx_pause_frames", 196 offsetof(struct ecore_eth_stats_common, tx_pause_frames)}, 197 {"rx_priority_flow_control_frames", 198 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)}, 199 {"tx_priority_flow_control_frames", 200 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)}, 201 202 {"rx_crc_errors", 203 offsetof(struct ecore_eth_stats_common, rx_crc_errors)}, 204 {"rx_align_errors", 205 offsetof(struct ecore_eth_stats_common, rx_align_errors)}, 206 {"rx_carrier_errors", 207 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)}, 208 {"rx_oversize_packet_errors", 209 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)}, 210 {"rx_jabber_errors", 211 offsetof(struct ecore_eth_stats_common, rx_jabbers)}, 212 {"rx_undersize_packet_errors", 213 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)}, 214 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)}, 215 {"rx_host_buffer_not_available", 216 offsetof(struct ecore_eth_stats_common, no_buff_discards)}, 217 /* Number of packets discarded because they are bigger than MTU */ 218 {"rx_packet_too_big_discards", 219 offsetof(struct ecore_eth_stats_common, 220 packet_too_big_discard)}, 221 {"rx_ttl_zero_discards", 222 offsetof(struct ecore_eth_stats_common, ttl0_discard)}, 223 {"rx_multi_function_tag_filter_discards", 224 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)}, 225 {"rx_mac_filter_discards", 226 offsetof(struct ecore_eth_stats_common, mac_filter_discards)}, 227 {"rx_hw_buffer_truncates", 228 offsetof(struct ecore_eth_stats_common, brb_truncates)}, 229 {"rx_hw_buffer_discards", 230 offsetof(struct ecore_eth_stats_common, brb_discards)}, 231 {"tx_error_drop_packets", 232 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)}, 233 234 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)}, 235 {"rx_mac_unicast_packets", 236 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)}, 237 {"rx_mac_multicast_packets", 238 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)}, 239 {"rx_mac_broadcast_packets", 240 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)}, 241 {"rx_mac_frames_ok", 242 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)}, 243 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)}, 244 {"tx_mac_unicast_packets", 245 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)}, 246 {"tx_mac_multicast_packets", 247 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)}, 248 {"tx_mac_broadcast_packets", 249 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)}, 250 251 {"lro_coalesced_packets", 252 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)}, 253 {"lro_coalesced_events", 254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)}, 255 {"lro_aborts_num", 256 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)}, 257 {"lro_not_coalesced_packets", 258 offsetof(struct ecore_eth_stats_common, 259 tpa_not_coalesced_pkts)}, 260 {"lro_coalesced_bytes", 261 offsetof(struct ecore_eth_stats_common, 262 tpa_coalesced_bytes)}, 263 }; 264 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = { 266 {"rx_1519_to_1522_byte_packets", 267 offsetof(struct ecore_eth_stats, bb) + 268 offsetof(struct ecore_eth_stats_bb, 269 rx_1519_to_1522_byte_packets)}, 270 {"rx_1519_to_2047_byte_packets", 271 offsetof(struct ecore_eth_stats, bb) + 272 offsetof(struct ecore_eth_stats_bb, 273 rx_1519_to_2047_byte_packets)}, 274 {"rx_2048_to_4095_byte_packets", 275 offsetof(struct ecore_eth_stats, bb) + 276 offsetof(struct ecore_eth_stats_bb, 277 rx_2048_to_4095_byte_packets)}, 278 {"rx_4096_to_9216_byte_packets", 279 offsetof(struct ecore_eth_stats, bb) + 280 offsetof(struct ecore_eth_stats_bb, 281 rx_4096_to_9216_byte_packets)}, 282 {"rx_9217_to_16383_byte_packets", 283 offsetof(struct ecore_eth_stats, bb) + 284 offsetof(struct ecore_eth_stats_bb, 285 rx_9217_to_16383_byte_packets)}, 286 287 {"tx_1519_to_2047_byte_packets", 288 offsetof(struct ecore_eth_stats, bb) + 289 offsetof(struct ecore_eth_stats_bb, 290 tx_1519_to_2047_byte_packets)}, 291 {"tx_2048_to_4095_byte_packets", 292 offsetof(struct ecore_eth_stats, bb) + 293 offsetof(struct ecore_eth_stats_bb, 294 tx_2048_to_4095_byte_packets)}, 295 {"tx_4096_to_9216_byte_packets", 296 offsetof(struct ecore_eth_stats, bb) + 297 offsetof(struct ecore_eth_stats_bb, 298 tx_4096_to_9216_byte_packets)}, 299 {"tx_9217_to_16383_byte_packets", 300 offsetof(struct ecore_eth_stats, bb) + 301 offsetof(struct ecore_eth_stats_bb, 302 tx_9217_to_16383_byte_packets)}, 303 304 {"tx_lpi_entry_count", 305 offsetof(struct ecore_eth_stats, bb) + 306 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)}, 307 {"tx_total_collisions", 308 offsetof(struct ecore_eth_stats, bb) + 309 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)}, 310 }; 311 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = { 313 {"rx_1519_to_max_byte_packets", 314 offsetof(struct ecore_eth_stats, ah) + 315 offsetof(struct ecore_eth_stats_ah, 316 rx_1519_to_max_byte_packets)}, 317 {"tx_1519_to_max_byte_packets", 318 offsetof(struct ecore_eth_stats, ah) + 319 offsetof(struct ecore_eth_stats_ah, 320 tx_1519_to_max_byte_packets)}, 321 }; 322 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 324 {"rx_q_segments", 325 offsetof(struct qede_rx_queue, rx_segs)}, 326 {"rx_q_hw_errors", 327 offsetof(struct qede_rx_queue, rx_hw_errors)}, 328 {"rx_q_allocation_errors", 329 offsetof(struct qede_rx_queue, rx_alloc_errors)} 330 }; 331 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 333 { 334 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 335 } 336 337 static void 338 qede_interrupt_handler(void *param) 339 { 340 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 341 struct qede_dev *qdev = eth_dev->data->dev_private; 342 struct ecore_dev *edev = &qdev->edev; 343 344 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 345 if (rte_intr_enable(eth_dev->intr_handle)) 346 DP_ERR(edev, "rte_intr_enable failed\n"); 347 } 348 349 static void 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 351 { 352 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 353 qdev->ops = qed_ops; 354 } 355 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 357 static void qede_print_adapter_info(struct qede_dev *qdev) 358 { 359 struct ecore_dev *edev = &qdev->edev; 360 struct qed_dev_info *info = &qdev->dev_info.common; 361 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 362 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 363 364 DP_INFO(edev, "*********************************\n"); 365 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 366 DP_INFO(edev, " Chip details : %s %c%d\n", 367 ECORE_IS_BB(edev) ? "BB" : "AH", 368 'A' + edev->chip_rev, 369 (int)edev->chip_metal); 370 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 371 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 372 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 373 ver_str, QEDE_PMD_VERSION); 374 DP_INFO(edev, " Driver version : %s\n", drv_ver); 375 DP_INFO(edev, " Firmware version : %s\n", ver_str); 376 377 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 378 "%d.%d.%d.%d", 379 (info->mfw_rev >> 24) & 0xff, 380 (info->mfw_rev >> 16) & 0xff, 381 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 382 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 383 DP_INFO(edev, " Firmware file : %s\n", fw_file); 384 DP_INFO(edev, "*********************************\n"); 385 } 386 #endif 387 388 static int 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 390 { 391 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 392 struct ecore_sp_vport_start_params params; 393 struct ecore_hwfn *p_hwfn; 394 int rc; 395 int i; 396 397 memset(¶ms, 0, sizeof(params)); 398 params.vport_id = 0; 399 params.mtu = mtu; 400 /* @DPDK - Disable FW placement */ 401 params.zero_placement_offset = 1; 402 for_each_hwfn(edev, i) { 403 p_hwfn = &edev->hwfns[i]; 404 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 405 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 406 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 407 if (rc != ECORE_SUCCESS) { 408 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 409 return rc; 410 } 411 } 412 ecore_reset_vport_stats(edev); 413 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 414 415 return 0; 416 } 417 418 static int 419 qede_stop_vport(struct ecore_dev *edev) 420 { 421 struct ecore_hwfn *p_hwfn; 422 uint8_t vport_id; 423 int rc; 424 int i; 425 426 vport_id = 0; 427 for_each_hwfn(edev, i) { 428 p_hwfn = &edev->hwfns[i]; 429 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 430 vport_id); 431 if (rc != ECORE_SUCCESS) { 432 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 433 return rc; 434 } 435 } 436 437 return 0; 438 } 439 440 /* Activate or deactivate vport via vport-update */ 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 442 { 443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 445 struct ecore_sp_vport_update_params params; 446 struct ecore_hwfn *p_hwfn; 447 uint8_t i; 448 int rc = -1; 449 450 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 451 params.vport_id = 0; 452 params.update_vport_active_rx_flg = 1; 453 params.update_vport_active_tx_flg = 1; 454 params.vport_active_rx_flg = flg; 455 params.vport_active_tx_flg = flg; 456 #ifndef RTE_LIBRTE_QEDE_VF_TX_SWITCH 457 if (IS_VF(edev)) { 458 params.update_tx_switching_flg = 1; 459 params.tx_switching_flg = !flg; 460 } 461 #endif 462 for_each_hwfn(edev, i) { 463 p_hwfn = &edev->hwfns[i]; 464 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 465 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 466 ECORE_SPQ_MODE_EBLOCK, NULL); 467 if (rc != ECORE_SUCCESS) { 468 DP_ERR(edev, "Failed to update vport\n"); 469 break; 470 } 471 } 472 DP_INFO(edev, "vport %s VF tx-switch %s\n", flg ? "activated" : "deactivated", 473 params.tx_switching_flg ? "enabled" : "disabled"); 474 return rc; 475 } 476 477 static void 478 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 479 uint16_t mtu, bool enable) 480 { 481 /* Enable LRO in split mode */ 482 sge_tpa_params->tpa_ipv4_en_flg = enable; 483 sge_tpa_params->tpa_ipv6_en_flg = enable; 484 sge_tpa_params->tpa_ipv4_tunn_en_flg = false; 485 sge_tpa_params->tpa_ipv6_tunn_en_flg = false; 486 /* set if tpa enable changes */ 487 sge_tpa_params->update_tpa_en_flg = 1; 488 /* set if tpa parameters should be handled */ 489 sge_tpa_params->update_tpa_param_flg = enable; 490 491 sge_tpa_params->max_buffers_per_cqe = 20; 492 /* Enable TPA in split mode. In this mode each TPA segment 493 * starts on the new BD, so there is one BD per segment. 494 */ 495 sge_tpa_params->tpa_pkt_split_flg = 1; 496 sge_tpa_params->tpa_hdr_data_split_flg = 0; 497 sge_tpa_params->tpa_gro_consistent_flg = 0; 498 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 499 sge_tpa_params->tpa_max_size = 0x7FFF; 500 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 501 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 502 } 503 504 /* Enable/disable LRO via vport-update */ 505 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 506 { 507 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 508 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 509 struct ecore_sp_vport_update_params params; 510 struct ecore_sge_tpa_params tpa_params; 511 struct ecore_hwfn *p_hwfn; 512 int rc; 513 int i; 514 515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 516 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 517 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 518 params.vport_id = 0; 519 params.sge_tpa_params = &tpa_params; 520 for_each_hwfn(edev, i) { 521 p_hwfn = &edev->hwfns[i]; 522 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 523 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 524 ECORE_SPQ_MODE_EBLOCK, NULL); 525 if (rc != ECORE_SUCCESS) { 526 DP_ERR(edev, "Failed to update LRO\n"); 527 return -1; 528 } 529 } 530 qdev->enable_lro = flg; 531 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 532 533 return 0; 534 } 535 536 /* Update MTU via vport-update without doing port restart. 537 * The vport must be deactivated before calling this API. 538 */ 539 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 540 { 541 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 542 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 543 struct ecore_sp_vport_update_params params; 544 struct ecore_hwfn *p_hwfn; 545 int rc; 546 int i; 547 548 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 549 params.vport_id = 0; 550 params.mtu = mtu; 551 params.vport_id = 0; 552 for_each_hwfn(edev, i) { 553 p_hwfn = &edev->hwfns[i]; 554 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 555 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 556 ECORE_SPQ_MODE_EBLOCK, NULL); 557 if (rc != ECORE_SUCCESS) { 558 DP_ERR(edev, "Failed to update MTU\n"); 559 return -1; 560 } 561 } 562 DP_INFO(edev, "MTU updated to %u\n", mtu); 563 564 return 0; 565 } 566 567 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 568 { 569 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 570 ucast->is_rx_filter = true; 571 ucast->is_tx_filter = true; 572 /* ucast->assert_on_error = true; - For debug */ 573 } 574 575 static int 576 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 577 enum qed_filter_rx_mode_type type) 578 { 579 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 580 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 581 struct ecore_filter_accept_flags flags; 582 583 memset(&flags, 0, sizeof(flags)); 584 585 flags.update_rx_mode_config = 1; 586 flags.update_tx_mode_config = 1; 587 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 588 ECORE_ACCEPT_MCAST_MATCHED | 589 ECORE_ACCEPT_BCAST; 590 591 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 592 ECORE_ACCEPT_MCAST_MATCHED | 593 ECORE_ACCEPT_BCAST; 594 595 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 596 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 597 if (IS_VF(edev)) { 598 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 599 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n"); 600 } 601 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 602 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 603 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC | 604 QED_FILTER_RX_MODE_TYPE_PROMISC)) { 605 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED | 606 ECORE_ACCEPT_MCAST_UNMATCHED; 607 } 608 609 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 610 ECORE_SPQ_MODE_CB, NULL); 611 } 612 613 static int 614 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 615 bool enable, bool mask) 616 { 617 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 618 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 619 enum _ecore_status_t rc = ECORE_INVAL; 620 struct ecore_ptt *p_ptt; 621 struct ecore_tunnel_info tunn; 622 struct ecore_hwfn *p_hwfn; 623 int i; 624 625 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 626 tunn.vxlan.b_update_mode = enable; 627 tunn.vxlan.b_mode_enabled = mask; 628 tunn.b_update_rx_cls = true; 629 tunn.b_update_tx_cls = true; 630 tunn.vxlan.tun_cls = clss; 631 632 for_each_hwfn(edev, i) { 633 p_hwfn = &edev->hwfns[i]; 634 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL; 635 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, 636 &tunn, ECORE_SPQ_MODE_CB, NULL); 637 if (rc != ECORE_SUCCESS) { 638 DP_ERR(edev, "Failed to update tunn_clss %u\n", 639 tunn.vxlan.tun_cls); 640 break; 641 } 642 } 643 644 if (rc == ECORE_SUCCESS) { 645 qdev->vxlan.enable = enable; 646 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0; 647 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled"); 648 } 649 650 return rc; 651 } 652 653 static int 654 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 655 bool add) 656 { 657 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 658 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 659 struct qede_ucast_entry *tmp = NULL; 660 struct qede_ucast_entry *u; 661 struct ether_addr *mac_addr; 662 663 mac_addr = (struct ether_addr *)ucast->mac; 664 if (add) { 665 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 666 if ((memcmp(mac_addr, &tmp->mac, 667 ETHER_ADDR_LEN) == 0) && 668 ucast->vni == tmp->vni && 669 ucast->vlan == tmp->vlan) { 670 DP_ERR(edev, "Unicast MAC is already added" 671 " with vlan = %u, vni = %u\n", 672 ucast->vlan, ucast->vni); 673 return -EEXIST; 674 } 675 } 676 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 677 RTE_CACHE_LINE_SIZE); 678 if (!u) { 679 DP_ERR(edev, "Did not allocate memory for ucast\n"); 680 return -ENOMEM; 681 } 682 ether_addr_copy(mac_addr, &u->mac); 683 u->vlan = ucast->vlan; 684 u->vni = ucast->vni; 685 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 686 qdev->num_uc_addr++; 687 } else { 688 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 689 if ((memcmp(mac_addr, &tmp->mac, 690 ETHER_ADDR_LEN) == 0) && 691 ucast->vlan == tmp->vlan && 692 ucast->vni == tmp->vni) 693 break; 694 } 695 if (tmp == NULL) { 696 DP_INFO(edev, "Unicast MAC is not found\n"); 697 return -EINVAL; 698 } 699 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 700 qdev->num_uc_addr--; 701 } 702 703 return 0; 704 } 705 706 static int 707 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast, 708 bool add) 709 { 710 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 711 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 712 struct ether_addr *mac_addr; 713 struct qede_mcast_entry *tmp = NULL; 714 struct qede_mcast_entry *m; 715 716 mac_addr = (struct ether_addr *)mcast->mac; 717 if (add) { 718 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 719 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) { 720 DP_ERR(edev, 721 "Multicast MAC is already added\n"); 722 return -EEXIST; 723 } 724 } 725 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 726 RTE_CACHE_LINE_SIZE); 727 if (!m) { 728 DP_ERR(edev, 729 "Did not allocate memory for mcast\n"); 730 return -ENOMEM; 731 } 732 ether_addr_copy(mac_addr, &m->mac); 733 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 734 qdev->num_mc_addr++; 735 } else { 736 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 737 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) 738 break; 739 } 740 if (tmp == NULL) { 741 DP_INFO(edev, "Multicast mac is not found\n"); 742 return -EINVAL; 743 } 744 SLIST_REMOVE(&qdev->mc_list_head, tmp, 745 qede_mcast_entry, list); 746 qdev->num_mc_addr--; 747 } 748 749 return 0; 750 } 751 752 static enum _ecore_status_t 753 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 754 bool add) 755 { 756 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 757 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 758 enum _ecore_status_t rc; 759 struct ecore_filter_mcast mcast; 760 struct qede_mcast_entry *tmp; 761 uint16_t j = 0; 762 763 /* Multicast */ 764 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) { 765 if (add) { 766 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) { 767 DP_ERR(edev, 768 "Mcast filter table limit exceeded, " 769 "Please enable mcast promisc mode\n"); 770 return -ECORE_INVAL; 771 } 772 } 773 rc = qede_mcast_filter(eth_dev, ucast, add); 774 if (rc == 0) { 775 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr); 776 memset(&mcast, 0, sizeof(mcast)); 777 mcast.num_mc_addrs = qdev->num_mc_addr; 778 mcast.opcode = ECORE_FILTER_ADD; 779 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 780 ether_addr_copy(&tmp->mac, 781 (struct ether_addr *)&mcast.mac[j]); 782 j++; 783 } 784 rc = ecore_filter_mcast_cmd(edev, &mcast, 785 ECORE_SPQ_MODE_CB, NULL); 786 } 787 if (rc != ECORE_SUCCESS) { 788 DP_ERR(edev, "Failed to add multicast filter" 789 " rc = %d, op = %d\n", rc, add); 790 } 791 } else { /* Unicast */ 792 if (add) { 793 if (qdev->num_uc_addr >= 794 qdev->dev_info.num_mac_filters) { 795 DP_ERR(edev, 796 "Ucast filter table limit exceeded," 797 " Please enable promisc mode\n"); 798 return -ECORE_INVAL; 799 } 800 } 801 rc = qede_ucast_filter(eth_dev, ucast, add); 802 if (rc == 0) 803 rc = ecore_filter_ucast_cmd(edev, ucast, 804 ECORE_SPQ_MODE_CB, NULL); 805 if (rc != ECORE_SUCCESS) { 806 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 807 rc, add); 808 } 809 } 810 811 return rc; 812 } 813 814 static int 815 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 816 __rte_unused uint32_t index, __rte_unused uint32_t pool) 817 { 818 struct ecore_filter_ucast ucast; 819 int re; 820 821 qede_set_ucast_cmn_params(&ucast); 822 ucast.type = ECORE_FILTER_MAC; 823 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 824 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 825 return re; 826 } 827 828 static void 829 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 830 { 831 struct qede_dev *qdev = eth_dev->data->dev_private; 832 struct ecore_dev *edev = &qdev->edev; 833 struct ecore_filter_ucast ucast; 834 835 PMD_INIT_FUNC_TRACE(edev); 836 837 if (index >= qdev->dev_info.num_mac_filters) { 838 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 839 index, qdev->dev_info.num_mac_filters); 840 return; 841 } 842 843 qede_set_ucast_cmn_params(&ucast); 844 ucast.opcode = ECORE_FILTER_REMOVE; 845 ucast.type = ECORE_FILTER_MAC; 846 847 /* Use the index maintained by rte */ 848 ether_addr_copy(ð_dev->data->mac_addrs[index], 849 (struct ether_addr *)&ucast.mac); 850 851 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL); 852 } 853 854 static void 855 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 856 { 857 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 858 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 859 860 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 861 mac_addr->addr_bytes)) { 862 DP_ERR(edev, "Setting MAC address is not allowed\n"); 863 ether_addr_copy(&qdev->primary_mac, 864 ð_dev->data->mac_addrs[0]); 865 return; 866 } 867 868 qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 869 } 870 871 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 872 { 873 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 874 struct ecore_sp_vport_update_params params; 875 struct ecore_hwfn *p_hwfn; 876 uint8_t i; 877 int rc; 878 879 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 880 params.vport_id = 0; 881 params.update_accept_any_vlan_flg = 1; 882 params.accept_any_vlan = flg; 883 for_each_hwfn(edev, i) { 884 p_hwfn = &edev->hwfns[i]; 885 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 886 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 887 ECORE_SPQ_MODE_EBLOCK, NULL); 888 if (rc != ECORE_SUCCESS) { 889 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 890 return; 891 } 892 } 893 894 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 895 } 896 897 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 898 { 899 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 900 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 901 struct ecore_sp_vport_update_params params; 902 struct ecore_hwfn *p_hwfn; 903 uint8_t i; 904 int rc; 905 906 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 907 params.vport_id = 0; 908 params.update_inner_vlan_removal_flg = 1; 909 params.inner_vlan_removal_flg = flg; 910 for_each_hwfn(edev, i) { 911 p_hwfn = &edev->hwfns[i]; 912 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 913 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 914 ECORE_SPQ_MODE_EBLOCK, NULL); 915 if (rc != ECORE_SUCCESS) { 916 DP_ERR(edev, "Failed to update vport\n"); 917 return -1; 918 } 919 } 920 921 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 922 return 0; 923 } 924 925 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 926 uint16_t vlan_id, int on) 927 { 928 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 929 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 930 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 931 struct qede_vlan_entry *tmp = NULL; 932 struct qede_vlan_entry *vlan; 933 struct ecore_filter_ucast ucast; 934 int rc; 935 936 if (on) { 937 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 938 DP_ERR(edev, "Reached max VLAN filter limit" 939 " enabling accept_any_vlan\n"); 940 qede_config_accept_any_vlan(qdev, true); 941 return 0; 942 } 943 944 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 945 if (tmp->vid == vlan_id) { 946 DP_ERR(edev, "VLAN %u already configured\n", 947 vlan_id); 948 return -EEXIST; 949 } 950 } 951 952 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 953 RTE_CACHE_LINE_SIZE); 954 955 if (!vlan) { 956 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 957 return -ENOMEM; 958 } 959 960 qede_set_ucast_cmn_params(&ucast); 961 ucast.opcode = ECORE_FILTER_ADD; 962 ucast.type = ECORE_FILTER_VLAN; 963 ucast.vlan = vlan_id; 964 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 965 NULL); 966 if (rc != 0) { 967 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 968 rc); 969 rte_free(vlan); 970 } else { 971 vlan->vid = vlan_id; 972 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 973 qdev->configured_vlans++; 974 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 975 vlan_id, qdev->configured_vlans); 976 } 977 } else { 978 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 979 if (tmp->vid == vlan_id) 980 break; 981 } 982 983 if (!tmp) { 984 if (qdev->configured_vlans == 0) { 985 DP_INFO(edev, 986 "No VLAN filters configured yet\n"); 987 return 0; 988 } 989 990 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 991 return -EINVAL; 992 } 993 994 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 995 996 qede_set_ucast_cmn_params(&ucast); 997 ucast.opcode = ECORE_FILTER_REMOVE; 998 ucast.type = ECORE_FILTER_VLAN; 999 ucast.vlan = vlan_id; 1000 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1001 NULL); 1002 if (rc != 0) { 1003 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 1004 vlan_id, rc); 1005 } else { 1006 qdev->configured_vlans--; 1007 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 1008 vlan_id, qdev->configured_vlans); 1009 } 1010 } 1011 1012 return rc; 1013 } 1014 1015 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 1016 { 1017 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1018 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1019 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1020 1021 if (mask & ETH_VLAN_STRIP_MASK) { 1022 if (rxmode->hw_vlan_strip) 1023 (void)qede_vlan_stripping(eth_dev, 1); 1024 else 1025 (void)qede_vlan_stripping(eth_dev, 0); 1026 } 1027 1028 if (mask & ETH_VLAN_FILTER_MASK) { 1029 /* VLAN filtering kicks in when a VLAN is added */ 1030 if (rxmode->hw_vlan_filter) { 1031 qede_vlan_filter_set(eth_dev, 0, 1); 1032 } else { 1033 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 1034 DP_ERR(edev, 1035 " Please remove existing VLAN filters" 1036 " before disabling VLAN filtering\n"); 1037 /* Signal app that VLAN filtering is still 1038 * enabled 1039 */ 1040 rxmode->hw_vlan_filter = true; 1041 } else { 1042 qede_vlan_filter_set(eth_dev, 0, 0); 1043 } 1044 } 1045 } 1046 1047 if (mask & ETH_VLAN_EXTEND_MASK) 1048 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q" 1049 " and classification is based on outer tag only\n"); 1050 1051 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n", 1052 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter); 1053 1054 return 0; 1055 } 1056 1057 static void qede_prandom_bytes(uint32_t *buff) 1058 { 1059 uint8_t i; 1060 1061 srand((unsigned int)time(NULL)); 1062 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 1063 buff[i] = rand(); 1064 } 1065 1066 int qede_config_rss(struct rte_eth_dev *eth_dev) 1067 { 1068 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1069 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 1070 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1071 #endif 1072 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 1073 struct rte_eth_rss_reta_entry64 reta_conf[2]; 1074 struct rte_eth_rss_conf rss_conf; 1075 uint32_t i, id, pos, q; 1076 1077 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 1078 if (!rss_conf.rss_key) { 1079 DP_INFO(edev, "Applying driver default key\n"); 1080 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1081 qede_prandom_bytes(&def_rss_key[0]); 1082 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 1083 } 1084 1085 /* Configure RSS hash */ 1086 if (qede_rss_hash_update(eth_dev, &rss_conf)) 1087 return -EINVAL; 1088 1089 /* Configure default RETA */ 1090 memset(reta_conf, 0, sizeof(reta_conf)); 1091 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 1092 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 1093 1094 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1095 id = i / RTE_RETA_GROUP_SIZE; 1096 pos = i % RTE_RETA_GROUP_SIZE; 1097 q = i % QEDE_RSS_COUNT(qdev); 1098 reta_conf[id].reta[pos] = q; 1099 } 1100 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1101 ECORE_RSS_IND_TABLE_SIZE)) 1102 return -EINVAL; 1103 1104 return 0; 1105 } 1106 1107 static void qede_fastpath_start(struct ecore_dev *edev) 1108 { 1109 struct ecore_hwfn *p_hwfn; 1110 int i; 1111 1112 for_each_hwfn(edev, i) { 1113 p_hwfn = &edev->hwfns[i]; 1114 ecore_hw_start_fastpath(p_hwfn); 1115 } 1116 } 1117 1118 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1119 { 1120 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1121 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1122 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1123 1124 PMD_INIT_FUNC_TRACE(edev); 1125 1126 /* Update MTU only if it has changed */ 1127 if (qdev->mtu != qdev->new_mtu) { 1128 if (qede_update_mtu(eth_dev, qdev->new_mtu)) 1129 goto err; 1130 qdev->mtu = qdev->new_mtu; 1131 } 1132 1133 /* Configure TPA parameters */ 1134 if (rxmode->enable_lro) { 1135 if (qede_enable_tpa(eth_dev, true)) 1136 return -EINVAL; 1137 /* Enable scatter mode for LRO */ 1138 if (!rxmode->enable_scatter) 1139 eth_dev->data->scattered_rx = 1; 1140 } 1141 1142 /* Start queues */ 1143 if (qede_start_queues(eth_dev)) 1144 goto err; 1145 1146 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1147 * enabling RSS. Hence RSS configuration is deferred upto this point. 1148 * Also, we would like to retain similar behavior in PF case, so we 1149 * don't do PF/VF specific check here. 1150 */ 1151 if (rxmode->mq_mode == ETH_MQ_RX_RSS) 1152 if (qede_config_rss(eth_dev)) 1153 goto err; 1154 1155 /* Enable vport*/ 1156 if (qede_activate_vport(eth_dev, true)) 1157 goto err; 1158 1159 /* Bring-up the link */ 1160 qede_dev_set_link_state(eth_dev, true); 1161 1162 /* Start/resume traffic */ 1163 qede_fastpath_start(edev); 1164 1165 DP_INFO(edev, "Device started\n"); 1166 1167 return 0; 1168 err: 1169 DP_ERR(edev, "Device start fails\n"); 1170 return -1; /* common error code is < 0 */ 1171 } 1172 1173 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1174 { 1175 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1176 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1177 1178 PMD_INIT_FUNC_TRACE(edev); 1179 1180 /* Disable vport */ 1181 if (qede_activate_vport(eth_dev, false)) 1182 return; 1183 1184 if (qdev->enable_lro) 1185 qede_enable_tpa(eth_dev, false); 1186 1187 /* Stop queues */ 1188 qede_stop_queues(eth_dev); 1189 1190 /* Disable traffic */ 1191 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1192 1193 /* Bring the link down */ 1194 qede_dev_set_link_state(eth_dev, false); 1195 1196 DP_INFO(edev, "Device is stopped\n"); 1197 } 1198 1199 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1200 { 1201 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1202 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1203 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1204 int ret; 1205 1206 PMD_INIT_FUNC_TRACE(edev); 1207 1208 /* Check requirements for 100G mode */ 1209 if (ECORE_IS_CMT(edev)) { 1210 if (eth_dev->data->nb_rx_queues < 2 || 1211 eth_dev->data->nb_tx_queues < 2) { 1212 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 1213 return -EINVAL; 1214 } 1215 1216 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 1217 (eth_dev->data->nb_tx_queues % 2 != 0)) { 1218 DP_ERR(edev, 1219 "100G mode needs even no. of RX/TX queues\n"); 1220 return -EINVAL; 1221 } 1222 } 1223 1224 /* Sanity checks and throw warnings */ 1225 if (rxmode->enable_scatter) 1226 eth_dev->data->scattered_rx = 1; 1227 1228 if (!rxmode->hw_strip_crc) 1229 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n"); 1230 1231 if (!rxmode->hw_ip_checksum) 1232 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled " 1233 "in hw\n"); 1234 if (rxmode->header_split) 1235 DP_INFO(edev, "Header split enable is not supported\n"); 1236 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode == 1237 ETH_MQ_RX_RSS)) { 1238 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1239 return -ENOTSUP; 1240 } 1241 /* Flow director mode check */ 1242 if (qede_check_fdir_support(eth_dev)) 1243 return -ENOTSUP; 1244 1245 /* Deallocate resources if held previously. It is needed only if the 1246 * queue count has been changed from previous configuration. If its 1247 * going to change then it means RX/TX queue setup will be called 1248 * again and the fastpath pointers will be reinitialized there. 1249 */ 1250 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues || 1251 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) { 1252 qede_dealloc_fp_resc(eth_dev); 1253 /* Proceed with updated queue count */ 1254 qdev->num_tx_queues = eth_dev->data->nb_tx_queues; 1255 qdev->num_rx_queues = eth_dev->data->nb_rx_queues; 1256 if (qede_alloc_fp_resc(qdev)) 1257 return -ENOMEM; 1258 } 1259 1260 /* VF's MTU has to be set using vport-start where as 1261 * PF's MTU can be updated via vport-update. 1262 */ 1263 if (IS_VF(edev)) { 1264 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len)) 1265 return -1; 1266 } else { 1267 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len)) 1268 return -1; 1269 } 1270 1271 qdev->mtu = rxmode->max_rx_pkt_len; 1272 qdev->new_mtu = qdev->mtu; 1273 1274 /* Enable VLAN offloads by default */ 1275 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1276 ETH_VLAN_FILTER_MASK | 1277 ETH_VLAN_EXTEND_MASK); 1278 if (ret) 1279 return ret; 1280 1281 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1282 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); 1283 1284 return 0; 1285 } 1286 1287 /* Info about HW descriptor ring limitations */ 1288 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1289 .nb_max = 0x8000, /* 32K */ 1290 .nb_min = 128, 1291 .nb_align = 128 /* lowest common multiple */ 1292 }; 1293 1294 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1295 .nb_max = 0x8000, /* 32K */ 1296 .nb_min = 256, 1297 .nb_align = 256, 1298 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1299 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1300 }; 1301 1302 static void 1303 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1304 struct rte_eth_dev_info *dev_info) 1305 { 1306 struct qede_dev *qdev = eth_dev->data->dev_private; 1307 struct ecore_dev *edev = &qdev->edev; 1308 struct qed_link_output link; 1309 uint32_t speed_cap = 0; 1310 1311 PMD_INIT_FUNC_TRACE(edev); 1312 1313 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1314 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1315 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1316 dev_info->rx_desc_lim = qede_rx_desc_lim; 1317 dev_info->tx_desc_lim = qede_tx_desc_lim; 1318 1319 if (IS_PF(edev)) 1320 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1321 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1322 else 1323 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1324 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1325 dev_info->max_tx_queues = dev_info->max_rx_queues; 1326 1327 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1328 dev_info->max_vfs = 0; 1329 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1330 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1331 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1332 1333 dev_info->default_txconf = (struct rte_eth_txconf) { 1334 .txq_flags = QEDE_TXQ_FLAGS, 1335 }; 1336 1337 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP | 1338 DEV_RX_OFFLOAD_IPV4_CKSUM | 1339 DEV_RX_OFFLOAD_UDP_CKSUM | 1340 DEV_RX_OFFLOAD_TCP_CKSUM | 1341 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1342 DEV_RX_OFFLOAD_TCP_LRO); 1343 1344 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1345 DEV_TX_OFFLOAD_IPV4_CKSUM | 1346 DEV_TX_OFFLOAD_UDP_CKSUM | 1347 DEV_TX_OFFLOAD_TCP_CKSUM | 1348 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1349 DEV_TX_OFFLOAD_TCP_TSO | 1350 DEV_TX_OFFLOAD_VXLAN_TNL_TSO); 1351 1352 memset(&link, 0, sizeof(struct qed_link_output)); 1353 qdev->ops->common->get_link(edev, &link); 1354 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1355 speed_cap |= ETH_LINK_SPEED_1G; 1356 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1357 speed_cap |= ETH_LINK_SPEED_10G; 1358 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1359 speed_cap |= ETH_LINK_SPEED_25G; 1360 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1361 speed_cap |= ETH_LINK_SPEED_40G; 1362 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1363 speed_cap |= ETH_LINK_SPEED_50G; 1364 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1365 speed_cap |= ETH_LINK_SPEED_100G; 1366 dev_info->speed_capa = speed_cap; 1367 } 1368 1369 /* return 0 means link status changed, -1 means not changed */ 1370 static int 1371 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1372 { 1373 struct qede_dev *qdev = eth_dev->data->dev_private; 1374 struct ecore_dev *edev = &qdev->edev; 1375 uint16_t link_duplex; 1376 struct qed_link_output link; 1377 struct rte_eth_link *curr = ð_dev->data->dev_link; 1378 1379 memset(&link, 0, sizeof(struct qed_link_output)); 1380 qdev->ops->common->get_link(edev, &link); 1381 1382 /* Link Speed */ 1383 curr->link_speed = link.speed; 1384 1385 /* Link Mode */ 1386 switch (link.duplex) { 1387 case QEDE_DUPLEX_HALF: 1388 link_duplex = ETH_LINK_HALF_DUPLEX; 1389 break; 1390 case QEDE_DUPLEX_FULL: 1391 link_duplex = ETH_LINK_FULL_DUPLEX; 1392 break; 1393 case QEDE_DUPLEX_UNKNOWN: 1394 default: 1395 link_duplex = -1; 1396 } 1397 curr->link_duplex = link_duplex; 1398 1399 /* Link Status */ 1400 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN; 1401 1402 /* AN */ 1403 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1404 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1405 1406 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1407 curr->link_speed, curr->link_duplex, 1408 curr->link_autoneg, curr->link_status); 1409 1410 /* return 0 means link status changed, -1 means not changed */ 1411 return ((curr->link_status == link.link_up) ? -1 : 0); 1412 } 1413 1414 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1415 { 1416 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1417 struct qede_dev *qdev = eth_dev->data->dev_private; 1418 struct ecore_dev *edev = &qdev->edev; 1419 1420 PMD_INIT_FUNC_TRACE(edev); 1421 #endif 1422 1423 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1424 1425 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1426 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1427 1428 qed_configure_filter_rx_mode(eth_dev, type); 1429 } 1430 1431 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1432 { 1433 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1434 struct qede_dev *qdev = eth_dev->data->dev_private; 1435 struct ecore_dev *edev = &qdev->edev; 1436 1437 PMD_INIT_FUNC_TRACE(edev); 1438 #endif 1439 1440 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1441 qed_configure_filter_rx_mode(eth_dev, 1442 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1443 else 1444 qed_configure_filter_rx_mode(eth_dev, 1445 QED_FILTER_RX_MODE_TYPE_REGULAR); 1446 } 1447 1448 static void qede_poll_sp_sb_cb(void *param) 1449 { 1450 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1451 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1452 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1453 int rc; 1454 1455 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1456 qede_interrupt_action(&edev->hwfns[1]); 1457 1458 rc = rte_eal_alarm_set(timer_period * US_PER_S, 1459 qede_poll_sp_sb_cb, 1460 (void *)eth_dev); 1461 if (rc != 0) { 1462 DP_ERR(edev, "Unable to start periodic" 1463 " timer rc %d\n", rc); 1464 assert(false && "Unable to start periodic timer"); 1465 } 1466 } 1467 1468 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1469 { 1470 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1471 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1472 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1473 1474 PMD_INIT_FUNC_TRACE(edev); 1475 1476 /* dev_stop() shall cleanup fp resources in hw but without releasing 1477 * dma memories and sw structures so that dev_start() can be called 1478 * by the app without reconfiguration. However, in dev_close() we 1479 * can release all the resources and device can be brought up newly 1480 */ 1481 if (eth_dev->data->dev_started) 1482 qede_dev_stop(eth_dev); 1483 1484 qede_stop_vport(edev); 1485 qede_fdir_dealloc_resc(eth_dev); 1486 qede_dealloc_fp_resc(eth_dev); 1487 1488 eth_dev->data->nb_rx_queues = 0; 1489 eth_dev->data->nb_tx_queues = 0; 1490 1491 qdev->ops->common->slowpath_stop(edev); 1492 qdev->ops->common->remove(edev); 1493 rte_intr_disable(&pci_dev->intr_handle); 1494 rte_intr_callback_unregister(&pci_dev->intr_handle, 1495 qede_interrupt_handler, (void *)eth_dev); 1496 if (ECORE_IS_CMT(edev)) 1497 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1498 } 1499 1500 static int 1501 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1502 { 1503 struct qede_dev *qdev = eth_dev->data->dev_private; 1504 struct ecore_dev *edev = &qdev->edev; 1505 struct ecore_eth_stats stats; 1506 unsigned int i = 0, j = 0, qid; 1507 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1508 struct qede_tx_queue *txq; 1509 1510 ecore_get_vport_stats(edev, &stats); 1511 1512 /* RX Stats */ 1513 eth_stats->ipackets = stats.common.rx_ucast_pkts + 1514 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts; 1515 1516 eth_stats->ibytes = stats.common.rx_ucast_bytes + 1517 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes; 1518 1519 eth_stats->ierrors = stats.common.rx_crc_errors + 1520 stats.common.rx_align_errors + 1521 stats.common.rx_carrier_errors + 1522 stats.common.rx_oversize_packets + 1523 stats.common.rx_jabbers + stats.common.rx_undersize_packets; 1524 1525 eth_stats->rx_nombuf = stats.common.no_buff_discards; 1526 1527 eth_stats->imissed = stats.common.mftag_filter_discards + 1528 stats.common.mac_filter_discards + 1529 stats.common.no_buff_discards + 1530 stats.common.brb_truncates + stats.common.brb_discards; 1531 1532 /* TX stats */ 1533 eth_stats->opackets = stats.common.tx_ucast_pkts + 1534 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts; 1535 1536 eth_stats->obytes = stats.common.tx_ucast_bytes + 1537 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes; 1538 1539 eth_stats->oerrors = stats.common.tx_err_drop_pkts; 1540 1541 /* Queue stats */ 1542 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1543 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1544 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1545 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1546 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) || 1547 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev))) 1548 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1549 "Not all the queue stats will be displayed. Set" 1550 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1551 " appropriately and retry.\n"); 1552 1553 for_each_rss(qid) { 1554 eth_stats->q_ipackets[i] = 1555 *(uint64_t *)( 1556 ((char *)(qdev->fp_array[qid].rxq)) + 1557 offsetof(struct qede_rx_queue, 1558 rcv_pkts)); 1559 eth_stats->q_errors[i] = 1560 *(uint64_t *)( 1561 ((char *)(qdev->fp_array[qid].rxq)) + 1562 offsetof(struct qede_rx_queue, 1563 rx_hw_errors)) + 1564 *(uint64_t *)( 1565 ((char *)(qdev->fp_array[qid].rxq)) + 1566 offsetof(struct qede_rx_queue, 1567 rx_alloc_errors)); 1568 i++; 1569 if (i == rxq_stat_cntrs) 1570 break; 1571 } 1572 1573 for_each_tss(qid) { 1574 txq = qdev->fp_array[qid].txq; 1575 eth_stats->q_opackets[j] = 1576 *((uint64_t *)(uintptr_t) 1577 (((uint64_t)(uintptr_t)(txq)) + 1578 offsetof(struct qede_tx_queue, 1579 xmit_pkts))); 1580 j++; 1581 if (j == txq_stat_cntrs) 1582 break; 1583 } 1584 1585 return 0; 1586 } 1587 1588 static unsigned 1589 qede_get_xstats_count(struct qede_dev *qdev) { 1590 if (ECORE_IS_BB(&qdev->edev)) 1591 return RTE_DIM(qede_xstats_strings) + 1592 RTE_DIM(qede_bb_xstats_strings) + 1593 (RTE_DIM(qede_rxq_xstats_strings) * 1594 RTE_MIN(QEDE_RSS_COUNT(qdev), 1595 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1596 else 1597 return RTE_DIM(qede_xstats_strings) + 1598 RTE_DIM(qede_ah_xstats_strings) + 1599 (RTE_DIM(qede_rxq_xstats_strings) * 1600 RTE_MIN(QEDE_RSS_COUNT(qdev), 1601 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1602 } 1603 1604 static int 1605 qede_get_xstats_names(struct rte_eth_dev *dev, 1606 struct rte_eth_xstat_name *xstats_names, 1607 __rte_unused unsigned int limit) 1608 { 1609 struct qede_dev *qdev = dev->data->dev_private; 1610 struct ecore_dev *edev = &qdev->edev; 1611 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1612 unsigned int i, qid, stat_idx = 0; 1613 unsigned int rxq_stat_cntrs; 1614 1615 if (xstats_names != NULL) { 1616 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1617 snprintf(xstats_names[stat_idx].name, 1618 sizeof(xstats_names[stat_idx].name), 1619 "%s", 1620 qede_xstats_strings[i].name); 1621 stat_idx++; 1622 } 1623 1624 if (ECORE_IS_BB(edev)) { 1625 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1626 snprintf(xstats_names[stat_idx].name, 1627 sizeof(xstats_names[stat_idx].name), 1628 "%s", 1629 qede_bb_xstats_strings[i].name); 1630 stat_idx++; 1631 } 1632 } else { 1633 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1634 snprintf(xstats_names[stat_idx].name, 1635 sizeof(xstats_names[stat_idx].name), 1636 "%s", 1637 qede_ah_xstats_strings[i].name); 1638 stat_idx++; 1639 } 1640 } 1641 1642 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1643 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1644 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1645 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1646 snprintf(xstats_names[stat_idx].name, 1647 sizeof(xstats_names[stat_idx].name), 1648 "%.4s%d%s", 1649 qede_rxq_xstats_strings[i].name, qid, 1650 qede_rxq_xstats_strings[i].name + 4); 1651 stat_idx++; 1652 } 1653 } 1654 } 1655 1656 return stat_cnt; 1657 } 1658 1659 static int 1660 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1661 unsigned int n) 1662 { 1663 struct qede_dev *qdev = dev->data->dev_private; 1664 struct ecore_dev *edev = &qdev->edev; 1665 struct ecore_eth_stats stats; 1666 const unsigned int num = qede_get_xstats_count(qdev); 1667 unsigned int i, qid, stat_idx = 0; 1668 unsigned int rxq_stat_cntrs; 1669 1670 if (n < num) 1671 return num; 1672 1673 ecore_get_vport_stats(edev, &stats); 1674 1675 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1676 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1677 qede_xstats_strings[i].offset); 1678 xstats[stat_idx].id = stat_idx; 1679 stat_idx++; 1680 } 1681 1682 if (ECORE_IS_BB(edev)) { 1683 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1684 xstats[stat_idx].value = 1685 *(uint64_t *)(((char *)&stats) + 1686 qede_bb_xstats_strings[i].offset); 1687 xstats[stat_idx].id = stat_idx; 1688 stat_idx++; 1689 } 1690 } else { 1691 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1692 xstats[stat_idx].value = 1693 *(uint64_t *)(((char *)&stats) + 1694 qede_ah_xstats_strings[i].offset); 1695 xstats[stat_idx].id = stat_idx; 1696 stat_idx++; 1697 } 1698 } 1699 1700 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1701 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1702 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1703 for_each_rss(qid) { 1704 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1705 xstats[stat_idx].value = *(uint64_t *)( 1706 ((char *)(qdev->fp_array[qid].rxq)) + 1707 qede_rxq_xstats_strings[i].offset); 1708 xstats[stat_idx].id = stat_idx; 1709 stat_idx++; 1710 } 1711 } 1712 } 1713 1714 return stat_idx; 1715 } 1716 1717 static void 1718 qede_reset_xstats(struct rte_eth_dev *dev) 1719 { 1720 struct qede_dev *qdev = dev->data->dev_private; 1721 struct ecore_dev *edev = &qdev->edev; 1722 1723 ecore_reset_vport_stats(edev); 1724 } 1725 1726 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1727 { 1728 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1729 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1730 struct qed_link_params link_params; 1731 int rc; 1732 1733 DP_INFO(edev, "setting link state %d\n", link_up); 1734 memset(&link_params, 0, sizeof(link_params)); 1735 link_params.link_up = link_up; 1736 rc = qdev->ops->common->set_link(edev, &link_params); 1737 if (rc != ECORE_SUCCESS) 1738 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1739 1740 return rc; 1741 } 1742 1743 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1744 { 1745 return qede_dev_set_link_state(eth_dev, true); 1746 } 1747 1748 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1749 { 1750 return qede_dev_set_link_state(eth_dev, false); 1751 } 1752 1753 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1754 { 1755 struct qede_dev *qdev = eth_dev->data->dev_private; 1756 struct ecore_dev *edev = &qdev->edev; 1757 1758 ecore_reset_vport_stats(edev); 1759 } 1760 1761 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 1762 { 1763 enum qed_filter_rx_mode_type type = 1764 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1765 1766 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1767 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 1768 1769 qed_configure_filter_rx_mode(eth_dev, type); 1770 } 1771 1772 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 1773 { 1774 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 1775 qed_configure_filter_rx_mode(eth_dev, 1776 QED_FILTER_RX_MODE_TYPE_PROMISC); 1777 else 1778 qed_configure_filter_rx_mode(eth_dev, 1779 QED_FILTER_RX_MODE_TYPE_REGULAR); 1780 } 1781 1782 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1783 struct rte_eth_fc_conf *fc_conf) 1784 { 1785 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1786 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1787 struct qed_link_output current_link; 1788 struct qed_link_params params; 1789 1790 memset(¤t_link, 0, sizeof(current_link)); 1791 qdev->ops->common->get_link(edev, ¤t_link); 1792 1793 memset(¶ms, 0, sizeof(params)); 1794 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 1795 if (fc_conf->autoneg) { 1796 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 1797 DP_ERR(edev, "Autoneg not supported\n"); 1798 return -EINVAL; 1799 } 1800 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 1801 } 1802 1803 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 1804 if (fc_conf->mode == RTE_FC_FULL) 1805 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 1806 QED_LINK_PAUSE_RX_ENABLE); 1807 if (fc_conf->mode == RTE_FC_TX_PAUSE) 1808 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 1809 if (fc_conf->mode == RTE_FC_RX_PAUSE) 1810 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 1811 1812 params.link_up = true; 1813 (void)qdev->ops->common->set_link(edev, ¶ms); 1814 1815 return 0; 1816 } 1817 1818 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1819 struct rte_eth_fc_conf *fc_conf) 1820 { 1821 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1822 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1823 struct qed_link_output current_link; 1824 1825 memset(¤t_link, 0, sizeof(current_link)); 1826 qdev->ops->common->get_link(edev, ¤t_link); 1827 1828 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 1829 fc_conf->autoneg = true; 1830 1831 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 1832 QED_LINK_PAUSE_TX_ENABLE)) 1833 fc_conf->mode = RTE_FC_FULL; 1834 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 1835 fc_conf->mode = RTE_FC_RX_PAUSE; 1836 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 1837 fc_conf->mode = RTE_FC_TX_PAUSE; 1838 else 1839 fc_conf->mode = RTE_FC_NONE; 1840 1841 return 0; 1842 } 1843 1844 static const uint32_t * 1845 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1846 { 1847 static const uint32_t ptypes[] = { 1848 RTE_PTYPE_L2_ETHER, 1849 RTE_PTYPE_L2_ETHER_VLAN, 1850 RTE_PTYPE_L3_IPV4, 1851 RTE_PTYPE_L3_IPV6, 1852 RTE_PTYPE_L4_TCP, 1853 RTE_PTYPE_L4_UDP, 1854 RTE_PTYPE_TUNNEL_VXLAN, 1855 RTE_PTYPE_L4_FRAG, 1856 /* Inner */ 1857 RTE_PTYPE_INNER_L2_ETHER, 1858 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1859 RTE_PTYPE_INNER_L3_IPV4, 1860 RTE_PTYPE_INNER_L3_IPV6, 1861 RTE_PTYPE_INNER_L4_TCP, 1862 RTE_PTYPE_INNER_L4_UDP, 1863 RTE_PTYPE_INNER_L4_FRAG, 1864 RTE_PTYPE_UNKNOWN 1865 }; 1866 1867 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 1868 return ptypes; 1869 1870 return NULL; 1871 } 1872 1873 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 1874 { 1875 *rss_caps = 0; 1876 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 1877 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 1878 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 1879 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 1880 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 1881 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 1882 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 1883 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 1884 } 1885 1886 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 1887 struct rte_eth_rss_conf *rss_conf) 1888 { 1889 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1890 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1891 struct ecore_sp_vport_update_params vport_update_params; 1892 struct ecore_rss_params rss_params; 1893 struct ecore_hwfn *p_hwfn; 1894 uint32_t *key = (uint32_t *)rss_conf->rss_key; 1895 uint64_t hf = rss_conf->rss_hf; 1896 uint8_t len = rss_conf->rss_key_len; 1897 uint8_t idx; 1898 uint8_t i; 1899 int rc; 1900 1901 memset(&vport_update_params, 0, sizeof(vport_update_params)); 1902 memset(&rss_params, 0, sizeof(rss_params)); 1903 1904 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 1905 (unsigned long)hf, len, key); 1906 1907 if (hf != 0) { 1908 /* Enabling RSS */ 1909 DP_INFO(edev, "Enabling rss\n"); 1910 1911 /* RSS caps */ 1912 qede_init_rss_caps(&rss_params.rss_caps, hf); 1913 rss_params.update_rss_capabilities = 1; 1914 1915 /* RSS hash key */ 1916 if (key) { 1917 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 1918 DP_ERR(edev, "RSS key length exceeds limit\n"); 1919 return -EINVAL; 1920 } 1921 DP_INFO(edev, "Applying user supplied hash key\n"); 1922 rss_params.update_rss_key = 1; 1923 memcpy(&rss_params.rss_key, key, len); 1924 } 1925 rss_params.rss_enable = 1; 1926 } 1927 1928 rss_params.update_rss_config = 1; 1929 /* tbl_size has to be set with capabilities */ 1930 rss_params.rss_table_size_log = 7; 1931 vport_update_params.vport_id = 0; 1932 /* pass the L2 handles instead of qids */ 1933 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 1934 idx = qdev->rss_ind_table[i]; 1935 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 1936 } 1937 vport_update_params.rss_params = &rss_params; 1938 1939 for_each_hwfn(edev, i) { 1940 p_hwfn = &edev->hwfns[i]; 1941 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1942 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 1943 ECORE_SPQ_MODE_EBLOCK, NULL); 1944 if (rc) { 1945 DP_ERR(edev, "vport-update for RSS failed\n"); 1946 return rc; 1947 } 1948 } 1949 qdev->rss_enable = rss_params.rss_enable; 1950 1951 /* Update local structure for hash query */ 1952 qdev->rss_conf.rss_hf = hf; 1953 qdev->rss_conf.rss_key_len = len; 1954 if (qdev->rss_enable) { 1955 if (qdev->rss_conf.rss_key == NULL) { 1956 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 1957 if (qdev->rss_conf.rss_key == NULL) { 1958 DP_ERR(edev, "No memory to store RSS key\n"); 1959 return -ENOMEM; 1960 } 1961 } 1962 if (key && len) { 1963 DP_INFO(edev, "Storing RSS key\n"); 1964 memcpy(qdev->rss_conf.rss_key, key, len); 1965 } 1966 } else if (!qdev->rss_enable && len == 0) { 1967 if (qdev->rss_conf.rss_key) { 1968 free(qdev->rss_conf.rss_key); 1969 qdev->rss_conf.rss_key = NULL; 1970 DP_INFO(edev, "Free RSS key\n"); 1971 } 1972 } 1973 1974 return 0; 1975 } 1976 1977 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 1978 struct rte_eth_rss_conf *rss_conf) 1979 { 1980 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1981 1982 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 1983 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 1984 1985 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 1986 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 1987 rss_conf->rss_key_len); 1988 return 0; 1989 } 1990 1991 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev, 1992 struct ecore_rss_params *rss) 1993 { 1994 int i, fn; 1995 bool rss_mode = 1; /* enable */ 1996 struct ecore_queue_cid *cid; 1997 struct ecore_rss_params *t_rss; 1998 1999 /* In regular scenario, we'd simply need to take input handlers. 2000 * But in CMT, we'd have to split the handlers according to the 2001 * engine they were configured on. We'd then have to understand 2002 * whether RSS is really required, since 2-queues on CMT doesn't 2003 * require RSS. 2004 */ 2005 2006 /* CMT should be round-robin */ 2007 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 2008 cid = rss->rss_ind_table[i]; 2009 2010 if (cid->p_owner == ECORE_LEADING_HWFN(edev)) 2011 t_rss = &rss[0]; 2012 else 2013 t_rss = &rss[1]; 2014 2015 t_rss->rss_ind_table[i / edev->num_hwfns] = cid; 2016 } 2017 2018 t_rss = &rss[1]; 2019 t_rss->update_rss_ind_table = 1; 2020 t_rss->rss_table_size_log = 7; 2021 t_rss->update_rss_config = 1; 2022 2023 /* Make sure RSS is actually required */ 2024 for_each_hwfn(edev, fn) { 2025 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns; 2026 i++) { 2027 if (rss[fn].rss_ind_table[i] != 2028 rss[fn].rss_ind_table[0]) 2029 break; 2030 } 2031 2032 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) { 2033 DP_INFO(edev, 2034 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2035 rss_mode = 0; 2036 goto out; 2037 } 2038 } 2039 2040 out: 2041 t_rss->rss_enable = rss_mode; 2042 2043 return rss_mode; 2044 } 2045 2046 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 2047 struct rte_eth_rss_reta_entry64 *reta_conf, 2048 uint16_t reta_size) 2049 { 2050 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2051 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2052 struct ecore_sp_vport_update_params vport_update_params; 2053 struct ecore_rss_params *params; 2054 struct ecore_hwfn *p_hwfn; 2055 uint16_t i, idx, shift; 2056 uint8_t entry; 2057 int rc = 0; 2058 2059 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2060 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 2061 reta_size); 2062 return -EINVAL; 2063 } 2064 2065 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2066 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns, 2067 RTE_CACHE_LINE_SIZE); 2068 if (params == NULL) { 2069 DP_ERR(edev, "failed to allocate memory\n"); 2070 return -ENOMEM; 2071 } 2072 2073 for (i = 0; i < reta_size; i++) { 2074 idx = i / RTE_RETA_GROUP_SIZE; 2075 shift = i % RTE_RETA_GROUP_SIZE; 2076 if (reta_conf[idx].mask & (1ULL << shift)) { 2077 entry = reta_conf[idx].reta[shift]; 2078 /* Pass rxq handles to ecore */ 2079 params->rss_ind_table[i] = 2080 qdev->fp_array[entry].rxq->handle; 2081 /* Update the local copy for RETA query command */ 2082 qdev->rss_ind_table[i] = entry; 2083 } 2084 } 2085 2086 params->update_rss_ind_table = 1; 2087 params->rss_table_size_log = 7; 2088 params->update_rss_config = 1; 2089 2090 /* Fix up RETA for CMT mode device */ 2091 if (ECORE_IS_CMT(edev)) 2092 qdev->rss_enable = qede_update_rss_parm_cmt(edev, 2093 params); 2094 vport_update_params.vport_id = 0; 2095 /* Use the current value of rss_enable */ 2096 params->rss_enable = qdev->rss_enable; 2097 vport_update_params.rss_params = params; 2098 2099 for_each_hwfn(edev, i) { 2100 p_hwfn = &edev->hwfns[i]; 2101 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2102 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2103 ECORE_SPQ_MODE_EBLOCK, NULL); 2104 if (rc) { 2105 DP_ERR(edev, "vport-update for RSS failed\n"); 2106 goto out; 2107 } 2108 } 2109 2110 out: 2111 rte_free(params); 2112 return rc; 2113 } 2114 2115 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 2116 struct rte_eth_rss_reta_entry64 *reta_conf, 2117 uint16_t reta_size) 2118 { 2119 struct qede_dev *qdev = eth_dev->data->dev_private; 2120 struct ecore_dev *edev = &qdev->edev; 2121 uint16_t i, idx, shift; 2122 uint8_t entry; 2123 2124 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2125 DP_ERR(edev, "reta_size %d is not supported\n", 2126 reta_size); 2127 return -EINVAL; 2128 } 2129 2130 for (i = 0; i < reta_size; i++) { 2131 idx = i / RTE_RETA_GROUP_SIZE; 2132 shift = i % RTE_RETA_GROUP_SIZE; 2133 if (reta_conf[idx].mask & (1ULL << shift)) { 2134 entry = qdev->rss_ind_table[i]; 2135 reta_conf[idx].reta[shift] = entry; 2136 } 2137 } 2138 2139 return 0; 2140 } 2141 2142 2143 2144 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 2145 { 2146 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 2147 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2148 struct rte_eth_dev_info dev_info = {0}; 2149 struct qede_fastpath *fp; 2150 uint32_t frame_size; 2151 uint16_t rx_buf_size; 2152 uint16_t bufsz; 2153 int i; 2154 2155 PMD_INIT_FUNC_TRACE(edev); 2156 qede_dev_info_get(dev, &dev_info); 2157 frame_size = mtu + QEDE_ETH_OVERHEAD; 2158 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { 2159 DP_ERR(edev, "MTU %u out of range\n", mtu); 2160 return -EINVAL; 2161 } 2162 if (!dev->data->scattered_rx && 2163 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2164 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2165 dev->data->min_rx_buf_size); 2166 return -EINVAL; 2167 } 2168 /* Temporarily replace I/O functions with dummy ones. It cannot 2169 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 2170 */ 2171 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 2172 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 2173 qede_dev_stop(dev); 2174 rte_delay_ms(1000); 2175 qdev->mtu = mtu; 2176 /* Fix up RX buf size for all queues of the port */ 2177 for_each_rss(i) { 2178 fp = &qdev->fp_array[i]; 2179 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2180 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2181 if (dev->data->scattered_rx) 2182 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD; 2183 else 2184 rx_buf_size = mtu + QEDE_ETH_OVERHEAD; 2185 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); 2186 fp->rxq->rx_buf_size = rx_buf_size; 2187 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size); 2188 } 2189 qede_dev_start(dev); 2190 if (frame_size > ETHER_MAX_LEN) 2191 dev->data->dev_conf.rxmode.jumbo_frame = 1; 2192 else 2193 dev->data->dev_conf.rxmode.jumbo_frame = 0; 2194 /* update max frame size */ 2195 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2196 /* Reassign back */ 2197 dev->rx_pkt_burst = qede_recv_pkts; 2198 dev->tx_pkt_burst = qede_xmit_pkts; 2199 2200 return 0; 2201 } 2202 2203 static int 2204 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev, 2205 struct rte_eth_udp_tunnel *tunnel_udp, 2206 bool add) 2207 { 2208 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2209 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2210 struct ecore_tunnel_info tunn; /* @DPDK */ 2211 struct ecore_hwfn *p_hwfn; 2212 struct ecore_ptt *p_ptt; 2213 uint16_t udp_port; 2214 int rc, i; 2215 2216 PMD_INIT_FUNC_TRACE(edev); 2217 2218 memset(&tunn, 0, sizeof(tunn)); 2219 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) { 2220 /* Enable VxLAN tunnel if needed before UDP port update using 2221 * default MAC/VLAN classification. 2222 */ 2223 if (add) { 2224 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) { 2225 DP_INFO(edev, 2226 "UDP port %u was already configured\n", 2227 tunnel_udp->udp_port); 2228 return ECORE_SUCCESS; 2229 } 2230 /* Enable VXLAN if it was not enabled while adding 2231 * VXLAN filter. 2232 */ 2233 if (!qdev->vxlan.enable) { 2234 rc = qede_vxlan_enable(eth_dev, 2235 ECORE_TUNN_CLSS_MAC_VLAN, true, true); 2236 if (rc != ECORE_SUCCESS) { 2237 DP_ERR(edev, "Failed to enable VXLAN " 2238 "prior to updating UDP port\n"); 2239 return rc; 2240 } 2241 } 2242 udp_port = tunnel_udp->udp_port; 2243 } else { 2244 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) { 2245 DP_ERR(edev, "UDP port %u doesn't exist\n", 2246 tunnel_udp->udp_port); 2247 return ECORE_INVAL; 2248 } 2249 udp_port = 0; 2250 } 2251 2252 tunn.vxlan_port.b_update_port = true; 2253 tunn.vxlan_port.port = udp_port; 2254 for_each_hwfn(edev, i) { 2255 p_hwfn = &edev->hwfns[i]; 2256 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL; 2257 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn, 2258 ECORE_SPQ_MODE_CB, NULL); 2259 if (rc != ECORE_SUCCESS) { 2260 DP_ERR(edev, "Unable to config UDP port %u\n", 2261 tunn.vxlan_port.port); 2262 if (IS_PF(edev)) 2263 ecore_ptt_release(p_hwfn, p_ptt); 2264 return rc; 2265 } 2266 } 2267 2268 qdev->vxlan.udp_port = udp_port; 2269 /* If the request is to delete UDP port and if the number of 2270 * VXLAN filters have reached 0 then VxLAN offload can be be 2271 * disabled. 2272 */ 2273 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0) 2274 return qede_vxlan_enable(eth_dev, 2275 ECORE_TUNN_CLSS_MAC_VLAN, false, true); 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int 2282 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 2283 struct rte_eth_udp_tunnel *tunnel_udp) 2284 { 2285 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false); 2286 } 2287 2288 static int 2289 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 2290 struct rte_eth_udp_tunnel *tunnel_udp) 2291 { 2292 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true); 2293 } 2294 2295 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 2296 uint32_t *clss, char *str) 2297 { 2298 uint16_t j; 2299 *clss = MAX_ECORE_TUNN_CLSS; 2300 2301 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 2302 if (filter == qede_tunn_types[j].rte_filter_type) { 2303 *type = qede_tunn_types[j].qede_type; 2304 *clss = qede_tunn_types[j].qede_tunn_clss; 2305 strcpy(str, qede_tunn_types[j].string); 2306 return; 2307 } 2308 } 2309 } 2310 2311 static int 2312 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 2313 const struct rte_eth_tunnel_filter_conf *conf, 2314 uint32_t type) 2315 { 2316 /* Init commmon ucast params first */ 2317 qede_set_ucast_cmn_params(ucast); 2318 2319 /* Copy out the required fields based on classification type */ 2320 ucast->type = type; 2321 2322 switch (type) { 2323 case ECORE_FILTER_VNI: 2324 ucast->vni = conf->tenant_id; 2325 break; 2326 case ECORE_FILTER_INNER_VLAN: 2327 ucast->vlan = conf->inner_vlan; 2328 break; 2329 case ECORE_FILTER_MAC: 2330 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2331 ETHER_ADDR_LEN); 2332 break; 2333 case ECORE_FILTER_INNER_MAC: 2334 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2335 ETHER_ADDR_LEN); 2336 break; 2337 case ECORE_FILTER_MAC_VNI_PAIR: 2338 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2339 ETHER_ADDR_LEN); 2340 ucast->vni = conf->tenant_id; 2341 break; 2342 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 2343 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2344 ETHER_ADDR_LEN); 2345 ucast->vni = conf->tenant_id; 2346 break; 2347 case ECORE_FILTER_INNER_PAIR: 2348 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2349 ETHER_ADDR_LEN); 2350 ucast->vlan = conf->inner_vlan; 2351 break; 2352 default: 2353 return -EINVAL; 2354 } 2355 2356 return ECORE_SUCCESS; 2357 } 2358 2359 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev, 2360 enum rte_filter_op filter_op, 2361 const struct rte_eth_tunnel_filter_conf *conf) 2362 { 2363 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2364 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2365 enum ecore_filter_ucast_type type; 2366 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS; 2367 struct ecore_filter_ucast ucast = {0}; 2368 char str[80]; 2369 uint16_t filter_type = 0; 2370 int rc; 2371 2372 PMD_INIT_FUNC_TRACE(edev); 2373 2374 switch (filter_op) { 2375 case RTE_ETH_FILTER_ADD: 2376 if (IS_VF(edev)) 2377 return qede_vxlan_enable(eth_dev, 2378 ECORE_TUNN_CLSS_MAC_VLAN, true, true); 2379 2380 filter_type = conf->filter_type; 2381 /* Determine if the given filter classification is supported */ 2382 qede_get_ecore_tunn_params(filter_type, &type, &clss, str); 2383 if (clss == MAX_ECORE_TUNN_CLSS) { 2384 DP_ERR(edev, "Unsupported filter type\n"); 2385 return -EINVAL; 2386 } 2387 /* Init tunnel ucast params */ 2388 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2389 if (rc != ECORE_SUCCESS) { 2390 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n", 2391 conf->filter_type); 2392 return rc; 2393 } 2394 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2395 str, filter_op, ucast.type); 2396 2397 ucast.opcode = ECORE_FILTER_ADD; 2398 2399 /* Skip MAC/VLAN if filter is based on VNI */ 2400 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2401 rc = qede_mac_int_ops(eth_dev, &ucast, 1); 2402 if (rc == 0) { 2403 /* Enable accept anyvlan */ 2404 qede_config_accept_any_vlan(qdev, true); 2405 } 2406 } else { 2407 rc = qede_ucast_filter(eth_dev, &ucast, 1); 2408 if (rc == 0) 2409 rc = ecore_filter_ucast_cmd(edev, &ucast, 2410 ECORE_SPQ_MODE_CB, NULL); 2411 } 2412 2413 if (rc != ECORE_SUCCESS) 2414 return rc; 2415 2416 qdev->vxlan.num_filters++; 2417 qdev->vxlan.filter_type = filter_type; 2418 if (!qdev->vxlan.enable) 2419 return qede_vxlan_enable(eth_dev, clss, true, true); 2420 2421 break; 2422 case RTE_ETH_FILTER_DELETE: 2423 if (IS_VF(edev)) 2424 return qede_vxlan_enable(eth_dev, 2425 ECORE_TUNN_CLSS_MAC_VLAN, false, true); 2426 2427 filter_type = conf->filter_type; 2428 /* Determine if the given filter classification is supported */ 2429 qede_get_ecore_tunn_params(filter_type, &type, &clss, str); 2430 if (clss == MAX_ECORE_TUNN_CLSS) { 2431 DP_ERR(edev, "Unsupported filter type\n"); 2432 return -EINVAL; 2433 } 2434 /* Init tunnel ucast params */ 2435 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2436 if (rc != ECORE_SUCCESS) { 2437 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n", 2438 conf->filter_type); 2439 return rc; 2440 } 2441 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2442 str, filter_op, ucast.type); 2443 2444 ucast.opcode = ECORE_FILTER_REMOVE; 2445 2446 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2447 rc = qede_mac_int_ops(eth_dev, &ucast, 0); 2448 } else { 2449 rc = qede_ucast_filter(eth_dev, &ucast, 0); 2450 if (rc == 0) 2451 rc = ecore_filter_ucast_cmd(edev, &ucast, 2452 ECORE_SPQ_MODE_CB, NULL); 2453 } 2454 if (rc != ECORE_SUCCESS) 2455 return rc; 2456 2457 qdev->vxlan.num_filters--; 2458 2459 /* Disable VXLAN if VXLAN filters become 0 */ 2460 if (qdev->vxlan.num_filters == 0) 2461 return qede_vxlan_enable(eth_dev, clss, false, true); 2462 break; 2463 default: 2464 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 2465 return -EINVAL; 2466 } 2467 2468 return 0; 2469 } 2470 2471 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 2472 enum rte_filter_type filter_type, 2473 enum rte_filter_op filter_op, 2474 void *arg) 2475 { 2476 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2477 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2478 struct rte_eth_tunnel_filter_conf *filter_conf = 2479 (struct rte_eth_tunnel_filter_conf *)arg; 2480 2481 switch (filter_type) { 2482 case RTE_ETH_FILTER_TUNNEL: 2483 switch (filter_conf->tunnel_type) { 2484 case RTE_TUNNEL_TYPE_VXLAN: 2485 DP_INFO(edev, 2486 "Packet steering to the specified Rx queue" 2487 " is not supported with VXLAN tunneling"); 2488 return(qede_vxlan_tunn_config(eth_dev, filter_op, 2489 filter_conf)); 2490 /* Place holders for future tunneling support */ 2491 case RTE_TUNNEL_TYPE_GENEVE: 2492 case RTE_TUNNEL_TYPE_TEREDO: 2493 case RTE_TUNNEL_TYPE_NVGRE: 2494 case RTE_TUNNEL_TYPE_IP_IN_GRE: 2495 case RTE_L2_TUNNEL_TYPE_E_TAG: 2496 DP_ERR(edev, "Unsupported tunnel type %d\n", 2497 filter_conf->tunnel_type); 2498 return -EINVAL; 2499 case RTE_TUNNEL_TYPE_NONE: 2500 default: 2501 return 0; 2502 } 2503 break; 2504 case RTE_ETH_FILTER_FDIR: 2505 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 2506 case RTE_ETH_FILTER_NTUPLE: 2507 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 2508 case RTE_ETH_FILTER_MACVLAN: 2509 case RTE_ETH_FILTER_ETHERTYPE: 2510 case RTE_ETH_FILTER_FLEXIBLE: 2511 case RTE_ETH_FILTER_SYN: 2512 case RTE_ETH_FILTER_HASH: 2513 case RTE_ETH_FILTER_L2_TUNNEL: 2514 case RTE_ETH_FILTER_MAX: 2515 default: 2516 DP_ERR(edev, "Unsupported filter type %d\n", 2517 filter_type); 2518 return -EINVAL; 2519 } 2520 2521 return 0; 2522 } 2523 2524 static const struct eth_dev_ops qede_eth_dev_ops = { 2525 .dev_configure = qede_dev_configure, 2526 .dev_infos_get = qede_dev_info_get, 2527 .rx_queue_setup = qede_rx_queue_setup, 2528 .rx_queue_release = qede_rx_queue_release, 2529 .tx_queue_setup = qede_tx_queue_setup, 2530 .tx_queue_release = qede_tx_queue_release, 2531 .dev_start = qede_dev_start, 2532 .dev_set_link_up = qede_dev_set_link_up, 2533 .dev_set_link_down = qede_dev_set_link_down, 2534 .link_update = qede_link_update, 2535 .promiscuous_enable = qede_promiscuous_enable, 2536 .promiscuous_disable = qede_promiscuous_disable, 2537 .allmulticast_enable = qede_allmulticast_enable, 2538 .allmulticast_disable = qede_allmulticast_disable, 2539 .dev_stop = qede_dev_stop, 2540 .dev_close = qede_dev_close, 2541 .stats_get = qede_get_stats, 2542 .stats_reset = qede_reset_stats, 2543 .xstats_get = qede_get_xstats, 2544 .xstats_reset = qede_reset_xstats, 2545 .xstats_get_names = qede_get_xstats_names, 2546 .mac_addr_add = qede_mac_addr_add, 2547 .mac_addr_remove = qede_mac_addr_remove, 2548 .mac_addr_set = qede_mac_addr_set, 2549 .vlan_offload_set = qede_vlan_offload_set, 2550 .vlan_filter_set = qede_vlan_filter_set, 2551 .flow_ctrl_set = qede_flow_ctrl_set, 2552 .flow_ctrl_get = qede_flow_ctrl_get, 2553 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2554 .rss_hash_update = qede_rss_hash_update, 2555 .rss_hash_conf_get = qede_rss_hash_conf_get, 2556 .reta_update = qede_rss_reta_update, 2557 .reta_query = qede_rss_reta_query, 2558 .mtu_set = qede_set_mtu, 2559 .filter_ctrl = qede_dev_filter_ctrl, 2560 .udp_tunnel_port_add = qede_udp_dst_port_add, 2561 .udp_tunnel_port_del = qede_udp_dst_port_del, 2562 }; 2563 2564 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 2565 .dev_configure = qede_dev_configure, 2566 .dev_infos_get = qede_dev_info_get, 2567 .rx_queue_setup = qede_rx_queue_setup, 2568 .rx_queue_release = qede_rx_queue_release, 2569 .tx_queue_setup = qede_tx_queue_setup, 2570 .tx_queue_release = qede_tx_queue_release, 2571 .dev_start = qede_dev_start, 2572 .dev_set_link_up = qede_dev_set_link_up, 2573 .dev_set_link_down = qede_dev_set_link_down, 2574 .link_update = qede_link_update, 2575 .promiscuous_enable = qede_promiscuous_enable, 2576 .promiscuous_disable = qede_promiscuous_disable, 2577 .allmulticast_enable = qede_allmulticast_enable, 2578 .allmulticast_disable = qede_allmulticast_disable, 2579 .dev_stop = qede_dev_stop, 2580 .dev_close = qede_dev_close, 2581 .stats_get = qede_get_stats, 2582 .stats_reset = qede_reset_stats, 2583 .xstats_get = qede_get_xstats, 2584 .xstats_reset = qede_reset_xstats, 2585 .xstats_get_names = qede_get_xstats_names, 2586 .vlan_offload_set = qede_vlan_offload_set, 2587 .vlan_filter_set = qede_vlan_filter_set, 2588 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2589 .rss_hash_update = qede_rss_hash_update, 2590 .rss_hash_conf_get = qede_rss_hash_conf_get, 2591 .reta_update = qede_rss_reta_update, 2592 .reta_query = qede_rss_reta_query, 2593 .mtu_set = qede_set_mtu, 2594 .udp_tunnel_port_add = qede_udp_dst_port_add, 2595 .udp_tunnel_port_del = qede_udp_dst_port_del, 2596 }; 2597 2598 static void qede_update_pf_params(struct ecore_dev *edev) 2599 { 2600 struct ecore_pf_params pf_params; 2601 2602 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 2603 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 2604 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 2605 qed_ops->common->update_pf_params(edev, &pf_params); 2606 } 2607 2608 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 2609 { 2610 struct rte_pci_device *pci_dev; 2611 struct rte_pci_addr pci_addr; 2612 struct qede_dev *adapter; 2613 struct ecore_dev *edev; 2614 struct qed_dev_eth_info dev_info; 2615 struct qed_slowpath_params params; 2616 static bool do_once = true; 2617 uint8_t bulletin_change; 2618 uint8_t vf_mac[ETHER_ADDR_LEN]; 2619 uint8_t is_mac_forced; 2620 bool is_mac_exist; 2621 /* Fix up ecore debug level */ 2622 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 2623 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 2624 int rc; 2625 2626 /* Extract key data structures */ 2627 adapter = eth_dev->data->dev_private; 2628 edev = &adapter->edev; 2629 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2630 pci_addr = pci_dev->addr; 2631 2632 PMD_INIT_FUNC_TRACE(edev); 2633 2634 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 2635 pci_addr.bus, pci_addr.devid, pci_addr.function, 2636 eth_dev->data->port_id); 2637 2638 eth_dev->rx_pkt_burst = qede_recv_pkts; 2639 eth_dev->tx_pkt_burst = qede_xmit_pkts; 2640 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 2641 2642 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2643 DP_ERR(edev, "Skipping device init from secondary process\n"); 2644 return 0; 2645 } 2646 2647 rte_eth_copy_pci_info(eth_dev, pci_dev); 2648 2649 /* @DPDK */ 2650 edev->vendor_id = pci_dev->id.vendor_id; 2651 edev->device_id = pci_dev->id.device_id; 2652 2653 qed_ops = qed_get_eth_ops(); 2654 if (!qed_ops) { 2655 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 2656 return -EINVAL; 2657 } 2658 2659 DP_INFO(edev, "Starting qede probe\n"); 2660 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 2661 dp_level, is_vf); 2662 if (rc != 0) { 2663 DP_ERR(edev, "qede probe failed rc %d\n", rc); 2664 return -ENODEV; 2665 } 2666 qede_update_pf_params(edev); 2667 rte_intr_callback_register(&pci_dev->intr_handle, 2668 qede_interrupt_handler, (void *)eth_dev); 2669 if (rte_intr_enable(&pci_dev->intr_handle)) { 2670 DP_ERR(edev, "rte_intr_enable() failed\n"); 2671 return -ENODEV; 2672 } 2673 2674 /* Start the Slowpath-process */ 2675 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 2676 params.int_mode = ECORE_INT_MODE_MSIX; 2677 params.drv_major = QEDE_PMD_VERSION_MAJOR; 2678 params.drv_minor = QEDE_PMD_VERSION_MINOR; 2679 params.drv_rev = QEDE_PMD_VERSION_REVISION; 2680 params.drv_eng = QEDE_PMD_VERSION_PATCH; 2681 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 2682 QEDE_PMD_DRV_VER_STR_SIZE); 2683 2684 /* For CMT mode device do periodic polling for slowpath events. 2685 * This is required since uio device uses only one MSI-x 2686 * interrupt vector but we need one for each engine. 2687 */ 2688 if (ECORE_IS_CMT(edev) && IS_PF(edev)) { 2689 rc = rte_eal_alarm_set(timer_period * US_PER_S, 2690 qede_poll_sp_sb_cb, 2691 (void *)eth_dev); 2692 if (rc != 0) { 2693 DP_ERR(edev, "Unable to start periodic" 2694 " timer rc %d\n", rc); 2695 return -EINVAL; 2696 } 2697 } 2698 2699 rc = qed_ops->common->slowpath_start(edev, ¶ms); 2700 if (rc) { 2701 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 2702 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2703 (void *)eth_dev); 2704 return -ENODEV; 2705 } 2706 2707 rc = qed_ops->fill_dev_info(edev, &dev_info); 2708 if (rc) { 2709 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 2710 qed_ops->common->slowpath_stop(edev); 2711 qed_ops->common->remove(edev); 2712 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2713 (void *)eth_dev); 2714 return -ENODEV; 2715 } 2716 2717 qede_alloc_etherdev(adapter, &dev_info); 2718 2719 adapter->ops->common->set_name(edev, edev->name); 2720 2721 if (!is_vf) 2722 adapter->dev_info.num_mac_filters = 2723 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 2724 ECORE_MAC); 2725 else 2726 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 2727 (uint32_t *)&adapter->dev_info.num_mac_filters); 2728 2729 /* Allocate memory for storing MAC addr */ 2730 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 2731 (ETHER_ADDR_LEN * 2732 adapter->dev_info.num_mac_filters), 2733 RTE_CACHE_LINE_SIZE); 2734 2735 if (eth_dev->data->mac_addrs == NULL) { 2736 DP_ERR(edev, "Failed to allocate MAC address\n"); 2737 qed_ops->common->slowpath_stop(edev); 2738 qed_ops->common->remove(edev); 2739 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 2740 (void *)eth_dev); 2741 return -ENOMEM; 2742 } 2743 2744 if (!is_vf) { 2745 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 2746 hw_info.hw_mac_addr, 2747 ð_dev->data->mac_addrs[0]); 2748 ether_addr_copy(ð_dev->data->mac_addrs[0], 2749 &adapter->primary_mac); 2750 } else { 2751 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 2752 &bulletin_change); 2753 if (bulletin_change) { 2754 is_mac_exist = 2755 ecore_vf_bulletin_get_forced_mac( 2756 ECORE_LEADING_HWFN(edev), 2757 vf_mac, 2758 &is_mac_forced); 2759 if (is_mac_exist && is_mac_forced) { 2760 DP_INFO(edev, "VF macaddr received from PF\n"); 2761 ether_addr_copy((struct ether_addr *)&vf_mac, 2762 ð_dev->data->mac_addrs[0]); 2763 ether_addr_copy(ð_dev->data->mac_addrs[0], 2764 &adapter->primary_mac); 2765 } else { 2766 DP_ERR(edev, "No VF macaddr assigned\n"); 2767 } 2768 } 2769 } 2770 2771 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 2772 2773 if (do_once) { 2774 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO 2775 qede_print_adapter_info(adapter); 2776 #endif 2777 do_once = false; 2778 } 2779 2780 adapter->num_tx_queues = 0; 2781 adapter->num_rx_queues = 0; 2782 SLIST_INIT(&adapter->fdir_info.fdir_list_head); 2783 SLIST_INIT(&adapter->vlan_list_head); 2784 SLIST_INIT(&adapter->uc_list_head); 2785 adapter->mtu = ETHER_MTU; 2786 adapter->new_mtu = ETHER_MTU; 2787 if (!is_vf) 2788 if (qede_start_vport(adapter, adapter->mtu)) 2789 return -1; 2790 2791 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 2792 adapter->primary_mac.addr_bytes[0], 2793 adapter->primary_mac.addr_bytes[1], 2794 adapter->primary_mac.addr_bytes[2], 2795 adapter->primary_mac.addr_bytes[3], 2796 adapter->primary_mac.addr_bytes[4], 2797 adapter->primary_mac.addr_bytes[5]); 2798 2799 DP_INFO(edev, "Device initialized\n"); 2800 2801 return 0; 2802 } 2803 2804 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 2805 { 2806 return qede_common_dev_init(eth_dev, 1); 2807 } 2808 2809 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 2810 { 2811 return qede_common_dev_init(eth_dev, 0); 2812 } 2813 2814 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 2815 { 2816 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 2817 struct qede_dev *qdev = eth_dev->data->dev_private; 2818 struct ecore_dev *edev = &qdev->edev; 2819 2820 PMD_INIT_FUNC_TRACE(edev); 2821 #endif 2822 2823 /* only uninitialize in the primary process */ 2824 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2825 return 0; 2826 2827 /* safe to close dev here */ 2828 qede_dev_close(eth_dev); 2829 2830 eth_dev->dev_ops = NULL; 2831 eth_dev->rx_pkt_burst = NULL; 2832 eth_dev->tx_pkt_burst = NULL; 2833 2834 if (eth_dev->data->mac_addrs) 2835 rte_free(eth_dev->data->mac_addrs); 2836 2837 eth_dev->data->mac_addrs = NULL; 2838 2839 return 0; 2840 } 2841 2842 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2843 { 2844 return qede_dev_common_uninit(eth_dev); 2845 } 2846 2847 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 2848 { 2849 return qede_dev_common_uninit(eth_dev); 2850 } 2851 2852 static const struct rte_pci_id pci_id_qedevf_map[] = { 2853 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2854 { 2855 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 2856 }, 2857 { 2858 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 2859 }, 2860 { 2861 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 2862 }, 2863 {.vendor_id = 0,} 2864 }; 2865 2866 static const struct rte_pci_id pci_id_qede_map[] = { 2867 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 2868 { 2869 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 2870 }, 2871 { 2872 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 2873 }, 2874 { 2875 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 2876 }, 2877 { 2878 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 2879 }, 2880 { 2881 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 2882 }, 2883 { 2884 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 2885 }, 2886 { 2887 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 2888 }, 2889 { 2890 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 2891 }, 2892 { 2893 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 2894 }, 2895 { 2896 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 2897 }, 2898 {.vendor_id = 0,} 2899 }; 2900 2901 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2902 struct rte_pci_device *pci_dev) 2903 { 2904 return rte_eth_dev_pci_generic_probe(pci_dev, 2905 sizeof(struct qede_dev), qedevf_eth_dev_init); 2906 } 2907 2908 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2909 { 2910 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 2911 } 2912 2913 static struct rte_pci_driver rte_qedevf_pmd = { 2914 .id_table = pci_id_qedevf_map, 2915 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2916 .probe = qedevf_eth_dev_pci_probe, 2917 .remove = qedevf_eth_dev_pci_remove, 2918 }; 2919 2920 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2921 struct rte_pci_device *pci_dev) 2922 { 2923 return rte_eth_dev_pci_generic_probe(pci_dev, 2924 sizeof(struct qede_dev), qede_eth_dev_init); 2925 } 2926 2927 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 2928 { 2929 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 2930 } 2931 2932 static struct rte_pci_driver rte_qede_pmd = { 2933 .id_table = pci_id_qede_map, 2934 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 2935 .probe = qede_eth_dev_pci_probe, 2936 .remove = qede_eth_dev_pci_remove, 2937 }; 2938 2939 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 2940 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 2941 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 2942 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 2943 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 2944 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 2945