1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #include "qede_ethdev.h" 8 #include <rte_alarm.h> 9 #include <rte_version.h> 10 #include <rte_kvargs.h> 11 12 /* Globals */ 13 int qede_logtype_init; 14 int qede_logtype_driver; 15 16 static const struct qed_eth_ops *qed_ops; 17 #define QEDE_SP_TIMER_PERIOD 10000 /* 100ms */ 18 19 /* VXLAN tunnel classification mapping */ 20 const struct _qede_udp_tunn_types { 21 uint16_t rte_filter_type; 22 enum ecore_filter_ucast_type qede_type; 23 enum ecore_tunn_clss qede_tunn_clss; 24 const char *string; 25 } qede_tunn_types[] = { 26 { 27 ETH_TUNNEL_FILTER_OMAC, 28 ECORE_FILTER_MAC, 29 ECORE_TUNN_CLSS_MAC_VLAN, 30 "outer-mac" 31 }, 32 { 33 ETH_TUNNEL_FILTER_TENID, 34 ECORE_FILTER_VNI, 35 ECORE_TUNN_CLSS_MAC_VNI, 36 "vni" 37 }, 38 { 39 ETH_TUNNEL_FILTER_IMAC, 40 ECORE_FILTER_INNER_MAC, 41 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 42 "inner-mac" 43 }, 44 { 45 ETH_TUNNEL_FILTER_IVLAN, 46 ECORE_FILTER_INNER_VLAN, 47 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 48 "inner-vlan" 49 }, 50 { 51 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID, 52 ECORE_FILTER_MAC_VNI_PAIR, 53 ECORE_TUNN_CLSS_MAC_VNI, 54 "outer-mac and vni" 55 }, 56 { 57 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC, 58 ECORE_FILTER_UNUSED, 59 MAX_ECORE_TUNN_CLSS, 60 "outer-mac and inner-mac" 61 }, 62 { 63 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN, 64 ECORE_FILTER_UNUSED, 65 MAX_ECORE_TUNN_CLSS, 66 "outer-mac and inner-vlan" 67 }, 68 { 69 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC, 70 ECORE_FILTER_INNER_MAC_VNI_PAIR, 71 ECORE_TUNN_CLSS_INNER_MAC_VNI, 72 "vni and inner-mac", 73 }, 74 { 75 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN, 76 ECORE_FILTER_UNUSED, 77 MAX_ECORE_TUNN_CLSS, 78 "vni and inner-vlan", 79 }, 80 { 81 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN, 82 ECORE_FILTER_INNER_PAIR, 83 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 84 "inner-mac and inner-vlan", 85 }, 86 { 87 ETH_TUNNEL_FILTER_OIP, 88 ECORE_FILTER_UNUSED, 89 MAX_ECORE_TUNN_CLSS, 90 "outer-IP" 91 }, 92 { 93 ETH_TUNNEL_FILTER_IIP, 94 ECORE_FILTER_UNUSED, 95 MAX_ECORE_TUNN_CLSS, 96 "inner-IP" 97 }, 98 { 99 RTE_TUNNEL_FILTER_IMAC_IVLAN, 100 ECORE_FILTER_UNUSED, 101 MAX_ECORE_TUNN_CLSS, 102 "IMAC_IVLAN" 103 }, 104 { 105 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID, 106 ECORE_FILTER_UNUSED, 107 MAX_ECORE_TUNN_CLSS, 108 "IMAC_IVLAN_TENID" 109 }, 110 { 111 RTE_TUNNEL_FILTER_IMAC_TENID, 112 ECORE_FILTER_UNUSED, 113 MAX_ECORE_TUNN_CLSS, 114 "IMAC_TENID" 115 }, 116 { 117 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC, 118 ECORE_FILTER_UNUSED, 119 MAX_ECORE_TUNN_CLSS, 120 "OMAC_TENID_IMAC" 121 }, 122 }; 123 124 struct rte_qede_xstats_name_off { 125 char name[RTE_ETH_XSTATS_NAME_SIZE]; 126 uint64_t offset; 127 }; 128 129 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = { 130 {"rx_unicast_bytes", 131 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)}, 132 {"rx_multicast_bytes", 133 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)}, 134 {"rx_broadcast_bytes", 135 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)}, 136 {"rx_unicast_packets", 137 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)}, 138 {"rx_multicast_packets", 139 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)}, 140 {"rx_broadcast_packets", 141 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)}, 142 143 {"tx_unicast_bytes", 144 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)}, 145 {"tx_multicast_bytes", 146 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)}, 147 {"tx_broadcast_bytes", 148 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)}, 149 {"tx_unicast_packets", 150 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)}, 151 {"tx_multicast_packets", 152 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)}, 153 {"tx_broadcast_packets", 154 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)}, 155 156 {"rx_64_byte_packets", 157 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)}, 158 {"rx_65_to_127_byte_packets", 159 offsetof(struct ecore_eth_stats_common, 160 rx_65_to_127_byte_packets)}, 161 {"rx_128_to_255_byte_packets", 162 offsetof(struct ecore_eth_stats_common, 163 rx_128_to_255_byte_packets)}, 164 {"rx_256_to_511_byte_packets", 165 offsetof(struct ecore_eth_stats_common, 166 rx_256_to_511_byte_packets)}, 167 {"rx_512_to_1023_byte_packets", 168 offsetof(struct ecore_eth_stats_common, 169 rx_512_to_1023_byte_packets)}, 170 {"rx_1024_to_1518_byte_packets", 171 offsetof(struct ecore_eth_stats_common, 172 rx_1024_to_1518_byte_packets)}, 173 {"tx_64_byte_packets", 174 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)}, 175 {"tx_65_to_127_byte_packets", 176 offsetof(struct ecore_eth_stats_common, 177 tx_65_to_127_byte_packets)}, 178 {"tx_128_to_255_byte_packets", 179 offsetof(struct ecore_eth_stats_common, 180 tx_128_to_255_byte_packets)}, 181 {"tx_256_to_511_byte_packets", 182 offsetof(struct ecore_eth_stats_common, 183 tx_256_to_511_byte_packets)}, 184 {"tx_512_to_1023_byte_packets", 185 offsetof(struct ecore_eth_stats_common, 186 tx_512_to_1023_byte_packets)}, 187 {"tx_1024_to_1518_byte_packets", 188 offsetof(struct ecore_eth_stats_common, 189 tx_1024_to_1518_byte_packets)}, 190 191 {"rx_mac_crtl_frames", 192 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)}, 193 {"tx_mac_control_frames", 194 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)}, 195 {"rx_pause_frames", 196 offsetof(struct ecore_eth_stats_common, rx_pause_frames)}, 197 {"tx_pause_frames", 198 offsetof(struct ecore_eth_stats_common, tx_pause_frames)}, 199 {"rx_priority_flow_control_frames", 200 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)}, 201 {"tx_priority_flow_control_frames", 202 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)}, 203 204 {"rx_crc_errors", 205 offsetof(struct ecore_eth_stats_common, rx_crc_errors)}, 206 {"rx_align_errors", 207 offsetof(struct ecore_eth_stats_common, rx_align_errors)}, 208 {"rx_carrier_errors", 209 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)}, 210 {"rx_oversize_packet_errors", 211 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)}, 212 {"rx_jabber_errors", 213 offsetof(struct ecore_eth_stats_common, rx_jabbers)}, 214 {"rx_undersize_packet_errors", 215 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)}, 216 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)}, 217 {"rx_host_buffer_not_available", 218 offsetof(struct ecore_eth_stats_common, no_buff_discards)}, 219 /* Number of packets discarded because they are bigger than MTU */ 220 {"rx_packet_too_big_discards", 221 offsetof(struct ecore_eth_stats_common, 222 packet_too_big_discard)}, 223 {"rx_ttl_zero_discards", 224 offsetof(struct ecore_eth_stats_common, ttl0_discard)}, 225 {"rx_multi_function_tag_filter_discards", 226 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)}, 227 {"rx_mac_filter_discards", 228 offsetof(struct ecore_eth_stats_common, mac_filter_discards)}, 229 {"rx_hw_buffer_truncates", 230 offsetof(struct ecore_eth_stats_common, brb_truncates)}, 231 {"rx_hw_buffer_discards", 232 offsetof(struct ecore_eth_stats_common, brb_discards)}, 233 {"tx_error_drop_packets", 234 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)}, 235 236 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)}, 237 {"rx_mac_unicast_packets", 238 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)}, 239 {"rx_mac_multicast_packets", 240 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)}, 241 {"rx_mac_broadcast_packets", 242 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)}, 243 {"rx_mac_frames_ok", 244 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)}, 245 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)}, 246 {"tx_mac_unicast_packets", 247 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)}, 248 {"tx_mac_multicast_packets", 249 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)}, 250 {"tx_mac_broadcast_packets", 251 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)}, 252 253 {"lro_coalesced_packets", 254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)}, 255 {"lro_coalesced_events", 256 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)}, 257 {"lro_aborts_num", 258 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)}, 259 {"lro_not_coalesced_packets", 260 offsetof(struct ecore_eth_stats_common, 261 tpa_not_coalesced_pkts)}, 262 {"lro_coalesced_bytes", 263 offsetof(struct ecore_eth_stats_common, 264 tpa_coalesced_bytes)}, 265 }; 266 267 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = { 268 {"rx_1519_to_1522_byte_packets", 269 offsetof(struct ecore_eth_stats, bb) + 270 offsetof(struct ecore_eth_stats_bb, 271 rx_1519_to_1522_byte_packets)}, 272 {"rx_1519_to_2047_byte_packets", 273 offsetof(struct ecore_eth_stats, bb) + 274 offsetof(struct ecore_eth_stats_bb, 275 rx_1519_to_2047_byte_packets)}, 276 {"rx_2048_to_4095_byte_packets", 277 offsetof(struct ecore_eth_stats, bb) + 278 offsetof(struct ecore_eth_stats_bb, 279 rx_2048_to_4095_byte_packets)}, 280 {"rx_4096_to_9216_byte_packets", 281 offsetof(struct ecore_eth_stats, bb) + 282 offsetof(struct ecore_eth_stats_bb, 283 rx_4096_to_9216_byte_packets)}, 284 {"rx_9217_to_16383_byte_packets", 285 offsetof(struct ecore_eth_stats, bb) + 286 offsetof(struct ecore_eth_stats_bb, 287 rx_9217_to_16383_byte_packets)}, 288 289 {"tx_1519_to_2047_byte_packets", 290 offsetof(struct ecore_eth_stats, bb) + 291 offsetof(struct ecore_eth_stats_bb, 292 tx_1519_to_2047_byte_packets)}, 293 {"tx_2048_to_4095_byte_packets", 294 offsetof(struct ecore_eth_stats, bb) + 295 offsetof(struct ecore_eth_stats_bb, 296 tx_2048_to_4095_byte_packets)}, 297 {"tx_4096_to_9216_byte_packets", 298 offsetof(struct ecore_eth_stats, bb) + 299 offsetof(struct ecore_eth_stats_bb, 300 tx_4096_to_9216_byte_packets)}, 301 {"tx_9217_to_16383_byte_packets", 302 offsetof(struct ecore_eth_stats, bb) + 303 offsetof(struct ecore_eth_stats_bb, 304 tx_9217_to_16383_byte_packets)}, 305 306 {"tx_lpi_entry_count", 307 offsetof(struct ecore_eth_stats, bb) + 308 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)}, 309 {"tx_total_collisions", 310 offsetof(struct ecore_eth_stats, bb) + 311 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)}, 312 }; 313 314 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = { 315 {"rx_1519_to_max_byte_packets", 316 offsetof(struct ecore_eth_stats, ah) + 317 offsetof(struct ecore_eth_stats_ah, 318 rx_1519_to_max_byte_packets)}, 319 {"tx_1519_to_max_byte_packets", 320 offsetof(struct ecore_eth_stats, ah) + 321 offsetof(struct ecore_eth_stats_ah, 322 tx_1519_to_max_byte_packets)}, 323 }; 324 325 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = { 326 {"rx_q_segments", 327 offsetof(struct qede_rx_queue, rx_segs)}, 328 {"rx_q_hw_errors", 329 offsetof(struct qede_rx_queue, rx_hw_errors)}, 330 {"rx_q_allocation_errors", 331 offsetof(struct qede_rx_queue, rx_alloc_errors)} 332 }; 333 334 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn) 335 { 336 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn)); 337 } 338 339 static void 340 qede_interrupt_handler_intx(void *param) 341 { 342 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 343 struct qede_dev *qdev = eth_dev->data->dev_private; 344 struct ecore_dev *edev = &qdev->edev; 345 u64 status; 346 347 /* Check if our device actually raised an interrupt */ 348 status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev)); 349 if (status & 0x1) { 350 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 351 352 if (rte_intr_enable(eth_dev->intr_handle)) 353 DP_ERR(edev, "rte_intr_enable failed\n"); 354 } 355 } 356 357 static void 358 qede_interrupt_handler(void *param) 359 { 360 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 361 struct qede_dev *qdev = eth_dev->data->dev_private; 362 struct ecore_dev *edev = &qdev->edev; 363 364 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 365 if (rte_intr_enable(eth_dev->intr_handle)) 366 DP_ERR(edev, "rte_intr_enable failed\n"); 367 } 368 369 static void 370 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info) 371 { 372 rte_memcpy(&qdev->dev_info, info, sizeof(*info)); 373 qdev->ops = qed_ops; 374 } 375 376 static void qede_print_adapter_info(struct qede_dev *qdev) 377 { 378 struct ecore_dev *edev = &qdev->edev; 379 struct qed_dev_info *info = &qdev->dev_info.common; 380 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; 381 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE]; 382 383 DP_INFO(edev, "*********************************\n"); 384 DP_INFO(edev, " DPDK version:%s\n", rte_version()); 385 DP_INFO(edev, " Chip details : %s %c%d\n", 386 ECORE_IS_BB(edev) ? "BB" : "AH", 387 'A' + edev->chip_rev, 388 (int)edev->chip_metal); 389 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d", 390 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng); 391 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s", 392 ver_str, QEDE_PMD_VERSION); 393 DP_INFO(edev, " Driver version : %s\n", drv_ver); 394 DP_INFO(edev, " Firmware version : %s\n", ver_str); 395 396 snprintf(ver_str, MCP_DRV_VER_STR_SIZE, 397 "%d.%d.%d.%d", 398 (info->mfw_rev >> 24) & 0xff, 399 (info->mfw_rev >> 16) & 0xff, 400 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff); 401 DP_INFO(edev, " Management Firmware version : %s\n", ver_str); 402 DP_INFO(edev, " Firmware file : %s\n", fw_file); 403 DP_INFO(edev, "*********************************\n"); 404 } 405 406 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats) 407 { 408 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 409 unsigned int i = 0, j = 0, qid; 410 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 411 struct qede_tx_queue *txq; 412 413 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n"); 414 415 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 416 RTE_ETHDEV_QUEUE_STAT_CNTRS); 417 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 418 RTE_ETHDEV_QUEUE_STAT_CNTRS); 419 420 for_each_rss(qid) { 421 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 422 offsetof(struct qede_rx_queue, rcv_pkts), 0, 423 sizeof(uint64_t)); 424 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 425 offsetof(struct qede_rx_queue, rx_hw_errors), 0, 426 sizeof(uint64_t)); 427 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + 428 offsetof(struct qede_rx_queue, rx_alloc_errors), 0, 429 sizeof(uint64_t)); 430 431 if (xstats) 432 for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++) 433 OSAL_MEMSET((((char *) 434 (qdev->fp_array[qid].rxq)) + 435 qede_rxq_xstats_strings[j].offset), 436 0, 437 sizeof(uint64_t)); 438 439 i++; 440 if (i == rxq_stat_cntrs) 441 break; 442 } 443 444 i = 0; 445 446 for_each_tss(qid) { 447 txq = qdev->fp_array[qid].txq; 448 449 OSAL_MEMSET((uint64_t *)(uintptr_t) 450 (((uint64_t)(uintptr_t)(txq)) + 451 offsetof(struct qede_tx_queue, xmit_pkts)), 0, 452 sizeof(uint64_t)); 453 454 i++; 455 if (i == txq_stat_cntrs) 456 break; 457 } 458 } 459 460 static int 461 qede_stop_vport(struct ecore_dev *edev) 462 { 463 struct ecore_hwfn *p_hwfn; 464 uint8_t vport_id; 465 int rc; 466 int i; 467 468 vport_id = 0; 469 for_each_hwfn(edev, i) { 470 p_hwfn = &edev->hwfns[i]; 471 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 472 vport_id); 473 if (rc != ECORE_SUCCESS) { 474 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc); 475 return rc; 476 } 477 } 478 479 DP_INFO(edev, "vport stopped\n"); 480 481 return 0; 482 } 483 484 static int 485 qede_start_vport(struct qede_dev *qdev, uint16_t mtu) 486 { 487 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 488 struct ecore_sp_vport_start_params params; 489 struct ecore_hwfn *p_hwfn; 490 int rc; 491 int i; 492 493 if (qdev->vport_started) 494 qede_stop_vport(edev); 495 496 memset(¶ms, 0, sizeof(params)); 497 params.vport_id = 0; 498 params.mtu = mtu; 499 /* @DPDK - Disable FW placement */ 500 params.zero_placement_offset = 1; 501 for_each_hwfn(edev, i) { 502 p_hwfn = &edev->hwfns[i]; 503 params.concrete_fid = p_hwfn->hw_info.concrete_fid; 504 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 505 rc = ecore_sp_vport_start(p_hwfn, ¶ms); 506 if (rc != ECORE_SUCCESS) { 507 DP_ERR(edev, "Start V-PORT failed %d\n", rc); 508 return rc; 509 } 510 } 511 ecore_reset_vport_stats(edev); 512 qdev->vport_started = true; 513 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu); 514 515 return 0; 516 } 517 518 #define QEDE_NPAR_TX_SWITCHING "npar_tx_switching" 519 #define QEDE_VF_TX_SWITCHING "vf_tx_switching" 520 521 /* Activate or deactivate vport via vport-update */ 522 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg) 523 { 524 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 525 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 526 struct ecore_sp_vport_update_params params; 527 struct ecore_hwfn *p_hwfn; 528 uint8_t i; 529 int rc = -1; 530 531 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 532 params.vport_id = 0; 533 params.update_vport_active_rx_flg = 1; 534 params.update_vport_active_tx_flg = 1; 535 params.vport_active_rx_flg = flg; 536 params.vport_active_tx_flg = flg; 537 if (~qdev->enable_tx_switching & flg) { 538 params.update_tx_switching_flg = 1; 539 params.tx_switching_flg = !flg; 540 } 541 for_each_hwfn(edev, i) { 542 p_hwfn = &edev->hwfns[i]; 543 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 544 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 545 ECORE_SPQ_MODE_EBLOCK, NULL); 546 if (rc != ECORE_SUCCESS) { 547 DP_ERR(edev, "Failed to update vport\n"); 548 break; 549 } 550 } 551 DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated"); 552 553 return rc; 554 } 555 556 static void 557 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params, 558 uint16_t mtu, bool enable) 559 { 560 /* Enable LRO in split mode */ 561 sge_tpa_params->tpa_ipv4_en_flg = enable; 562 sge_tpa_params->tpa_ipv6_en_flg = enable; 563 sge_tpa_params->tpa_ipv4_tunn_en_flg = enable; 564 sge_tpa_params->tpa_ipv6_tunn_en_flg = enable; 565 /* set if tpa enable changes */ 566 sge_tpa_params->update_tpa_en_flg = 1; 567 /* set if tpa parameters should be handled */ 568 sge_tpa_params->update_tpa_param_flg = enable; 569 570 sge_tpa_params->max_buffers_per_cqe = 20; 571 /* Enable TPA in split mode. In this mode each TPA segment 572 * starts on the new BD, so there is one BD per segment. 573 */ 574 sge_tpa_params->tpa_pkt_split_flg = 1; 575 sge_tpa_params->tpa_hdr_data_split_flg = 0; 576 sge_tpa_params->tpa_gro_consistent_flg = 0; 577 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 578 sge_tpa_params->tpa_max_size = 0x7FFF; 579 sge_tpa_params->tpa_min_size_to_start = mtu / 2; 580 sge_tpa_params->tpa_min_size_to_cont = mtu / 2; 581 } 582 583 /* Enable/disable LRO via vport-update */ 584 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg) 585 { 586 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 587 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 588 struct ecore_sp_vport_update_params params; 589 struct ecore_sge_tpa_params tpa_params; 590 struct ecore_hwfn *p_hwfn; 591 int rc; 592 int i; 593 594 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 595 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params)); 596 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg); 597 params.vport_id = 0; 598 params.sge_tpa_params = &tpa_params; 599 for_each_hwfn(edev, i) { 600 p_hwfn = &edev->hwfns[i]; 601 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 602 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 603 ECORE_SPQ_MODE_EBLOCK, NULL); 604 if (rc != ECORE_SUCCESS) { 605 DP_ERR(edev, "Failed to update LRO\n"); 606 return -1; 607 } 608 } 609 qdev->enable_lro = flg; 610 eth_dev->data->lro = flg; 611 612 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled"); 613 614 return 0; 615 } 616 617 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast) 618 { 619 memset(ucast, 0, sizeof(struct ecore_filter_ucast)); 620 ucast->is_rx_filter = true; 621 ucast->is_tx_filter = true; 622 /* ucast->assert_on_error = true; - For debug */ 623 } 624 625 static int 626 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev, 627 enum qed_filter_rx_mode_type type) 628 { 629 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 630 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 631 struct ecore_filter_accept_flags flags; 632 633 memset(&flags, 0, sizeof(flags)); 634 635 flags.update_rx_mode_config = 1; 636 flags.update_tx_mode_config = 1; 637 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 638 ECORE_ACCEPT_MCAST_MATCHED | 639 ECORE_ACCEPT_BCAST; 640 641 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED | 642 ECORE_ACCEPT_MCAST_MATCHED | 643 ECORE_ACCEPT_BCAST; 644 645 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { 646 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 647 if (IS_VF(edev)) { 648 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED; 649 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n"); 650 } 651 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { 652 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED; 653 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC | 654 QED_FILTER_RX_MODE_TYPE_PROMISC)) { 655 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED | 656 ECORE_ACCEPT_MCAST_UNMATCHED; 657 } 658 659 return ecore_filter_accept_cmd(edev, 0, flags, false, false, 660 ECORE_SPQ_MODE_CB, NULL); 661 } 662 663 static int 664 qede_tunnel_update(struct qede_dev *qdev, 665 struct ecore_tunnel_info *tunn_info) 666 { 667 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 668 enum _ecore_status_t rc = ECORE_INVAL; 669 struct ecore_hwfn *p_hwfn; 670 struct ecore_ptt *p_ptt; 671 int i; 672 673 for_each_hwfn(edev, i) { 674 p_hwfn = &edev->hwfns[i]; 675 if (IS_PF(edev)) { 676 p_ptt = ecore_ptt_acquire(p_hwfn); 677 if (!p_ptt) { 678 DP_ERR(p_hwfn, "Can't acquire PTT\n"); 679 return -EAGAIN; 680 } 681 } else { 682 p_ptt = NULL; 683 } 684 685 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, 686 tunn_info, ECORE_SPQ_MODE_CB, NULL); 687 if (IS_PF(edev)) 688 ecore_ptt_release(p_hwfn, p_ptt); 689 690 if (rc != ECORE_SUCCESS) 691 break; 692 } 693 694 return rc; 695 } 696 697 static int 698 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 699 bool enable) 700 { 701 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 702 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 703 enum _ecore_status_t rc = ECORE_INVAL; 704 struct ecore_tunnel_info tunn; 705 706 if (qdev->vxlan.enable == enable) 707 return ECORE_SUCCESS; 708 709 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 710 tunn.vxlan.b_update_mode = true; 711 tunn.vxlan.b_mode_enabled = enable; 712 tunn.b_update_rx_cls = true; 713 tunn.b_update_tx_cls = true; 714 tunn.vxlan.tun_cls = clss; 715 716 tunn.vxlan_port.b_update_port = true; 717 tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0; 718 719 rc = qede_tunnel_update(qdev, &tunn); 720 if (rc == ECORE_SUCCESS) { 721 qdev->vxlan.enable = enable; 722 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0; 723 DP_INFO(edev, "vxlan is %s, UDP port = %d\n", 724 enable ? "enabled" : "disabled", qdev->vxlan.udp_port); 725 } else { 726 DP_ERR(edev, "Failed to update tunn_clss %u\n", 727 tunn.vxlan.tun_cls); 728 } 729 730 return rc; 731 } 732 733 static int 734 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 735 bool enable) 736 { 737 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 738 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 739 enum _ecore_status_t rc = ECORE_INVAL; 740 struct ecore_tunnel_info tunn; 741 742 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 743 tunn.l2_geneve.b_update_mode = true; 744 tunn.l2_geneve.b_mode_enabled = enable; 745 tunn.ip_geneve.b_update_mode = true; 746 tunn.ip_geneve.b_mode_enabled = enable; 747 tunn.l2_geneve.tun_cls = clss; 748 tunn.ip_geneve.tun_cls = clss; 749 tunn.b_update_rx_cls = true; 750 tunn.b_update_tx_cls = true; 751 752 tunn.geneve_port.b_update_port = true; 753 tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0; 754 755 rc = qede_tunnel_update(qdev, &tunn); 756 if (rc == ECORE_SUCCESS) { 757 qdev->geneve.enable = enable; 758 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0; 759 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n", 760 enable ? "enabled" : "disabled", qdev->geneve.udp_port); 761 } else { 762 DP_ERR(edev, "Failed to update tunn_clss %u\n", 763 clss); 764 } 765 766 return rc; 767 } 768 769 static int 770 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 771 bool enable) 772 { 773 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 774 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 775 enum _ecore_status_t rc = ECORE_INVAL; 776 struct ecore_tunnel_info tunn; 777 778 memset(&tunn, 0, sizeof(struct ecore_tunnel_info)); 779 tunn.ip_gre.b_update_mode = true; 780 tunn.ip_gre.b_mode_enabled = enable; 781 tunn.ip_gre.tun_cls = clss; 782 tunn.ip_gre.tun_cls = clss; 783 tunn.b_update_rx_cls = true; 784 tunn.b_update_tx_cls = true; 785 786 rc = qede_tunnel_update(qdev, &tunn); 787 if (rc == ECORE_SUCCESS) { 788 qdev->ipgre.enable = enable; 789 DP_INFO(edev, "IPGRE is %s\n", 790 enable ? "enabled" : "disabled"); 791 } else { 792 DP_ERR(edev, "Failed to update tunn_clss %u\n", 793 clss); 794 } 795 796 return rc; 797 } 798 799 static int 800 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss, 801 enum rte_eth_tunnel_type tunn_type, bool enable) 802 { 803 int rc = -EINVAL; 804 805 switch (tunn_type) { 806 case RTE_TUNNEL_TYPE_VXLAN: 807 rc = qede_vxlan_enable(eth_dev, clss, enable); 808 break; 809 case RTE_TUNNEL_TYPE_GENEVE: 810 rc = qede_geneve_enable(eth_dev, clss, enable); 811 break; 812 case RTE_TUNNEL_TYPE_IP_IN_GRE: 813 rc = qede_ipgre_enable(eth_dev, clss, enable); 814 break; 815 default: 816 rc = -EINVAL; 817 break; 818 } 819 820 return rc; 821 } 822 823 static int 824 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 825 bool add) 826 { 827 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 828 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 829 struct qede_ucast_entry *tmp = NULL; 830 struct qede_ucast_entry *u; 831 struct ether_addr *mac_addr; 832 833 mac_addr = (struct ether_addr *)ucast->mac; 834 if (add) { 835 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 836 if ((memcmp(mac_addr, &tmp->mac, 837 ETHER_ADDR_LEN) == 0) && 838 ucast->vni == tmp->vni && 839 ucast->vlan == tmp->vlan) { 840 DP_INFO(edev, "Unicast MAC is already added" 841 " with vlan = %u, vni = %u\n", 842 ucast->vlan, ucast->vni); 843 return 0; 844 } 845 } 846 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry), 847 RTE_CACHE_LINE_SIZE); 848 if (!u) { 849 DP_ERR(edev, "Did not allocate memory for ucast\n"); 850 return -ENOMEM; 851 } 852 ether_addr_copy(mac_addr, &u->mac); 853 u->vlan = ucast->vlan; 854 u->vni = ucast->vni; 855 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list); 856 qdev->num_uc_addr++; 857 } else { 858 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) { 859 if ((memcmp(mac_addr, &tmp->mac, 860 ETHER_ADDR_LEN) == 0) && 861 ucast->vlan == tmp->vlan && 862 ucast->vni == tmp->vni) 863 break; 864 } 865 if (tmp == NULL) { 866 DP_INFO(edev, "Unicast MAC is not found\n"); 867 return -EINVAL; 868 } 869 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list); 870 qdev->num_uc_addr--; 871 } 872 873 return 0; 874 } 875 876 static int 877 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs, 878 uint32_t mc_addrs_num) 879 { 880 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 881 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 882 struct ecore_filter_mcast mcast; 883 struct qede_mcast_entry *m = NULL; 884 uint8_t i; 885 int rc; 886 887 for (i = 0; i < mc_addrs_num; i++) { 888 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry), 889 RTE_CACHE_LINE_SIZE); 890 if (!m) { 891 DP_ERR(edev, "Did not allocate memory for mcast\n"); 892 return -ENOMEM; 893 } 894 ether_addr_copy(&mc_addrs[i], &m->mac); 895 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list); 896 } 897 memset(&mcast, 0, sizeof(mcast)); 898 mcast.num_mc_addrs = mc_addrs_num; 899 mcast.opcode = ECORE_FILTER_ADD; 900 for (i = 0; i < mc_addrs_num; i++) 901 ether_addr_copy(&mc_addrs[i], (struct ether_addr *) 902 &mcast.mac[i]); 903 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 904 if (rc != ECORE_SUCCESS) { 905 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc); 906 return -1; 907 } 908 909 return 0; 910 } 911 912 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev) 913 { 914 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 915 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 916 struct qede_mcast_entry *tmp = NULL; 917 struct ecore_filter_mcast mcast; 918 int j; 919 int rc; 920 921 memset(&mcast, 0, sizeof(mcast)); 922 mcast.num_mc_addrs = qdev->num_mc_addr; 923 mcast.opcode = ECORE_FILTER_REMOVE; 924 j = 0; 925 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) { 926 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]); 927 j++; 928 } 929 rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL); 930 if (rc != ECORE_SUCCESS) { 931 DP_ERR(edev, "Failed to delete multicast filter\n"); 932 return -1; 933 } 934 /* Init the list */ 935 while (!SLIST_EMPTY(&qdev->mc_list_head)) { 936 tmp = SLIST_FIRST(&qdev->mc_list_head); 937 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list); 938 } 939 SLIST_INIT(&qdev->mc_list_head); 940 941 return 0; 942 } 943 944 static enum _ecore_status_t 945 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast, 946 bool add) 947 { 948 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 949 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 950 enum _ecore_status_t rc = ECORE_INVAL; 951 952 if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) { 953 DP_ERR(edev, "Ucast filter table limit exceeded," 954 " Please enable promisc mode\n"); 955 return ECORE_INVAL; 956 } 957 958 rc = qede_ucast_filter(eth_dev, ucast, add); 959 if (rc == 0) 960 rc = ecore_filter_ucast_cmd(edev, ucast, 961 ECORE_SPQ_MODE_CB, NULL); 962 if (rc != ECORE_SUCCESS) 963 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n", 964 rc, add); 965 966 return rc; 967 } 968 969 static int 970 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr, 971 __rte_unused uint32_t index, __rte_unused uint32_t pool) 972 { 973 struct ecore_filter_ucast ucast; 974 int re; 975 976 if (!is_valid_assigned_ether_addr(mac_addr)) 977 return -EINVAL; 978 979 qede_set_ucast_cmn_params(&ucast); 980 ucast.opcode = ECORE_FILTER_ADD; 981 ucast.type = ECORE_FILTER_MAC; 982 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac); 983 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1); 984 return re; 985 } 986 987 static void 988 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index) 989 { 990 struct qede_dev *qdev = eth_dev->data->dev_private; 991 struct ecore_dev *edev = &qdev->edev; 992 struct ecore_filter_ucast ucast; 993 994 PMD_INIT_FUNC_TRACE(edev); 995 996 if (index >= qdev->dev_info.num_mac_filters) { 997 DP_ERR(edev, "Index %u is above MAC filter limit %u\n", 998 index, qdev->dev_info.num_mac_filters); 999 return; 1000 } 1001 1002 if (!is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index])) 1003 return; 1004 1005 qede_set_ucast_cmn_params(&ucast); 1006 ucast.opcode = ECORE_FILTER_REMOVE; 1007 ucast.type = ECORE_FILTER_MAC; 1008 1009 /* Use the index maintained by rte */ 1010 ether_addr_copy(ð_dev->data->mac_addrs[index], 1011 (struct ether_addr *)&ucast.mac); 1012 1013 qede_mac_int_ops(eth_dev, &ucast, false); 1014 } 1015 1016 static int 1017 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr) 1018 { 1019 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1020 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1021 1022 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev), 1023 mac_addr->addr_bytes)) { 1024 DP_ERR(edev, "Setting MAC address is not allowed\n"); 1025 return -EPERM; 1026 } 1027 1028 qede_mac_addr_remove(eth_dev, 0); 1029 1030 return qede_mac_addr_add(eth_dev, mac_addr, 0, 0); 1031 } 1032 1033 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg) 1034 { 1035 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1036 struct ecore_sp_vport_update_params params; 1037 struct ecore_hwfn *p_hwfn; 1038 uint8_t i; 1039 int rc; 1040 1041 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1042 params.vport_id = 0; 1043 params.update_accept_any_vlan_flg = 1; 1044 params.accept_any_vlan = flg; 1045 for_each_hwfn(edev, i) { 1046 p_hwfn = &edev->hwfns[i]; 1047 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1048 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1049 ECORE_SPQ_MODE_EBLOCK, NULL); 1050 if (rc != ECORE_SUCCESS) { 1051 DP_ERR(edev, "Failed to configure accept-any-vlan\n"); 1052 return; 1053 } 1054 } 1055 1056 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled"); 1057 } 1058 1059 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg) 1060 { 1061 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1062 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1063 struct ecore_sp_vport_update_params params; 1064 struct ecore_hwfn *p_hwfn; 1065 uint8_t i; 1066 int rc; 1067 1068 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 1069 params.vport_id = 0; 1070 params.update_inner_vlan_removal_flg = 1; 1071 params.inner_vlan_removal_flg = flg; 1072 for_each_hwfn(edev, i) { 1073 p_hwfn = &edev->hwfns[i]; 1074 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 1075 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 1076 ECORE_SPQ_MODE_EBLOCK, NULL); 1077 if (rc != ECORE_SUCCESS) { 1078 DP_ERR(edev, "Failed to update vport\n"); 1079 return -1; 1080 } 1081 } 1082 1083 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled"); 1084 return 0; 1085 } 1086 1087 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, 1088 uint16_t vlan_id, int on) 1089 { 1090 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1091 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1092 struct qed_dev_eth_info *dev_info = &qdev->dev_info; 1093 struct qede_vlan_entry *tmp = NULL; 1094 struct qede_vlan_entry *vlan; 1095 struct ecore_filter_ucast ucast; 1096 int rc; 1097 1098 if (on) { 1099 if (qdev->configured_vlans == dev_info->num_vlan_filters) { 1100 DP_ERR(edev, "Reached max VLAN filter limit" 1101 " enabling accept_any_vlan\n"); 1102 qede_config_accept_any_vlan(qdev, true); 1103 return 0; 1104 } 1105 1106 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1107 if (tmp->vid == vlan_id) { 1108 DP_INFO(edev, "VLAN %u already configured\n", 1109 vlan_id); 1110 return 0; 1111 } 1112 } 1113 1114 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry), 1115 RTE_CACHE_LINE_SIZE); 1116 1117 if (!vlan) { 1118 DP_ERR(edev, "Did not allocate memory for VLAN\n"); 1119 return -ENOMEM; 1120 } 1121 1122 qede_set_ucast_cmn_params(&ucast); 1123 ucast.opcode = ECORE_FILTER_ADD; 1124 ucast.type = ECORE_FILTER_VLAN; 1125 ucast.vlan = vlan_id; 1126 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1127 NULL); 1128 if (rc != 0) { 1129 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id, 1130 rc); 1131 rte_free(vlan); 1132 } else { 1133 vlan->vid = vlan_id; 1134 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list); 1135 qdev->configured_vlans++; 1136 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n", 1137 vlan_id, qdev->configured_vlans); 1138 } 1139 } else { 1140 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) { 1141 if (tmp->vid == vlan_id) 1142 break; 1143 } 1144 1145 if (!tmp) { 1146 if (qdev->configured_vlans == 0) { 1147 DP_INFO(edev, 1148 "No VLAN filters configured yet\n"); 1149 return 0; 1150 } 1151 1152 DP_ERR(edev, "VLAN %u not configured\n", vlan_id); 1153 return -EINVAL; 1154 } 1155 1156 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list); 1157 1158 qede_set_ucast_cmn_params(&ucast); 1159 ucast.opcode = ECORE_FILTER_REMOVE; 1160 ucast.type = ECORE_FILTER_VLAN; 1161 ucast.vlan = vlan_id; 1162 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, 1163 NULL); 1164 if (rc != 0) { 1165 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n", 1166 vlan_id, rc); 1167 } else { 1168 qdev->configured_vlans--; 1169 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n", 1170 vlan_id, qdev->configured_vlans); 1171 } 1172 } 1173 1174 return rc; 1175 } 1176 1177 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 1178 { 1179 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1180 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1181 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1182 1183 if (mask & ETH_VLAN_STRIP_MASK) { 1184 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1185 (void)qede_vlan_stripping(eth_dev, 1); 1186 else 1187 (void)qede_vlan_stripping(eth_dev, 0); 1188 } 1189 1190 if (mask & ETH_VLAN_FILTER_MASK) { 1191 /* VLAN filtering kicks in when a VLAN is added */ 1192 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 1193 qede_vlan_filter_set(eth_dev, 0, 1); 1194 } else { 1195 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */ 1196 DP_ERR(edev, 1197 " Please remove existing VLAN filters" 1198 " before disabling VLAN filtering\n"); 1199 /* Signal app that VLAN filtering is still 1200 * enabled 1201 */ 1202 eth_dev->data->dev_conf.rxmode.offloads |= 1203 DEV_RX_OFFLOAD_VLAN_FILTER; 1204 } else { 1205 qede_vlan_filter_set(eth_dev, 0, 0); 1206 } 1207 } 1208 } 1209 1210 if (mask & ETH_VLAN_EXTEND_MASK) 1211 DP_ERR(edev, "Extend VLAN not supported\n"); 1212 1213 qdev->vlan_offload_mask = mask; 1214 1215 DP_INFO(edev, "VLAN offload mask %d\n", mask); 1216 1217 return 0; 1218 } 1219 1220 static void qede_prandom_bytes(uint32_t *buff) 1221 { 1222 uint8_t i; 1223 1224 srand((unsigned int)time(NULL)); 1225 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++) 1226 buff[i] = rand(); 1227 } 1228 1229 int qede_config_rss(struct rte_eth_dev *eth_dev) 1230 { 1231 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1232 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1233 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE]; 1234 struct rte_eth_rss_reta_entry64 reta_conf[2]; 1235 struct rte_eth_rss_conf rss_conf; 1236 uint32_t i, id, pos, q; 1237 1238 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf; 1239 if (!rss_conf.rss_key) { 1240 DP_INFO(edev, "Applying driver default key\n"); 1241 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1242 qede_prandom_bytes(&def_rss_key[0]); 1243 rss_conf.rss_key = (uint8_t *)&def_rss_key[0]; 1244 } 1245 1246 /* Configure RSS hash */ 1247 if (qede_rss_hash_update(eth_dev, &rss_conf)) 1248 return -EINVAL; 1249 1250 /* Configure default RETA */ 1251 memset(reta_conf, 0, sizeof(reta_conf)); 1252 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) 1253 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX; 1254 1255 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 1256 id = i / RTE_RETA_GROUP_SIZE; 1257 pos = i % RTE_RETA_GROUP_SIZE; 1258 q = i % QEDE_RSS_COUNT(qdev); 1259 reta_conf[id].reta[pos] = q; 1260 } 1261 if (qede_rss_reta_update(eth_dev, &reta_conf[0], 1262 ECORE_RSS_IND_TABLE_SIZE)) 1263 return -EINVAL; 1264 1265 return 0; 1266 } 1267 1268 static void qede_fastpath_start(struct ecore_dev *edev) 1269 { 1270 struct ecore_hwfn *p_hwfn; 1271 int i; 1272 1273 for_each_hwfn(edev, i) { 1274 p_hwfn = &edev->hwfns[i]; 1275 ecore_hw_start_fastpath(p_hwfn); 1276 } 1277 } 1278 1279 static int qede_dev_start(struct rte_eth_dev *eth_dev) 1280 { 1281 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1282 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1283 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1284 1285 PMD_INIT_FUNC_TRACE(edev); 1286 1287 /* Update MTU only if it has changed */ 1288 if (eth_dev->data->mtu != qdev->mtu) { 1289 if (qede_update_mtu(eth_dev, qdev->mtu)) 1290 goto err; 1291 } 1292 1293 /* Configure TPA parameters */ 1294 if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1295 if (qede_enable_tpa(eth_dev, true)) 1296 return -EINVAL; 1297 /* Enable scatter mode for LRO */ 1298 if (!eth_dev->data->scattered_rx) 1299 rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER; 1300 } 1301 1302 /* Start queues */ 1303 if (qede_start_queues(eth_dev)) 1304 goto err; 1305 1306 if (IS_PF(edev)) 1307 qede_reset_queue_stats(qdev, true); 1308 1309 /* Newer SR-IOV PF driver expects RX/TX queues to be started before 1310 * enabling RSS. Hence RSS configuration is deferred upto this point. 1311 * Also, we would like to retain similar behavior in PF case, so we 1312 * don't do PF/VF specific check here. 1313 */ 1314 if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 1315 if (qede_config_rss(eth_dev)) 1316 goto err; 1317 1318 /* Enable vport*/ 1319 if (qede_activate_vport(eth_dev, true)) 1320 goto err; 1321 1322 /* Update link status */ 1323 qede_link_update(eth_dev, 0); 1324 1325 /* Start/resume traffic */ 1326 qede_fastpath_start(edev); 1327 1328 DP_INFO(edev, "Device started\n"); 1329 1330 return 0; 1331 err: 1332 DP_ERR(edev, "Device start fails\n"); 1333 return -1; /* common error code is < 0 */ 1334 } 1335 1336 static void qede_dev_stop(struct rte_eth_dev *eth_dev) 1337 { 1338 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1339 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1340 1341 PMD_INIT_FUNC_TRACE(edev); 1342 1343 /* Disable vport */ 1344 if (qede_activate_vport(eth_dev, false)) 1345 return; 1346 1347 if (qdev->enable_lro) 1348 qede_enable_tpa(eth_dev, false); 1349 1350 /* Stop queues */ 1351 qede_stop_queues(eth_dev); 1352 1353 /* Disable traffic */ 1354 ecore_hw_stop_fastpath(edev); /* TBD - loop */ 1355 1356 DP_INFO(edev, "Device is stopped\n"); 1357 } 1358 1359 const char *valid_args[] = { 1360 QEDE_NPAR_TX_SWITCHING, 1361 QEDE_VF_TX_SWITCHING, 1362 NULL, 1363 }; 1364 1365 static int qede_args_check(const char *key, const char *val, void *opaque) 1366 { 1367 unsigned long tmp; 1368 int ret = 0; 1369 struct rte_eth_dev *eth_dev = opaque; 1370 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1371 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1372 1373 errno = 0; 1374 tmp = strtoul(val, NULL, 0); 1375 if (errno) { 1376 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val); 1377 return errno; 1378 } 1379 1380 if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) || 1381 ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) { 1382 qdev->enable_tx_switching = !!tmp; 1383 DP_INFO(edev, "Disabling %s tx-switching\n", 1384 strcmp(QEDE_NPAR_TX_SWITCHING, key) ? 1385 "VF" : "NPAR"); 1386 } 1387 1388 return ret; 1389 } 1390 1391 static int qede_args(struct rte_eth_dev *eth_dev) 1392 { 1393 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1394 struct rte_kvargs *kvlist; 1395 struct rte_devargs *devargs; 1396 int ret; 1397 int i; 1398 1399 devargs = pci_dev->device.devargs; 1400 if (!devargs) 1401 return 0; /* return success */ 1402 1403 kvlist = rte_kvargs_parse(devargs->args, valid_args); 1404 if (kvlist == NULL) 1405 return -EINVAL; 1406 1407 /* Process parameters. */ 1408 for (i = 0; (valid_args[i] != NULL); ++i) { 1409 if (rte_kvargs_count(kvlist, valid_args[i])) { 1410 ret = rte_kvargs_process(kvlist, valid_args[i], 1411 qede_args_check, eth_dev); 1412 if (ret != ECORE_SUCCESS) { 1413 rte_kvargs_free(kvlist); 1414 return ret; 1415 } 1416 } 1417 } 1418 rte_kvargs_free(kvlist); 1419 1420 return 0; 1421 } 1422 1423 static int qede_dev_configure(struct rte_eth_dev *eth_dev) 1424 { 1425 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1426 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1427 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1428 int ret; 1429 1430 PMD_INIT_FUNC_TRACE(edev); 1431 1432 /* Check requirements for 100G mode */ 1433 if (ECORE_IS_CMT(edev)) { 1434 if (eth_dev->data->nb_rx_queues < 2 || 1435 eth_dev->data->nb_tx_queues < 2) { 1436 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); 1437 return -EINVAL; 1438 } 1439 1440 if ((eth_dev->data->nb_rx_queues % 2 != 0) || 1441 (eth_dev->data->nb_tx_queues % 2 != 0)) { 1442 DP_ERR(edev, 1443 "100G mode needs even no. of RX/TX queues\n"); 1444 return -EINVAL; 1445 } 1446 } 1447 1448 /* We need to have min 1 RX queue.There is no min check in 1449 * rte_eth_dev_configure(), so we are checking it here. 1450 */ 1451 if (eth_dev->data->nb_rx_queues == 0) { 1452 DP_ERR(edev, "Minimum one RX queue is required\n"); 1453 return -EINVAL; 1454 } 1455 1456 /* Enable Tx switching by default */ 1457 qdev->enable_tx_switching = 1; 1458 1459 /* Parse devargs and fix up rxmode */ 1460 if (qede_args(eth_dev)) 1461 DP_NOTICE(edev, false, 1462 "Invalid devargs supplied, requested change will not take effect\n"); 1463 1464 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || 1465 rxmode->mq_mode == ETH_MQ_RX_RSS)) { 1466 DP_ERR(edev, "Unsupported multi-queue mode\n"); 1467 return -ENOTSUP; 1468 } 1469 /* Flow director mode check */ 1470 if (qede_check_fdir_support(eth_dev)) 1471 return -ENOTSUP; 1472 1473 qede_dealloc_fp_resc(eth_dev); 1474 qdev->num_tx_queues = eth_dev->data->nb_tx_queues; 1475 qdev->num_rx_queues = eth_dev->data->nb_rx_queues; 1476 if (qede_alloc_fp_resc(qdev)) 1477 return -ENOMEM; 1478 1479 /* If jumbo enabled adjust MTU */ 1480 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) 1481 eth_dev->data->mtu = 1482 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1483 ETHER_HDR_LEN - ETHER_CRC_LEN; 1484 1485 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) 1486 eth_dev->data->scattered_rx = 1; 1487 1488 if (qede_start_vport(qdev, eth_dev->data->mtu)) 1489 return -1; 1490 1491 qdev->mtu = eth_dev->data->mtu; 1492 1493 /* Enable VLAN offloads by default */ 1494 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK | 1495 ETH_VLAN_FILTER_MASK); 1496 if (ret) 1497 return ret; 1498 1499 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n", 1500 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); 1501 1502 return 0; 1503 } 1504 1505 /* Info about HW descriptor ring limitations */ 1506 static const struct rte_eth_desc_lim qede_rx_desc_lim = { 1507 .nb_max = 0x8000, /* 32K */ 1508 .nb_min = 128, 1509 .nb_align = 128 /* lowest common multiple */ 1510 }; 1511 1512 static const struct rte_eth_desc_lim qede_tx_desc_lim = { 1513 .nb_max = 0x8000, /* 32K */ 1514 .nb_min = 256, 1515 .nb_align = 256, 1516 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET, 1517 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 1518 }; 1519 1520 static void 1521 qede_dev_info_get(struct rte_eth_dev *eth_dev, 1522 struct rte_eth_dev_info *dev_info) 1523 { 1524 struct qede_dev *qdev = eth_dev->data->dev_private; 1525 struct ecore_dev *edev = &qdev->edev; 1526 struct qed_link_output link; 1527 uint32_t speed_cap = 0; 1528 1529 PMD_INIT_FUNC_TRACE(edev); 1530 1531 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE; 1532 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; 1533 dev_info->rx_desc_lim = qede_rx_desc_lim; 1534 dev_info->tx_desc_lim = qede_tx_desc_lim; 1535 1536 if (IS_PF(edev)) 1537 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1538 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2); 1539 else 1540 dev_info->max_rx_queues = (uint16_t)RTE_MIN( 1541 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); 1542 dev_info->max_tx_queues = dev_info->max_rx_queues; 1543 1544 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters; 1545 dev_info->max_vfs = 0; 1546 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE; 1547 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t); 1548 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL; 1549 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 1550 DEV_RX_OFFLOAD_UDP_CKSUM | 1551 DEV_RX_OFFLOAD_TCP_CKSUM | 1552 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1553 DEV_RX_OFFLOAD_TCP_LRO | 1554 DEV_RX_OFFLOAD_CRC_STRIP | 1555 DEV_RX_OFFLOAD_KEEP_CRC | 1556 DEV_RX_OFFLOAD_SCATTER | 1557 DEV_RX_OFFLOAD_JUMBO_FRAME | 1558 DEV_RX_OFFLOAD_VLAN_FILTER | 1559 DEV_RX_OFFLOAD_VLAN_STRIP); 1560 dev_info->rx_queue_offload_capa = 0; 1561 1562 /* TX offloads are on a per-packet basis, so it is applicable 1563 * to both at port and queue levels. 1564 */ 1565 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT | 1566 DEV_TX_OFFLOAD_IPV4_CKSUM | 1567 DEV_TX_OFFLOAD_UDP_CKSUM | 1568 DEV_TX_OFFLOAD_TCP_CKSUM | 1569 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1570 DEV_TX_OFFLOAD_MULTI_SEGS | 1571 DEV_TX_OFFLOAD_TCP_TSO | 1572 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 1573 DEV_TX_OFFLOAD_GENEVE_TNL_TSO); 1574 dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa; 1575 1576 dev_info->default_txconf = (struct rte_eth_txconf) { 1577 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS, 1578 }; 1579 1580 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1581 /* Packets are always dropped if no descriptors are available */ 1582 .rx_drop_en = 1, 1583 .offloads = 0, 1584 }; 1585 1586 memset(&link, 0, sizeof(struct qed_link_output)); 1587 qdev->ops->common->get_link(edev, &link); 1588 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) 1589 speed_cap |= ETH_LINK_SPEED_1G; 1590 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) 1591 speed_cap |= ETH_LINK_SPEED_10G; 1592 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) 1593 speed_cap |= ETH_LINK_SPEED_25G; 1594 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) 1595 speed_cap |= ETH_LINK_SPEED_40G; 1596 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) 1597 speed_cap |= ETH_LINK_SPEED_50G; 1598 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) 1599 speed_cap |= ETH_LINK_SPEED_100G; 1600 dev_info->speed_capa = speed_cap; 1601 } 1602 1603 /* return 0 means link status changed, -1 means not changed */ 1604 int 1605 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) 1606 { 1607 struct qede_dev *qdev = eth_dev->data->dev_private; 1608 struct ecore_dev *edev = &qdev->edev; 1609 struct qed_link_output q_link; 1610 struct rte_eth_link link; 1611 uint16_t link_duplex; 1612 1613 memset(&q_link, 0, sizeof(q_link)); 1614 memset(&link, 0, sizeof(link)); 1615 1616 qdev->ops->common->get_link(edev, &q_link); 1617 1618 /* Link Speed */ 1619 link.link_speed = q_link.speed; 1620 1621 /* Link Mode */ 1622 switch (q_link.duplex) { 1623 case QEDE_DUPLEX_HALF: 1624 link_duplex = ETH_LINK_HALF_DUPLEX; 1625 break; 1626 case QEDE_DUPLEX_FULL: 1627 link_duplex = ETH_LINK_FULL_DUPLEX; 1628 break; 1629 case QEDE_DUPLEX_UNKNOWN: 1630 default: 1631 link_duplex = -1; 1632 } 1633 link.link_duplex = link_duplex; 1634 1635 /* Link Status */ 1636 link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 1637 1638 /* AN */ 1639 link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ? 1640 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 1641 1642 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n", 1643 link.link_speed, link.link_duplex, 1644 link.link_autoneg, link.link_status); 1645 1646 return rte_eth_linkstatus_set(eth_dev, &link); 1647 } 1648 1649 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev) 1650 { 1651 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1652 struct qede_dev *qdev = eth_dev->data->dev_private; 1653 struct ecore_dev *edev = &qdev->edev; 1654 1655 PMD_INIT_FUNC_TRACE(edev); 1656 #endif 1657 1658 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC; 1659 1660 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1661 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 1662 1663 qed_configure_filter_rx_mode(eth_dev, type); 1664 } 1665 1666 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev) 1667 { 1668 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 1669 struct qede_dev *qdev = eth_dev->data->dev_private; 1670 struct ecore_dev *edev = &qdev->edev; 1671 1672 PMD_INIT_FUNC_TRACE(edev); 1673 #endif 1674 1675 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1) 1676 qed_configure_filter_rx_mode(eth_dev, 1677 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC); 1678 else 1679 qed_configure_filter_rx_mode(eth_dev, 1680 QED_FILTER_RX_MODE_TYPE_REGULAR); 1681 } 1682 1683 static void qede_poll_sp_sb_cb(void *param) 1684 { 1685 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 1686 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1687 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1688 int rc; 1689 1690 qede_interrupt_action(ECORE_LEADING_HWFN(edev)); 1691 qede_interrupt_action(&edev->hwfns[1]); 1692 1693 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 1694 qede_poll_sp_sb_cb, 1695 (void *)eth_dev); 1696 if (rc != 0) { 1697 DP_ERR(edev, "Unable to start periodic" 1698 " timer rc %d\n", rc); 1699 assert(false && "Unable to start periodic timer"); 1700 } 1701 } 1702 1703 static void qede_dev_close(struct rte_eth_dev *eth_dev) 1704 { 1705 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1706 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1707 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1708 1709 PMD_INIT_FUNC_TRACE(edev); 1710 1711 /* dev_stop() shall cleanup fp resources in hw but without releasing 1712 * dma memories and sw structures so that dev_start() can be called 1713 * by the app without reconfiguration. However, in dev_close() we 1714 * can release all the resources and device can be brought up newly 1715 */ 1716 if (eth_dev->data->dev_started) 1717 qede_dev_stop(eth_dev); 1718 1719 qede_stop_vport(edev); 1720 qdev->vport_started = false; 1721 qede_fdir_dealloc_resc(eth_dev); 1722 qede_dealloc_fp_resc(eth_dev); 1723 1724 eth_dev->data->nb_rx_queues = 0; 1725 eth_dev->data->nb_tx_queues = 0; 1726 1727 /* Bring the link down */ 1728 qede_dev_set_link_state(eth_dev, false); 1729 qdev->ops->common->slowpath_stop(edev); 1730 qdev->ops->common->remove(edev); 1731 rte_intr_disable(&pci_dev->intr_handle); 1732 rte_intr_callback_unregister(&pci_dev->intr_handle, 1733 qede_interrupt_handler, (void *)eth_dev); 1734 if (ECORE_IS_CMT(edev)) 1735 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev); 1736 } 1737 1738 static int 1739 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats) 1740 { 1741 struct qede_dev *qdev = eth_dev->data->dev_private; 1742 struct ecore_dev *edev = &qdev->edev; 1743 struct ecore_eth_stats stats; 1744 unsigned int i = 0, j = 0, qid; 1745 unsigned int rxq_stat_cntrs, txq_stat_cntrs; 1746 struct qede_tx_queue *txq; 1747 1748 ecore_get_vport_stats(edev, &stats); 1749 1750 /* RX Stats */ 1751 eth_stats->ipackets = stats.common.rx_ucast_pkts + 1752 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts; 1753 1754 eth_stats->ibytes = stats.common.rx_ucast_bytes + 1755 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes; 1756 1757 eth_stats->ierrors = stats.common.rx_crc_errors + 1758 stats.common.rx_align_errors + 1759 stats.common.rx_carrier_errors + 1760 stats.common.rx_oversize_packets + 1761 stats.common.rx_jabbers + stats.common.rx_undersize_packets; 1762 1763 eth_stats->rx_nombuf = stats.common.no_buff_discards; 1764 1765 eth_stats->imissed = stats.common.mftag_filter_discards + 1766 stats.common.mac_filter_discards + 1767 stats.common.no_buff_discards + 1768 stats.common.brb_truncates + stats.common.brb_discards; 1769 1770 /* TX stats */ 1771 eth_stats->opackets = stats.common.tx_ucast_pkts + 1772 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts; 1773 1774 eth_stats->obytes = stats.common.tx_ucast_bytes + 1775 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes; 1776 1777 eth_stats->oerrors = stats.common.tx_err_drop_pkts; 1778 1779 /* Queue stats */ 1780 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1781 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1782 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev), 1783 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1784 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) || 1785 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev))) 1786 DP_VERBOSE(edev, ECORE_MSG_DEBUG, 1787 "Not all the queue stats will be displayed. Set" 1788 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param" 1789 " appropriately and retry.\n"); 1790 1791 for_each_rss(qid) { 1792 eth_stats->q_ipackets[i] = 1793 *(uint64_t *)( 1794 ((char *)(qdev->fp_array[qid].rxq)) + 1795 offsetof(struct qede_rx_queue, 1796 rcv_pkts)); 1797 eth_stats->q_errors[i] = 1798 *(uint64_t *)( 1799 ((char *)(qdev->fp_array[qid].rxq)) + 1800 offsetof(struct qede_rx_queue, 1801 rx_hw_errors)) + 1802 *(uint64_t *)( 1803 ((char *)(qdev->fp_array[qid].rxq)) + 1804 offsetof(struct qede_rx_queue, 1805 rx_alloc_errors)); 1806 i++; 1807 if (i == rxq_stat_cntrs) 1808 break; 1809 } 1810 1811 for_each_tss(qid) { 1812 txq = qdev->fp_array[qid].txq; 1813 eth_stats->q_opackets[j] = 1814 *((uint64_t *)(uintptr_t) 1815 (((uint64_t)(uintptr_t)(txq)) + 1816 offsetof(struct qede_tx_queue, 1817 xmit_pkts))); 1818 j++; 1819 if (j == txq_stat_cntrs) 1820 break; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static unsigned 1827 qede_get_xstats_count(struct qede_dev *qdev) { 1828 if (ECORE_IS_BB(&qdev->edev)) 1829 return RTE_DIM(qede_xstats_strings) + 1830 RTE_DIM(qede_bb_xstats_strings) + 1831 (RTE_DIM(qede_rxq_xstats_strings) * 1832 RTE_MIN(QEDE_RSS_COUNT(qdev), 1833 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1834 else 1835 return RTE_DIM(qede_xstats_strings) + 1836 RTE_DIM(qede_ah_xstats_strings) + 1837 (RTE_DIM(qede_rxq_xstats_strings) * 1838 RTE_MIN(QEDE_RSS_COUNT(qdev), 1839 RTE_ETHDEV_QUEUE_STAT_CNTRS)); 1840 } 1841 1842 static int 1843 qede_get_xstats_names(struct rte_eth_dev *dev, 1844 struct rte_eth_xstat_name *xstats_names, 1845 __rte_unused unsigned int limit) 1846 { 1847 struct qede_dev *qdev = dev->data->dev_private; 1848 struct ecore_dev *edev = &qdev->edev; 1849 const unsigned int stat_cnt = qede_get_xstats_count(qdev); 1850 unsigned int i, qid, stat_idx = 0; 1851 unsigned int rxq_stat_cntrs; 1852 1853 if (xstats_names != NULL) { 1854 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1855 snprintf(xstats_names[stat_idx].name, 1856 sizeof(xstats_names[stat_idx].name), 1857 "%s", 1858 qede_xstats_strings[i].name); 1859 stat_idx++; 1860 } 1861 1862 if (ECORE_IS_BB(edev)) { 1863 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1864 snprintf(xstats_names[stat_idx].name, 1865 sizeof(xstats_names[stat_idx].name), 1866 "%s", 1867 qede_bb_xstats_strings[i].name); 1868 stat_idx++; 1869 } 1870 } else { 1871 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1872 snprintf(xstats_names[stat_idx].name, 1873 sizeof(xstats_names[stat_idx].name), 1874 "%s", 1875 qede_ah_xstats_strings[i].name); 1876 stat_idx++; 1877 } 1878 } 1879 1880 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1881 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1882 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1883 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1884 snprintf(xstats_names[stat_idx].name, 1885 sizeof(xstats_names[stat_idx].name), 1886 "%.4s%d%s", 1887 qede_rxq_xstats_strings[i].name, qid, 1888 qede_rxq_xstats_strings[i].name + 4); 1889 stat_idx++; 1890 } 1891 } 1892 } 1893 1894 return stat_cnt; 1895 } 1896 1897 static int 1898 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1899 unsigned int n) 1900 { 1901 struct qede_dev *qdev = dev->data->dev_private; 1902 struct ecore_dev *edev = &qdev->edev; 1903 struct ecore_eth_stats stats; 1904 const unsigned int num = qede_get_xstats_count(qdev); 1905 unsigned int i, qid, stat_idx = 0; 1906 unsigned int rxq_stat_cntrs; 1907 1908 if (n < num) 1909 return num; 1910 1911 ecore_get_vport_stats(edev, &stats); 1912 1913 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) { 1914 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) + 1915 qede_xstats_strings[i].offset); 1916 xstats[stat_idx].id = stat_idx; 1917 stat_idx++; 1918 } 1919 1920 if (ECORE_IS_BB(edev)) { 1921 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) { 1922 xstats[stat_idx].value = 1923 *(uint64_t *)(((char *)&stats) + 1924 qede_bb_xstats_strings[i].offset); 1925 xstats[stat_idx].id = stat_idx; 1926 stat_idx++; 1927 } 1928 } else { 1929 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) { 1930 xstats[stat_idx].value = 1931 *(uint64_t *)(((char *)&stats) + 1932 qede_ah_xstats_strings[i].offset); 1933 xstats[stat_idx].id = stat_idx; 1934 stat_idx++; 1935 } 1936 } 1937 1938 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev), 1939 RTE_ETHDEV_QUEUE_STAT_CNTRS); 1940 for (qid = 0; qid < rxq_stat_cntrs; qid++) { 1941 for_each_rss(qid) { 1942 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { 1943 xstats[stat_idx].value = *(uint64_t *)( 1944 ((char *)(qdev->fp_array[qid].rxq)) + 1945 qede_rxq_xstats_strings[i].offset); 1946 xstats[stat_idx].id = stat_idx; 1947 stat_idx++; 1948 } 1949 } 1950 } 1951 1952 return stat_idx; 1953 } 1954 1955 static void 1956 qede_reset_xstats(struct rte_eth_dev *dev) 1957 { 1958 struct qede_dev *qdev = dev->data->dev_private; 1959 struct ecore_dev *edev = &qdev->edev; 1960 1961 ecore_reset_vport_stats(edev); 1962 qede_reset_queue_stats(qdev, true); 1963 } 1964 1965 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up) 1966 { 1967 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 1968 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 1969 struct qed_link_params link_params; 1970 int rc; 1971 1972 DP_INFO(edev, "setting link state %d\n", link_up); 1973 memset(&link_params, 0, sizeof(link_params)); 1974 link_params.link_up = link_up; 1975 rc = qdev->ops->common->set_link(edev, &link_params); 1976 if (rc != ECORE_SUCCESS) 1977 DP_ERR(edev, "Unable to set link state %d\n", link_up); 1978 1979 return rc; 1980 } 1981 1982 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev) 1983 { 1984 return qede_dev_set_link_state(eth_dev, true); 1985 } 1986 1987 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev) 1988 { 1989 return qede_dev_set_link_state(eth_dev, false); 1990 } 1991 1992 static void qede_reset_stats(struct rte_eth_dev *eth_dev) 1993 { 1994 struct qede_dev *qdev = eth_dev->data->dev_private; 1995 struct ecore_dev *edev = &qdev->edev; 1996 1997 ecore_reset_vport_stats(edev); 1998 qede_reset_queue_stats(qdev, false); 1999 } 2000 2001 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev) 2002 { 2003 enum qed_filter_rx_mode_type type = 2004 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC; 2005 2006 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 2007 type |= QED_FILTER_RX_MODE_TYPE_PROMISC; 2008 2009 qed_configure_filter_rx_mode(eth_dev, type); 2010 } 2011 2012 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev) 2013 { 2014 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1) 2015 qed_configure_filter_rx_mode(eth_dev, 2016 QED_FILTER_RX_MODE_TYPE_PROMISC); 2017 else 2018 qed_configure_filter_rx_mode(eth_dev, 2019 QED_FILTER_RX_MODE_TYPE_REGULAR); 2020 } 2021 2022 static int 2023 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs, 2024 uint32_t mc_addrs_num) 2025 { 2026 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2027 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2028 uint8_t i; 2029 2030 if (mc_addrs_num > ECORE_MAX_MC_ADDRS) { 2031 DP_ERR(edev, "Reached max multicast filters limit," 2032 "Please enable multicast promisc mode\n"); 2033 return -ENOSPC; 2034 } 2035 2036 for (i = 0; i < mc_addrs_num; i++) { 2037 if (!is_multicast_ether_addr(&mc_addrs[i])) { 2038 DP_ERR(edev, "Not a valid multicast MAC\n"); 2039 return -EINVAL; 2040 } 2041 } 2042 2043 /* Flush all existing entries */ 2044 if (qede_del_mcast_filters(eth_dev)) 2045 return -1; 2046 2047 /* Set new mcast list */ 2048 return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num); 2049 } 2050 2051 /* Update MTU via vport-update without doing port restart. 2052 * The vport must be deactivated before calling this API. 2053 */ 2054 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) 2055 { 2056 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2057 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2058 struct ecore_hwfn *p_hwfn; 2059 int rc; 2060 int i; 2061 2062 if (IS_PF(edev)) { 2063 struct ecore_sp_vport_update_params params; 2064 2065 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params)); 2066 params.vport_id = 0; 2067 params.mtu = mtu; 2068 params.vport_id = 0; 2069 for_each_hwfn(edev, i) { 2070 p_hwfn = &edev->hwfns[i]; 2071 params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2072 rc = ecore_sp_vport_update(p_hwfn, ¶ms, 2073 ECORE_SPQ_MODE_EBLOCK, NULL); 2074 if (rc != ECORE_SUCCESS) 2075 goto err; 2076 } 2077 } else { 2078 for_each_hwfn(edev, i) { 2079 p_hwfn = &edev->hwfns[i]; 2080 rc = ecore_vf_pf_update_mtu(p_hwfn, mtu); 2081 if (rc == ECORE_INVAL) { 2082 DP_INFO(edev, "VF MTU Update TLV not supported\n"); 2083 /* Recreate vport */ 2084 rc = qede_start_vport(qdev, mtu); 2085 if (rc != ECORE_SUCCESS) 2086 goto err; 2087 2088 /* Restore config lost due to vport stop */ 2089 if (eth_dev->data->promiscuous) 2090 qede_promiscuous_enable(eth_dev); 2091 else 2092 qede_promiscuous_disable(eth_dev); 2093 2094 if (eth_dev->data->all_multicast) 2095 qede_allmulticast_enable(eth_dev); 2096 else 2097 qede_allmulticast_disable(eth_dev); 2098 2099 qede_vlan_offload_set(eth_dev, 2100 qdev->vlan_offload_mask); 2101 } else if (rc != ECORE_SUCCESS) { 2102 goto err; 2103 } 2104 } 2105 } 2106 DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu); 2107 2108 return 0; 2109 2110 err: 2111 DP_ERR(edev, "Failed to update MTU\n"); 2112 return -1; 2113 } 2114 2115 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev, 2116 struct rte_eth_fc_conf *fc_conf) 2117 { 2118 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2119 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2120 struct qed_link_output current_link; 2121 struct qed_link_params params; 2122 2123 memset(¤t_link, 0, sizeof(current_link)); 2124 qdev->ops->common->get_link(edev, ¤t_link); 2125 2126 memset(¶ms, 0, sizeof(params)); 2127 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; 2128 if (fc_conf->autoneg) { 2129 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) { 2130 DP_ERR(edev, "Autoneg not supported\n"); 2131 return -EINVAL; 2132 } 2133 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; 2134 } 2135 2136 /* Pause is assumed to be supported (SUPPORTED_Pause) */ 2137 if (fc_conf->mode == RTE_FC_FULL) 2138 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE | 2139 QED_LINK_PAUSE_RX_ENABLE); 2140 if (fc_conf->mode == RTE_FC_TX_PAUSE) 2141 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE; 2142 if (fc_conf->mode == RTE_FC_RX_PAUSE) 2143 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; 2144 2145 params.link_up = true; 2146 (void)qdev->ops->common->set_link(edev, ¶ms); 2147 2148 return 0; 2149 } 2150 2151 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev, 2152 struct rte_eth_fc_conf *fc_conf) 2153 { 2154 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2155 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2156 struct qed_link_output current_link; 2157 2158 memset(¤t_link, 0, sizeof(current_link)); 2159 qdev->ops->common->get_link(edev, ¤t_link); 2160 2161 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE) 2162 fc_conf->autoneg = true; 2163 2164 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE | 2165 QED_LINK_PAUSE_TX_ENABLE)) 2166 fc_conf->mode = RTE_FC_FULL; 2167 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE) 2168 fc_conf->mode = RTE_FC_RX_PAUSE; 2169 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE) 2170 fc_conf->mode = RTE_FC_TX_PAUSE; 2171 else 2172 fc_conf->mode = RTE_FC_NONE; 2173 2174 return 0; 2175 } 2176 2177 static const uint32_t * 2178 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 2179 { 2180 static const uint32_t ptypes[] = { 2181 RTE_PTYPE_L2_ETHER, 2182 RTE_PTYPE_L2_ETHER_VLAN, 2183 RTE_PTYPE_L3_IPV4, 2184 RTE_PTYPE_L3_IPV6, 2185 RTE_PTYPE_L4_TCP, 2186 RTE_PTYPE_L4_UDP, 2187 RTE_PTYPE_TUNNEL_VXLAN, 2188 RTE_PTYPE_L4_FRAG, 2189 RTE_PTYPE_TUNNEL_GENEVE, 2190 RTE_PTYPE_TUNNEL_GRE, 2191 /* Inner */ 2192 RTE_PTYPE_INNER_L2_ETHER, 2193 RTE_PTYPE_INNER_L2_ETHER_VLAN, 2194 RTE_PTYPE_INNER_L3_IPV4, 2195 RTE_PTYPE_INNER_L3_IPV6, 2196 RTE_PTYPE_INNER_L4_TCP, 2197 RTE_PTYPE_INNER_L4_UDP, 2198 RTE_PTYPE_INNER_L4_FRAG, 2199 RTE_PTYPE_UNKNOWN 2200 }; 2201 2202 if (eth_dev->rx_pkt_burst == qede_recv_pkts) 2203 return ptypes; 2204 2205 return NULL; 2206 } 2207 2208 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf) 2209 { 2210 *rss_caps = 0; 2211 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0; 2212 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0; 2213 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0; 2214 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0; 2215 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0; 2216 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0; 2217 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0; 2218 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0; 2219 } 2220 2221 int qede_rss_hash_update(struct rte_eth_dev *eth_dev, 2222 struct rte_eth_rss_conf *rss_conf) 2223 { 2224 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2225 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2226 struct ecore_sp_vport_update_params vport_update_params; 2227 struct ecore_rss_params rss_params; 2228 struct ecore_hwfn *p_hwfn; 2229 uint32_t *key = (uint32_t *)rss_conf->rss_key; 2230 uint64_t hf = rss_conf->rss_hf; 2231 uint8_t len = rss_conf->rss_key_len; 2232 uint8_t idx; 2233 uint8_t i; 2234 int rc; 2235 2236 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2237 memset(&rss_params, 0, sizeof(rss_params)); 2238 2239 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n", 2240 (unsigned long)hf, len, key); 2241 2242 if (hf != 0) { 2243 /* Enabling RSS */ 2244 DP_INFO(edev, "Enabling rss\n"); 2245 2246 /* RSS caps */ 2247 qede_init_rss_caps(&rss_params.rss_caps, hf); 2248 rss_params.update_rss_capabilities = 1; 2249 2250 /* RSS hash key */ 2251 if (key) { 2252 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) { 2253 DP_ERR(edev, "RSS key length exceeds limit\n"); 2254 return -EINVAL; 2255 } 2256 DP_INFO(edev, "Applying user supplied hash key\n"); 2257 rss_params.update_rss_key = 1; 2258 memcpy(&rss_params.rss_key, key, len); 2259 } 2260 rss_params.rss_enable = 1; 2261 } 2262 2263 rss_params.update_rss_config = 1; 2264 /* tbl_size has to be set with capabilities */ 2265 rss_params.rss_table_size_log = 7; 2266 vport_update_params.vport_id = 0; 2267 /* pass the L2 handles instead of qids */ 2268 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { 2269 idx = i % QEDE_RSS_COUNT(qdev); 2270 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle; 2271 } 2272 vport_update_params.rss_params = &rss_params; 2273 2274 for_each_hwfn(edev, i) { 2275 p_hwfn = &edev->hwfns[i]; 2276 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2277 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2278 ECORE_SPQ_MODE_EBLOCK, NULL); 2279 if (rc) { 2280 DP_ERR(edev, "vport-update for RSS failed\n"); 2281 return rc; 2282 } 2283 } 2284 qdev->rss_enable = rss_params.rss_enable; 2285 2286 /* Update local structure for hash query */ 2287 qdev->rss_conf.rss_hf = hf; 2288 qdev->rss_conf.rss_key_len = len; 2289 if (qdev->rss_enable) { 2290 if (qdev->rss_conf.rss_key == NULL) { 2291 qdev->rss_conf.rss_key = (uint8_t *)malloc(len); 2292 if (qdev->rss_conf.rss_key == NULL) { 2293 DP_ERR(edev, "No memory to store RSS key\n"); 2294 return -ENOMEM; 2295 } 2296 } 2297 if (key && len) { 2298 DP_INFO(edev, "Storing RSS key\n"); 2299 memcpy(qdev->rss_conf.rss_key, key, len); 2300 } 2301 } else if (!qdev->rss_enable && len == 0) { 2302 if (qdev->rss_conf.rss_key) { 2303 free(qdev->rss_conf.rss_key); 2304 qdev->rss_conf.rss_key = NULL; 2305 DP_INFO(edev, "Free RSS key\n"); 2306 } 2307 } 2308 2309 return 0; 2310 } 2311 2312 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 2313 struct rte_eth_rss_conf *rss_conf) 2314 { 2315 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2316 2317 rss_conf->rss_hf = qdev->rss_conf.rss_hf; 2318 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len; 2319 2320 if (rss_conf->rss_key && qdev->rss_conf.rss_key) 2321 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key, 2322 rss_conf->rss_key_len); 2323 return 0; 2324 } 2325 2326 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev, 2327 struct ecore_rss_params *rss) 2328 { 2329 int i, fn; 2330 bool rss_mode = 1; /* enable */ 2331 struct ecore_queue_cid *cid; 2332 struct ecore_rss_params *t_rss; 2333 2334 /* In regular scenario, we'd simply need to take input handlers. 2335 * But in CMT, we'd have to split the handlers according to the 2336 * engine they were configured on. We'd then have to understand 2337 * whether RSS is really required, since 2-queues on CMT doesn't 2338 * require RSS. 2339 */ 2340 2341 /* CMT should be round-robin */ 2342 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) { 2343 cid = rss->rss_ind_table[i]; 2344 2345 if (cid->p_owner == ECORE_LEADING_HWFN(edev)) 2346 t_rss = &rss[0]; 2347 else 2348 t_rss = &rss[1]; 2349 2350 t_rss->rss_ind_table[i / edev->num_hwfns] = cid; 2351 } 2352 2353 t_rss = &rss[1]; 2354 t_rss->update_rss_ind_table = 1; 2355 t_rss->rss_table_size_log = 7; 2356 t_rss->update_rss_config = 1; 2357 2358 /* Make sure RSS is actually required */ 2359 for_each_hwfn(edev, fn) { 2360 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns; 2361 i++) { 2362 if (rss[fn].rss_ind_table[i] != 2363 rss[fn].rss_ind_table[0]) 2364 break; 2365 } 2366 2367 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) { 2368 DP_INFO(edev, 2369 "CMT - 1 queue per-hwfn; Disabling RSS\n"); 2370 rss_mode = 0; 2371 goto out; 2372 } 2373 } 2374 2375 out: 2376 t_rss->rss_enable = rss_mode; 2377 2378 return rss_mode; 2379 } 2380 2381 int qede_rss_reta_update(struct rte_eth_dev *eth_dev, 2382 struct rte_eth_rss_reta_entry64 *reta_conf, 2383 uint16_t reta_size) 2384 { 2385 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2386 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2387 struct ecore_sp_vport_update_params vport_update_params; 2388 struct ecore_rss_params *params; 2389 struct ecore_hwfn *p_hwfn; 2390 uint16_t i, idx, shift; 2391 uint8_t entry; 2392 int rc = 0; 2393 2394 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2395 DP_ERR(edev, "reta_size %d is not supported by hardware\n", 2396 reta_size); 2397 return -EINVAL; 2398 } 2399 2400 memset(&vport_update_params, 0, sizeof(vport_update_params)); 2401 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns, 2402 RTE_CACHE_LINE_SIZE); 2403 if (params == NULL) { 2404 DP_ERR(edev, "failed to allocate memory\n"); 2405 return -ENOMEM; 2406 } 2407 2408 for (i = 0; i < reta_size; i++) { 2409 idx = i / RTE_RETA_GROUP_SIZE; 2410 shift = i % RTE_RETA_GROUP_SIZE; 2411 if (reta_conf[idx].mask & (1ULL << shift)) { 2412 entry = reta_conf[idx].reta[shift]; 2413 /* Pass rxq handles to ecore */ 2414 params->rss_ind_table[i] = 2415 qdev->fp_array[entry].rxq->handle; 2416 /* Update the local copy for RETA query command */ 2417 qdev->rss_ind_table[i] = entry; 2418 } 2419 } 2420 2421 params->update_rss_ind_table = 1; 2422 params->rss_table_size_log = 7; 2423 params->update_rss_config = 1; 2424 2425 /* Fix up RETA for CMT mode device */ 2426 if (ECORE_IS_CMT(edev)) 2427 qdev->rss_enable = qede_update_rss_parm_cmt(edev, 2428 params); 2429 vport_update_params.vport_id = 0; 2430 /* Use the current value of rss_enable */ 2431 params->rss_enable = qdev->rss_enable; 2432 vport_update_params.rss_params = params; 2433 2434 for_each_hwfn(edev, i) { 2435 p_hwfn = &edev->hwfns[i]; 2436 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 2437 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 2438 ECORE_SPQ_MODE_EBLOCK, NULL); 2439 if (rc) { 2440 DP_ERR(edev, "vport-update for RSS failed\n"); 2441 goto out; 2442 } 2443 } 2444 2445 out: 2446 rte_free(params); 2447 return rc; 2448 } 2449 2450 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev, 2451 struct rte_eth_rss_reta_entry64 *reta_conf, 2452 uint16_t reta_size) 2453 { 2454 struct qede_dev *qdev = eth_dev->data->dev_private; 2455 struct ecore_dev *edev = &qdev->edev; 2456 uint16_t i, idx, shift; 2457 uint8_t entry; 2458 2459 if (reta_size > ETH_RSS_RETA_SIZE_128) { 2460 DP_ERR(edev, "reta_size %d is not supported\n", 2461 reta_size); 2462 return -EINVAL; 2463 } 2464 2465 for (i = 0; i < reta_size; i++) { 2466 idx = i / RTE_RETA_GROUP_SIZE; 2467 shift = i % RTE_RETA_GROUP_SIZE; 2468 if (reta_conf[idx].mask & (1ULL << shift)) { 2469 entry = qdev->rss_ind_table[i]; 2470 reta_conf[idx].reta[shift] = entry; 2471 } 2472 } 2473 2474 return 0; 2475 } 2476 2477 2478 2479 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 2480 { 2481 struct qede_dev *qdev = QEDE_INIT_QDEV(dev); 2482 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2483 struct rte_eth_dev_info dev_info = {0}; 2484 struct qede_fastpath *fp; 2485 uint32_t max_rx_pkt_len; 2486 uint32_t frame_size; 2487 uint16_t rx_buf_size; 2488 uint16_t bufsz; 2489 bool restart = false; 2490 int i; 2491 2492 PMD_INIT_FUNC_TRACE(edev); 2493 qede_dev_info_get(dev, &dev_info); 2494 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2495 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD; 2496 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) { 2497 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n", 2498 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN - 2499 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD); 2500 return -EINVAL; 2501 } 2502 if (!dev->data->scattered_rx && 2503 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 2504 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n", 2505 dev->data->min_rx_buf_size); 2506 return -EINVAL; 2507 } 2508 /* Temporarily replace I/O functions with dummy ones. It cannot 2509 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL. 2510 */ 2511 dev->rx_pkt_burst = qede_rxtx_pkts_dummy; 2512 dev->tx_pkt_burst = qede_rxtx_pkts_dummy; 2513 if (dev->data->dev_started) { 2514 dev->data->dev_started = 0; 2515 qede_dev_stop(dev); 2516 restart = true; 2517 } 2518 rte_delay_ms(1000); 2519 qdev->mtu = mtu; 2520 2521 /* Fix up RX buf size for all queues of the port */ 2522 for_each_rss(i) { 2523 fp = &qdev->fp_array[i]; 2524 if (fp->rxq != NULL) { 2525 bufsz = (uint16_t)rte_pktmbuf_data_room_size( 2526 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 2527 if (dev->data->scattered_rx) 2528 rx_buf_size = bufsz + ETHER_HDR_LEN + 2529 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD; 2530 else 2531 rx_buf_size = frame_size; 2532 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size); 2533 fp->rxq->rx_buf_size = rx_buf_size; 2534 DP_INFO(edev, "RX buffer size %u\n", rx_buf_size); 2535 } 2536 } 2537 if (max_rx_pkt_len > ETHER_MAX_LEN) 2538 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 2539 else 2540 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2541 2542 if (!dev->data->dev_started && restart) { 2543 qede_dev_start(dev); 2544 dev->data->dev_started = 1; 2545 } 2546 2547 /* update max frame size */ 2548 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len; 2549 /* Reassign back */ 2550 dev->rx_pkt_burst = qede_recv_pkts; 2551 dev->tx_pkt_burst = qede_xmit_pkts; 2552 2553 return 0; 2554 } 2555 2556 static int 2557 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev, 2558 struct rte_eth_udp_tunnel *tunnel_udp) 2559 { 2560 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2561 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2562 struct ecore_tunnel_info tunn; /* @DPDK */ 2563 uint16_t udp_port; 2564 int rc; 2565 2566 PMD_INIT_FUNC_TRACE(edev); 2567 2568 memset(&tunn, 0, sizeof(tunn)); 2569 2570 switch (tunnel_udp->prot_type) { 2571 case RTE_TUNNEL_TYPE_VXLAN: 2572 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) { 2573 DP_ERR(edev, "UDP port %u doesn't exist\n", 2574 tunnel_udp->udp_port); 2575 return ECORE_INVAL; 2576 } 2577 udp_port = 0; 2578 2579 tunn.vxlan_port.b_update_port = true; 2580 tunn.vxlan_port.port = udp_port; 2581 2582 rc = qede_tunnel_update(qdev, &tunn); 2583 if (rc != ECORE_SUCCESS) { 2584 DP_ERR(edev, "Unable to config UDP port %u\n", 2585 tunn.vxlan_port.port); 2586 return rc; 2587 } 2588 2589 qdev->vxlan.udp_port = udp_port; 2590 /* If the request is to delete UDP port and if the number of 2591 * VXLAN filters have reached 0 then VxLAN offload can be be 2592 * disabled. 2593 */ 2594 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0) 2595 return qede_vxlan_enable(eth_dev, 2596 ECORE_TUNN_CLSS_MAC_VLAN, false); 2597 2598 break; 2599 case RTE_TUNNEL_TYPE_GENEVE: 2600 if (qdev->geneve.udp_port != tunnel_udp->udp_port) { 2601 DP_ERR(edev, "UDP port %u doesn't exist\n", 2602 tunnel_udp->udp_port); 2603 return ECORE_INVAL; 2604 } 2605 2606 udp_port = 0; 2607 2608 tunn.geneve_port.b_update_port = true; 2609 tunn.geneve_port.port = udp_port; 2610 2611 rc = qede_tunnel_update(qdev, &tunn); 2612 if (rc != ECORE_SUCCESS) { 2613 DP_ERR(edev, "Unable to config UDP port %u\n", 2614 tunn.vxlan_port.port); 2615 return rc; 2616 } 2617 2618 qdev->vxlan.udp_port = udp_port; 2619 /* If the request is to delete UDP port and if the number of 2620 * GENEVE filters have reached 0 then GENEVE offload can be be 2621 * disabled. 2622 */ 2623 if (qdev->geneve.enable && qdev->geneve.num_filters == 0) 2624 return qede_geneve_enable(eth_dev, 2625 ECORE_TUNN_CLSS_MAC_VLAN, false); 2626 2627 break; 2628 2629 default: 2630 return ECORE_INVAL; 2631 } 2632 2633 return 0; 2634 2635 } 2636 static int 2637 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev, 2638 struct rte_eth_udp_tunnel *tunnel_udp) 2639 { 2640 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2641 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2642 struct ecore_tunnel_info tunn; /* @DPDK */ 2643 uint16_t udp_port; 2644 int rc; 2645 2646 PMD_INIT_FUNC_TRACE(edev); 2647 2648 memset(&tunn, 0, sizeof(tunn)); 2649 2650 switch (tunnel_udp->prot_type) { 2651 case RTE_TUNNEL_TYPE_VXLAN: 2652 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) { 2653 DP_INFO(edev, 2654 "UDP port %u for VXLAN was already configured\n", 2655 tunnel_udp->udp_port); 2656 return ECORE_SUCCESS; 2657 } 2658 2659 /* Enable VxLAN tunnel with default MAC/VLAN classification if 2660 * it was not enabled while adding VXLAN filter before UDP port 2661 * update. 2662 */ 2663 if (!qdev->vxlan.enable) { 2664 rc = qede_vxlan_enable(eth_dev, 2665 ECORE_TUNN_CLSS_MAC_VLAN, true); 2666 if (rc != ECORE_SUCCESS) { 2667 DP_ERR(edev, "Failed to enable VXLAN " 2668 "prior to updating UDP port\n"); 2669 return rc; 2670 } 2671 } 2672 udp_port = tunnel_udp->udp_port; 2673 2674 tunn.vxlan_port.b_update_port = true; 2675 tunn.vxlan_port.port = udp_port; 2676 2677 rc = qede_tunnel_update(qdev, &tunn); 2678 if (rc != ECORE_SUCCESS) { 2679 DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n", 2680 udp_port); 2681 return rc; 2682 } 2683 2684 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port); 2685 2686 qdev->vxlan.udp_port = udp_port; 2687 break; 2688 case RTE_TUNNEL_TYPE_GENEVE: 2689 if (qdev->geneve.udp_port == tunnel_udp->udp_port) { 2690 DP_INFO(edev, 2691 "UDP port %u for GENEVE was already configured\n", 2692 tunnel_udp->udp_port); 2693 return ECORE_SUCCESS; 2694 } 2695 2696 /* Enable GENEVE tunnel with default MAC/VLAN classification if 2697 * it was not enabled while adding GENEVE filter before UDP port 2698 * update. 2699 */ 2700 if (!qdev->geneve.enable) { 2701 rc = qede_geneve_enable(eth_dev, 2702 ECORE_TUNN_CLSS_MAC_VLAN, true); 2703 if (rc != ECORE_SUCCESS) { 2704 DP_ERR(edev, "Failed to enable GENEVE " 2705 "prior to updating UDP port\n"); 2706 return rc; 2707 } 2708 } 2709 udp_port = tunnel_udp->udp_port; 2710 2711 tunn.geneve_port.b_update_port = true; 2712 tunn.geneve_port.port = udp_port; 2713 2714 rc = qede_tunnel_update(qdev, &tunn); 2715 if (rc != ECORE_SUCCESS) { 2716 DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n", 2717 udp_port); 2718 return rc; 2719 } 2720 2721 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port); 2722 2723 qdev->geneve.udp_port = udp_port; 2724 break; 2725 default: 2726 return ECORE_INVAL; 2727 } 2728 2729 return 0; 2730 } 2731 2732 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type, 2733 uint32_t *clss, char *str) 2734 { 2735 uint16_t j; 2736 *clss = MAX_ECORE_TUNN_CLSS; 2737 2738 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) { 2739 if (filter == qede_tunn_types[j].rte_filter_type) { 2740 *type = qede_tunn_types[j].qede_type; 2741 *clss = qede_tunn_types[j].qede_tunn_clss; 2742 strcpy(str, qede_tunn_types[j].string); 2743 return; 2744 } 2745 } 2746 } 2747 2748 static int 2749 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast, 2750 const struct rte_eth_tunnel_filter_conf *conf, 2751 uint32_t type) 2752 { 2753 /* Init commmon ucast params first */ 2754 qede_set_ucast_cmn_params(ucast); 2755 2756 /* Copy out the required fields based on classification type */ 2757 ucast->type = type; 2758 2759 switch (type) { 2760 case ECORE_FILTER_VNI: 2761 ucast->vni = conf->tenant_id; 2762 break; 2763 case ECORE_FILTER_INNER_VLAN: 2764 ucast->vlan = conf->inner_vlan; 2765 break; 2766 case ECORE_FILTER_MAC: 2767 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2768 ETHER_ADDR_LEN); 2769 break; 2770 case ECORE_FILTER_INNER_MAC: 2771 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2772 ETHER_ADDR_LEN); 2773 break; 2774 case ECORE_FILTER_MAC_VNI_PAIR: 2775 memcpy(ucast->mac, conf->outer_mac.addr_bytes, 2776 ETHER_ADDR_LEN); 2777 ucast->vni = conf->tenant_id; 2778 break; 2779 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 2780 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2781 ETHER_ADDR_LEN); 2782 ucast->vni = conf->tenant_id; 2783 break; 2784 case ECORE_FILTER_INNER_PAIR: 2785 memcpy(ucast->mac, conf->inner_mac.addr_bytes, 2786 ETHER_ADDR_LEN); 2787 ucast->vlan = conf->inner_vlan; 2788 break; 2789 default: 2790 return -EINVAL; 2791 } 2792 2793 return ECORE_SUCCESS; 2794 } 2795 2796 static int 2797 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2798 const struct rte_eth_tunnel_filter_conf *conf, 2799 __attribute__((unused)) enum rte_filter_op filter_op, 2800 enum ecore_tunn_clss *clss, 2801 bool add) 2802 { 2803 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2804 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2805 struct ecore_filter_ucast ucast = {0}; 2806 enum ecore_filter_ucast_type type; 2807 uint16_t filter_type = 0; 2808 char str[80]; 2809 int rc; 2810 2811 filter_type = conf->filter_type; 2812 /* Determine if the given filter classification is supported */ 2813 qede_get_ecore_tunn_params(filter_type, &type, clss, str); 2814 if (*clss == MAX_ECORE_TUNN_CLSS) { 2815 DP_ERR(edev, "Unsupported filter type\n"); 2816 return -EINVAL; 2817 } 2818 /* Init tunnel ucast params */ 2819 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type); 2820 if (rc != ECORE_SUCCESS) { 2821 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n", 2822 conf->filter_type); 2823 return rc; 2824 } 2825 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n", 2826 str, filter_op, ucast.type); 2827 2828 ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE; 2829 2830 /* Skip MAC/VLAN if filter is based on VNI */ 2831 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) { 2832 rc = qede_mac_int_ops(eth_dev, &ucast, add); 2833 if ((rc == 0) && add) { 2834 /* Enable accept anyvlan */ 2835 qede_config_accept_any_vlan(qdev, true); 2836 } 2837 } else { 2838 rc = qede_ucast_filter(eth_dev, &ucast, add); 2839 if (rc == 0) 2840 rc = ecore_filter_ucast_cmd(edev, &ucast, 2841 ECORE_SPQ_MODE_CB, NULL); 2842 } 2843 2844 return rc; 2845 } 2846 2847 static int 2848 qede_tunn_filter_config(struct rte_eth_dev *eth_dev, 2849 enum rte_filter_op filter_op, 2850 const struct rte_eth_tunnel_filter_conf *conf) 2851 { 2852 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2853 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2854 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS; 2855 bool add; 2856 int rc; 2857 2858 PMD_INIT_FUNC_TRACE(edev); 2859 2860 switch (filter_op) { 2861 case RTE_ETH_FILTER_ADD: 2862 add = true; 2863 break; 2864 case RTE_ETH_FILTER_DELETE: 2865 add = false; 2866 break; 2867 default: 2868 DP_ERR(edev, "Unsupported operation %d\n", filter_op); 2869 return -EINVAL; 2870 } 2871 2872 if (IS_VF(edev)) 2873 return qede_tunn_enable(eth_dev, 2874 ECORE_TUNN_CLSS_MAC_VLAN, 2875 conf->tunnel_type, add); 2876 2877 rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add); 2878 if (rc != ECORE_SUCCESS) 2879 return rc; 2880 2881 if (add) { 2882 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) { 2883 qdev->vxlan.num_filters++; 2884 qdev->vxlan.filter_type = conf->filter_type; 2885 } else { /* GENEVE */ 2886 qdev->geneve.num_filters++; 2887 qdev->geneve.filter_type = conf->filter_type; 2888 } 2889 2890 if (!qdev->vxlan.enable || !qdev->geneve.enable || 2891 !qdev->ipgre.enable) 2892 return qede_tunn_enable(eth_dev, clss, 2893 conf->tunnel_type, 2894 true); 2895 } else { 2896 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) 2897 qdev->vxlan.num_filters--; 2898 else /*GENEVE*/ 2899 qdev->geneve.num_filters--; 2900 2901 /* Disable VXLAN if VXLAN filters become 0 */ 2902 if ((qdev->vxlan.num_filters == 0) || 2903 (qdev->geneve.num_filters == 0)) 2904 return qede_tunn_enable(eth_dev, clss, 2905 conf->tunnel_type, 2906 false); 2907 } 2908 2909 return 0; 2910 } 2911 2912 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev, 2913 enum rte_filter_type filter_type, 2914 enum rte_filter_op filter_op, 2915 void *arg) 2916 { 2917 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev); 2918 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev); 2919 struct rte_eth_tunnel_filter_conf *filter_conf = 2920 (struct rte_eth_tunnel_filter_conf *)arg; 2921 2922 switch (filter_type) { 2923 case RTE_ETH_FILTER_TUNNEL: 2924 switch (filter_conf->tunnel_type) { 2925 case RTE_TUNNEL_TYPE_VXLAN: 2926 case RTE_TUNNEL_TYPE_GENEVE: 2927 case RTE_TUNNEL_TYPE_IP_IN_GRE: 2928 DP_INFO(edev, 2929 "Packet steering to the specified Rx queue" 2930 " is not supported with UDP tunneling"); 2931 return(qede_tunn_filter_config(eth_dev, filter_op, 2932 filter_conf)); 2933 case RTE_TUNNEL_TYPE_TEREDO: 2934 case RTE_TUNNEL_TYPE_NVGRE: 2935 case RTE_L2_TUNNEL_TYPE_E_TAG: 2936 DP_ERR(edev, "Unsupported tunnel type %d\n", 2937 filter_conf->tunnel_type); 2938 return -EINVAL; 2939 case RTE_TUNNEL_TYPE_NONE: 2940 default: 2941 return 0; 2942 } 2943 break; 2944 case RTE_ETH_FILTER_FDIR: 2945 return qede_fdir_filter_conf(eth_dev, filter_op, arg); 2946 case RTE_ETH_FILTER_NTUPLE: 2947 return qede_ntuple_filter_conf(eth_dev, filter_op, arg); 2948 case RTE_ETH_FILTER_MACVLAN: 2949 case RTE_ETH_FILTER_ETHERTYPE: 2950 case RTE_ETH_FILTER_FLEXIBLE: 2951 case RTE_ETH_FILTER_SYN: 2952 case RTE_ETH_FILTER_HASH: 2953 case RTE_ETH_FILTER_L2_TUNNEL: 2954 case RTE_ETH_FILTER_MAX: 2955 default: 2956 DP_ERR(edev, "Unsupported filter type %d\n", 2957 filter_type); 2958 return -EINVAL; 2959 } 2960 2961 return 0; 2962 } 2963 2964 static const struct eth_dev_ops qede_eth_dev_ops = { 2965 .dev_configure = qede_dev_configure, 2966 .dev_infos_get = qede_dev_info_get, 2967 .rx_queue_setup = qede_rx_queue_setup, 2968 .rx_queue_release = qede_rx_queue_release, 2969 .tx_queue_setup = qede_tx_queue_setup, 2970 .tx_queue_release = qede_tx_queue_release, 2971 .dev_start = qede_dev_start, 2972 .dev_set_link_up = qede_dev_set_link_up, 2973 .dev_set_link_down = qede_dev_set_link_down, 2974 .link_update = qede_link_update, 2975 .promiscuous_enable = qede_promiscuous_enable, 2976 .promiscuous_disable = qede_promiscuous_disable, 2977 .allmulticast_enable = qede_allmulticast_enable, 2978 .allmulticast_disable = qede_allmulticast_disable, 2979 .set_mc_addr_list = qede_set_mc_addr_list, 2980 .dev_stop = qede_dev_stop, 2981 .dev_close = qede_dev_close, 2982 .stats_get = qede_get_stats, 2983 .stats_reset = qede_reset_stats, 2984 .xstats_get = qede_get_xstats, 2985 .xstats_reset = qede_reset_xstats, 2986 .xstats_get_names = qede_get_xstats_names, 2987 .mac_addr_add = qede_mac_addr_add, 2988 .mac_addr_remove = qede_mac_addr_remove, 2989 .mac_addr_set = qede_mac_addr_set, 2990 .vlan_offload_set = qede_vlan_offload_set, 2991 .vlan_filter_set = qede_vlan_filter_set, 2992 .flow_ctrl_set = qede_flow_ctrl_set, 2993 .flow_ctrl_get = qede_flow_ctrl_get, 2994 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 2995 .rss_hash_update = qede_rss_hash_update, 2996 .rss_hash_conf_get = qede_rss_hash_conf_get, 2997 .reta_update = qede_rss_reta_update, 2998 .reta_query = qede_rss_reta_query, 2999 .mtu_set = qede_set_mtu, 3000 .filter_ctrl = qede_dev_filter_ctrl, 3001 .udp_tunnel_port_add = qede_udp_dst_port_add, 3002 .udp_tunnel_port_del = qede_udp_dst_port_del, 3003 }; 3004 3005 static const struct eth_dev_ops qede_eth_vf_dev_ops = { 3006 .dev_configure = qede_dev_configure, 3007 .dev_infos_get = qede_dev_info_get, 3008 .rx_queue_setup = qede_rx_queue_setup, 3009 .rx_queue_release = qede_rx_queue_release, 3010 .tx_queue_setup = qede_tx_queue_setup, 3011 .tx_queue_release = qede_tx_queue_release, 3012 .dev_start = qede_dev_start, 3013 .dev_set_link_up = qede_dev_set_link_up, 3014 .dev_set_link_down = qede_dev_set_link_down, 3015 .link_update = qede_link_update, 3016 .promiscuous_enable = qede_promiscuous_enable, 3017 .promiscuous_disable = qede_promiscuous_disable, 3018 .allmulticast_enable = qede_allmulticast_enable, 3019 .allmulticast_disable = qede_allmulticast_disable, 3020 .set_mc_addr_list = qede_set_mc_addr_list, 3021 .dev_stop = qede_dev_stop, 3022 .dev_close = qede_dev_close, 3023 .stats_get = qede_get_stats, 3024 .stats_reset = qede_reset_stats, 3025 .xstats_get = qede_get_xstats, 3026 .xstats_reset = qede_reset_xstats, 3027 .xstats_get_names = qede_get_xstats_names, 3028 .vlan_offload_set = qede_vlan_offload_set, 3029 .vlan_filter_set = qede_vlan_filter_set, 3030 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get, 3031 .rss_hash_update = qede_rss_hash_update, 3032 .rss_hash_conf_get = qede_rss_hash_conf_get, 3033 .reta_update = qede_rss_reta_update, 3034 .reta_query = qede_rss_reta_query, 3035 .mtu_set = qede_set_mtu, 3036 .udp_tunnel_port_add = qede_udp_dst_port_add, 3037 .udp_tunnel_port_del = qede_udp_dst_port_del, 3038 .mac_addr_add = qede_mac_addr_add, 3039 .mac_addr_remove = qede_mac_addr_remove, 3040 .mac_addr_set = qede_mac_addr_set, 3041 }; 3042 3043 static void qede_update_pf_params(struct ecore_dev *edev) 3044 { 3045 struct ecore_pf_params pf_params; 3046 3047 memset(&pf_params, 0, sizeof(struct ecore_pf_params)); 3048 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS; 3049 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR; 3050 qed_ops->common->update_pf_params(edev, &pf_params); 3051 } 3052 3053 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) 3054 { 3055 struct rte_pci_device *pci_dev; 3056 struct rte_pci_addr pci_addr; 3057 struct qede_dev *adapter; 3058 struct ecore_dev *edev; 3059 struct qed_dev_eth_info dev_info; 3060 struct qed_slowpath_params params; 3061 static bool do_once = true; 3062 uint8_t bulletin_change; 3063 uint8_t vf_mac[ETHER_ADDR_LEN]; 3064 uint8_t is_mac_forced; 3065 bool is_mac_exist; 3066 /* Fix up ecore debug level */ 3067 uint32_t dp_module = ~0 & ~ECORE_MSG_HW; 3068 uint8_t dp_level = ECORE_LEVEL_VERBOSE; 3069 uint32_t int_mode; 3070 int rc; 3071 3072 /* Extract key data structures */ 3073 adapter = eth_dev->data->dev_private; 3074 adapter->ethdev = eth_dev; 3075 edev = &adapter->edev; 3076 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3077 pci_addr = pci_dev->addr; 3078 3079 PMD_INIT_FUNC_TRACE(edev); 3080 3081 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u", 3082 pci_addr.bus, pci_addr.devid, pci_addr.function, 3083 eth_dev->data->port_id); 3084 3085 eth_dev->rx_pkt_burst = qede_recv_pkts; 3086 eth_dev->tx_pkt_burst = qede_xmit_pkts; 3087 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts; 3088 3089 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3090 DP_ERR(edev, "Skipping device init from secondary process\n"); 3091 return 0; 3092 } 3093 3094 rte_eth_copy_pci_info(eth_dev, pci_dev); 3095 3096 /* @DPDK */ 3097 edev->vendor_id = pci_dev->id.vendor_id; 3098 edev->device_id = pci_dev->id.device_id; 3099 3100 qed_ops = qed_get_eth_ops(); 3101 if (!qed_ops) { 3102 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n"); 3103 return -EINVAL; 3104 } 3105 3106 DP_INFO(edev, "Starting qede probe\n"); 3107 rc = qed_ops->common->probe(edev, pci_dev, dp_module, 3108 dp_level, is_vf); 3109 if (rc != 0) { 3110 DP_ERR(edev, "qede probe failed rc %d\n", rc); 3111 return -ENODEV; 3112 } 3113 qede_update_pf_params(edev); 3114 3115 switch (pci_dev->intr_handle.type) { 3116 case RTE_INTR_HANDLE_UIO_INTX: 3117 case RTE_INTR_HANDLE_VFIO_LEGACY: 3118 int_mode = ECORE_INT_MODE_INTA; 3119 rte_intr_callback_register(&pci_dev->intr_handle, 3120 qede_interrupt_handler_intx, 3121 (void *)eth_dev); 3122 break; 3123 default: 3124 int_mode = ECORE_INT_MODE_MSIX; 3125 rte_intr_callback_register(&pci_dev->intr_handle, 3126 qede_interrupt_handler, 3127 (void *)eth_dev); 3128 } 3129 3130 if (rte_intr_enable(&pci_dev->intr_handle)) { 3131 DP_ERR(edev, "rte_intr_enable() failed\n"); 3132 return -ENODEV; 3133 } 3134 3135 /* Start the Slowpath-process */ 3136 memset(¶ms, 0, sizeof(struct qed_slowpath_params)); 3137 3138 params.int_mode = int_mode; 3139 params.drv_major = QEDE_PMD_VERSION_MAJOR; 3140 params.drv_minor = QEDE_PMD_VERSION_MINOR; 3141 params.drv_rev = QEDE_PMD_VERSION_REVISION; 3142 params.drv_eng = QEDE_PMD_VERSION_PATCH; 3143 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX, 3144 QEDE_PMD_DRV_VER_STR_SIZE); 3145 3146 /* For CMT mode device do periodic polling for slowpath events. 3147 * This is required since uio device uses only one MSI-x 3148 * interrupt vector but we need one for each engine. 3149 */ 3150 if (ECORE_IS_CMT(edev) && IS_PF(edev)) { 3151 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD, 3152 qede_poll_sp_sb_cb, 3153 (void *)eth_dev); 3154 if (rc != 0) { 3155 DP_ERR(edev, "Unable to start periodic" 3156 " timer rc %d\n", rc); 3157 return -EINVAL; 3158 } 3159 } 3160 3161 rc = qed_ops->common->slowpath_start(edev, ¶ms); 3162 if (rc) { 3163 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc); 3164 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3165 (void *)eth_dev); 3166 return -ENODEV; 3167 } 3168 3169 rc = qed_ops->fill_dev_info(edev, &dev_info); 3170 if (rc) { 3171 DP_ERR(edev, "Cannot get device_info rc %d\n", rc); 3172 qed_ops->common->slowpath_stop(edev); 3173 qed_ops->common->remove(edev); 3174 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3175 (void *)eth_dev); 3176 return -ENODEV; 3177 } 3178 3179 qede_alloc_etherdev(adapter, &dev_info); 3180 3181 adapter->ops->common->set_name(edev, edev->name); 3182 3183 if (!is_vf) 3184 adapter->dev_info.num_mac_filters = 3185 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev), 3186 ECORE_MAC); 3187 else 3188 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev), 3189 (uint32_t *)&adapter->dev_info.num_mac_filters); 3190 3191 /* Allocate memory for storing MAC addr */ 3192 eth_dev->data->mac_addrs = rte_zmalloc(edev->name, 3193 (ETHER_ADDR_LEN * 3194 adapter->dev_info.num_mac_filters), 3195 RTE_CACHE_LINE_SIZE); 3196 3197 if (eth_dev->data->mac_addrs == NULL) { 3198 DP_ERR(edev, "Failed to allocate MAC address\n"); 3199 qed_ops->common->slowpath_stop(edev); 3200 qed_ops->common->remove(edev); 3201 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, 3202 (void *)eth_dev); 3203 return -ENOMEM; 3204 } 3205 3206 if (!is_vf) { 3207 ether_addr_copy((struct ether_addr *)edev->hwfns[0]. 3208 hw_info.hw_mac_addr, 3209 ð_dev->data->mac_addrs[0]); 3210 ether_addr_copy(ð_dev->data->mac_addrs[0], 3211 &adapter->primary_mac); 3212 } else { 3213 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev), 3214 &bulletin_change); 3215 if (bulletin_change) { 3216 is_mac_exist = 3217 ecore_vf_bulletin_get_forced_mac( 3218 ECORE_LEADING_HWFN(edev), 3219 vf_mac, 3220 &is_mac_forced); 3221 if (is_mac_exist) { 3222 DP_INFO(edev, "VF macaddr received from PF\n"); 3223 ether_addr_copy((struct ether_addr *)&vf_mac, 3224 ð_dev->data->mac_addrs[0]); 3225 ether_addr_copy(ð_dev->data->mac_addrs[0], 3226 &adapter->primary_mac); 3227 } else { 3228 DP_ERR(edev, "No VF macaddr assigned\n"); 3229 } 3230 } 3231 } 3232 3233 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops; 3234 3235 if (do_once) { 3236 qede_print_adapter_info(adapter); 3237 do_once = false; 3238 } 3239 3240 /* Bring-up the link */ 3241 qede_dev_set_link_state(eth_dev, true); 3242 3243 adapter->num_tx_queues = 0; 3244 adapter->num_rx_queues = 0; 3245 SLIST_INIT(&adapter->fdir_info.fdir_list_head); 3246 SLIST_INIT(&adapter->vlan_list_head); 3247 SLIST_INIT(&adapter->uc_list_head); 3248 SLIST_INIT(&adapter->mc_list_head); 3249 adapter->mtu = ETHER_MTU; 3250 adapter->vport_started = false; 3251 3252 /* VF tunnel offloads is enabled by default in PF driver */ 3253 adapter->vxlan.num_filters = 0; 3254 adapter->geneve.num_filters = 0; 3255 adapter->ipgre.num_filters = 0; 3256 if (is_vf) { 3257 adapter->vxlan.enable = true; 3258 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC | 3259 ETH_TUNNEL_FILTER_IVLAN; 3260 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT; 3261 adapter->geneve.enable = true; 3262 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC | 3263 ETH_TUNNEL_FILTER_IVLAN; 3264 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT; 3265 adapter->ipgre.enable = true; 3266 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC | 3267 ETH_TUNNEL_FILTER_IVLAN; 3268 } else { 3269 adapter->vxlan.enable = false; 3270 adapter->geneve.enable = false; 3271 adapter->ipgre.enable = false; 3272 } 3273 3274 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", 3275 adapter->primary_mac.addr_bytes[0], 3276 adapter->primary_mac.addr_bytes[1], 3277 adapter->primary_mac.addr_bytes[2], 3278 adapter->primary_mac.addr_bytes[3], 3279 adapter->primary_mac.addr_bytes[4], 3280 adapter->primary_mac.addr_bytes[5]); 3281 3282 DP_INFO(edev, "Device initialized\n"); 3283 3284 return 0; 3285 } 3286 3287 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev) 3288 { 3289 return qede_common_dev_init(eth_dev, 1); 3290 } 3291 3292 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev) 3293 { 3294 return qede_common_dev_init(eth_dev, 0); 3295 } 3296 3297 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev) 3298 { 3299 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT 3300 struct qede_dev *qdev = eth_dev->data->dev_private; 3301 struct ecore_dev *edev = &qdev->edev; 3302 3303 PMD_INIT_FUNC_TRACE(edev); 3304 #endif 3305 3306 /* only uninitialize in the primary process */ 3307 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3308 return 0; 3309 3310 /* safe to close dev here */ 3311 qede_dev_close(eth_dev); 3312 3313 eth_dev->dev_ops = NULL; 3314 eth_dev->rx_pkt_burst = NULL; 3315 eth_dev->tx_pkt_burst = NULL; 3316 3317 if (eth_dev->data->mac_addrs) 3318 rte_free(eth_dev->data->mac_addrs); 3319 3320 eth_dev->data->mac_addrs = NULL; 3321 3322 return 0; 3323 } 3324 3325 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3326 { 3327 return qede_dev_common_uninit(eth_dev); 3328 } 3329 3330 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev) 3331 { 3332 return qede_dev_common_uninit(eth_dev); 3333 } 3334 3335 static const struct rte_pci_id pci_id_qedevf_map[] = { 3336 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3337 { 3338 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF) 3339 }, 3340 { 3341 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV) 3342 }, 3343 { 3344 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV) 3345 }, 3346 {.vendor_id = 0,} 3347 }; 3348 3349 static const struct rte_pci_id pci_id_qede_map[] = { 3350 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev) 3351 { 3352 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E) 3353 }, 3354 { 3355 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S) 3356 }, 3357 { 3358 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40) 3359 }, 3360 { 3361 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25) 3362 }, 3363 { 3364 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100) 3365 }, 3366 { 3367 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50) 3368 }, 3369 { 3370 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G) 3371 }, 3372 { 3373 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G) 3374 }, 3375 { 3376 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G) 3377 }, 3378 { 3379 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G) 3380 }, 3381 {.vendor_id = 0,} 3382 }; 3383 3384 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3385 struct rte_pci_device *pci_dev) 3386 { 3387 return rte_eth_dev_pci_generic_probe(pci_dev, 3388 sizeof(struct qede_dev), qedevf_eth_dev_init); 3389 } 3390 3391 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3392 { 3393 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit); 3394 } 3395 3396 static struct rte_pci_driver rte_qedevf_pmd = { 3397 .id_table = pci_id_qedevf_map, 3398 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3399 .probe = qedevf_eth_dev_pci_probe, 3400 .remove = qedevf_eth_dev_pci_remove, 3401 }; 3402 3403 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3404 struct rte_pci_device *pci_dev) 3405 { 3406 return rte_eth_dev_pci_generic_probe(pci_dev, 3407 sizeof(struct qede_dev), qede_eth_dev_init); 3408 } 3409 3410 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev) 3411 { 3412 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit); 3413 } 3414 3415 static struct rte_pci_driver rte_qede_pmd = { 3416 .id_table = pci_id_qede_map, 3417 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3418 .probe = qede_eth_dev_pci_probe, 3419 .remove = qede_eth_dev_pci_remove, 3420 }; 3421 3422 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd); 3423 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map); 3424 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci"); 3425 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd); 3426 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map); 3427 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci"); 3428 3429 RTE_INIT(qede_init_log) 3430 { 3431 qede_logtype_init = rte_log_register("pmd.net.qede.init"); 3432 if (qede_logtype_init >= 0) 3433 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE); 3434 qede_logtype_driver = rte_log_register("pmd.net.qede.driver"); 3435 if (qede_logtype_driver >= 0) 3436 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE); 3437 } 3438