xref: /dpdk/drivers/net/qede/base/ecore_sp_commands.h (revision d80e42cce4c7017ed8c99dabb8ae444a492acc1c)
1 /*
2  * Copyright (c) 2016 - 2018 Cavium Inc.
3  * All rights reserved.
4  * www.cavium.com
5  *
6  * See LICENSE.qede_pmd for copyright and licensing details.
7  */
8 
9 #ifndef __ECORE_SP_COMMANDS_H__
10 #define __ECORE_SP_COMMANDS_H__
11 
12 #include "ecore.h"
13 #include "ecore_spq.h"
14 #include "ecore_sp_api.h"
15 
16 #define ECORE_SP_EQ_COMPLETION  0x01
17 #define ECORE_SP_CQE_COMPLETION 0x02
18 
19 struct ecore_sp_init_data {
20 	/* The CID and FID aren't necessarily derived from hwfn,
21 	 * e.g., in IOV scenarios. CID might defer between SPQ and
22 	 * other elements.
23 	 */
24 	u32				cid;
25 	u16				opaque_fid;
26 
27 	/* Information regarding operation upon sending & completion */
28 	enum spq_mode			comp_mode;
29 	struct ecore_spq_comp_cb	*p_comp_data;
30 
31 };
32 
33 /**
34  * @brief Acquire and initialize and SPQ entry for a given ramrod.
35  *
36  * @param p_hwfn
37  * @param pp_ent - will be filled with a pointer to an entry upon success
38  * @param cmd - dependent upon protocol
39  * @param protocol
40  * @param p_data - various configuration required for ramrod
41  *
42  * @return ECORE_SUCCESS upon success, otherwise failure.
43  */
44 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
45 					   struct ecore_spq_entry **pp_ent,
46 					   u8 cmd,
47 					   u8 protocol,
48 					   struct ecore_sp_init_data *p_data);
49 
50 /**
51  * @brief ecore_sp_pf_start - PF Function Start Ramrod
52  *
53  * This ramrod is sent to initialize a physical function (PF). It will
54  * configure the function related parameters and write its completion to the
55  * event ring specified in the parameters.
56  *
57  * Ramrods complete on the common event ring for the PF. This ring is
58  * allocated by the driver on host memory and its parameters are written
59  * to the internal RAM of the UStorm by the Function Start Ramrod.
60  *
61  * @param p_hwfn
62  * @param p_ptt
63  * @param p_tunn - pf start tunneling configuration
64  * @param allow_npar_tx_switch - npar tx switching to be used
65  *	  for vports configured for tx-switching.
66  *
67  * @return enum _ecore_status_t
68  */
69 
70 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
71 				       struct ecore_ptt *p_ptt,
72 				       struct ecore_tunnel_info *p_tunn,
73 				       bool allow_npar_tx_switch);
74 
75 /**
76  * @brief ecore_sp_pf_update - PF Function Update Ramrod
77  *
78  * This ramrod updates function-related parameters. Every parameter can be
79  * updated independently, according to configuration flags.
80  *
81  * @note Final phase API.
82  *
83  * @param p_hwfn
84  *
85  * @return enum _ecore_status_t
86  */
87 
88 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn);
89 
90 /**
91  * @brief ecore_sp_pf_stop - PF Function Stop Ramrod
92  *
93  * This ramrod is sent to close a Physical Function (PF). It is the last ramrod
94  * sent and the last completion written to the PFs Event Ring. This ramrod also
95  * deletes the context for the Slowhwfn connection on this PF.
96  *
97  * @note Not required for first packet.
98  *
99  * @param p_hwfn
100  *
101  * @return enum _ecore_status_t
102  */
103 
104 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);
105 
106 /**
107  * @brief ecore_sp_heartbeat_ramrod - Send empty Ramrod
108  *
109  * @param p_hwfn
110  *
111  * @return enum _ecore_status_t
112  */
113 
114 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);
115 
116 struct ecore_rl_update_params {
117 	u8 qcn_update_param_flg;
118 	u8 dcqcn_update_param_flg;
119 	u8 rl_init_flg;
120 	u8 rl_start_flg;
121 	u8 rl_stop_flg;
122 	u8 rl_id_first;
123 	u8 rl_id_last;
124 	u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
125 	u32 rl_bc_rate; /* Byte Counter Limit */
126 	u32 rl_max_rate; /* Maximum rate in Mbps resolution */
127 	u32 rl_r_ai; /* Active increase rate */
128 	u32 rl_r_hai; /* Hyper active increase rate */
129 	u32 dcqcn_gd; /* DCQCN Alpha update gain */
130 	u32 dcqcn_k_us; /* DCQCN Alpha update interval */
131 	u32 dcqcn_timeuot_us;
132 	u32 qcn_timeuot_us;
133 };
134 
135 /**
136  * @brief ecore_sp_rl_update - Update rate limiters
137  *
138  * @param p_hwfn
139  * @param params
140  *
141  * @return enum _ecore_status_t
142  */
143 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
144 					struct ecore_rl_update_params *params);
145 
146 /**
147  * @brief ecore_sp_pf_update_stag - PF STAG value update Ramrod
148  *
149  * @param p_hwfn
150  *
151  * @return enum _ecore_status_t
152  */
153 
154 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn);
155 
156 /**
157  * @brief ecore_sp_pf_update_ufp - PF ufp update Ramrod
158  *
159  * @param p_hwfn
160  *
161  * @return enum _ecore_status_t
162  */
163 enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn);
164 
165 #endif /*__ECORE_SP_COMMANDS_H__*/
166