1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #ifndef __ECORE_INT_API_H__ 10 #define __ECORE_INT_API_H__ 11 12 #ifndef __EXTRACT__LINUX__ 13 #define ECORE_SB_IDX 0x0002 14 15 #define RX_PI 0 16 #define TX_PI(tc) (RX_PI + 1 + tc) 17 18 #ifndef ECORE_INT_MODE 19 #define ECORE_INT_MODE 20 enum ecore_int_mode { 21 ECORE_INT_MODE_INTA, 22 ECORE_INT_MODE_MSIX, 23 ECORE_INT_MODE_MSI, 24 ECORE_INT_MODE_POLL, 25 }; 26 #endif 27 28 struct ecore_sb_info { 29 struct status_block_e4 *sb_virt; 30 dma_addr_t sb_phys; 31 u32 sb_ack; /* Last given ack */ 32 u16 igu_sb_id; 33 void OSAL_IOMEM *igu_addr; 34 u8 flags; 35 #define ECORE_SB_INFO_INIT 0x1 36 #define ECORE_SB_INFO_SETUP 0x2 37 38 #ifdef ECORE_CONFIG_DIRECT_HWFN 39 struct ecore_hwfn *p_hwfn; 40 #endif 41 struct ecore_dev *p_dev; 42 }; 43 44 struct ecore_sb_info_dbg { 45 u32 igu_prod; 46 u32 igu_cons; 47 u16 pi[PIS_PER_SB_E4]; 48 }; 49 50 struct ecore_sb_cnt_info { 51 /* Original, current, and free SBs for PF */ 52 int orig; 53 int cnt; 54 int free_cnt; 55 56 /* Original, current and free SBS for child VFs */ 57 int iov_orig; 58 int iov_cnt; 59 int free_cnt_iov; 60 }; 61 62 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info) 63 { 64 u32 prod = 0; 65 u16 rc = 0; 66 67 /* barrier(); status block is written to by the chip */ 68 /* FIXME: need some sort of barrier. */ 69 prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) & 70 STATUS_BLOCK_E4_PROD_INDEX_MASK; 71 if (sb_info->sb_ack != prod) { 72 sb_info->sb_ack = prod; 73 rc |= ECORE_SB_IDX; 74 } 75 76 OSAL_MMIOWB(sb_info->p_dev); 77 return rc; 78 } 79 80 /** 81 * 82 * @brief This function creates an update command for interrupts that is 83 * written to the IGU. 84 * 85 * @param sb_info - This is the structure allocated and 86 * initialized per status block. Assumption is 87 * that it was initialized using ecore_sb_init 88 * @param int_cmd - Enable/Disable/Nop 89 * @param upd_flg - whether igu consumer should be 90 * updated. 91 * 92 * @return OSAL_INLINE void 93 */ 94 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info, 95 enum igu_int_cmd int_cmd, u8 upd_flg) 96 { 97 struct igu_prod_cons_update igu_ack = { 0 }; 98 99 igu_ack.sb_id_and_flags = 100 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 101 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 102 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 103 (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 104 105 #ifdef ECORE_CONFIG_DIRECT_HWFN 106 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr, 107 igu_ack.sb_id_and_flags); 108 #else 109 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags); 110 #endif 111 /* Both segments (interrupts & acks) are written to same place address; 112 * Need to guarantee all commands will be received (in-order) by HW. 113 */ 114 OSAL_MMIOWB(sb_info->p_dev); 115 OSAL_BARRIER(sb_info->p_dev); 116 } 117 118 #ifdef ECORE_CONFIG_DIRECT_HWFN 119 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn, 120 void OSAL_IOMEM *addr, 121 int size, u32 *data) 122 #else 123 static OSAL_INLINE void __internal_ram_wr(__rte_unused void *p_hwfn, 124 void OSAL_IOMEM *addr, 125 int size, u32 *data) 126 #endif 127 { 128 unsigned int i; 129 130 for (i = 0; i < size / sizeof(*data); i++) 131 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]); 132 } 133 134 #ifdef ECORE_CONFIG_DIRECT_HWFN 135 static OSAL_INLINE void __internal_ram_wr_relaxed(struct ecore_hwfn *p_hwfn, 136 void OSAL_IOMEM * addr, 137 int size, u32 *data) 138 #else 139 static OSAL_INLINE void __internal_ram_wr_relaxed(__rte_unused void *p_hwfn, 140 void OSAL_IOMEM * addr, 141 int size, u32 *data) 142 #endif 143 { 144 unsigned int i; 145 146 for (i = 0; i < size / sizeof(*data); i++) 147 DIRECT_REG_WR_RELAXED(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], 148 data[i]); 149 } 150 151 #ifdef ECORE_CONFIG_DIRECT_HWFN 152 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn, 153 void OSAL_IOMEM * addr, 154 int size, u32 *data) 155 { 156 __internal_ram_wr_relaxed(p_hwfn, addr, size, data); 157 } 158 #else 159 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr, 160 int size, u32 *data) 161 { 162 __internal_ram_wr_relaxed(OSAL_NULL, addr, size, data); 163 } 164 #endif 165 166 #endif 167 168 struct ecore_hwfn; 169 struct ecore_ptt; 170 171 enum ecore_coalescing_fsm { 172 ECORE_COAL_RX_STATE_MACHINE, 173 ECORE_COAL_TX_STATE_MACHINE 174 }; 175 176 /** 177 * @brief ecore_int_cau_conf_pi - configure cau for a given 178 * status block 179 * 180 * @param p_hwfn 181 * @param p_ptt 182 * @param p_sb 183 * @param pi_index 184 * @param state 185 * @param timeset 186 */ 187 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn, 188 struct ecore_ptt *p_ptt, 189 struct ecore_sb_info *p_sb, 190 u32 pi_index, 191 enum ecore_coalescing_fsm coalescing_fsm, 192 u8 timeset); 193 194 /** 195 * 196 * @brief ecore_int_igu_enable_int - enable device interrupts 197 * 198 * @param p_hwfn 199 * @param p_ptt 200 * @param int_mode - interrupt mode to use 201 */ 202 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn, 203 struct ecore_ptt *p_ptt, 204 enum ecore_int_mode int_mode); 205 206 /** 207 * 208 * @brief ecore_int_igu_disable_int - disable device interrupts 209 * 210 * @param p_hwfn 211 * @param p_ptt 212 */ 213 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn, 214 struct ecore_ptt *p_ptt); 215 216 /** 217 * 218 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc 219 * register from igu. 220 * 221 * @param p_hwfn 222 * 223 * @return u64 224 */ 225 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn); 226 227 #define ECORE_SP_SB_ID 0xffff 228 229 /** 230 * @brief ecore_int_sb_init - Initializes the sb_info structure. 231 * 232 * once the structure is initialized it can be passed to sb related functions. 233 * 234 * @param p_hwfn 235 * @param p_ptt 236 * @param sb_info points to an uninitialized (but 237 * allocated) sb_info structure 238 * @param sb_virt_addr 239 * @param sb_phy_addr 240 * @param sb_id the sb_id to be used (zero based in driver) 241 * should use ECORE_SP_SB_ID for SP Status block 242 * 243 * @return enum _ecore_status_t 244 */ 245 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn, 246 struct ecore_ptt *p_ptt, 247 struct ecore_sb_info *sb_info, 248 void *sb_virt_addr, 249 dma_addr_t sb_phy_addr, u16 sb_id); 250 /** 251 * @brief ecore_int_sb_setup - Setup the sb. 252 * 253 * @param p_hwfn 254 * @param p_ptt 255 * @param sb_info initialized sb_info structure 256 */ 257 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn, 258 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info); 259 260 /** 261 * @brief ecore_int_sb_release - releases the sb_info structure. 262 * 263 * once the structure is released, it's memory can be freed 264 * 265 * @param p_hwfn 266 * @param sb_info points to an allocated sb_info structure 267 * @param sb_id the sb_id to be used (zero based in driver) 268 * should never be equal to ECORE_SP_SB_ID 269 * (SP Status block) 270 * 271 * @return enum _ecore_status_t 272 */ 273 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn, 274 struct ecore_sb_info *sb_info, 275 u16 sb_id); 276 277 /** 278 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the 279 * default status block. 280 * 281 * @param p_hwfn - pointer to hwfn 282 * 283 */ 284 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie); 285 286 /** 287 * @brief ecore_int_get_num_sbs - get the number of status 288 * blocks configured for this funciton in the igu. 289 * 290 * @param p_hwfn 291 * @param p_sb_cnt_info 292 * 293 * @return 294 */ 295 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn, 296 struct ecore_sb_cnt_info *p_sb_cnt_info); 297 298 /** 299 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR 300 * release. The API need to be called after releasing all slowpath IRQs 301 * of the device. 302 * 303 * @param p_dev 304 * 305 */ 306 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev); 307 308 /** 309 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is 310 * preventing attentions from being reasserted, or following the 311 * attributes of the specific attention. 312 * 313 * @param p_dev 314 * @param clr_enable 315 * 316 */ 317 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable); 318 319 /** 320 * @brief Read debug information regarding a given SB. 321 * 322 * @param p_hwfn 323 * @param p_ptt 324 * @param p_sb - point to Status block for which we want to get info. 325 * @param p_info - pointer to struct to fill with information regarding SB. 326 * 327 * @return ECORE_SUCCESS if pointer is filled; failure otherwise. 328 */ 329 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn, 330 struct ecore_ptt *p_ptt, 331 struct ecore_sb_info *p_sb, 332 struct ecore_sb_info_dbg *p_info); 333 334 /** 335 * @brief - Move a free Status block between PF and child VF 336 * 337 * @param p_hwfn 338 * @param p_ptt 339 * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming 340 * from VF, given-up if moving to VF] 341 * @param b_to_vf - PF->VF == true, VF->PF == false 342 * 343 * @return ECORE_SUCCESS if SB successfully moved. 344 */ 345 enum _ecore_status_t 346 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 347 u16 sb_id, bool b_to_vf); 348 #endif 349