1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2019 NXP 3 */ 4 5 #include "pfe_logs.h" 6 #include "pfe_mod.h" 7 8 #define PFE_MTU_RESET_MASK 0xC000FFFF 9 10 void *cbus_base_addr; 11 void *ddr_base_addr; 12 unsigned long ddr_phys_base_addr; 13 unsigned int ddr_size; 14 static struct pe_info pe[MAX_PE]; 15 16 /* Initializes the PFE library. 17 * Must be called before using any of the library functions. 18 * 19 * @param[in] cbus_base CBUS virtual base address (as mapped in 20 * the host CPU address space) 21 * @param[in] ddr_base PFE DDR range virtual base address (as 22 * mapped in the host CPU address space) 23 * @param[in] ddr_phys_base PFE DDR range physical base address (as 24 * mapped in platform) 25 * @param[in] size PFE DDR range size (as defined by the host 26 * software) 27 */ 28 void 29 pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, 30 unsigned int size) 31 { 32 cbus_base_addr = cbus_base; 33 ddr_base_addr = ddr_base; 34 ddr_phys_base_addr = ddr_phys_base; 35 ddr_size = size; 36 37 pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); 38 pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); 39 pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; 40 pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 41 pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 42 pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 43 44 pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); 45 pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); 46 pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; 47 pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 48 pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 49 pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 50 51 pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); 52 pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); 53 pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; 54 pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 55 pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 56 pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 57 58 pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); 59 pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); 60 pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; 61 pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 62 pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 63 pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 64 65 pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); 66 pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); 67 pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; 68 pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 69 pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 70 pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 71 72 pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); 73 pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); 74 pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; 75 pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; 76 pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; 77 pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; 78 79 pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); 80 pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); 81 pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; 82 pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; 83 pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; 84 pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; 85 86 pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1); 87 pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1); 88 pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE; 89 pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; 90 pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; 91 pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; 92 93 pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3); 94 pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3); 95 pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE; 96 pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; 97 pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; 98 pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; 99 100 #if !defined(CONFIG_FSL_PFE_UTIL_DISABLED) 101 pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR; 102 pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA; 103 pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR; 104 pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA; 105 #endif 106 } 107 108 /**************************** MTIP GEMAC ***************************/ 109 110 /* Enable Rx Checksum Engine. With this enabled, Frame with bad IP, 111 * TCP or UDP checksums are discarded 112 * 113 * @param[in] base GEMAC base address. 114 */ 115 void 116 gemac_enable_rx_checksum_offload(__rte_unused void *base) 117 { 118 /*Do not find configuration to do this */ 119 } 120 121 /* Disable Rx Checksum Engine. 122 * 123 * @param[in] base GEMAC base address. 124 */ 125 void 126 gemac_disable_rx_checksum_offload(__rte_unused void *base) 127 { 128 /*Do not find configuration to do this */ 129 } 130 131 /* GEMAC set speed. 132 * @param[in] base GEMAC base address 133 * @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) 134 */ 135 void 136 gemac_set_speed(void *base, enum mac_speed gem_speed) 137 { 138 u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; 139 u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; 140 141 switch (gem_speed) { 142 case SPEED_10M: 143 rcr |= EMAC_RCNTRL_RMII_10T; 144 break; 145 146 case SPEED_1000M: 147 ecr |= EMAC_ECNTRL_SPEED; 148 break; 149 150 case SPEED_100M: 151 default: 152 /*It is in 100M mode */ 153 break; 154 } 155 writel(ecr, (base + EMAC_ECNTRL_REG)); 156 writel(rcr, (base + EMAC_RCNTRL_REG)); 157 } 158 159 /* GEMAC set duplex. 160 * @param[in] base GEMAC base address 161 * @param[in] duplex GEMAC duplex mode (Full, Half) 162 */ 163 void 164 gemac_set_duplex(void *base, int duplex) 165 { 166 if (duplex == DUPLEX_HALF) { 167 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base 168 + EMAC_TCNTRL_REG); 169 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base 170 + EMAC_RCNTRL_REG)); 171 } else { 172 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base 173 + EMAC_TCNTRL_REG); 174 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base 175 + EMAC_RCNTRL_REG)); 176 } 177 } 178 179 /* GEMAC set mode. 180 * @param[in] base GEMAC base address 181 * @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) 182 */ 183 void 184 gemac_set_mode(void *base, __rte_unused int mode) 185 { 186 u32 val = readl(base + EMAC_RCNTRL_REG); 187 188 /*Remove loopbank*/ 189 val &= ~EMAC_RCNTRL_LOOP; 190 191 /*Enable flow control and MII mode*/ 192 val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE | EMAC_RCNTRL_CRC_FWD); 193 194 writel(val, base + EMAC_RCNTRL_REG); 195 } 196 197 /* GEMAC enable function. 198 * @param[in] base GEMAC base address 199 */ 200 void 201 gemac_enable(void *base) 202 { 203 writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + 204 EMAC_ECNTRL_REG); 205 } 206 207 /* GEMAC disable function. 208 * @param[in] base GEMAC base address 209 */ 210 void 211 gemac_disable(void *base) 212 { 213 writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + 214 EMAC_ECNTRL_REG); 215 } 216 217 /* GEMAC TX disable function. 218 * @param[in] base GEMAC base address 219 */ 220 void 221 gemac_tx_disable(void *base) 222 { 223 writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + 224 EMAC_TCNTRL_REG); 225 } 226 227 void 228 gemac_tx_enable(void *base) 229 { 230 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + 231 EMAC_TCNTRL_REG); 232 } 233 234 /* Sets the hash register of the MAC. 235 * This register is used for matching unicast and multicast frames. 236 * 237 * @param[in] base GEMAC base address. 238 * @param[in] hash 64-bit hash to be configured. 239 */ 240 void 241 gemac_set_hash(void *base, struct pfe_mac_addr *hash) 242 { 243 writel(hash->bottom, base + EMAC_GALR); 244 writel(hash->top, base + EMAC_GAUR); 245 } 246 247 void 248 gemac_set_laddrN(void *base, struct pfe_mac_addr *address, 249 unsigned int entry_index) 250 { 251 if (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX) 252 return; 253 254 entry_index = entry_index - 1; 255 if (entry_index < 1) { 256 writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); 257 writel((htonl(address->top) | 0x8808), base + 258 EMAC_PHY_ADDR_HIGH); 259 } else { 260 writel(htonl(address->bottom), base + ((entry_index - 1) * 8) 261 + EMAC_SMAC_0_0); 262 writel((htonl(address->top) | 0x8808), base + ((entry_index - 263 1) * 8) + EMAC_SMAC_0_1); 264 } 265 } 266 267 void 268 gemac_clear_laddrN(void *base, unsigned int entry_index) 269 { 270 if (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX) 271 return; 272 273 entry_index = entry_index - 1; 274 if (entry_index < 1) { 275 writel(0, base + EMAC_PHY_ADDR_LOW); 276 writel(0, base + EMAC_PHY_ADDR_HIGH); 277 } else { 278 writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); 279 writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); 280 } 281 } 282 283 /* Set the loopback mode of the MAC. This can be either no loopback for 284 * normal operation, local loopback through MAC internal loopback module or PHY 285 * loopback for external loopback through a PHY. This asserts the external 286 * loop pin. 287 * 288 * @param[in] base GEMAC base address. 289 * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC 290 * Loopback, 291 * LB_EXT - PHY Loopback. 292 */ 293 void 294 gemac_set_loop(void *base, __rte_unused enum mac_loop gem_loop) 295 { 296 pr_info("%s()\n", __func__); 297 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + 298 EMAC_RCNTRL_REG)); 299 } 300 301 /* GEMAC allow frames 302 * @param[in] base GEMAC base address 303 */ 304 void 305 gemac_enable_copy_all(void *base) 306 { 307 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + 308 EMAC_RCNTRL_REG)); 309 } 310 311 /* GEMAC do not allow frames 312 * @param[in] base GEMAC base address 313 */ 314 void 315 gemac_disable_copy_all(void *base) 316 { 317 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + 318 EMAC_RCNTRL_REG)); 319 } 320 321 /* GEMAC allow broadcast function. 322 * @param[in] base GEMAC base address 323 */ 324 void 325 gemac_allow_broadcast(void *base) 326 { 327 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + 328 EMAC_RCNTRL_REG); 329 } 330 331 /* GEMAC no broadcast function. 332 * @param[in] base GEMAC base address 333 */ 334 void 335 gemac_no_broadcast(void *base) 336 { 337 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + 338 EMAC_RCNTRL_REG); 339 } 340 341 /* GEMAC enable 1536 rx function. 342 * @param[in] base GEMAC base address 343 */ 344 void 345 gemac_enable_1536_rx(void *base) 346 { 347 /* Set 1536 as Maximum frame length */ 348 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) 349 | (1536 << 16), 350 base + EMAC_RCNTRL_REG); 351 } 352 353 /* GEMAC set Max rx function. 354 * @param[in] base GEMAC base address 355 */ 356 int 357 gemac_set_rx(void *base, int mtu) 358 { 359 if (mtu < HIF_RX_PKT_MIN_SIZE || mtu > JUMBO_FRAME_SIZE) { 360 PFE_PMD_ERR("Invalid or not support MTU size"); 361 return -1; 362 } 363 364 if (pfe_svr == SVR_LS1012A_REV1 && 365 mtu > (MAX_MTU_ON_REV1 + PFE_ETH_OVERHEAD)) { 366 PFE_PMD_ERR("Max supported MTU on Rev1 is %d", MAX_MTU_ON_REV1); 367 return -1; 368 } 369 370 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) 371 | (mtu << 16), 372 base + EMAC_RCNTRL_REG); 373 return 0; 374 } 375 376 /* GEMAC enable jumbo function. 377 * @param[in] base GEMAC base address 378 */ 379 void 380 gemac_enable_rx_jmb(void *base) 381 { 382 if (pfe_svr == SVR_LS1012A_REV1) { 383 PFE_PMD_ERR("Jumbo not supported on Rev1"); 384 return; 385 } 386 387 writel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) | 388 (JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG); 389 } 390 391 /* GEMAC enable stacked vlan function. 392 * @param[in] base GEMAC base address 393 */ 394 void 395 gemac_enable_stacked_vlan(__rte_unused void *base) 396 { 397 /* MTIP doesn't support stacked vlan */ 398 } 399 400 /* GEMAC enable pause rx function. 401 * @param[in] base GEMAC base address 402 */ 403 void 404 gemac_enable_pause_rx(void *base) 405 { 406 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, 407 base + EMAC_RCNTRL_REG); 408 } 409 410 /* GEMAC disable pause rx function. 411 * @param[in] base GEMAC base address 412 */ 413 void 414 gemac_disable_pause_rx(void *base) 415 { 416 writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, 417 base + EMAC_RCNTRL_REG); 418 } 419 420 /* GEMAC enable pause tx function. 421 * @param[in] base GEMAC base address 422 */ 423 void 424 gemac_enable_pause_tx(void *base) 425 { 426 writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY); 427 } 428 429 /* GEMAC disable pause tx function. 430 * @param[in] base GEMAC base address 431 */ 432 void 433 gemac_disable_pause_tx(void *base) 434 { 435 writel(0x0, base + EMAC_RX_SECTION_EMPTY); 436 } 437 438 /* GEMAC wol configuration 439 * @param[in] base GEMAC base address 440 * @param[in] wol_conf WoL register configuration 441 */ 442 void 443 gemac_set_wol(void *base, u32 wol_conf) 444 { 445 u32 val = readl(base + EMAC_ECNTRL_REG); 446 447 if (wol_conf) 448 val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); 449 else 450 val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); 451 writel(val, base + EMAC_ECNTRL_REG); 452 } 453 454 /* Sets Gemac bus width to 64bit 455 * @param[in] base GEMAC base address 456 * @param[in] width gemac bus width to be set possible values are 32/64/128 457 */ 458 void 459 gemac_set_bus_width(__rte_unused void *base, __rte_unused int width) 460 { 461 } 462 463 /* Sets Gemac configuration. 464 * @param[in] base GEMAC base address 465 * @param[in] cfg GEMAC configuration 466 */ 467 void 468 gemac_set_config(void *base, struct gemac_cfg *cfg) 469 { 470 /*GEMAC config taken from VLSI */ 471 writel(0x00000004, base + EMAC_TFWR_STR_FWD); 472 writel(0x00000005, base + EMAC_RX_SECTION_FULL); 473 474 if (pfe_svr == SVR_LS1012A_REV1) 475 writel(0x00000768, base + EMAC_TRUNC_FL); 476 else 477 writel(0x00003fff, base + EMAC_TRUNC_FL); 478 479 writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); 480 writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); 481 482 gemac_set_mode(base, cfg->mode); 483 484 gemac_set_speed(base, cfg->speed); 485 486 gemac_set_duplex(base, cfg->duplex); 487 } 488 489 /**************************** GPI ***************************/ 490 491 /* Initializes a GPI block. 492 * @param[in] base GPI base address 493 * @param[in] cfg GPI configuration 494 */ 495 void 496 gpi_init(void *base, struct gpi_cfg *cfg) 497 { 498 gpi_reset(base); 499 500 gpi_disable(base); 501 502 gpi_set_config(base, cfg); 503 } 504 505 /* Resets a GPI block. 506 * @param[in] base GPI base address 507 */ 508 void 509 gpi_reset(void *base) 510 { 511 writel(CORE_SW_RESET, base + GPI_CTRL); 512 } 513 514 /* Enables a GPI block. 515 * @param[in] base GPI base address 516 */ 517 void 518 gpi_enable(void *base) 519 { 520 writel(CORE_ENABLE, base + GPI_CTRL); 521 } 522 523 /* Disables a GPI block. 524 * @param[in] base GPI base address 525 */ 526 void 527 gpi_disable(void *base) 528 { 529 writel(CORE_DISABLE, base + GPI_CTRL); 530 } 531 532 /* Sets the configuration of a GPI block. 533 * @param[in] base GPI base address 534 * @param[in] cfg GPI configuration 535 */ 536 void 537 gpi_set_config(void *base, struct gpi_cfg *cfg) 538 { 539 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base 540 + GPI_LMEM_ALLOC_ADDR); 541 writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base 542 + GPI_LMEM_FREE_ADDR); 543 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base 544 + GPI_DDR_ALLOC_ADDR); 545 writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base 546 + GPI_DDR_FREE_ADDR); 547 writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); 548 writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); 549 writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); 550 writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); 551 writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); 552 writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); 553 writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); 554 555 writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | 556 GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); 557 writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); 558 writel(cfg->aseq_len, base + GPI_DTX_ASEQ); 559 writel(1, base + GPI_TOE_CHKSUM_EN); 560 561 if (cfg->mtip_pause_reg) { 562 writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); 563 writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); 564 } 565 } 566 567 /**************************** HIF ***************************/ 568 /* Initializes HIF copy block. 569 * 570 */ 571 void 572 hif_init(void) 573 { 574 /*Initialize HIF registers*/ 575 writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, 576 HIF_POLL_CTRL); 577 } 578 579 /* Enable hif tx DMA and interrupt 580 * 581 */ 582 void 583 hif_tx_enable(void) 584 { 585 writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL); 586 writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), 587 HIF_INT_ENABLE); 588 } 589 590 /* Disable hif tx DMA and interrupt 591 * 592 */ 593 void 594 hif_tx_disable(void) 595 { 596 u32 hif_int; 597 598 writel(0, HIF_TX_CTRL); 599 600 hif_int = readl(HIF_INT_ENABLE); 601 hif_int &= HIF_TXPKT_INT_EN; 602 writel(hif_int, HIF_INT_ENABLE); 603 } 604 605 /* Enable hif rx DMA and interrupt 606 * 607 */ 608 void 609 hif_rx_enable(void) 610 { 611 hif_rx_dma_start(); 612 writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), 613 HIF_INT_ENABLE); 614 } 615 616 /* Disable hif rx DMA and interrupt 617 * 618 */ 619 void 620 hif_rx_disable(void) 621 { 622 u32 hif_int; 623 624 writel(0, HIF_RX_CTRL); 625 626 hif_int = readl(HIF_INT_ENABLE); 627 hif_int &= HIF_RXPKT_INT_EN; 628 writel(hif_int, HIF_INT_ENABLE); 629 } 630