1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 NXP 3 */ 4 5 #ifndef _PFE_H_ 6 #define _PFE_H_ 7 8 #include "cbus.h" 9 10 /* 11 * WARNING: non atomic version. 12 */ 13 static inline void 14 set_bit(unsigned long nr, void *addr) 15 { 16 int *m = ((int *)addr) + (nr >> 5); 17 *m |= 1 << (nr & 31); 18 } 19 20 static inline int 21 test_bit(int nr, const void *addr) 22 { 23 return (1UL & (((const int *)addr)[nr >> 5] >> (nr & 31))) != 0UL; 24 } 25 26 /* 27 * WARNING: non atomic version. 28 */ 29 static inline void 30 clear_bit(unsigned long nr, void *addr) 31 { 32 int *m = ((int *)addr) + (nr >> 5); 33 *m &= ~(1 << (nr & 31)); 34 } 35 36 /* 37 * WARNING: non atomic version. 38 */ 39 static inline int 40 test_and_clear_bit(unsigned long nr, void *addr) 41 { 42 unsigned long mask = 1 << (nr & 0x1f); 43 int *m = ((int *)addr) + (nr >> 5); 44 int old = *m; 45 46 *m = old & ~mask; 47 return (old & mask) != 0; 48 } 49 50 /* 51 * WARNING: non atomic version. 52 */ 53 static inline int 54 test_and_set_bit(unsigned long nr, void *addr) 55 { 56 unsigned long mask = 1 << (nr & 0x1f); 57 int *m = ((int *)addr) + (nr >> 5); 58 int old = *m; 59 60 *m = old | mask; 61 return (old & mask) != 0; 62 } 63 64 #ifndef BIT 65 #define BIT(nr) (1UL << (nr)) 66 #endif 67 #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) 68 /* 69 * Only valid for mem access register interface 70 */ 71 #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) 72 #define CLASS_DMEM_SIZE 0x00002000 73 #define CLASS_IMEM_SIZE 0x00008000 74 75 #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) 76 /* 77 * Only valid for mem access register interface 78 */ 79 #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) 80 #define TMU_DMEM_SIZE 0x00000800 81 #define TMU_IMEM_SIZE 0x00002000 82 83 #define UTIL_DMEM_BASE_ADDR 0x00000000 84 #define UTIL_DMEM_SIZE 0x00002000 85 86 #define PE_LMEM_BASE_ADDR 0xc3010000 87 #define PE_LMEM_SIZE 0x8000 88 #define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) 89 90 #define DMEM_BASE_ADDR 0x00000000 91 #define DMEM_SIZE 0x2000 /* TMU has less... */ 92 #define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) 93 94 #define PMEM_BASE_ADDR 0x00010000 95 #define PMEM_SIZE 0x8000 /* TMU has less... */ 96 #define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) 97 98 #define writel(v, p) ({*(volatile unsigned int *)(p) = (v); }) 99 #define readl(p) (*(const volatile unsigned int *)(p)) 100 101 /* These check memory ranges from PE point of view/memory map */ 102 #define IS_DMEM(addr, len) \ 103 ({ typeof(addr) addr_ = (addr); \ 104 ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \ 105 (((unsigned long)(addr_) + (len)) <= DMEM_END); }) 106 107 #define IS_PMEM(addr, len) \ 108 ({ typeof(addr) addr_ = (addr); \ 109 ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \ 110 (((unsigned long)(addr_) + (len)) <= PMEM_END); }) 111 112 #define IS_PE_LMEM(addr, len) \ 113 ({ typeof(addr) addr_ = (addr); \ 114 ((unsigned long)(addr_) >= \ 115 PE_LMEM_BASE_ADDR) && \ 116 (((unsigned long)(addr_) + \ 117 (len)) <= PE_LMEM_END); }) 118 119 #define IS_PFE_LMEM(addr, len) \ 120 ({ typeof(addr) addr_ = (addr); \ 121 ((unsigned long)(addr_) >= \ 122 CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \ 123 (((unsigned long)(addr_) + (len)) <= \ 124 CBUS_VIRT_TO_PFE(LMEM_END)); }) 125 126 #define __IS_PHYS_DDR(addr, len) \ 127 ({ typeof(addr) addr_ = (addr); \ 128 ((unsigned long)(addr_) >= \ 129 DDR_PHYS_BASE_ADDR) && \ 130 (((unsigned long)(addr_) + (len)) <= \ 131 DDR_PHYS_END); }) 132 133 #define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len) 134 135 /* 136 * If using a run-time virtual address for the cbus base address use this code 137 */ 138 extern void *cbus_base_addr; 139 extern void *ddr_base_addr; 140 extern unsigned long ddr_phys_base_addr; 141 extern unsigned int ddr_size; 142 143 #define CBUS_BASE_ADDR cbus_base_addr 144 #define DDR_PHYS_BASE_ADDR ddr_phys_base_addr 145 #define DDR_BASE_ADDR ddr_base_addr 146 #define DDR_SIZE ddr_size 147 148 #define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE) 149 150 #define LS1012A_PFE_RESET_WA /* 151 * PFE doesn't have global reset and re-init 152 * should takecare few things to make PFE 153 * functional after reset 154 */ 155 #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address 156 * as seen by PE's. 157 */ 158 /* CBUS physical base address as seen by PE's. */ 159 #define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 160 161 #define DDR_PHYS_TO_PFE(p) (((unsigned long)(p)) & 0x7FFFFFFF) 162 #define DDR_PFE_TO_PHYS(p) (((unsigned long)(p)) | 0x80000000) 163 #define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \ 164 PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) 165 /* Translates to PFE address map */ 166 167 #define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR) 168 #define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR) 169 #define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p))) 170 171 #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \ 172 PFE_CBUS_PHYS_BASE_ADDR) 173 #define CBUS_PFE_TO_VIRT(p) (((unsigned long)(p) - \ 174 PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR) 175 176 /* The below part of the code is used in QOS control driver from host */ 177 #define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by 178 * pe's 179 */ 180 181 enum { 182 CLASS0_ID = 0, 183 CLASS1_ID, 184 CLASS2_ID, 185 CLASS3_ID, 186 CLASS4_ID, 187 CLASS5_ID, 188 TMU0_ID, 189 TMU1_ID, 190 TMU2_ID, 191 TMU3_ID, 192 #if !defined(CONFIG_FSL_PFE_UTIL_DISABLED) 193 UTIL_ID, 194 #endif 195 MAX_PE 196 }; 197 198 #define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\ 199 BIT(CLASS2_ID) | BIT(CLASS3_ID) |\ 200 BIT(CLASS4_ID) | BIT(CLASS5_ID)) 201 #define CLASS_MAX_ID CLASS5_ID 202 203 #define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\ 204 BIT(TMU3_ID)) 205 206 #define TMU_MAX_ID TMU3_ID 207 208 #if !defined(CONFIG_FSL_PFE_UTIL_DISABLED) 209 #define UTIL_MASK BIT(UTIL_ID) 210 #endif 211 212 struct pe_status { 213 u32 cpu_state; 214 u32 activity_counter; 215 u32 rx; 216 union { 217 u32 tx; 218 u32 tmu_qstatus; 219 }; 220 u32 drop; 221 #if defined(CFG_PE_DEBUG) 222 u32 debug_indicator; 223 u32 debug[16]; 224 #endif 225 } __rte_aligned(16); 226 227 struct pe_sync_mailbox { 228 u32 stop; 229 u32 stopped; 230 }; 231 232 /* Drop counter definitions */ 233 234 #define CLASS_NUM_DROP_COUNTERS 13 235 #define UTIL_NUM_DROP_COUNTERS 8 236 237 /* PE information. 238 * Structure containing PE's specific information. It is used to create 239 * generic C functions common to all PE's. 240 * Before using the library functions this structure needs to be initialized 241 * with the different registers virtual addresses 242 * (according to the ARM MMU mmaping). The default initialization supports a 243 * virtual == physical mapping. 244 */ 245 struct pe_info { 246 u32 dmem_base_addr; /* PE's dmem base address */ 247 u32 pmem_base_addr; /* PE's pmem base address */ 248 u32 pmem_size; /* PE's pmem size */ 249 250 void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register 251 * address 252 */ 253 void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register 254 * address 255 */ 256 void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register 257 * address 258 */ 259 }; 260 261 void pe_lmem_read(u32 *dst, u32 len, u32 offset); 262 void pe_lmem_write(u32 *src, u32 len, u32 offset); 263 264 void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); 265 void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); 266 267 u32 pe_pmem_read(int id, u32 addr, u8 size); 268 269 void pe_dmem_write(int id, u32 val, u32 addr, u8 size); 270 u32 pe_dmem_read(int id, u32 addr, u8 size); 271 void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len); 272 void class_pe_lmem_memset(u32 dst, int val, unsigned int len); 273 void class_bus_write(u32 val, u32 addr, u8 size); 274 u32 class_bus_read(u32 addr, u8 size); 275 276 #define class_bus_readl(addr) class_bus_read(addr, 4) 277 #define class_bus_readw(addr) class_bus_read(addr, 2) 278 #define class_bus_readb(addr) class_bus_read(addr, 1) 279 280 #define class_bus_writel(val, addr) class_bus_write(val, addr, 4) 281 #define class_bus_writew(val, addr) class_bus_write(val, addr, 2) 282 #define class_bus_writeb(val, addr) class_bus_write(val, addr, 1) 283 284 #define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4) 285 #define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2) 286 #define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1) 287 288 #define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4) 289 #define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2) 290 #define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1) 291 292 /*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */ 293 //int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, 294 // struct device *dev); 295 296 void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, 297 unsigned int ddr_size); 298 void bmu_init(void *base, struct BMU_CFG *cfg); 299 void bmu_reset(void *base); 300 void bmu_enable(void *base); 301 void bmu_disable(void *base); 302 void bmu_set_config(void *base, struct BMU_CFG *cfg); 303 304 /* 305 * An enumerated type for loopback values. This can be one of three values, no 306 * loopback -normal operation, local loopback with internal loopback module of 307 * MAC or PHY loopback which is through the external PHY. 308 */ 309 #ifndef __MAC_LOOP_ENUM__ 310 #define __MAC_LOOP_ENUM__ 311 enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL}; 312 #endif 313 314 /* Get Chip Revision level 315 * 316 */ 317 static inline unsigned int CHIP_REVISION(void) 318 { 319 /*For LS1012A return always 1 */ 320 return 1; 321 } 322 323 /* Start HIF rx DMA 324 * 325 */ 326 static inline void hif_rx_dma_start(void) 327 { 328 writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL); 329 } 330 331 /* Start HIF tx DMA 332 * 333 */ 334 static inline void hif_tx_dma_start(void) 335 { 336 writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL); 337 } 338 339 #endif /* _PFE_H_ */ 340