1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <stdio.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdint.h> 9 #include <stdlib.h> 10 #include <string.h> 11 #include <unistd.h> 12 13 #include <eventdev_pmd.h> 14 #include <rte_alarm.h> 15 #include <rte_branch_prediction.h> 16 #include <bus_vdev_driver.h> 17 #include <rte_cycles.h> 18 #include <rte_debug.h> 19 #include <dev_driver.h> 20 #include <rte_devargs.h> 21 #include <rte_kvargs.h> 22 #include <rte_malloc.h> 23 #include <rte_mbuf_pool_ops.h> 24 #include <rte_prefetch.h> 25 26 #include "octeontx_ethdev.h" 27 #include "octeontx_rxtx.h" 28 #include "octeontx_logs.h" 29 #include "octeontx_stats.h" 30 31 /* Useful in stopping/closing event device if no of 32 * eth ports are using it. 33 */ 34 uint16_t evdev_refcnt; 35 36 #define OCTEONTX_QLM_MODE_SGMII 7 37 #define OCTEONTX_QLM_MODE_XFI 12 38 39 struct evdev_priv_data { 40 OFFLOAD_FLAGS; /*Sequence should not be changed */ 41 } __rte_cache_aligned; 42 43 struct octeontx_vdev_init_params { 44 uint8_t nr_port; 45 }; 46 47 uint16_t 48 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX]; 49 50 enum octeontx_link_speed { 51 OCTEONTX_LINK_SPEED_SGMII, 52 OCTEONTX_LINK_SPEED_XAUI, 53 OCTEONTX_LINK_SPEED_RXAUI, 54 OCTEONTX_LINK_SPEED_10G_R, 55 OCTEONTX_LINK_SPEED_40G_R, 56 OCTEONTX_LINK_SPEED_RESERVE1, 57 OCTEONTX_LINK_SPEED_QSGMII, 58 OCTEONTX_LINK_SPEED_RESERVE2, 59 OCTEONTX_LINK_SPEED_UNKNOWN = 255 60 }; 61 62 RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_mbox, mbox, NOTICE); 63 RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_init, init, NOTICE); 64 RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_driver, driver, NOTICE); 65 66 /* Parse integer from integer argument */ 67 static int 68 parse_integer_arg(const char *key __rte_unused, 69 const char *value, void *extra_args) 70 { 71 int *i = (int *)extra_args; 72 73 *i = atoi(value); 74 if (*i < 0) { 75 octeontx_log_err("argument has to be positive."); 76 return -1; 77 } 78 79 return 0; 80 } 81 82 static int 83 octeontx_parse_vdev_init_params(struct octeontx_vdev_init_params *params, 84 struct rte_vdev_device *dev) 85 { 86 struct rte_kvargs *kvlist = NULL; 87 int ret = 0; 88 89 static const char * const octeontx_vdev_valid_params[] = { 90 OCTEONTX_VDEV_NR_PORT_ARG, 91 NULL 92 }; 93 94 const char *input_args = rte_vdev_device_args(dev); 95 if (params == NULL) 96 return -EINVAL; 97 98 99 if (input_args) { 100 kvlist = rte_kvargs_parse(input_args, 101 octeontx_vdev_valid_params); 102 if (kvlist == NULL) 103 return -1; 104 105 ret = rte_kvargs_process(kvlist, 106 OCTEONTX_VDEV_NR_PORT_ARG, 107 &parse_integer_arg, 108 ¶ms->nr_port); 109 if (ret < 0) 110 goto free_kvlist; 111 } 112 113 free_kvlist: 114 rte_kvargs_free(kvlist); 115 return ret; 116 } 117 118 static int 119 octeontx_port_open(struct octeontx_nic *nic) 120 { 121 octeontx_mbox_bgx_port_conf_t bgx_port_conf; 122 octeontx_mbox_bgx_port_fifo_cfg_t fifo_cfg; 123 int res; 124 125 res = 0; 126 memset(&bgx_port_conf, 0x0, sizeof(bgx_port_conf)); 127 PMD_INIT_FUNC_TRACE(); 128 129 res = octeontx_bgx_port_open(nic->port_id, &bgx_port_conf); 130 if (res < 0) { 131 octeontx_log_err("failed to open port %d", res); 132 return res; 133 } 134 135 nic->node = bgx_port_conf.node; 136 nic->port_ena = bgx_port_conf.enable; 137 nic->base_ichan = bgx_port_conf.base_chan; 138 nic->base_ochan = bgx_port_conf.base_chan; 139 nic->num_ichans = bgx_port_conf.num_chans; 140 nic->num_ochans = bgx_port_conf.num_chans; 141 nic->bgx_mtu = bgx_port_conf.mtu; 142 nic->bpen = bgx_port_conf.bpen; 143 nic->fcs_strip = bgx_port_conf.fcs_strip; 144 nic->bcast_mode = bgx_port_conf.bcast_mode; 145 nic->mcast_mode = bgx_port_conf.mcast_mode; 146 nic->speed = bgx_port_conf.mode; 147 148 nic->duplex = RTE_ETH_LINK_FULL_DUPLEX; 149 memset(&fifo_cfg, 0x0, sizeof(fifo_cfg)); 150 151 res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg); 152 if (res < 0) { 153 octeontx_log_err("failed to get port %d fifo cfg", res); 154 return res; 155 } 156 157 nic->fc.rx_fifosz = fifo_cfg.rx_fifosz; 158 159 memcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0], 160 RTE_ETHER_ADDR_LEN); 161 162 octeontx_log_dbg("port opened %d", nic->port_id); 163 return res; 164 } 165 166 static void 167 octeontx_link_status_print(struct rte_eth_dev *eth_dev, 168 struct rte_eth_link *link) 169 { 170 if (link && link->link_status) 171 octeontx_log_info("Port %u: Link Up - speed %u Mbps - %s", 172 (eth_dev->data->port_id), 173 link->link_speed, 174 link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? 175 "full-duplex" : "half-duplex"); 176 else 177 octeontx_log_info("Port %d: Link Down", 178 (int)(eth_dev->data->port_id)); 179 } 180 181 static inline uint32_t 182 octeontx_parse_link_speeds(uint32_t link_speeds) 183 { 184 uint32_t link_speed = OCTEONTX_LINK_SPEED_UNKNOWN; 185 186 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 187 link_speed = OCTEONTX_LINK_SPEED_40G_R; 188 189 if (link_speeds & RTE_ETH_LINK_SPEED_10G) { 190 link_speed = OCTEONTX_LINK_SPEED_XAUI; 191 link_speed |= OCTEONTX_LINK_SPEED_RXAUI; 192 link_speed |= OCTEONTX_LINK_SPEED_10G_R; 193 } 194 195 if (link_speeds & RTE_ETH_LINK_SPEED_5G) 196 link_speed = OCTEONTX_LINK_SPEED_QSGMII; 197 198 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 199 link_speed = OCTEONTX_LINK_SPEED_SGMII; 200 201 return link_speed; 202 } 203 204 static inline uint8_t 205 octeontx_parse_eth_link_duplex(uint32_t link_speeds) 206 { 207 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || 208 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) 209 return RTE_ETH_LINK_HALF_DUPLEX; 210 else 211 return RTE_ETH_LINK_FULL_DUPLEX; 212 } 213 214 static int 215 octeontx_apply_link_speed(struct rte_eth_dev *dev) 216 { 217 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 218 struct rte_eth_conf *conf = &dev->data->dev_conf; 219 octeontx_mbox_bgx_port_change_mode_t cfg; 220 221 if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) 222 return 0; 223 224 cfg.speed = octeontx_parse_link_speeds(conf->link_speeds); 225 cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; 226 cfg.duplex = octeontx_parse_eth_link_duplex(conf->link_speeds); 227 cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? 228 OCTEONTX_QLM_MODE_SGMII : 229 (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? 230 OCTEONTX_QLM_MODE_XFI : 0); 231 232 if (cfg.speed != OCTEONTX_LINK_SPEED_UNKNOWN && 233 (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { 234 nic->speed = cfg.speed; 235 nic->duplex = cfg.duplex; 236 return octeontx_bgx_port_change_mode(nic->port_id, &cfg); 237 } else { 238 return 0; 239 } 240 } 241 242 static void 243 octeontx_link_status_update(struct octeontx_nic *nic, 244 struct rte_eth_link *link) 245 { 246 memset(link, 0, sizeof(*link)); 247 248 link->link_status = nic->link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 249 250 switch (nic->speed) { 251 case OCTEONTX_LINK_SPEED_SGMII: 252 link->link_speed = RTE_ETH_SPEED_NUM_1G; 253 break; 254 255 case OCTEONTX_LINK_SPEED_XAUI: 256 link->link_speed = RTE_ETH_SPEED_NUM_10G; 257 break; 258 259 case OCTEONTX_LINK_SPEED_RXAUI: 260 case OCTEONTX_LINK_SPEED_10G_R: 261 link->link_speed = RTE_ETH_SPEED_NUM_10G; 262 break; 263 case OCTEONTX_LINK_SPEED_QSGMII: 264 link->link_speed = RTE_ETH_SPEED_NUM_5G; 265 break; 266 case OCTEONTX_LINK_SPEED_40G_R: 267 link->link_speed = RTE_ETH_SPEED_NUM_40G; 268 break; 269 270 case OCTEONTX_LINK_SPEED_RESERVE1: 271 case OCTEONTX_LINK_SPEED_RESERVE2: 272 default: 273 link->link_speed = RTE_ETH_SPEED_NUM_NONE; 274 octeontx_log_err("incorrect link speed %d", nic->speed); 275 break; 276 } 277 278 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 279 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 280 } 281 282 static void 283 octeontx_link_status_poll(void *arg) 284 { 285 struct octeontx_nic *nic = arg; 286 struct rte_eth_link link; 287 struct rte_eth_dev *dev; 288 int res; 289 290 PMD_INIT_FUNC_TRACE(); 291 292 dev = nic->dev; 293 294 res = octeontx_bgx_port_link_status(nic->port_id); 295 if (res < 0) { 296 octeontx_log_err("Failed to get port %d link status", 297 nic->port_id); 298 } else { 299 if (nic->link_up != (uint8_t)res) { 300 nic->link_up = (uint8_t)res; 301 octeontx_link_status_update(nic, &link); 302 octeontx_link_status_print(dev, &link); 303 rte_eth_linkstatus_set(dev, &link); 304 rte_eth_dev_callback_process(dev, 305 RTE_ETH_EVENT_INTR_LSC, 306 NULL); 307 } 308 } 309 310 res = rte_eal_alarm_set(OCCTX_INTR_POLL_INTERVAL_MS * 1000, 311 octeontx_link_status_poll, nic); 312 if (res < 0) 313 octeontx_log_err("Failed to restart alarm for port %d, err: %d", 314 nic->port_id, res); 315 } 316 317 static void 318 octeontx_port_close(struct octeontx_nic *nic) 319 { 320 PMD_INIT_FUNC_TRACE(); 321 322 rte_eal_alarm_cancel(octeontx_link_status_poll, nic); 323 octeontx_bgx_port_close(nic->port_id); 324 octeontx_log_dbg("port closed %d", nic->port_id); 325 } 326 327 static int 328 octeontx_port_start(struct octeontx_nic *nic) 329 { 330 PMD_INIT_FUNC_TRACE(); 331 332 return octeontx_bgx_port_start(nic->port_id); 333 } 334 335 static int 336 octeontx_port_stop(struct octeontx_nic *nic) 337 { 338 PMD_INIT_FUNC_TRACE(); 339 340 return octeontx_bgx_port_stop(nic->port_id); 341 } 342 343 static int 344 octeontx_port_promisc_set(struct octeontx_nic *nic, int en) 345 { 346 struct rte_eth_dev *dev; 347 int res; 348 349 res = 0; 350 PMD_INIT_FUNC_TRACE(); 351 dev = nic->dev; 352 353 res = octeontx_bgx_port_promisc_set(nic->port_id, en); 354 if (res < 0) { 355 octeontx_log_err("failed to set promiscuous mode %d", 356 nic->port_id); 357 return res; 358 } 359 360 /* Set proper flag for the mode */ 361 dev->data->promiscuous = (en != 0) ? 1 : 0; 362 363 octeontx_log_dbg("port %d : promiscuous mode %s", 364 nic->port_id, en ? "set" : "unset"); 365 366 return 0; 367 } 368 369 static int 370 octeontx_port_stats(struct octeontx_nic *nic, struct rte_eth_stats *stats) 371 { 372 octeontx_mbox_bgx_port_stats_t bgx_stats; 373 int res; 374 375 PMD_INIT_FUNC_TRACE(); 376 377 res = octeontx_bgx_port_stats(nic->port_id, &bgx_stats); 378 if (res < 0) { 379 octeontx_log_err("failed to get port stats %d", nic->port_id); 380 return res; 381 } 382 383 stats->ipackets = bgx_stats.rx_packets; 384 stats->ibytes = bgx_stats.rx_bytes; 385 stats->imissed = bgx_stats.rx_dropped; 386 stats->ierrors = bgx_stats.rx_errors; 387 stats->opackets = bgx_stats.tx_packets; 388 stats->obytes = bgx_stats.tx_bytes; 389 stats->oerrors = bgx_stats.tx_errors; 390 391 octeontx_log_dbg("port%d stats inpkts=%" PRIx64 " outpkts=%" PRIx64 "", 392 nic->port_id, stats->ipackets, stats->opackets); 393 394 return 0; 395 } 396 397 static int 398 octeontx_port_stats_clr(struct octeontx_nic *nic) 399 { 400 PMD_INIT_FUNC_TRACE(); 401 402 return octeontx_bgx_port_stats_clr(nic->port_id); 403 } 404 405 static inline void 406 devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf, 407 struct rte_event_dev_info *info) 408 { 409 memset(dev_conf, 0, sizeof(struct rte_event_dev_config)); 410 dev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns; 411 412 dev_conf->nb_event_ports = info->max_event_ports; 413 dev_conf->nb_event_queues = info->max_event_queues; 414 415 dev_conf->nb_event_queue_flows = info->max_event_queue_flows; 416 dev_conf->nb_event_port_dequeue_depth = 417 info->max_event_port_dequeue_depth; 418 dev_conf->nb_event_port_enqueue_depth = 419 info->max_event_port_enqueue_depth; 420 dev_conf->nb_event_port_enqueue_depth = 421 info->max_event_port_enqueue_depth; 422 dev_conf->nb_events_limit = 423 info->max_num_events; 424 } 425 426 static uint16_t 427 octeontx_tx_offload_flags(struct rte_eth_dev *eth_dev) 428 { 429 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 430 uint16_t flags = 0; 431 432 if (nic->tx_offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM || 433 nic->tx_offloads & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM) 434 flags |= OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F; 435 436 if (nic->tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM || 437 nic->tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM || 438 nic->tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM || 439 nic->tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) 440 flags |= OCCTX_TX_OFFLOAD_L3_L4_CSUM_F; 441 442 if (!(nic->tx_offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)) 443 flags |= OCCTX_TX_OFFLOAD_MBUF_NOFF_F; 444 445 if (nic->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) 446 flags |= OCCTX_TX_MULTI_SEG_F; 447 448 return flags; 449 } 450 451 static uint16_t 452 octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev) 453 { 454 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 455 uint16_t flags = 0; 456 457 if (nic->rx_offloads & (RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 458 RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) 459 flags |= OCCTX_RX_OFFLOAD_CSUM_F; 460 461 if (nic->rx_offloads & (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 462 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM)) 463 flags |= OCCTX_RX_OFFLOAD_CSUM_F; 464 465 if (nic->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 466 flags |= OCCTX_RX_MULTI_SEG_F; 467 eth_dev->data->scattered_rx = 1; 468 /* If scatter mode is enabled, TX should also be in multi 469 * seg mode, else memory leak will occur 470 */ 471 nic->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 472 } 473 474 return flags; 475 } 476 477 static int 478 octeontx_dev_configure(struct rte_eth_dev *dev) 479 { 480 struct rte_eth_dev_data *data = dev->data; 481 struct rte_eth_conf *conf = &data->dev_conf; 482 struct rte_eth_rxmode *rxmode = &conf->rxmode; 483 struct rte_eth_txmode *txmode = &conf->txmode; 484 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 485 int ret; 486 487 PMD_INIT_FUNC_TRACE(); 488 RTE_SET_USED(conf); 489 490 if (!rte_eal_has_hugepages()) { 491 octeontx_log_err("huge page is not configured"); 492 return -EINVAL; 493 } 494 495 if (txmode->mq_mode) { 496 octeontx_log_err("tx mq_mode DCB or VMDq not supported"); 497 return -EINVAL; 498 } 499 500 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE && 501 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) { 502 octeontx_log_err("unsupported rx qmode %d", rxmode->mq_mode); 503 return -EINVAL; 504 } 505 506 if (!(txmode->offloads & RTE_ETH_TX_OFFLOAD_MT_LOCKFREE)) { 507 PMD_INIT_LOG(NOTICE, "cant disable lockfree tx"); 508 txmode->offloads |= RTE_ETH_TX_OFFLOAD_MT_LOCKFREE; 509 } 510 511 if (conf->dcb_capability_en) { 512 octeontx_log_err("DCB enable not supported"); 513 return -EINVAL; 514 } 515 516 nic->num_tx_queues = dev->data->nb_tx_queues; 517 518 if (!nic->reconfigure) { 519 ret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ, 520 nic->num_tx_queues, 521 nic->base_ochan); 522 if (ret) { 523 octeontx_log_err("failed to open channel %d no-of-txq %d", 524 nic->base_ochan, nic->num_tx_queues); 525 return -EFAULT; 526 } 527 528 ret = octeontx_dev_vlan_offload_init(dev); 529 if (ret) { 530 octeontx_log_err("failed to initialize vlan offload"); 531 return -EFAULT; 532 } 533 534 nic->pki.classifier_enable = false; 535 nic->pki.hash_enable = true; 536 nic->pki.initialized = false; 537 } 538 539 nic->rx_offloads |= rxmode->offloads; 540 nic->tx_offloads |= txmode->offloads; 541 nic->rx_offload_flags |= octeontx_rx_offload_flags(dev); 542 nic->tx_offload_flags |= octeontx_tx_offload_flags(dev); 543 544 nic->reconfigure = true; 545 546 return 0; 547 } 548 549 static int 550 octeontx_dev_close(struct rte_eth_dev *dev) 551 { 552 struct octeontx_txq *txq = NULL; 553 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 554 unsigned int i; 555 int ret; 556 557 PMD_INIT_FUNC_TRACE(); 558 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 559 return 0; 560 561 /* Stopping/closing event device once all eth ports are closed. */ 562 if (__atomic_fetch_sub(&evdev_refcnt, 1, __ATOMIC_ACQUIRE) - 1 == 0) { 563 rte_event_dev_stop(nic->evdev); 564 rte_event_dev_close(nic->evdev); 565 } 566 567 octeontx_dev_flow_ctrl_fini(dev); 568 569 octeontx_dev_vlan_offload_fini(dev); 570 571 ret = octeontx_pko_channel_close(nic->base_ochan); 572 if (ret < 0) { 573 octeontx_log_err("failed to close channel %d VF%d %d %d", 574 nic->base_ochan, nic->port_id, nic->num_tx_queues, 575 ret); 576 } 577 /* Free txq resources for this port */ 578 for (i = 0; i < nic->num_tx_queues; i++) { 579 txq = dev->data->tx_queues[i]; 580 if (!txq) 581 continue; 582 583 rte_free(txq); 584 } 585 586 octeontx_port_close(nic); 587 nic->reconfigure = false; 588 589 return 0; 590 } 591 592 static int 593 octeontx_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 594 { 595 uint32_t buffsz, frame_size = mtu + OCCTX_L2_OVERHEAD; 596 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 597 struct rte_eth_dev_data *data = eth_dev->data; 598 int rc = 0; 599 600 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 601 602 /* Refuse MTU that requires the support of scattered packets 603 * when this feature has not been enabled before. 604 */ 605 if (data->dev_started && frame_size > buffsz && 606 !(nic->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) { 607 octeontx_log_err("Scatter mode is disabled"); 608 return -EINVAL; 609 } 610 611 /* Check <seg size> * <max_seg> >= max_frame */ 612 if ((nic->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) && 613 (frame_size > buffsz * OCCTX_RX_NB_SEG_MAX)) 614 return -EINVAL; 615 616 rc = octeontx_pko_send_mtu(nic->port_id, frame_size); 617 if (rc) 618 return rc; 619 620 rc = octeontx_bgx_port_mtu_set(nic->port_id, frame_size); 621 if (rc) 622 return rc; 623 624 octeontx_log_info("Received pkt beyond maxlen %d will be dropped", 625 frame_size); 626 627 return rc; 628 } 629 630 static int 631 octeontx_recheck_rx_offloads(struct octeontx_rxq *rxq) 632 { 633 struct rte_eth_dev *eth_dev = rxq->eth_dev; 634 struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev); 635 struct rte_eth_dev_data *data = eth_dev->data; 636 struct rte_pktmbuf_pool_private *mbp_priv; 637 struct evdev_priv_data *evdev_priv; 638 struct rte_eventdev *dev; 639 uint32_t buffsz; 640 641 /* Get rx buffer size */ 642 mbp_priv = rte_mempool_get_priv(rxq->pool); 643 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 644 645 /* Setup scatter mode if needed by jumbo */ 646 if (data->mtu > buffsz) { 647 nic->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; 648 nic->rx_offload_flags |= octeontx_rx_offload_flags(eth_dev); 649 nic->tx_offload_flags |= octeontx_tx_offload_flags(eth_dev); 650 } 651 652 /* Sharing offload flags via eventdev priv region */ 653 dev = &rte_eventdevs[rxq->evdev]; 654 evdev_priv = dev->data->dev_private; 655 evdev_priv->rx_offload_flags = nic->rx_offload_flags; 656 evdev_priv->tx_offload_flags = nic->tx_offload_flags; 657 658 /* Setup MTU */ 659 nic->mtu = data->mtu; 660 661 return 0; 662 } 663 664 static int 665 octeontx_dev_start(struct rte_eth_dev *dev) 666 { 667 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 668 struct octeontx_rxq *rxq; 669 int ret, i; 670 671 PMD_INIT_FUNC_TRACE(); 672 /* Rechecking if any new offload set to update 673 * rx/tx burst function pointer accordingly. 674 */ 675 for (i = 0; i < dev->data->nb_rx_queues; i++) { 676 rxq = dev->data->rx_queues[i]; 677 octeontx_recheck_rx_offloads(rxq); 678 } 679 680 /* Setting up the mtu */ 681 ret = octeontx_dev_mtu_set(dev, nic->mtu); 682 if (ret) { 683 octeontx_log_err("Failed to set default MTU size %d", ret); 684 goto error; 685 } 686 687 /* Apply new link configurations if changed */ 688 ret = octeontx_apply_link_speed(dev); 689 if (ret) { 690 octeontx_log_err("Failed to set link configuration: %d", ret); 691 goto error; 692 } 693 694 /* 695 * Tx start 696 */ 697 octeontx_set_tx_function(dev); 698 ret = octeontx_pko_channel_start(nic->base_ochan); 699 if (ret < 0) { 700 octeontx_log_err("fail to conf VF%d no. txq %d chan %d ret %d", 701 nic->port_id, nic->num_tx_queues, nic->base_ochan, 702 ret); 703 goto error; 704 } 705 706 /* 707 * Rx start 708 */ 709 dev->rx_pkt_burst = octeontx_recv_pkts; 710 ret = octeontx_pki_port_start(nic->port_id); 711 if (ret < 0) { 712 octeontx_log_err("fail to start Rx on port %d", nic->port_id); 713 goto channel_stop_error; 714 } 715 716 /* 717 * Start port 718 */ 719 ret = octeontx_port_start(nic); 720 if (ret < 0) { 721 octeontx_log_err("failed start port %d", ret); 722 goto pki_port_stop_error; 723 } 724 725 PMD_TX_LOG(DEBUG, "pko: start channel %d no.of txq %d port %d", 726 nic->base_ochan, nic->num_tx_queues, nic->port_id); 727 728 ret = rte_event_dev_start(nic->evdev); 729 if (ret < 0) { 730 octeontx_log_err("failed to start evdev: ret (%d)", ret); 731 goto pki_port_stop_error; 732 } 733 734 /* Success */ 735 return ret; 736 737 pki_port_stop_error: 738 octeontx_pki_port_stop(nic->port_id); 739 channel_stop_error: 740 octeontx_pko_channel_stop(nic->base_ochan); 741 error: 742 return ret; 743 } 744 745 static int 746 octeontx_dev_stop(struct rte_eth_dev *dev) 747 { 748 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 749 int ret; 750 751 PMD_INIT_FUNC_TRACE(); 752 753 ret = octeontx_port_stop(nic); 754 if (ret < 0) { 755 octeontx_log_err("failed to req stop port %d res=%d", 756 nic->port_id, ret); 757 return ret; 758 } 759 760 ret = octeontx_pki_port_stop(nic->port_id); 761 if (ret < 0) { 762 octeontx_log_err("failed to stop pki port %d res=%d", 763 nic->port_id, ret); 764 return ret; 765 } 766 767 ret = octeontx_pko_channel_stop(nic->base_ochan); 768 if (ret < 0) { 769 octeontx_log_err("failed to stop channel %d VF%d %d %d", 770 nic->base_ochan, nic->port_id, nic->num_tx_queues, 771 ret); 772 return ret; 773 } 774 775 return 0; 776 } 777 778 static int 779 octeontx_dev_promisc_enable(struct rte_eth_dev *dev) 780 { 781 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 782 783 PMD_INIT_FUNC_TRACE(); 784 return octeontx_port_promisc_set(nic, 1); 785 } 786 787 static int 788 octeontx_dev_promisc_disable(struct rte_eth_dev *dev) 789 { 790 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 791 792 PMD_INIT_FUNC_TRACE(); 793 return octeontx_port_promisc_set(nic, 0); 794 } 795 796 static int 797 octeontx_port_link_status(struct octeontx_nic *nic) 798 { 799 int res; 800 801 PMD_INIT_FUNC_TRACE(); 802 res = octeontx_bgx_port_link_status(nic->port_id); 803 if (res < 0) { 804 octeontx_log_err("failed to get port %d link status", 805 nic->port_id); 806 return res; 807 } 808 809 if (nic->link_up != (uint8_t)res || nic->print_flag == -1) { 810 nic->link_up = (uint8_t)res; 811 nic->print_flag = 1; 812 } 813 octeontx_log_dbg("port %d link status %d", nic->port_id, nic->link_up); 814 815 return res; 816 } 817 818 /* 819 * Return 0 means link status changed, -1 means not changed 820 */ 821 static int 822 octeontx_dev_link_update(struct rte_eth_dev *dev, 823 int wait_to_complete __rte_unused) 824 { 825 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 826 struct rte_eth_link link; 827 int res; 828 829 PMD_INIT_FUNC_TRACE(); 830 831 res = octeontx_port_link_status(nic); 832 if (res < 0) { 833 octeontx_log_err("failed to request link status %d", res); 834 return res; 835 } 836 837 octeontx_link_status_update(nic, &link); 838 if (nic->print_flag) { 839 octeontx_link_status_print(nic->dev, &link); 840 nic->print_flag = 0; 841 } 842 843 return rte_eth_linkstatus_set(dev, &link); 844 } 845 846 static int 847 octeontx_port_mcast_set(struct octeontx_nic *nic, int en) 848 { 849 struct rte_eth_dev *dev; 850 int res; 851 852 res = 0; 853 PMD_INIT_FUNC_TRACE(); 854 dev = nic->dev; 855 856 res = octeontx_bgx_port_multicast_set(nic->port_id, en); 857 if (res < 0) { 858 octeontx_log_err("failed to set multicast mode %d", 859 nic->port_id); 860 return res; 861 } 862 863 /* Set proper flag for the mode */ 864 dev->data->all_multicast = (en != 0) ? 1 : 0; 865 866 octeontx_log_dbg("port %d : multicast mode %s", 867 nic->port_id, en ? "set" : "unset"); 868 869 return 0; 870 } 871 872 static int 873 octeontx_allmulticast_enable(struct rte_eth_dev *dev) 874 { 875 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 876 877 PMD_INIT_FUNC_TRACE(); 878 return octeontx_port_mcast_set(nic, 1); 879 } 880 881 static int 882 octeontx_allmulticast_disable(struct rte_eth_dev *dev) 883 { 884 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 885 886 PMD_INIT_FUNC_TRACE(); 887 return octeontx_port_mcast_set(nic, 0); 888 } 889 890 static inline int octeontx_dev_total_xstat(void) 891 { 892 return NUM_BGX_XSTAT; 893 } 894 895 static int 896 octeontx_port_xstats(struct octeontx_nic *nic, struct rte_eth_xstat *xstats, 897 unsigned int n) 898 { 899 octeontx_mbox_bgx_port_stats_t bgx_stats; 900 int stat_cnt, res, si, i; 901 902 res = octeontx_bgx_port_xstats(nic->port_id, &bgx_stats); 903 if (res < 0) { 904 octeontx_log_err("failed to get port stats %d", nic->port_id); 905 return res; 906 } 907 908 si = 0; 909 /* Fill BGX stats */ 910 stat_cnt = (n > NUM_BGX_XSTAT) ? NUM_BGX_XSTAT : n; 911 n = n - stat_cnt; 912 for (i = 0; i < stat_cnt; i++) { 913 xstats[si].id = si; 914 xstats[si].value = *(uint64_t *)(((char *)&bgx_stats) + 915 octeontx_bgx_xstats[i].soffset); 916 si++; 917 } 918 /*TODO: Similarly fill rest of HW stats */ 919 920 return si; 921 } 922 923 static int 924 octeontx_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 925 uint64_t *stat_val, unsigned int n) 926 { 927 unsigned int i, xstat_cnt = octeontx_dev_total_xstat(); 928 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 929 struct rte_eth_xstat xstats[xstat_cnt]; 930 931 octeontx_port_xstats(nic, xstats, xstat_cnt); 932 for (i = 0; i < n; i++) { 933 if (ids[i] >= xstat_cnt) { 934 PMD_INIT_LOG(ERR, "out of range id value"); 935 return -1; 936 } 937 stat_val[i] = xstats[ids[i]].value; 938 } 939 return n; 940 } 941 942 static int 943 octeontx_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 944 struct rte_eth_xstat_name *xstats_names, 945 unsigned int size) 946 { 947 int stat_cnt, si, i; 948 949 if (xstats_names) { 950 si = 0; 951 /* Fill BGX stats */ 952 stat_cnt = (size > NUM_BGX_XSTAT) ? NUM_BGX_XSTAT : size; 953 size = size - stat_cnt; 954 for (i = 0; i < stat_cnt; i++) { 955 strlcpy(xstats_names[si].name, 956 octeontx_bgx_xstats[i].sname, 957 sizeof(xstats_names[si].name)); 958 si++; 959 } 960 /*TODO: Similarly fill rest of HW stats */ 961 return si; 962 } else { 963 return octeontx_dev_total_xstat(); 964 } 965 } 966 967 static void build_xstat_names(struct rte_eth_xstat_name *xstat_names) 968 { 969 unsigned int i; 970 971 for (i = 0; i < NUM_BGX_XSTAT; i++) { 972 strlcpy(xstat_names[i].name, octeontx_bgx_xstats[i].sname, 973 RTE_ETH_XSTATS_NAME_SIZE); 974 } 975 } 976 977 static int 978 octeontx_dev_xstats_get_names_by_id(struct rte_eth_dev *dev __rte_unused, 979 const uint64_t *ids, 980 struct rte_eth_xstat_name *stat_names, 981 unsigned int n) 982 { 983 unsigned int i, xstat_cnt = octeontx_dev_total_xstat(); 984 struct rte_eth_xstat_name xstat_names[xstat_cnt]; 985 986 build_xstat_names(xstat_names); 987 for (i = 0; i < n; i++) { 988 if (ids[i] >= xstat_cnt) { 989 PMD_INIT_LOG(ERR, "out of range id value"); 990 return -1; 991 } 992 strlcpy(stat_names[i].name, xstat_names[ids[i]].name, 993 sizeof(stat_names[i].name)); 994 } 995 /*TODO: Similarly fill rest of HW stats */ 996 997 return n; 998 } 999 1000 static int 1001 octeontx_dev_xstats_get(struct rte_eth_dev *dev, 1002 struct rte_eth_xstat *xstats, 1003 unsigned int n) 1004 { 1005 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1006 1007 PMD_INIT_FUNC_TRACE(); 1008 return octeontx_port_xstats(nic, xstats, n); 1009 } 1010 1011 static int 1012 octeontx_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1013 { 1014 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1015 1016 PMD_INIT_FUNC_TRACE(); 1017 return octeontx_port_stats(nic, stats); 1018 } 1019 1020 static int 1021 octeontx_dev_stats_reset(struct rte_eth_dev *dev) 1022 { 1023 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1024 1025 PMD_INIT_FUNC_TRACE(); 1026 return octeontx_port_stats_clr(nic); 1027 } 1028 1029 static void 1030 octeontx_dev_mac_addr_del(struct rte_eth_dev *dev, uint32_t index) 1031 { 1032 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1033 int ret; 1034 1035 ret = octeontx_bgx_port_mac_del(nic->port_id, index); 1036 if (ret != 0) 1037 octeontx_log_err("failed to del MAC address filter on port %d", 1038 nic->port_id); 1039 } 1040 1041 static int 1042 octeontx_dev_mac_addr_add(struct rte_eth_dev *dev, 1043 struct rte_ether_addr *mac_addr, 1044 uint32_t index, 1045 __rte_unused uint32_t vmdq) 1046 { 1047 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1048 int ret; 1049 1050 ret = octeontx_bgx_port_mac_add(nic->port_id, mac_addr->addr_bytes, 1051 index); 1052 if (ret < 0) { 1053 octeontx_log_err("failed to add MAC address filter on port %d", 1054 nic->port_id); 1055 return ret; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int 1062 octeontx_dev_default_mac_addr_set(struct rte_eth_dev *dev, 1063 struct rte_ether_addr *addr) 1064 { 1065 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1066 int ret; 1067 1068 ret = octeontx_bgx_port_mac_set(nic->port_id, addr->addr_bytes); 1069 if (ret == 0) { 1070 /* Update same mac address to BGX CAM table */ 1071 ret = octeontx_bgx_port_mac_add(nic->port_id, addr->addr_bytes, 1072 0); 1073 } 1074 if (ret < 0) { 1075 octeontx_log_err("failed to set MAC address on port %d", 1076 nic->port_id); 1077 } 1078 1079 return ret; 1080 } 1081 1082 static int 1083 octeontx_dev_info(struct rte_eth_dev *dev, 1084 struct rte_eth_dev_info *dev_info) 1085 { 1086 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1087 1088 /* Autonegotiation may be disabled */ 1089 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 1090 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_100M | 1091 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G | 1092 RTE_ETH_LINK_SPEED_40G; 1093 1094 /* Min/Max MTU supported */ 1095 dev_info->min_rx_bufsize = OCCTX_MIN_FRS; 1096 dev_info->max_rx_pktlen = OCCTX_MAX_FRS; 1097 dev_info->max_mtu = dev_info->max_rx_pktlen - OCCTX_L2_OVERHEAD; 1098 dev_info->min_mtu = dev_info->min_rx_bufsize - OCCTX_L2_OVERHEAD; 1099 1100 dev_info->max_mac_addrs = 1101 octeontx_bgx_port_mac_entries_get(nic->port_id); 1102 dev_info->max_rx_queues = 1; 1103 dev_info->max_tx_queues = PKO_MAX_NUM_DQ; 1104 dev_info->min_rx_bufsize = 0; 1105 1106 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1107 .rx_free_thresh = 0, 1108 .rx_drop_en = 0, 1109 .offloads = OCTEONTX_RX_OFFLOADS, 1110 }; 1111 1112 dev_info->default_txconf = (struct rte_eth_txconf) { 1113 .tx_free_thresh = 0, 1114 .offloads = OCTEONTX_TX_OFFLOADS, 1115 }; 1116 1117 dev_info->rx_offload_capa = OCTEONTX_RX_OFFLOADS; 1118 dev_info->tx_offload_capa = OCTEONTX_TX_OFFLOADS; 1119 dev_info->rx_queue_offload_capa = OCTEONTX_RX_OFFLOADS; 1120 dev_info->tx_queue_offload_capa = OCTEONTX_TX_OFFLOADS; 1121 1122 return 0; 1123 } 1124 1125 static void 1126 octeontx_dq_info_getter(octeontx_dq_t *dq, void *out) 1127 { 1128 ((octeontx_dq_t *)out)->lmtline_va = dq->lmtline_va; 1129 ((octeontx_dq_t *)out)->ioreg_va = dq->ioreg_va; 1130 ((octeontx_dq_t *)out)->fc_status_va = dq->fc_status_va; 1131 } 1132 1133 static int 1134 octeontx_vf_start_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 1135 uint16_t qidx) 1136 { 1137 struct octeontx_txq *txq; 1138 int res; 1139 1140 PMD_INIT_FUNC_TRACE(); 1141 1142 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) 1143 return 0; 1144 1145 txq = dev->data->tx_queues[qidx]; 1146 1147 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 1148 &txq->dq, 1149 sizeof(octeontx_dq_t), 1150 txq->queue_id, 1151 octeontx_dq_info_getter); 1152 if (res < 0) { 1153 res = -EFAULT; 1154 goto close_port; 1155 } 1156 1157 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 1158 return res; 1159 1160 close_port: 1161 (void)octeontx_port_stop(nic); 1162 octeontx_pko_channel_stop(nic->base_ochan); 1163 octeontx_pko_channel_close(nic->base_ochan); 1164 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1165 return res; 1166 } 1167 1168 int 1169 octeontx_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1170 { 1171 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1172 1173 PMD_INIT_FUNC_TRACE(); 1174 qidx = qidx % PKO_VF_NUM_DQ; 1175 return octeontx_vf_start_tx_queue(dev, nic, qidx); 1176 } 1177 1178 static inline int 1179 octeontx_vf_stop_tx_queue(struct rte_eth_dev *dev, struct octeontx_nic *nic, 1180 uint16_t qidx) 1181 { 1182 int ret = 0; 1183 1184 RTE_SET_USED(nic); 1185 PMD_INIT_FUNC_TRACE(); 1186 1187 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) 1188 return 0; 1189 1190 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1191 return ret; 1192 } 1193 1194 int 1195 octeontx_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1196 { 1197 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1198 1199 PMD_INIT_FUNC_TRACE(); 1200 qidx = qidx % PKO_VF_NUM_DQ; 1201 1202 return octeontx_vf_stop_tx_queue(dev, nic, qidx); 1203 } 1204 1205 static void 1206 octeontx_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1207 { 1208 int res; 1209 1210 PMD_INIT_FUNC_TRACE(); 1211 1212 if (dev->data->tx_queues[qid]) { 1213 res = octeontx_dev_tx_queue_stop(dev, qid); 1214 if (res < 0) 1215 octeontx_log_err("failed stop tx_queue(%d)\n", qid); 1216 1217 rte_free(dev->data->tx_queues[qid]); 1218 } 1219 } 1220 1221 static int 1222 octeontx_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1223 uint16_t nb_desc, unsigned int socket_id, 1224 const struct rte_eth_txconf *tx_conf __rte_unused) 1225 { 1226 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1227 struct octeontx_txq *txq = NULL; 1228 uint16_t dq_num; 1229 int res = 0; 1230 1231 RTE_SET_USED(nb_desc); 1232 RTE_SET_USED(socket_id); 1233 1234 dq_num = (nic->pko_vfid * PKO_VF_NUM_DQ) + qidx; 1235 1236 /* Socket id check */ 1237 if (socket_id != (unsigned int)SOCKET_ID_ANY && 1238 socket_id != (unsigned int)nic->node) 1239 PMD_TX_LOG(INFO, "socket_id expected %d, configured %d", 1240 socket_id, nic->node); 1241 1242 /* Free memory prior to re-allocation if needed. */ 1243 if (dev->data->tx_queues[qidx] != NULL) { 1244 PMD_TX_LOG(DEBUG, "freeing memory prior to re-allocation %d", 1245 qidx); 1246 octeontx_dev_tx_queue_release(dev, qidx); 1247 dev->data->tx_queues[qidx] = NULL; 1248 } 1249 1250 /* Allocating tx queue data structure */ 1251 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct octeontx_txq), 1252 RTE_CACHE_LINE_SIZE, nic->node); 1253 if (txq == NULL) { 1254 octeontx_log_err("failed to allocate txq=%d", qidx); 1255 res = -ENOMEM; 1256 goto err; 1257 } 1258 1259 txq->eth_dev = dev; 1260 txq->queue_id = dq_num; 1261 dev->data->tx_queues[qidx] = txq; 1262 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1263 1264 res = octeontx_pko_channel_query_dqs(nic->base_ochan, 1265 &txq->dq, 1266 sizeof(octeontx_dq_t), 1267 txq->queue_id, 1268 octeontx_dq_info_getter); 1269 if (res < 0) { 1270 res = -EFAULT; 1271 goto err; 1272 } 1273 1274 PMD_TX_LOG(DEBUG, "[%d]:[%d] txq=%p nb_desc=%d lmtline=%p ioreg_va=%p fc_status_va=%p", 1275 qidx, txq->queue_id, txq, nb_desc, txq->dq.lmtline_va, 1276 txq->dq.ioreg_va, 1277 txq->dq.fc_status_va); 1278 1279 return res; 1280 1281 err: 1282 rte_free(txq); 1283 1284 return res; 1285 } 1286 1287 static int 1288 octeontx_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1289 uint16_t nb_desc, unsigned int socket_id, 1290 const struct rte_eth_rxconf *rx_conf, 1291 struct rte_mempool *mb_pool) 1292 { 1293 struct octeontx_nic *nic = octeontx_pmd_priv(dev); 1294 struct rte_mempool_ops *mp_ops = NULL; 1295 struct octeontx_rxq *rxq = NULL; 1296 pki_pktbuf_cfg_t pktbuf_conf; 1297 pki_hash_cfg_t pki_hash; 1298 pki_qos_cfg_t pki_qos; 1299 uintptr_t pool; 1300 int ret, port; 1301 uint16_t gaura; 1302 unsigned int ev_queues = (nic->ev_queues * nic->port_id) + qidx; 1303 unsigned int ev_ports = (nic->ev_ports * nic->port_id) + qidx; 1304 1305 RTE_SET_USED(nb_desc); 1306 1307 memset(&pktbuf_conf, 0, sizeof(pktbuf_conf)); 1308 memset(&pki_hash, 0, sizeof(pki_hash)); 1309 memset(&pki_qos, 0, sizeof(pki_qos)); 1310 1311 mp_ops = rte_mempool_get_ops(mb_pool->ops_index); 1312 if (strcmp(mp_ops->name, "octeontx_fpavf")) { 1313 octeontx_log_err("failed to find octeontx_fpavf mempool"); 1314 return -ENOTSUP; 1315 } 1316 1317 /* Handle forbidden configurations */ 1318 if (nic->pki.classifier_enable) { 1319 octeontx_log_err("cannot setup queue %d. " 1320 "Classifier option unsupported", qidx); 1321 return -EINVAL; 1322 } 1323 1324 port = nic->port_id; 1325 1326 /* Rx deferred start is not supported */ 1327 if (rx_conf->rx_deferred_start) { 1328 octeontx_log_err("rx deferred start not supported"); 1329 return -EINVAL; 1330 } 1331 1332 /* Verify queue index */ 1333 if (qidx >= dev->data->nb_rx_queues) { 1334 octeontx_log_err("QID %d not supported (0 - %d available)\n", 1335 qidx, (dev->data->nb_rx_queues - 1)); 1336 return -ENOTSUP; 1337 } 1338 1339 /* Socket id check */ 1340 if (socket_id != (unsigned int)SOCKET_ID_ANY && 1341 socket_id != (unsigned int)nic->node) 1342 PMD_RX_LOG(INFO, "socket_id expected %d, configured %d", 1343 socket_id, nic->node); 1344 1345 /* Allocating rx queue data structure */ 1346 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct octeontx_rxq), 1347 RTE_CACHE_LINE_SIZE, nic->node); 1348 if (rxq == NULL) { 1349 octeontx_log_err("failed to allocate rxq=%d", qidx); 1350 return -ENOMEM; 1351 } 1352 1353 if (!nic->pki.initialized) { 1354 pktbuf_conf.port_type = 0; 1355 pki_hash.port_type = 0; 1356 pki_qos.port_type = 0; 1357 1358 pktbuf_conf.mmask.f_wqe_skip = 1; 1359 pktbuf_conf.mmask.f_first_skip = 1; 1360 pktbuf_conf.mmask.f_later_skip = 1; 1361 pktbuf_conf.mmask.f_mbuff_size = 1; 1362 pktbuf_conf.mmask.f_cache_mode = 1; 1363 1364 pktbuf_conf.wqe_skip = OCTTX_PACKET_WQE_SKIP; 1365 pktbuf_conf.first_skip = OCTTX_PACKET_FIRST_SKIP(mb_pool); 1366 pktbuf_conf.later_skip = OCTTX_PACKET_LATER_SKIP; 1367 pktbuf_conf.mbuff_size = (mb_pool->elt_size - 1368 RTE_PKTMBUF_HEADROOM - 1369 rte_pktmbuf_priv_size(mb_pool) - 1370 sizeof(struct rte_mbuf)); 1371 1372 pktbuf_conf.cache_mode = PKI_OPC_MODE_STF2_STT; 1373 1374 ret = octeontx_pki_port_pktbuf_config(port, &pktbuf_conf); 1375 if (ret != 0) { 1376 octeontx_log_err("fail to configure pktbuf for port %d", 1377 port); 1378 rte_free(rxq); 1379 return ret; 1380 } 1381 PMD_RX_LOG(DEBUG, "Port %d Rx pktbuf configured:\n" 1382 "\tmbuf_size:\t0x%0x\n" 1383 "\twqe_skip:\t0x%0x\n" 1384 "\tfirst_skip:\t0x%0x\n" 1385 "\tlater_skip:\t0x%0x\n" 1386 "\tcache_mode:\t%s\n", 1387 port, 1388 pktbuf_conf.mbuff_size, 1389 pktbuf_conf.wqe_skip, 1390 pktbuf_conf.first_skip, 1391 pktbuf_conf.later_skip, 1392 (pktbuf_conf.cache_mode == 1393 PKI_OPC_MODE_STT) ? 1394 "STT" : 1395 (pktbuf_conf.cache_mode == 1396 PKI_OPC_MODE_STF) ? 1397 "STF" : 1398 (pktbuf_conf.cache_mode == 1399 PKI_OPC_MODE_STF1_STT) ? 1400 "STF1_STT" : "STF2_STT"); 1401 1402 if (nic->pki.hash_enable) { 1403 pki_hash.tag_dlc = 1; 1404 pki_hash.tag_slc = 1; 1405 pki_hash.tag_dlf = 1; 1406 pki_hash.tag_slf = 1; 1407 pki_hash.tag_prt = 1; 1408 octeontx_pki_port_hash_config(port, &pki_hash); 1409 } 1410 1411 pool = (uintptr_t)mb_pool->pool_id; 1412 1413 /* Get the gaura Id */ 1414 gaura = octeontx_fpa_bufpool_gaura(pool); 1415 1416 pki_qos.qpg_qos = PKI_QPG_QOS_NONE; 1417 pki_qos.num_entry = 1; 1418 pki_qos.drop_policy = 0; 1419 pki_qos.tag_type = 0L; 1420 pki_qos.qos_entry[0].port_add = 0; 1421 pki_qos.qos_entry[0].gaura = gaura; 1422 pki_qos.qos_entry[0].ggrp_ok = ev_queues; 1423 pki_qos.qos_entry[0].ggrp_bad = ev_queues; 1424 pki_qos.qos_entry[0].grptag_bad = 0; 1425 pki_qos.qos_entry[0].grptag_ok = 0; 1426 1427 ret = octeontx_pki_port_create_qos(port, &pki_qos); 1428 if (ret < 0) { 1429 octeontx_log_err("failed to create QOS port=%d, q=%d", 1430 port, qidx); 1431 rte_free(rxq); 1432 return ret; 1433 } 1434 nic->pki.initialized = true; 1435 } 1436 1437 rxq->port_id = nic->port_id; 1438 rxq->eth_dev = dev; 1439 rxq->queue_id = qidx; 1440 rxq->evdev = nic->evdev; 1441 rxq->ev_queues = ev_queues; 1442 rxq->ev_ports = ev_ports; 1443 rxq->pool = mb_pool; 1444 1445 octeontx_recheck_rx_offloads(rxq); 1446 dev->data->rx_queues[qidx] = rxq; 1447 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1448 1449 return 0; 1450 } 1451 1452 static void 1453 octeontx_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1454 { 1455 rte_free(dev->data->rx_queues[qid]); 1456 } 1457 1458 static const uint32_t * 1459 octeontx_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1460 { 1461 static const uint32_t ptypes[] = { 1462 RTE_PTYPE_L3_IPV4, 1463 RTE_PTYPE_L3_IPV4_EXT, 1464 RTE_PTYPE_L3_IPV6, 1465 RTE_PTYPE_L3_IPV6_EXT, 1466 RTE_PTYPE_L4_TCP, 1467 RTE_PTYPE_L4_UDP, 1468 RTE_PTYPE_L4_FRAG, 1469 RTE_PTYPE_UNKNOWN 1470 }; 1471 1472 if (dev->rx_pkt_burst == octeontx_recv_pkts) 1473 return ptypes; 1474 1475 return NULL; 1476 } 1477 1478 static int 1479 octeontx_pool_ops(struct rte_eth_dev *dev, const char *pool) 1480 { 1481 RTE_SET_USED(dev); 1482 1483 if (!strcmp(pool, "octeontx_fpavf")) 1484 return 0; 1485 1486 return -ENOTSUP; 1487 } 1488 1489 /* Initialize and register driver with DPDK Application */ 1490 static const struct eth_dev_ops octeontx_dev_ops = { 1491 .dev_configure = octeontx_dev_configure, 1492 .dev_infos_get = octeontx_dev_info, 1493 .dev_close = octeontx_dev_close, 1494 .dev_start = octeontx_dev_start, 1495 .dev_stop = octeontx_dev_stop, 1496 .promiscuous_enable = octeontx_dev_promisc_enable, 1497 .promiscuous_disable = octeontx_dev_promisc_disable, 1498 .link_update = octeontx_dev_link_update, 1499 .stats_get = octeontx_dev_stats_get, 1500 .stats_reset = octeontx_dev_stats_reset, 1501 .mac_addr_remove = octeontx_dev_mac_addr_del, 1502 .mac_addr_add = octeontx_dev_mac_addr_add, 1503 .mac_addr_set = octeontx_dev_default_mac_addr_set, 1504 .vlan_offload_set = octeontx_dev_vlan_offload_set, 1505 .vlan_filter_set = octeontx_dev_vlan_filter_set, 1506 .tx_queue_start = octeontx_dev_tx_queue_start, 1507 .tx_queue_stop = octeontx_dev_tx_queue_stop, 1508 .tx_queue_setup = octeontx_dev_tx_queue_setup, 1509 .tx_queue_release = octeontx_dev_tx_queue_release, 1510 .rx_queue_setup = octeontx_dev_rx_queue_setup, 1511 .rx_queue_release = octeontx_dev_rx_queue_release, 1512 .dev_set_link_up = octeontx_dev_set_link_up, 1513 .dev_set_link_down = octeontx_dev_set_link_down, 1514 .dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get, 1515 .mtu_set = octeontx_dev_mtu_set, 1516 .pool_ops_supported = octeontx_pool_ops, 1517 .flow_ctrl_get = octeontx_dev_flow_ctrl_get, 1518 .flow_ctrl_set = octeontx_dev_flow_ctrl_set, 1519 .xstats_get = octeontx_dev_xstats_get, 1520 .xstats_get_by_id = octeontx_dev_xstats_get_by_id, 1521 .xstats_get_names = octeontx_dev_xstats_get_names, 1522 .xstats_get_names_by_id = octeontx_dev_xstats_get_names_by_id, 1523 .allmulticast_enable = octeontx_allmulticast_enable, 1524 .allmulticast_disable = octeontx_allmulticast_disable, 1525 }; 1526 1527 /* Create Ethdev interface per BGX LMAC ports */ 1528 static int 1529 octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev, 1530 int socket_id) 1531 { 1532 int res; 1533 size_t pko_vfid; 1534 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1535 struct octeontx_nic *nic = NULL; 1536 struct rte_eth_dev *eth_dev = NULL; 1537 struct rte_eth_dev_data *data; 1538 const char *name = rte_vdev_device_name(dev); 1539 int max_entries; 1540 1541 PMD_INIT_FUNC_TRACE(); 1542 1543 sprintf(octtx_name, "%s_%d", name, port); 1544 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1545 eth_dev = rte_eth_dev_attach_secondary(octtx_name); 1546 if (eth_dev == NULL) 1547 return -ENODEV; 1548 1549 eth_dev->dev_ops = &octeontx_dev_ops; 1550 eth_dev->device = &dev->device; 1551 octeontx_set_tx_function(eth_dev); 1552 eth_dev->rx_pkt_burst = octeontx_recv_pkts; 1553 rte_eth_dev_probing_finish(eth_dev); 1554 return 0; 1555 } 1556 1557 /* Reserve an ethdev entry */ 1558 eth_dev = rte_eth_dev_allocate(octtx_name); 1559 if (eth_dev == NULL) { 1560 octeontx_log_err("failed to allocate rte_eth_dev"); 1561 res = -ENOMEM; 1562 goto err; 1563 } 1564 data = eth_dev->data; 1565 1566 nic = rte_zmalloc_socket(octtx_name, sizeof(*nic), 0, socket_id); 1567 if (nic == NULL) { 1568 octeontx_log_err("failed to allocate nic structure"); 1569 res = -ENOMEM; 1570 goto err; 1571 } 1572 data->dev_private = nic; 1573 pko_vfid = octeontx_pko_get_vfid(); 1574 1575 if (pko_vfid == SIZE_MAX) { 1576 octeontx_log_err("failed to get pko vfid"); 1577 res = -ENODEV; 1578 goto err; 1579 } 1580 1581 nic->pko_vfid = pko_vfid; 1582 nic->port_id = port; 1583 nic->evdev = evdev; 1584 __atomic_fetch_add(&evdev_refcnt, 1, __ATOMIC_ACQUIRE); 1585 1586 res = octeontx_port_open(nic); 1587 if (res < 0) 1588 goto err; 1589 1590 /* Rx side port configuration */ 1591 res = octeontx_pki_port_open(port); 1592 if (res != 0) { 1593 octeontx_log_err("failed to open PKI port %d", port); 1594 res = -ENODEV; 1595 goto err; 1596 } 1597 1598 eth_dev->device = &dev->device; 1599 eth_dev->intr_handle = NULL; 1600 eth_dev->data->numa_node = dev->device.numa_node; 1601 1602 data->port_id = eth_dev->data->port_id; 1603 1604 nic->ev_queues = 1; 1605 nic->ev_ports = 1; 1606 nic->print_flag = -1; 1607 nic->reconfigure = false; 1608 1609 data->dev_link.link_status = RTE_ETH_LINK_DOWN; 1610 data->dev_started = 0; 1611 data->promiscuous = 0; 1612 data->all_multicast = 0; 1613 data->scattered_rx = 0; 1614 1615 /* Get maximum number of supported MAC entries */ 1616 max_entries = octeontx_bgx_port_mac_entries_get(nic->port_id); 1617 if (max_entries < 0) { 1618 octeontx_log_err("Failed to get max entries for mac addr"); 1619 res = -ENOTSUP; 1620 goto err; 1621 } 1622 1623 data->mac_addrs = rte_zmalloc_socket(octtx_name, max_entries * 1624 RTE_ETHER_ADDR_LEN, 0, 1625 socket_id); 1626 if (data->mac_addrs == NULL) { 1627 octeontx_log_err("failed to allocate memory for mac_addrs"); 1628 res = -ENOMEM; 1629 goto err; 1630 } 1631 1632 eth_dev->dev_ops = &octeontx_dev_ops; 1633 1634 /* Finally save ethdev pointer to the NIC structure */ 1635 nic->dev = eth_dev; 1636 1637 if (nic->port_id != data->port_id) { 1638 octeontx_log_err("eth_dev->port_id (%d) is diff to orig (%d)", 1639 data->port_id, nic->port_id); 1640 res = -EINVAL; 1641 goto free_mac_addrs; 1642 } 1643 1644 res = rte_eal_alarm_set(OCCTX_INTR_POLL_INTERVAL_MS * 1000, 1645 octeontx_link_status_poll, nic); 1646 if (res) { 1647 octeontx_log_err("Failed to start link polling alarm"); 1648 goto err; 1649 } 1650 1651 /* Update port_id mac to eth_dev */ 1652 memcpy(data->mac_addrs, nic->mac_addr, RTE_ETHER_ADDR_LEN); 1653 1654 /* Update same mac address to BGX CAM table at index 0 */ 1655 octeontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0); 1656 1657 res = octeontx_dev_flow_ctrl_init(eth_dev); 1658 if (res < 0) 1659 goto err; 1660 1661 PMD_INIT_LOG(DEBUG, "ethdev info: "); 1662 PMD_INIT_LOG(DEBUG, "port %d, port_ena %d ochan %d num_ochan %d tx_q %d", 1663 nic->port_id, nic->port_ena, 1664 nic->base_ochan, nic->num_ochans, 1665 nic->num_tx_queues); 1666 PMD_INIT_LOG(DEBUG, "speed %d mtu %d", nic->speed, nic->bgx_mtu); 1667 1668 rte_octeontx_pchan_map[(nic->base_ochan >> 8) & 0x7] 1669 [(nic->base_ochan >> 4) & 0xF] = data->port_id; 1670 1671 rte_eth_dev_probing_finish(eth_dev); 1672 return data->port_id; 1673 1674 free_mac_addrs: 1675 rte_free(data->mac_addrs); 1676 data->mac_addrs = NULL; 1677 err: 1678 if (nic) 1679 octeontx_port_close(nic); 1680 1681 rte_eth_dev_release_port(eth_dev); 1682 1683 return res; 1684 } 1685 1686 /* Un initialize octeontx device */ 1687 static int 1688 octeontx_remove(struct rte_vdev_device *dev) 1689 { 1690 char octtx_name[OCTEONTX_MAX_NAME_LEN]; 1691 struct rte_eth_dev *eth_dev = NULL; 1692 struct octeontx_nic *nic = NULL; 1693 int i; 1694 1695 if (dev == NULL) 1696 return -EINVAL; 1697 1698 for (i = 0; i < OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT; i++) { 1699 sprintf(octtx_name, "eth_octeontx_%d", i); 1700 1701 eth_dev = rte_eth_dev_allocated(octtx_name); 1702 if (eth_dev == NULL) 1703 continue; /* port already released */ 1704 1705 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1706 rte_eth_dev_release_port(eth_dev); 1707 continue; 1708 } 1709 1710 nic = octeontx_pmd_priv(eth_dev); 1711 rte_event_dev_stop(nic->evdev); 1712 PMD_INIT_LOG(INFO, "Closing octeontx device %s", octtx_name); 1713 octeontx_dev_close(eth_dev); 1714 rte_eth_dev_release_port(eth_dev); 1715 } 1716 1717 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1718 return 0; 1719 1720 /* Free FC resource */ 1721 octeontx_pko_fc_free(); 1722 1723 return 0; 1724 } 1725 1726 /* Initialize octeontx device */ 1727 static int 1728 octeontx_probe(struct rte_vdev_device *dev) 1729 { 1730 const char *dev_name; 1731 static int probe_once; 1732 uint8_t socket_id, qlist; 1733 int tx_vfcnt, port_id, evdev, qnum, pnum, res, i; 1734 struct rte_event_dev_config dev_conf; 1735 const char *eventdev_name = "event_octeontx"; 1736 struct rte_event_dev_info info; 1737 struct rte_eth_dev *eth_dev; 1738 1739 struct octeontx_vdev_init_params init_params = { 1740 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 1741 }; 1742 1743 dev_name = rte_vdev_device_name(dev); 1744 1745 if (rte_eal_process_type() == RTE_PROC_SECONDARY && 1746 strlen(rte_vdev_device_args(dev)) == 0) { 1747 eth_dev = rte_eth_dev_attach_secondary(dev_name); 1748 if (!eth_dev) { 1749 PMD_INIT_LOG(ERR, "Failed to probe %s", dev_name); 1750 return -1; 1751 } 1752 /* TODO: request info from primary to set up Rx and Tx */ 1753 eth_dev->dev_ops = &octeontx_dev_ops; 1754 eth_dev->device = &dev->device; 1755 rte_eth_dev_probing_finish(eth_dev); 1756 return 0; 1757 } 1758 1759 res = octeontx_parse_vdev_init_params(&init_params, dev); 1760 if (res < 0) 1761 return -EINVAL; 1762 1763 if (init_params.nr_port > OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT) { 1764 octeontx_log_err("nr_port (%d) > max (%d)", init_params.nr_port, 1765 OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT); 1766 return -ENOTSUP; 1767 } 1768 1769 PMD_INIT_LOG(DEBUG, "initializing %s pmd", dev_name); 1770 1771 socket_id = rte_socket_id(); 1772 1773 tx_vfcnt = octeontx_pko_vf_count(); 1774 1775 if (tx_vfcnt < init_params.nr_port) { 1776 octeontx_log_err("not enough PKO (%d) for port number (%d)", 1777 tx_vfcnt, init_params.nr_port); 1778 return -EINVAL; 1779 } 1780 evdev = rte_event_dev_get_dev_id(eventdev_name); 1781 if (evdev < 0) { 1782 octeontx_log_err("eventdev %s not found", eventdev_name); 1783 return -ENODEV; 1784 } 1785 1786 res = rte_event_dev_info_get(evdev, &info); 1787 if (res < 0) { 1788 octeontx_log_err("failed to eventdev info %d", res); 1789 return -EINVAL; 1790 } 1791 1792 PMD_INIT_LOG(DEBUG, "max_queue %d max_port %d", 1793 info.max_event_queues, info.max_event_ports); 1794 1795 if (octeontx_pko_init_fc(tx_vfcnt)) 1796 return -ENOMEM; 1797 1798 devconf_set_default_sane_values(&dev_conf, &info); 1799 res = rte_event_dev_configure(evdev, &dev_conf); 1800 if (res < 0) 1801 goto parse_error; 1802 1803 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, 1804 (uint32_t *)&pnum); 1805 rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, 1806 (uint32_t *)&qnum); 1807 if (pnum < qnum) { 1808 octeontx_log_err("too few event ports (%d) for event_q(%d)", 1809 pnum, qnum); 1810 res = -EINVAL; 1811 goto parse_error; 1812 } 1813 1814 /* Enable all queues available */ 1815 for (i = 0; i < qnum; i++) { 1816 res = rte_event_queue_setup(evdev, i, NULL); 1817 if (res < 0) { 1818 octeontx_log_err("failed to setup event_q(%d): res %d", 1819 i, res); 1820 goto parse_error; 1821 } 1822 } 1823 1824 /* Enable all ports available */ 1825 for (i = 0; i < pnum; i++) { 1826 res = rte_event_port_setup(evdev, i, NULL); 1827 if (res < 0) { 1828 res = -ENODEV; 1829 octeontx_log_err("failed to setup ev port(%d) res=%d", 1830 i, res); 1831 goto parse_error; 1832 } 1833 } 1834 1835 __atomic_store_n(&evdev_refcnt, 0, __ATOMIC_RELEASE); 1836 /* 1837 * Do 1:1 links for ports & queues. All queues would be mapped to 1838 * one port. If there are more ports than queues, then some ports 1839 * won't be linked to any queue. 1840 */ 1841 for (i = 0; i < qnum; i++) { 1842 /* Link one queue to one event port */ 1843 qlist = i; 1844 res = rte_event_port_link(evdev, i, &qlist, NULL, 1); 1845 if (res < 0) { 1846 res = -ENODEV; 1847 octeontx_log_err("failed to link port (%d): res=%d", 1848 i, res); 1849 goto parse_error; 1850 } 1851 } 1852 1853 /* Create ethdev interface */ 1854 for (i = 0; i < init_params.nr_port; i++) { 1855 port_id = octeontx_create(dev, i, evdev, socket_id); 1856 if (port_id < 0) { 1857 octeontx_log_err("failed to create device %s", 1858 dev_name); 1859 res = -ENODEV; 1860 goto parse_error; 1861 } 1862 1863 PMD_INIT_LOG(INFO, "created ethdev %s for port %d", dev_name, 1864 port_id); 1865 } 1866 1867 if (probe_once) { 1868 octeontx_log_err("interface %s not supported", dev_name); 1869 octeontx_remove(dev); 1870 res = -ENOTSUP; 1871 goto parse_error; 1872 } 1873 rte_mbuf_set_platform_mempool_ops("octeontx_fpavf"); 1874 probe_once = 1; 1875 1876 return 0; 1877 1878 parse_error: 1879 octeontx_pko_fc_free(); 1880 return res; 1881 } 1882 1883 static struct rte_vdev_driver octeontx_pmd_drv = { 1884 .probe = octeontx_probe, 1885 .remove = octeontx_remove, 1886 }; 1887 1888 RTE_PMD_REGISTER_VDEV(OCTEONTX_PMD, octeontx_pmd_drv); 1889 RTE_PMD_REGISTER_ALIAS(OCTEONTX_PMD, eth_octeontx); 1890 RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX_PMD, "nr_port=<int> "); 1891